upd with pci scan

This commit is contained in:
Ole Algoritme
2022-12-03 20:08:58 +01:00
parent 334c289d83
commit cbdfbd2615
195 changed files with 184 additions and 275 deletions

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@@ -1,5 +1,6 @@
all: all:
gcc gddr6.c include/nva/gpu.c include/nva/nva.c include/nva/chipset.c include/nva/regspace.c -o gddr6 -lpciaccess gcc -O3 -Wall -o gddr6 gddr6.c -lpci
clean: clean:
rm -rf gddr6 rm -f gddr6

159
gddr6.c
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@@ -1,92 +1,99 @@
#include <stdio.h> #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <unistd.h> #include <unistd.h>
#include "include/nva/nva.h" #include <string.h>
#include "include/ampere/ga100/dev_boot.h" #include <errno.h>
#include <fcntl.h>
#include <sys/mman.h>
#include <pci/pci.h>
enum { struct device
NVIDIA_MMIO_MASK_PMC = 0x00000FFF, {
NVIDIA_MMIO_MASK_PBUS = 0x00001FFF, uint32_t bar0;
NVIDIA_MASK_ALL = 0x0000FFFF, uint32_t offset;
uint16_t dev_id;
const char *arch;
const char *name;
}; };
struct pmc_id { static struct device devices[] = {
uint8_t stepping; { .bar0 = 0xEC000000, .offset = 0x0000E2A8, .dev_id = 0x2684, .arch = "AD102", .name = "RTX 4090" },
uint8_t device_id; { .bar0 = 0xFB000000, .offset = 0x0000E2A8, .dev_id = 0x1337, .arch = "GA102", .name = "RTX 3090" },
uint16_t gpu_id; { .bar0 = 0xFB000000, .offset = 0x0000EE50, .dev_id = 0x1337, .arch = "GA104", .name = "RTX 3070" },
}; };
void PMC_ID (uint32_t value, struct device * pci_detect_dev()
struct pmc_id *id) { {
id->stepping = (value << 0) >> 0; struct pci_access *pacc = NULL;
id->device_id = (value << 0) >> 12; struct pci_dev *dev = NULL;
id->gpu_id = (value << 0) >> 20; struct device *device = NULL;
pacc = pci_alloc();
pci_init(pacc);
pci_scan_bus(pacc);
for (dev = pacc->devices; dev; dev = dev->next) {
pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
for (uint32_t i = 0; i < 3; i++) {
if (dev->device_id == devices[i].dev_id) {
device = &devices[i];
}
}
}
pci_cleanup(pacc);
return device;
} }
void read_temps(int cnum, uint32_t offset) { int main(int argc, char **argv)
uint32_t temp = 0; {
while(1) { int fd;
temp = nva_rd32(cnum, offset); int map_size = 4096UL;
temp = (temp & 0x00000fff) / 0x20; void *map_base, *virt_addr;
fprintf(stderr, "\rGDDR6 VRAM Temp: %d°c", temp); uint32_t read_result, base_offset, temp;
fflush(stderr); uint32_t offset;
sleep(1); struct device *device = NULL;
}
}
int main(int argc, char **argv) { char *MEM_RES = "\x2f\x64\x65\x76\x2f\x6d\x65\x6d";
int c;
int i;
int cnum = 0;
int mask = NVIDIA_MASK_ALL;
if (nva_init()) { device = pci_detect_dev();
fprintf (stderr, "PCI init failure!. Are you r00t?\n"); offset = device->bar0 + device->offset;
return 1;
if (device == NULL) {
printf("No compatible devices device. \n");
exit(-1);
} }
while ((c = getopt (argc, argv, "c:")) != -1) printf("Device: %s (%s / 0x%04x) \n", device->name, device->arch, device->dev_id);
switch (c) {
case 'c': while (1) {
sscanf(optarg, "%d", &cnum); if ((fd = open(MEM_RES, O_RDWR | O_SYNC)) == -1) {
break; printf("Can't read memory. Are you r00t?\n");
default: exit(-1);
break; }
base_offset = offset & ~(sysconf(_SC_PAGE_SIZE)-1);
map_base = mmap(0, map_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, base_offset);
if (!map_base) {
printf("Can't map memory. Are you r00t?\n");
exit(-1);
}
virt_addr = map_base + offset - base_offset;
read_result = *((uint32_t *) virt_addr);
temp = (read_result & 0x00000fff) / 0x20;
printf("\rGDDR6X VRAM Temp: %d°c", temp);
fflush(stdout);
if (munmap(map_base, map_size) == -1) {
printf("Can't unmap memory!\n");
exit(-1);
}
close(fd);
sleep(1);
} }
if (cnum >= nva_cardsnum) {
if (nva_cardsnum)
fprintf (stderr, "No valid card.\n");
else
fprintf (stderr, "No cards found.\n");
return 1;
}
if (mask & NVIDIA_MMIO_MASK_PMC) {
uint32_t pmc_boot_0 = nva_rd32(cnum, NV_PMC_BOOT_0);
struct pmc_id id;
PMC_ID(pmc_boot_0, &id);
switch (id.gpu_id) {
uint32_t offset;
case 0xb72: { // ga102
// TODO: temps over 100 might fail
offset = 0x0000E2A8;
read_temps(cnum, offset);
}
break;
case 0xb74: { // ga104
offset = 0x0000EE50;
read_temps(cnum, offset);
}
break;
default:
fprintf (stderr, "No valid card.\n");
break;
}
}
return 0; return 0;
} }

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@@ -1,11 +0,0 @@
all:
gcc -c gddr6_asm.s -o gddr6_asm.o
gcc gddr6_asm.o -o gddr6_asm
gcc -c gddr6.c -o gddr6.o
gcc gddr6.o -o gddr6
clean:
rm -f *.o
rm -f gddr6_asm gddr6

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@@ -1,58 +0,0 @@
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <fcntl.h>
#include <sys/mman.h>
int main(int argc, char **argv)
{
int fd;
int map_size = 4096UL;
void *map_base, *virt_addr;
uint32_t read_result, base_offset, temp;
//uint32_t bar = 0xFB000000; // GA102 + GA104
uint32_t bar = 0xEC000000; // AD102 (RTX 4090)
uint32_t offset = bar + 0x0000E2A8; // GA102 + AD102
//uint32_t offset = bar + 0x0000EE50; // GA104
char *MEM_RES = "\x2f\x64\x65\x76\x2f\x6d\x65\x6d";
while (1)
{
if ((fd = open(MEM_RES, O_RDWR | O_SYNC)) == -1)
{
printf("Can't read memory. Are you r00t?\n");
exit(-1);
}
base_offset = offset & ~(sysconf(_SC_PAGE_SIZE)-1);
map_base = mmap(0, map_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, base_offset);
if (!map_base)
{
printf("Can't map memory. Are you r00t?\n");
exit(-1);
}
virt_addr = map_base + offset - base_offset;
read_result = *((uint32_t *) virt_addr);
temp = (read_result & 0x00000fff) / 0x20;
printf("\rGDDR6X VRAM Temp: %d°c", temp);
fflush(stdout);
if (munmap(map_base, map_size) == -1)
{
printf("Can't unmap memory!\n");
exit(-1);
}
close(fd);
sleep(1);
}
return 0;
}

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@@ -1,127 +0,0 @@
.file "gddr6.s"
.text
.section .rodata
.LC0:
.string "/dev/mem"
.LC1:
.string "\rGDDR6 VRAM Temp: %d\302\260c"
.text
.globl main
.type main, @function
main:
.LFB6:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $80, %rsp
movl %edi, -68(%rbp)
movq %rsi, -80(%rbp)
movl $4096, -56(%rbp)
movl $-83886080, -52(%rbp)
movl -52(%rbp), %eax
addl $58024, %eax
movl %eax, -48(%rbp)
leaq .LC0(%rip), %rax
movq %rax, -24(%rbp)
.L5:
movq -24(%rbp), %rax
movl $1052674, %esi
movq %rax, %rdi
movl $0, %eax
call open@PLT
movl %eax, -44(%rbp)
cmpl $-1, -44(%rbp)
jne .L2
movl $-1, %edi
call exit@PLT
.L2:
movl $30, %edi
call sysconf@PLT
subl $1, %eax
notl %eax
movl %eax, %edx
movl -48(%rbp), %eax
andl %edx, %eax
movl %eax, -40(%rbp)
movl -40(%rbp), %ecx
movl -56(%rbp), %eax
cltq
movl -44(%rbp), %edx
movq %rcx, %r9
movl %edx, %r8d
movl $1, %ecx
movl $3, %edx
movq %rax, %rsi
movl $0, %edi
call mmap@PLT
movq %rax, -16(%rbp)
cmpq $0, -16(%rbp)
jne .L3
movl $-1, %edi
call exit@PLT
.L3:
movl -48(%rbp), %edx
movl -40(%rbp), %eax
subq %rax, %rdx
movq -16(%rbp), %rax
addq %rdx, %rax
movq %rax, -8(%rbp)
movq -8(%rbp), %rax
movl (%rax), %eax
movl %eax, -36(%rbp)
movl -36(%rbp), %eax
andl $4095, %eax
movl %eax, -32(%rbp)
movl -32(%rbp), %eax
shrl $5, %eax
movl %eax, -28(%rbp)
movl -28(%rbp), %eax
movl %eax, %esi
leaq .LC1(%rip), %rdi
movl $0, %eax
call printf@PLT
movq stdout(%rip), %rax
movq %rax, %rdi
call fflush@PLT
movl -56(%rbp), %eax
movslq %eax, %rdx
movq -16(%rbp), %rax
movq %rdx, %rsi
movq %rax, %rdi
call munmap@PLT
cmpl $-1, %eax
jne .L4
movl $-1, %edi
call exit@PLT
.L4:
movl -44(%rbp), %eax
movl %eax, %edi
call close@PLT
movl $1, %edi
call sleep@PLT
jmp .L5
.cfi_endproc
.LFE6:
.size main, .-main
.ident "GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.1) 9.4.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:

5
nva/Makefile Normal file
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@@ -0,0 +1,5 @@
all:
gcc gddr6.c include/nva/gpu.c include/nva/nva.c include/nva/chipset.c include/nva/regspace.c -o gddr6 -lpciaccess
clean:
rm -rf gddr6

92
nva/gddr6.c Normal file
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@@ -0,0 +1,92 @@
#include <stdio.h>
#include <unistd.h>
#include "include/nva/nva.h"
#include "include/ampere/ga100/dev_boot.h"
enum {
NVIDIA_MMIO_MASK_PMC = 0x00000FFF,
NVIDIA_MMIO_MASK_PBUS = 0x00001FFF,
NVIDIA_MASK_ALL = 0x0000FFFF,
};
struct pmc_id {
uint8_t stepping;
uint8_t device_id;
uint16_t gpu_id;
};
void PMC_ID (uint32_t value,
struct pmc_id *id) {
id->stepping = (value << 0) >> 0;
id->device_id = (value << 0) >> 12;
id->gpu_id = (value << 0) >> 20;
}
void read_temps(int cnum, uint32_t offset) {
uint32_t temp = 0;
while(1) {
temp = nva_rd32(cnum, offset);
temp = (temp & 0x00000fff) / 0x20;
fprintf(stderr, "\rGDDR6 VRAM Temp: %d°c", temp);
fflush(stderr);
sleep(1);
}
}
int main(int argc, char **argv) {
int c;
int i;
int cnum = 0;
int mask = NVIDIA_MASK_ALL;
if (nva_init()) {
fprintf (stderr, "PCI init failure!. Are you r00t?\n");
return 1;
}
while ((c = getopt (argc, argv, "c:")) != -1)
switch (c) {
case 'c':
sscanf(optarg, "%d", &cnum);
break;
default:
break;
}
if (cnum >= nva_cardsnum) {
if (nva_cardsnum)
fprintf (stderr, "No valid card.\n");
else
fprintf (stderr, "No cards found.\n");
return 1;
}
if (mask & NVIDIA_MMIO_MASK_PMC) {
uint32_t pmc_boot_0 = nva_rd32(cnum, NV_PMC_BOOT_0);
struct pmc_id id;
PMC_ID(pmc_boot_0, &id);
switch (id.gpu_id) {
uint32_t offset;
case 0xb72: { // ga102
// TODO: temps over 100 might fail
offset = 0x0000E2A8;
read_temps(cnum, offset);
}
break;
case 0xb74: { // ga104
offset = 0x0000EE50;
read_temps(cnum, offset);
}
break;
default:
fprintf (stderr, "No valid card.\n");
break;
}
}
return 0;
}

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