743 lines
67 KiB
C
743 lines
67 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_nvlphyctl_ip_h__
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#define __ga102_dev_nvlphyctl_ip_h__
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/* This file is autogenerated. Do not edit */
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#define NV_NVLPHYCTL 0x00002DFF:0x00002800 /* RW--D */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0 0x00002b10 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1 0x00002b14 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8 0x00002800 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_ABORT_LEN 11:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_ABORT_LEN_INIT 0x00000376 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_S2T_DIS 12:12 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_S2T_DIS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_T2S_DIS 13:13 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_T2S_DIS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_DELAY 24:14 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_DELAY_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_LEN 31:25 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_LEN_INIT 0x00000054 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_LEN_MINIMUM 0x0000002d /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7 0x00002818 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAREADY 7:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAREADY_INIT 0x00000082 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_DATAREADY 15:8 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_DATAREADY_INIT 0x00000055 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAEN 23:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAEN_INIT 0x00000082 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_SLEEP 31:24 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_SLEEP_INIT 0x00000055 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6 0x0000281c /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6__PRIV_LEVEL_MASK 0x00002b14 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL 0:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN 3:3 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_NOT_COMPLETE 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_COMPLETE 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY 26:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_ZERO 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL 31:27 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL_ZERO 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0 0x00002820 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_IDDQ_DIS 0:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_IDDQ_DIS_SLEEP 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_IDDQ_DIS_WAKE 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_SLEEP_DIS 1:1 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_SLEEP_DIS_SLEEP 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_SLEEP_DIS_WAKE 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_READY 3:3 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_READY_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_READY_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_EN 4:4 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RXCAL_OVERLAP 8:8 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RXCAL_OVERLAP_OFF 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RXCAL_OVERLAP_ON 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_IDDQ_DIS 9:9 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_IDDQ_DIS_SLEEP 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_IDDQ_DIS_WAKE 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_SLEEP_DIS 10:10 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_SLEEP_DIS_SLEEP 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_SLEEP_DIS_WAKE 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_DATA_EN 11:11 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_DATA_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_DATA_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1 0x00002824 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_SETUP 7:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_SETUP_INIT 0x00000013 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_HOLD 15:8 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_HOLD_INIT 0x00000013 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_STROBE_PULSE 23:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_STROBE_PULSE_INIT 0x00000034 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_READ_DELAY 31:24 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_READ_DELAY_INIT 0x00000013 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2 0x00002828 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_IDDQ_SLEEP 7:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_IDDQ_SLEEP_INIT 0x00000055 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_IDDQ 15:8 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_IDDQ_INIT 0x00000015 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_RXCAL 23:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_RXCAL_INIT 0x00000082 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_DATAREADY_SLEEP 31:24 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_DATAREADY_SLEEP_INIT 0x00000055 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3 0x0000282c /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_IDDQ_STEP 7:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_IDDQ_STEP_MINIMUM 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP 15:8 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP_INIT 0x0000003c /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP_MINIMUM 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP_MAXIMUM 0x000000ff /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_STEP 23:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_STEP_INIT 0x00000027 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_STEP_MINIMUM 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_DATAEN 31:24 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_DATAEN_MINIMUM 0x00000055 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4 0x00002830 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP 7:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP_INIT 0x0000003c /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP_MAXIMUM 0x000000ff /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP_MINIMUM 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP 15:8 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP_INIT 0x0000003c /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP_MAXIMUM 0x000000ff /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP_MINIMUM 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_EN_DONE 23:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_EN_DONE_INIT 0x0000003c /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_EN_DONE_MINIMUM 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_5 0x00002834 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_5__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_5_DATAREADY_DATAEN 15:8 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_CFG_CTL_5_DATAREADY_DATAEN_INIT 0x00000055 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0 0x00002838 /* R--4R */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0__PRIV_LEVEL_MASK 0x00002b14 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_IDDQ_DIS_STS 0:0 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_SLEEP_DIS_STS 1:1 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RXCAL_DONE 2:2 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_READY_STS 3:3 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_EN_STS 4:4 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_IDDQ_DIS_STS 5:5 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_SLEEP_DIS_STS 6:6 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_DATA_EN_STS 7:7 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1 0x0000283c /* R--4R */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1__PRIV_LEVEL_MASK 0x00002b14 /* */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L0_BUSY 0:0 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L1_BUSY 1:1 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L2_BUSY 2:2 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L3_BUSY 3:3 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L4_BUSY 4:4 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_RXEQ_DONE 19:16 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_RXCAL_DONE 27:24 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_SPARE(i) (0x00002a80+(i)*0x4) /* RW-4A */
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#define NV_NVLPHYCTL_COMMON_SPARE__SIZE_1 1 /* */
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#define NV_NVLPHYCTL_COMMON_SPARE__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_SPARE_INIT_TRAIN_HW_CLEAR 0:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_SPARE_INIT_TRAIN_HW_CLEAR_ON 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_SPARE_INIT_TRAIN_HW_CLEAR_OFF 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_SPARE_CYA_BUG_2706432 1:1 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_SPARE_CYA_BUG_2706432_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_SPARE_CYA_BUG_2706432_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_SPARE_FIELD 31:2 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_SPARE_FIELD_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_MULTICAST 0x00002b00 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_MULTICAST__PRIV_LEVEL_MASK 0x00002b14 /* */
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#define NV_NVLPHYCTL_COMMON_MULTICAST_LANE_ENABLE 3:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_MULTICAST_LANE_ENABLE_INIT 0x0000000f /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE 17:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_LOW_SELECTED_BUS 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_OR_ALL_BUSSES 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_AND_ALL_BUSSES 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_ZEROS 0x00000003 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0 0x00002b20 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0_DATA 31:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0_DATA_INIT 0x0000baad /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1 0x00002b24 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1__PRIV_LEVEL_MASK 0x00002b14 /* */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1_DATA 31:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1_DATA_INIT 0x0000baad /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM 0x00002b30 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM__PRIV_LEVEL_MASK 0x00002b14 /* */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM_DATA 31:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM_DATA_INIT 0x0000baad /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM 0x00002b34 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM_DATA 31:0 /* RWIVF */
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#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM_DATA_INIT 0x0000baad /* RWI-V */
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#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL 0x00002b80 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE 3:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_32_CLKS 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_64_CLKS 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_128_CLKS 0x00000002 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_256_CLKS 0x00000003 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG 0x00002b84 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TWAIT 15:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TWAIT_INIT 0x0000030d /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TPOLL 31:16 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TPOLL_INIT 0x0000011c /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL 0x00002b88 /* RW-4R */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL_MAX_ATTEMPTS 3:0 /* RWEVF */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL_MAX_ATTEMPTS_INIT 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL_MAX_ATTEMPTS_INFINITE 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS 0x00002b8c /* R--4R */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS__PRIV_LEVEL_MASK 0x00002b10 /* */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_ATTEMPT_COUNT 3:0 /* R-XVF */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_LANESFOUND 11:8 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_LANESFOUND_NONE 0x00000000 /* R---V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_LANESFOUND_ALL 0x0000000f /* R---V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS 29:28 /* R--VF */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_INIT 0x00000000 /* R---V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_SEARCH 0x00000001 /* R---V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_FOUND 0x00000002 /* R---V */
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#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_TIMEOUT 0x00000003 /* R---V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0(i) (0x00002868+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1(i) (0x0000286c+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1(i) (0x00002840+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ 0:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_PWR_UP 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_PWR_DOWN 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_OVRD 1:1 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_TERM_EN 2:2 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_TERM_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_TERM_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_EN 3:3 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_BYP 4:4 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_BYP_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_BYP_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_STATUS 6:6 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_MODE_OVRD 7:7 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_MODE_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_MODE_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_MODE_OVRD 8:8 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_MODE_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_MODE_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_STATUS 15:14 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ 16:16 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_PWR_UP 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_PWR_DOWN 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_OVRD 17:17 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_EN 18:18 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_MODE 19:19 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_MODE_OHM50 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_MODE_OHM10K 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE 21:20 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE_HIGH_FREQ 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE_LOW_FREQ 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE_DC 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_EN 22:22 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_TH 25:24 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_TH_NOMINAL 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_BYP 26:26 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_BYP_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_BYP_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_CFG_RESET 30:30 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_CFG_RESET_OFF 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_CFG_RESET_ON 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_LANE_RESET 31:31 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_LANE_RESET_OFF 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_1_LANE_RESET_ON 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2(i) (0x00002844+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ 0:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_PWR_UP 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_PWR_DOWN 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_OVRD 1:1 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP 5:4 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_PWR_DOWN 0x00000003 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_P2 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_P1 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_PWR_UP 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_READY 6:6 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_READY_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_READY_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_EN 7:7 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ 8:8 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_PWR_UP 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_PWR_DOWN 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_OVRD 9:9 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP 13:12 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_PWR_DOWN 0x00000003 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_P2 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_P1 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_PWR_UP 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_DATA_EN 15:15 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_DATA_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_DATA_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_PWR_OVRD 20:20 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_PWR_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_PWR_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_PWR_OVRD 21:21 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_PWR_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_PWR_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID 26:24 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_OVRD 27:27 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID 30:28 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_OVRD 31:31 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3(i) (0x00002848+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_DATA 1:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_DATA_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_DATA_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_READY 2:2 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_READY_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_READY_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_MODE 4:3 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_MODE_DIFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_MODE_SGL_END 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_OVRD 5:5 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_RATE_ID 8:6 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_RATE_ID_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_DATA 10:9 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE 12:11 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE_DIFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE_SGL_END 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE_PWM_DIFF 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_EN 13:13 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_OVRD 14:14 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC 15:15 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OVRD 16:16 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD 18:17 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_HOLD 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_ECTL 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_HSCTL 0x00000002 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_EOM_STATUS_MASK 19:19 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_EOM_STATUS_MASK_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_EN 20:20 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_EN 21:21 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_OVRD 23:23 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_EN 24:24 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_EN_OFF 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_EN_ON 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_OVRD 27:27 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_LOOP_OFF 28:28 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_LOOP_OFF_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_EN 29:29 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_EN_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_OVRD 30:30 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_OVRD_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_EN 31:31 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4(i) (0x0000284c+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN 0:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_DONE 1:1 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN 4:4 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_DONE 5:5 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_DONE 9:9 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD 12:12 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD 13:13 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD 14:14 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN 15:15 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_STATUS 31:16 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_5(i) (0x00002850+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_5__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_5__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_5_MISC_CTRL 7:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_5_MISC_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_5_MISC_OUT 23:16 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6(i) (0x00002854+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDATA 15:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDATA_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_ADDR 25:16 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_ADDR_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_SECURE 29:29 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_SECURE_INIT 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDS 30:30 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDS_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDS_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_RDS 31:31 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_RDS_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_RDS_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_7(i) (0x00002858+(i)*0x40) /* R--4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_7__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_7__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_7_CFG_RDATA 15:0 /* R--VF */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1(i) (0x00002860+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPOST 5:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPOST_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE1 11:8 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE1_INIT 0x00000004 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE2 18:16 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE2_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_RESERVED 23:23 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_RESERVED_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_AMP 29:24 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_AMP_INIT 0x00000027 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8(i) (0x00002864+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1 /* */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD 0:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN 1:1 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE 27:27 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD 28:28 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD 29:29 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET 30:30 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OFF 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_ON 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET 31:31 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OFF 0x00000000 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_ON 0x00000001 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1(i) (0x00002870+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPOST 5:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPOST_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE1 11:8 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE1_INIT 0x00000004 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE2 18:16 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE2_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_PRECODE_EN 23:23 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_PRECODE_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_PRECODE_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_AMP 29:24 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_AMP_INIT 0x00000027 /* RWE-V */
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#define NV_NVLPHYCTL_LANE_SCRATCH_WARM(i) (0x00002874+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_SCRATCH_WARM__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_SCRATCH_WARM__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1 /* */
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#define NV_NVLPHYCTL_LANE_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_NVLPHYCTL_LANE_SCRATCH_WARM_DATA_INIT 0x0000baad /* RWE-V */
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#define NV_NVLPHYCTL_LANE_SCRATCH_COLD(i) (0x00002878+(i)*0x40) /* RW-4A */
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#define NV_NVLPHYCTL_LANE_SCRATCH_COLD__SIZE_1 5 /* */
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#define NV_NVLPHYCTL_LANE_SCRATCH_COLD__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
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#define NV_NVLPHYCTL_LANE_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_NVLPHYCTL_LANE_SCRATCH_COLD_DATA_INIT 0x0000baad /* RWI-V */
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#endif // __ga102_dev_nvlphyctl_ip_h__
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