12688 lines
1.3 MiB
12688 lines
1.3 MiB
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_ltc_h__
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#define __ga102_dev_ltc_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PLTCG 0x0017ffff:0x00140000 /* RW--D */
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#define NV_PLTCG_LTC0 0x00140000 /* RW--L */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK 0x00140064 /* RWE4R */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cgate" /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_MISC_LTC_NUM_ACTIVE_LTCS 0x00140000 /* RW-4R */
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#define NV_PLTCG_LTC0_MISC_LTC_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_LTC_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_FB_ID 0x00140018 /* R--4R */
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#define NV_PLTCG_LTC0_MISC_FB_ID_VAL 7:0 /* R-XVF */
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#define NV_PLTCG_LTC0_MISC_LTC_PM 0x00140028 /* RW-4R */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_ENABLE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_ENABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT 3:1 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_GRP0 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_GRP1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_GRP2 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_GRP3 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_GRP4 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_GRP5 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_GRP6 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SELECT_STATIC_PATTERN_AA_8_GROUP 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT 6:4 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_2 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_3 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_4 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_5 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_6 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_VC_SELECT_ALL 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SECTOR_COUNT_SELECT 8:7 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SECTOR_COUNT_SELECT_REQUEST 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SECTOR_COUNT_SELECT_MISS 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_PM_SECTOR_COUNT_SELECT_HIT 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG 0x0014002c /* RW-4R */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_NUM_ACTIVE_LTS_PER_LTC 2:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_NUM_ACTIVE_LTS_PER_LTC_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_NUM_ACTIVE_LTS_PER_LTC_MAX 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION 6:4 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION_MIN 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION_MAX 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_LOWER_LTS_PAIR 8:8 /* R-XVF */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_LOWER_LTS_PAIR_DISABLED 0x1 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_LOWER_LTS_PAIR_ENABLED 0x0 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_UPPER_LTS_PAIR 9:9 /* R-XVF */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_UPPER_LTS_PAIR_DISABLED 0x1 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_UPPER_LTS_PAIR_ENABLED 0x0 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_SLICE_DISABLE 13:10 /* R-XVF */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_SLICE_DISABLE_ALL_ENABLED 0x0 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE0_DISABLED 0x1 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE1_DISABLED 0x2 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE2_DISABLED 0x4 /* R---V */
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#define NV_PLTCG_LTC0_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE3_DISABLED 0x8 /* R---V */
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#define NV_PLTCG_LTC0_MISC_CG1 0x00140050 /* RW-4R */
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#define NV_PLTCG_LTC0_MISC_CG1__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_CG1_SLCG 31:1 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_CG1_SLCG_DISABLED 0x7fffffff /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG 0x00140030 /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG1 0x00140034 /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG1__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG 0x00140038 /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_EN 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DIS_EARLY_WUP 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DEEP_ELPG_EN 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_ELPG_EN 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DIDT_DELAY 23:20 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_DIDT_DELAY_HWINIT 0xa /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_RESET_DURATION 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_RESET_DURATION_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_CLAMP_DELAY 29:27 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_CLAMP_DELAY_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_ZONE_OFF_MASK 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_SOFT_GATING_EN 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG1 0x0014003c /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG1__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG1_ZONE_SEQ 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG1_ZONE_MASK 31:24 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_DCMP_PRI_DCMP_PG1_ZONE_MASK_HWINIT 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG 0x00140040 /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG1 0x00140044 /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG1__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG 0x00140048 /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_BLPG_EN 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DIS_EARLY_WUP 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DEEP_ELPG_EN 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_ELPG_EN 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DIDT_DELAY 23:20 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_DIDT_DELAY_HWINIT 0xa /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_RESET_DURATION 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_RESET_DURATION_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_CLAMP_DELAY 29:27 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_CLAMP_DELAY_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_ZONE_OFF_MASK 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_SOFT_GATING_EN 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG1 0x0014004c /* RWI4R */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG1__PRIV_LEVEL_MASK 0x00140064 /* */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG1_ZONE_SEQ 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWI-V */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG1_ZONE_MASK 31:24 /* RWIVF */
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#define NV_PLTCG_LTC0_MISC_PRI_LTC_PG1_ZONE_MASK_HWINIT 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0 0x00140400 /* RW--L */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK 0x00140418 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_iq" /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK 0x001405a8 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cbc" /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK 0x001405d8 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_vpr_leakage" /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK 0x001405d4 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_dstg" /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK 0x001405c4 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya_ecc" /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK 0x00140590 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK 0x001405c0 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya" /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK 0x001405d0 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_tstg" /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK 0x001405bc /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK 0x00140584 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK 0x001405dc /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cgate" /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK 0x00140594 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK 0x00140598 /* RWE4R */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya_coh" /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTS0_CYA_COH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL 0x001404e4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL__PRIV_LEVEL_MASK 0x001405d8 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_MIN 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_MAX 0x001c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_CONFIG 0x0000 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TRIGGER_CTL 0x0001 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_1 0x0002 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_2 0x0003 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_3 0x0004 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_4 0x0005 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_MASK_LO 0x0006 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_MASK_HI 0x0007 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_VAL_LO 0x0008 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_VAL_HI 0x0009 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_1 0x000a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_2 0x000b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_3 0x000c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_4 0x000d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_MASK_LO 0x000e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_MASK_HI 0x000f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_VAL_LO 0x0010 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_VAL_HI 0x0011 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_DIN_TRIGGER_CTL 0x0012 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_DOUT_TRIGGER_CTL 0x0013 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_DATA_TRIGGER_VAL_LO 0x0014 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_DATA_TRIGGER_VAL_HI 0x0015 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_DIN_SAMPLE_CTL 0x0016 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_DOUT_SAMPLE_CTL 0x0017 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_CTL 0x0018 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_BUFFER_DEPTH 0x0019 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_STATUS 0x001a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_STATUS_2 0x001b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILA_BUFFER_READ 0x001c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_CBC_DEBUG 0x0100 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_TG_DEBUG 0x0101 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE1_INFO0 0x0102 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE1_INFO1 0x0103 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE2_INFO0 0x0104 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE2_INFO1 0x0105 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_READINCR 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_READINCR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_READINCR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_WRITEINCR 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_WRITEINCR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_CTRL_WRITEINCR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE 0x001404e8 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE__PRIV_LEVEL_MASK 0x001405d8 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_VAL 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_ILA 1:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_USECBC_PARTIAL 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_USECBC_FULL 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_TRIGGER_ONLY 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE 5:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_A 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_C 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TSTAMP_TRIG_BIT 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TSTAMP_TRIG_BIT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC 15:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_ZERO 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_12_5 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_25_0 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_37_5 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_50_0 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_62_5 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_75_0 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_87_5 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_EV_CNT 31:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_EV_CNT_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK 15:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_ALL_ENABLE 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK 30:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_ALL_ENABLE 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_RESERVED 31:31 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_RESERVED_VAL 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_ID 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK_EXACT 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_ID 22:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK 30:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK_EXACT 0x7f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE_INCLUSIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE_EXCLUSIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MASK 31:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MASK_ALL_ADDRESSES 0x0000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_HI_MASK 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_HI_MASK_ALL_ADDRESSES 0x000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_VAL_LO_PADR 31:7 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_VAL_HI_PADR 23:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK 15:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_ALL_ENABLE 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK 30:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_ALL_ENABLE 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_ID 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK_EXACT 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_ID 22:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK 30:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK_EXACT 0x7f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE_INCLUSIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE_EXCLUSIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MASK 31:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MASK_ALL_ADDRESSES 0x0000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_HI_MASK 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_HI_MASK_ALL_ADDRESSES 0x000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_VAL_LO_PADR 31:7 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_VAL_HI_PADR 23:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_BYTE_MASK 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_BYTE_MASK_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_QWORD_SEL 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_QWORD_SEL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_SPKT_MASK 25:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_SPKT_MASK_ALL_ENABLE 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_BYTE_MASK 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_BYTE_MASK_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_QWORD_SEL 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_QWORD_SEL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_SPKT_MASK 23:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_SPKT_MASK_ALL_ENABLE 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DATA_TRIGGER_VAL_LO_DATA 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DATA_TRIGGER_VAL_HI_DATA 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_DATA_SEL 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_DATA_SEL_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SPKT_MASK 17:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SPKT_MASK_ALL_ENABLE 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_DATA_SEL 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_DATA_SEL_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SPKT_MASK 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SPKT_MASK_ALL_ENABLE 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE_TRIGGER 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE_PMON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_CNT 15:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_CNT_INIT 0x0000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE 31:31 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE_128BIT 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE_256BIT 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INDEX 11:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED 14:14 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE 15:15 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_LAST_INDEX 27:16 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_LAST_INDEX_INIT 0x000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY 30:30 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY_FALSE 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY_TRUE 0x1 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED 31:31 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON 5:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG 0:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN 1:1 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT 2:2 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP 3:3 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON 4:4 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL 5:5 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_BUFFER_READ 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_CBC_DEBUG 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_TG_DEBUG 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE1_INFO0 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE1_INFO1 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE2_INFO0 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE2_INFO1 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL 0x001404ec /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL__PRIV_LEVEL_MASK 0x00140590 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS 0x001404f0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_RESET 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_RESET_TASK 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_STATUS_RESET_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CORRECTED_ERR_COUNT 0x001404f4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001404f8 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS 0x001404fc /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_INDEX 31:0 /* R-XVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_LOCATION 21:0 /* R-XVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM 29:22 /* R-XVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM0 0x00 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM2 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM3 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO0 0x00 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM0 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM1 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM2 0x04 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM3 0x05 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM4 0x06 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM5 0x07 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM6 0x08 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM7 0x09 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM0 0x0a /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM1 0x0b /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM2 0x0c /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM3 0x0d /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM4 0x0e /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM5 0x0f /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM6 0x10 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM7 0x11 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM0 0x12 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM1 0x13 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM2 0x14 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM3 0x15 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM4 0x16 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM5 0x17 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM6 0x18 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM7 0x19 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRA_RAM 0x1a /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_LRU_RAM 0x1b /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM 0x1c /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM 0x1d /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_COPY_RAM 0x1e /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_STATE 0x1f /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_PAIR 0x20 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_INFO 0x21 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_RAM 0x22 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_LRU_RAM 0x23 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO2 0x24 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_LCN_COMP_STAT 0x25 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS 0x26 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM0 0x00 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM2 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM3 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM4 0x04 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM5 0x05 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM6 0x06 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM7 0x07 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK0 0x08 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK1 0x09 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK2 0x0a /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK3 0x0b /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_SUBUNIT 31:30 /* R-XVF */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_SUBUNIT_RSTG 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_SUBUNIT_TSTG 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_SUBUNIT_DSTG 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_SUBUNIT_CLIENT_POISON_RETURNED 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM0_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM1_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM2_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM3_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO0_ROW 8:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO1_ROW 8:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRA_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_LRU_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM_SLICE 3:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM_ROW 11:4 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM_SLICE 3:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM_ROW 11:4 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_LRU_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO2_ROW 8:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_LCN_COMP_STAT_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS_SLICE 3:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS_ROW 11:4 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK0_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK1_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK2_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTS0_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK3_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CST_RDI_INDEX 0x00140400 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CST_RDI_INDEX_ADDRESS 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CST_RDI_INDEX_ADDRESS_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CST_RDI_INDEX_ADDRESS_MAX 0xffff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CST_RDI_DATA(i) (0x001405ac+(i)*4) /* R--4A */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CST_RDI_DATA__SIZE_1 4 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CST_RDI_DATA_FIELD 31:0 /* R-XVF */
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#define NV_PLTCG_LTC0_LTS0_INTR 0x0014040c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_IQ 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_IQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_IQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_IQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_CBC 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_CBC_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_CBC_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_CBC_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_TSTG 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_TSTG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_TSTG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_TSTG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_DSTG 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_DSTG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_DSTG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_IDLE_ERROR_DSTG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_EVICTED_CB 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EVICTED_CB_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EVICTED_CB_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EVICTED_CB_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLOCKLINEAR_CB 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLOCKLINEAR_CB_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLOCKLINEAR_CB_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLOCKLINEAR_CB_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_SEC_ERROR 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_SEC_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_SEC_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_SEC_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_DED_ERROR 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_DED_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_DED_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ECC_DED_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_DEBUG 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_DEBUG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_DEBUG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_DEBUG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_ATOMIC_TO_Z 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_ATOMIC_TO_Z_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ATOMIC_TO_Z_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ATOMIC_TO_Z_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_ATOMIC 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_ATOMIC_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_ATOMIC_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_ATOMIC_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLKACTIVITY_ERR 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLKACTIVITY_ERR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLKACTIVITY_ERR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_BLKACTIVITY_ERR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT_ACCESS 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT_ACCESS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT_ACCESS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR_ILLEGAL_COMPSTAT_ACCESS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_IQ 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_IQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_IQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_CBC 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_CBC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_CBC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_TSTG 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_TSTG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_TSTG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_DSTG 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_DSTG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_IDLE_ERROR_DSTG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_EVICTED_CB 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_EVICTED_CB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_EVICTED_CB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_COMPSTAT 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_COMPSTAT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_COMPSTAT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_BLOCKLINEAR_CB 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_BLOCKLINEAR_CB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_BLOCKLINEAR_CB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ECC_SEC_ERROR 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ECC_SEC_ERROR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ECC_SEC_ERROR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ECC_DED_ERROR 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ECC_DED_ERROR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ECC_DED_ERROR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_DEBUG 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_DEBUG_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_DEBUG_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ATOMIC_TO_Z 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ATOMIC_TO_Z_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ATOMIC_TO_Z_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_ATOMIC 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_ATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_ATOMIC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_BLKACTIVITY_ERR 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_BLKACTIVITY_ERR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_BLKACTIVITY_ERR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_COMPSTAT_ACCESS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2 0x00140408 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_INVALID_TDTAG 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_INVALID_TDTAG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_INVALID_TDTAG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_INVALID_TDTAG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_TRDONE 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_TRDONE_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_TRDONE_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_TRDONE_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_INVALID_SUBID 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_PRBRS 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIN_UNEXPECTED_PRBRS 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIN_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIN_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIN_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIMO_UNEXPECTED_PRBRS 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIMO_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIMO_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBIMO_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_MISSING_DATA 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_MISSING_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_MISSING_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_MISSING_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_UNEXPECTED_DATA 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_UNEXPECTED_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_UNEXPECTED_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBX_UNEXPECTED_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_UNEXPECTED_PA7 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_UNEXPECTED_PA7_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_UNEXPECTED_PA7_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_PRBRS_UNEXPECTED_PA7_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_UNEXPECTED_PA7 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_UNEXPECTED_PA7_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_UNEXPECTED_PA7_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_TRDONE_UNEXPECTED_PA7_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_SYSFILL_BYPASS_INVALID_SUBID 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_SYSFILL_BYPASS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_SYSFILL_BYPASS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_SYSFILL_BYPASS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_SYSFILL_BYPASS 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_SYSFILL_BYPASS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_SYSFILL_BYPASS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_UNEXPECTED_SYSFILL_BYPASS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_PRBRS 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_TRDONE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_TRDONE_INVALID_TDTAG 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_TRDONE_INVALID_TDTAG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_TRDONE_INVALID_TDTAG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_TRDONE 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_TRDONE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_TRDONE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBRS_INVALID_SUBID 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBRS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBRS_INVALID_SUBID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_PRBRS 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBIN_UNEXPECTED_PRBRS 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBIN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBIN_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBX_MISSING_DATA 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBX_MISSING_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBX_MISSING_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBX_UNEXPECTED_DATA 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBX_UNEXPECTED_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBX_UNEXPECTED_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBRS_UNEXPECTED_PA7 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBRS_UNEXPECTED_PA7_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_PRBRS_UNEXPECTED_PA7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_TRDONE_UNEXPECTED_PA7 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_TRDONE_UNEXPECTED_PA7_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_TRDONE_UNEXPECTED_PA7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3 0x00140588 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_NINB_NCNP_REQ 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_NINB_NCNP_REQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_NINB_NCNP_REQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_NINB_NCNP_REQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_CREQ_NCNP_REQ 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_RMWRS_INVALID_SUBID 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_RMWRS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_RMWRS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_RMWRS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_UNEXPECTED_RMWRS 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_UNEXPECTED_RMWRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_UNEXPECTED_RMWRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_UNEXPECTED_RMWRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ECC_CORRECTED 7:7 /* R-XVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ECC_CORRECTED_NOT_PENDING 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ECC_CORRECTED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ECC_UNCORRECTED 8:8 /* R-XVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ECC_UNCORRECTED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_VOLATILE_TO_COMPRESSED 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_VOLATILE_TO_COMPRESSED_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_VOLATILE_TO_COMPRESSED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_VOLATILE_TO_COMPRESSED_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE1 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE2 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_KIND_INVALID 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_KIND_INVALID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_KIND_INVALID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_KIND_INVALID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_COMPTAG_INVALID 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_COMPTAG_INVALID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_COMPTAG_INVALID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_DTM_COMPTAG_INVALID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CDCMP_IP_ERROR 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CDCMP_IP_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CDCMP_IP_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_CDCMP_IP_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_RMWRS_INVALID_SUBID 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_RMWRS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_RMWRS_INVALID_SUBID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_UNEXPECTED_RMWRS 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_UNEXPECTED_RMWRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_UNEXPECTED_RMWRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_VOLATILE_TO_COMPRESSED 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_VOLATILE_TO_COMPRESSED_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_VOLATILE_TO_COMPRESSED_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_DTM_KIND_INVALID 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_DTM_KIND_INVALID_ENABLED 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_DTM_KIND_INVALID_DISABLED 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_DTM_COMPTAG_INVALID 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_DTM_COMPTAG_INVALID_ENABLED 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_DTM_COMPTAG_INVALID_DISABLED 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CDCMP_IP_ERROR 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CDCMP_IP_ERROR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_INTR3_EN_CDCMP_IP_ERROR_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS 0x00140410 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_LTC_STOP 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_LTC_STOP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_LTC_STOP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_RSTG_BUSY 8:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_TSTG_BUSY 9:9 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_DSTG_BUSY 10:10 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_A_BUSY 11:11 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_WAITING_FOR_XBAR_CMD_CREDITS 20:20 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_WAITING_FOR_XBAR_DATA_CREDITS 21:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_STATUS_WAITING_FOR_SYSMEM_FILL_DATA 22:22 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG 0x00140414 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_FLUSH 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_FLUSH_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_FLUSH_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_FLUSH_ABORT 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_FLUSH_ABORT_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_FLUSH_ABORT_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_STATUS_CBC_NOT_READY 8:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_ELPG_STATUS_TSTG_NOT_READY 9:9 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0 0x0014041c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0__PRIV_LEVEL_MASK 0x001405c4 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_ECC_MISS_MASK 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_EVICT_NORMAL 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_EVICT_NORMAL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_EVICT_NORMAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_EVICT_NORMAL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_TO_GENERIC 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_TO_GENERIC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_TO_GENERIC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_TO_GENERIC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_COMPRESSIBLE 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_COMPRESSIBLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_COMPRESSIBLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_REMAP_COMPRESSIBLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_STATUS_SELECT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_STATUS_SELECT_INIT 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_STATUS_SELECT_DISABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_CREQ_RD_NCP 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_CREQ_RD_NCP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_CREQ_RD_NCP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_FORCE_CREQ_RD_NCP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_SPARE 31:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_SPARE_UCREQ_LIVELOCK_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_CFG_0_SPARE_UCREQ_LIVELOCK_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_XBAR_STATUS_0 0x00140420 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_XBAR_STATUS_0_VALUE 31:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_XBAR_STATUS_0_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0 0x0014043c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0__PRIV_LEVEL_MASK 0x00140418 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_ISO_WEIGHT 2:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_ISO_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_NISO_NB_WEIGHT 6:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_NISO_NB_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_PLC_WEIGHT 10:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_PLC_WEIGHT_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_PLC_PRIORITY 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_PLC_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_PLC_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_PLC_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_NB_WEIGHT 14:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_NB_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_B_WEIGHT 18:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_B_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_RESP_WEIGHT 22:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_RESP_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_RESP_PRIORITY 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_RESP_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_RESP_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_RESP_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_CREQ_WEIGHT 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_WRR_CREQ_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_LL 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_LL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_RESP 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_RESP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_RESP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_RESP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_CREQ 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1 0x00140440 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1__PRIV_LEVEL_MASK 0x00140418 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1_WRR_LL_WEIGHT 6:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1_WRR_LL_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1_LL_PRIORITY 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1_LL_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1_LL_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_1_LL_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3 0x00140444 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3__PRIV_LEVEL_MASK 0x00140418 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG_INIT 0xa /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG 10:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG_MAX 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG 14:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG_MAX 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_ISO_NACK_CTRL 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_RECIRCULATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_RECIRCULATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_RECIRCULATE_AFTER_DRAINING_PENDING 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_RECIRCULATE_IMMEDIATELY 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ISO 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ISO_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ISO_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ISO_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NB 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NB_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_B 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_B_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_B_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_B_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_SPARE_25 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_SPARE_25_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG 31:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_MIN 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0 0x00140448 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0__PRIV_LEVEL_MASK 0x00140418 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_LL 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_LL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_B 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_B_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_B_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_B_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NB 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NISO_NB 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_RESP 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_RESP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_RESP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_RESP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_CREQ 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_CREQ_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_CREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_ARB_VERIF_0_THROTTLE_CREQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0 0x00140460 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_MODE_TIMEOUT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_MODE_TIMEOUT_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_BALANCE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_FNIC2LTC_FILL 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_LTC2FNIC_REQ 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_TIMEOUT 27:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_BALANCE_TIMEOUT_INIT 0xf80 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_REQUEST_BASED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_SUBPACKET_BASED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0 0x00140464 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_ECO_CYA 2:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_ECO_CYA_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_PLC_128B_OPTIMIZATION 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_PLC_128B_OPTIMIZATION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_PLC_128B_OPTIMIZATION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_PLC_128B_OPTIMIZATION__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS 10:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_UNLIMITED 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0 0x00140468 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_THRESHOLD 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_THRESHOLD_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_THRESHOLD_MAX 0x36 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_UNALLOC_VC_INTERLOCK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_UNALLOC_VC_INTERLOCK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_UNALLOC_VC_INTERLOCK_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_MIN_LIMIT 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_MIN_LIMIT_INIT 0x6 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_NUM_ACTIVE_LINES 19:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_NUM_ACTIVE_LINES_INIT 0x40 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_NUM_ACTIVE_LINES_ALL 0x40 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1 0x0014046c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_CLEAN_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_CLEAN_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_INVALIDATE 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_INVALIDATE_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_INVALIDATE_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_CLEAR 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_CLEAR_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_CLEAR_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_DISABLE_INVALIDATE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_DISABLE_INVALIDATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_DISABLE_INVALIDATE_ACTIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_DISABLE_INVALIDATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_DISABLE_INVALIDATE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_1_DISABLE_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_2 0x00140470 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_2_CLEAR_LOWER_BOUND 19:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_2_CLEAR_LOWER_BOUND_INIT 0x00000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_3 0x00140474 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_3_CLEAR_UPPER_BOUND 19:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0xfffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_BASE 0x00140478 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_BASE__PRIV_LEVEL_MASK 0x001405a8 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ALIGNMENT_SHIFT 0x0000000b /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_BASE_ADDRESS 25:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_BASE_HUB_SAFE 31:31 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS 0x0014047c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK 0x00140594 /* */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_SERIALIZE 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_SERIALIZE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_SERIALIZE_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_SERIALIZE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM 0x00140480 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE 9:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_4 0x004 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_5 0x005 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_6 0x006 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_7 0x007 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_8 0x008 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_10 0x00a /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_11 0x00b /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_12 0x00c /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_13 0x00d /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_14 0x00e /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_16 0x010 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_20 0x014 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_22 0x016 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_24 0x018 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_26 0x01a /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_28 0x01c /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_32 0x020 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_44 0x02c /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_64 0x040 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_128 0x080 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_DIVIDE_ROUNDING 11:10 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_DIVIDE_ROUNDING_2K 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_DIVIDE_ROUNDING_4K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_DIVIDE_ROUNDING_8K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_DIVIDE_ROUNDING_16K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_SWIZZLE_ROUNDING 13:12 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_64K 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_128K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_256K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_512K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_NUM_CACHE_LINES 23:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_NUM_CACHE_LINES_16 0x10 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_NUM_CACHE_LINES_20 0x14 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_NUM_CACHE_LINES_32 0x20 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_NUM_CACHE_LINES_40 0x28 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_NUM_CACHE_LINES_64 0x40 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE 27:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_512 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_1K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_2K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_4K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_8K 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_16K 0x5 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_32K 0x6 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_CACHE_LINE_SIZE_64K 0x7 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_SLICES_PER_LTC 31:28 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_SLICES_PER_LTC_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_SLICES_PER_LTC_2 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_SLICES_PER_LTC_3 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM_SLICES_PER_LTC_4 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CLEAR_GOB_VALUE 0x001405a4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_CLEAR_GOB_VALUE_COMPBITS 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CBC_CLEAR_GOB_VALUE_COMPBITS_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CBC_CLEAR_GOB_VALUE_COMPBITS_UNCOMPRESSED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS 0x0014048c /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_FILL_CMD_STATE 2:1 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_CLEAN_CMD_STATE 5:3 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_EVICT_DATA_STATE 7:6 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_CLEAR_CMD_STATE 11:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_NUM_WRITEBUFF_REQ 15:12 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_PIPE_VLD 16:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_WRITEBUFF_COMMIT_VLD 17:17 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_AVAIL_LRU_TAG_VLD 18:18 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_AVAIL_DIRTY_TAG_VLD 19:19 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_FILL_PEND 20:20 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_CLEAN_PEND 21:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_STATUS_DIRTY_PEND 22:22 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0 0x00140490 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0__PRIV_LEVEL_MASK 0x001405d0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK_TO_CROP 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK_STALL 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_CROP_RDWR 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_CROP_RDWR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_CROP_RDWR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_ZROP_RDWR 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_ZROP_RDWR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_ZROP_RDWR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_NISO_NB_WR 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_NISO_NB_WR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_NISO_NB_WR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_HOLD_INUSE 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_HOLD_INUSE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_HOLD_INUSE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_FORCE_LDST_TO_ATM 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_FORCE_LDST_TO_ATM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_FORCE_LDST_TO_ATM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_TEST_WITHOUT_FB 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_TEST_WITHOUT_FB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_TEST_WITHOUT_FB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_VOLATILE_READ 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_VOLATILE_READ_PER_SECTOR 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_VOLATILE_READ_PER_LINE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_VOLATILE_PART_CLR_FULL 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_VOLATILE_PART_CLR_FULL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_RMW 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_RMW_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_RMW_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_ISO_RD 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_ISO_RD_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_INTERLOCK_ISO_RD_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_SAME_SET 20:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_SAME_SET_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_SAME_SET_ONE_CYCLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_SAME_SET_TWO_CYCLES 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_SAME_SET_ONE_AND_TWO_CYCLES 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_ISO_WITHOUT_ICC 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_ISO_WITHOUT_ICC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_ISO_WITHOUT_ICC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_SPARE 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_SPARE_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_L2_ECC_FILL_ON_WR 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_L2_ECC_FILL_ON_WR_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_0_L2_ECC_FILL_ON_WR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4 0x00140534 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4__PRIV_LEVEL_MASK 0x00140584 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_VOL_BYPASS_GATOM 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_VOL_BYPASS_GATOM_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_VOL_BYPASS_GATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FORCE_ISO_MISS 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FORCE_ISO_MISS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FORCE_ISO_MISS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_RD_CACHING 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_RD_CACHING_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_RD_CACHING_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_WR_CACHING 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_WR_CACHING_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_WR_CACHING_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_VOLBYPASS 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_VOLBYPASS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_VOLBYPASS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FAIL_GC_COND_RD 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FAIL_GC_COND_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FAIL_GC_COND_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_LC_PROMOTION 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_LC_PROMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_LC_PROMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_PREFETCH 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_PREFETCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_PREFETCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_256B_PROMOTE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_256B_PROMOTE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_256B_PROMOTE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_ISO_CBC_RD 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_ISO_CBC_RD_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SAME_SET_ISO_CBC_RD_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_CMGMT_PLC_INVALID 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_CMGMT_PLC_INVALID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_CMGMT_PLC_INVALID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_CMGMT_PLC_INFLIGHT 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_CMGMT_PLC_INFLIGHT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_CMGMT_PLC_INFLIGHT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_GMK_COLOR_128B_RMW 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_GMK_COLOR_128B_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_GMK_COLOR_128B_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SEND_CR_ON_MISS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SEND_CR_ON_MISS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_SEND_CR_ON_MISS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_NISO_NB_TO_VC_LL 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_NISO_NB_TO_VC_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_NISO_NB_TO_VC_LL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FAIL_GMK_COND_RD 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FAIL_GMK_COND_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_4_FAIL_GMK_COND_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5 0x00140504 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5__PRIV_LEVEL_MASK 0x001405a8 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_ROP_DATA 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_ROP_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_ROP_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_RAST_DATA 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_RAST_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_RAST_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_PE_DATA 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_PE_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_PE_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_SCC_DATA 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_SCC_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_SCC_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_TEX_DATA 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_TEX_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_TEX_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_TEX_ALL_DATA 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_TEX_ALL_DATA_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_TEX_ALL_DATA_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_TEX_ALL_DATA__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_ALL_DATA 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_ALL_DATA_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_ALL_DATA_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_COMPRESSED_DATA 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_COMPRESSED_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_5_DISCARD_COMPRESSED_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1 0x00140494 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS_INIT 0xffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS_GF100_1 0x0001 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_WAYS_GF100_ALL 0xffff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_HALF 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_SETS_QUARTER 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES 22:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_7_8TH 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_6_8TH 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_5_8TH 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_4_8TH 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_3_8TH 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_2_8TH 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_1_8TH 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD 27:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_MIN 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_1 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_2 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_4 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_8 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_16 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_32 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_64 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_128 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_256 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_MAX 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ECC_HUB_RMW_DISABLE 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ECC_HUB_RMW_DISABLE_CE_ONLY 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_ECC_HUB_RMW_DISABLE_ALL 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_CACHE_HUB_WEAK_VOL 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_CACHE_HUB_WEAK_VOL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_1_CACHE_HUB_WEAK_VOL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2 0x00140498 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ALL_PROMOTE 1:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_HUB_PROMOTE 3:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CE_PROMOTE 5:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_FE_PROMOTE 7:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_FE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_FE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_FE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PD_PROMOTE 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PD_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PD_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PD_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CTX_PROMOTE 11:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SCC_PROMOTE 13:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE 15:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_ON_128B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_ON_SECT0 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L1_PROMOTE 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_T1_PROMOTE 19:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_T1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_T1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_T1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PE_PROMOTE 21:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_PE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_RAST_PROMOTE 23:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ROP_PROMOTE 25:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GCC_PROMOTE 27:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE 29:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_ON_128B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_ON_SECT0 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3 0x0014049c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ALL_PROMOTE 1:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_HUB_PROMOTE 3:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CE_PROMOTE 5:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_FE_PROMOTE 7:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_FE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_FE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_FE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PD_PROMOTE 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PD_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PD_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PD_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CTX_PROMOTE 11:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_SCC_PROMOTE 13:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PROMOTE 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PROMOTE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PROMOTE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_L1_PROMOTE 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_L1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_L1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_L1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_T1_PROMOTE 19:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_T1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_T1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_T1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PE_PROMOTE 21:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_PE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_RAST_PROMOTE 23:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ROP_PROMOTE 25:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GCC_PROMOTE 27:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE 29:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_FETCH_PARTIAL_CATOM 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_FETCH_PARTIAL_CATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_FETCH_PARTIAL_CATOM_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CFG_3_FETCH_PARTIAL_CATOM_32B 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0 0x001404a0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0__PRIV_LEVEL_MASK 0x001405bc /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_DISABLE_INVALIDATE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_DISABLE_INVALIDATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_DISABLE_INVALIDATE_ACTIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_DISABLE_INVALIDATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_DISABLE_INVALIDATE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_0_DISABLE_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1 0x001404a4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1__PRIV_LEVEL_MASK 0x001405bc /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS 0x001404a8 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_DIRTY 1:1 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_INUSE 2:2 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_FULL 3:3 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_ISO_RDAT_CREDIT_IDLE 4:4 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_WRCOUNT_IDLE 5:5 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_ISO_LOCKED_WITHOUT_ICC 6:6 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_ACTIVE_ATOM 7:7 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_PENDING_FB_MISS_REQ 16:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_STALLED_ON_CLEAN_IF 17:17 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_STALLED_ON_READ_IF 18:18 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_STALLED_ON_ICC 19:19 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_STATUS_CACHELINES_PINNED 24:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0 0x001404ac /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0__PRIV_LEVEL_MASK 0x001405bc /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_RD_PINNED 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_RD_PINNED_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_SYSMEM_RD_PINNED 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_SYSMEM_RD_PINNED_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST_INIT 0x03 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_ATOMIC 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_0_MAX_WAYS_ATOMIC_INIT 0x0b /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1 0x0014059c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1__PRIV_LEVEL_MASK 0x001405bc /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_MAX_WAYS_EVICT_FIRST 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_MAX_WAYS_EVICT_FIRST_INIT 0x10 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_MIN_WAYS_EVICT_NORMAL_DIRTY 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_MIN_WAYS_EVICT_NORMAL_DIRTY_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_DISABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_DISABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_DISABLE_NORMAL 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_THRESHOLD 22:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_THRESHOLD_DISABLED 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_THRESHOLD_0 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_THRESHOLD_INIT 0x05 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_MAX_WAYS_PROBING 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_MAX_WAYS_PROBING_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_ATOMIC_COH_RMW 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_ATOMIC_COH_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_ATOMIC_COH_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2 0x001404b0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2__PRIV_LEVEL_MASK 0x001405d0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_INIT 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_ONE 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_INIT 0x0e /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_ONE 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_COMPR_WR_INVAL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_COMPR_WR_INVAL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_COMPR_WR_INVAL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_COMPR_WR_INVAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_BYPASS_MODE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_BYPASS_MODE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_BYPASS_MODE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3 0x001404b4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3__PRIV_LEVEL_MASK 0x001405d0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_WRITE_THRESHOLD_STOP 9:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_WRITE_THRESHOLD_STOP_INIT 0x030 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES 13:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_7_8TH 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_6_8TH 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_5_8TH 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_4_8TH 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_3_8TH 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_2_8TH 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_1_8TH 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES 15:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_NONE 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_2_3RD 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_1_3RD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_SYSMEM_WB_THRESHOLD 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_SYSMEM_WB_THRESHOLD_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4 0x001404b8 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD_INIT 0x02 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD 9:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD_INIT 0x04 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK_STRICT 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL_FULL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL_FULL_NON_READ 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS 15:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_25PCT 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_50PCT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_75PCT 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_100PCT 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE 19:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_0PCT 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_25PCT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_50PCT 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_100PCT 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT 22:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_ANY 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_ALLOCATION 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_NON_EF_ALLOCATION 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_VERIF 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD 26:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_MIN 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_4_BG_DEMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5 0x001404bc /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5__PRIV_LEVEL_MASK 0x001405bc /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_TIER1_CLEAN_THRESHOLD 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_TIER1_CLEAN_THRESHOLD_INIT 0x07 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_TIER2_CLEAN_THRESHOLD 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_TIER2_CLEAN_THRESHOLD_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST 20:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST_INIT 0x0d /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST_FOR_COMPUTE 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD1 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD2 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD3 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC 29:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD1 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD2 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD3 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE 0x001404c0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_BUCKET_SIZE_INIT 0x020 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_LEAK_COUNT_DISABLE 0x000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_LEAK_SIZE_32B 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_LEAK_SIZE_64B 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_LEAK_SIZE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_THROTTLE_LEAK_SIZE_256B 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0 0x001404c4 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_STATE 10:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_STATE_IDLE 0x000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_WRITE 13:12 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_WRITE_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_WRITE_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_WRITE_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_WRITE_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_HIT 15:14 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_HIT_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_HIT_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_HIT_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_HIT_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_SYSRD 17:16 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_SYSRD_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_SYSRD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_SYSRD_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_IMM_SYSRD_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ISO 19:18 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ISO_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ISO_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ISO_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ISO_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ELSE 21:20 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ELSE_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ELSE_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ELSE_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_ELSE_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_SYSRD 23:22 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_SYSRD_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_SYSRD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_SYSRD_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_0_MISS_SYSRD_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1 0x001404c8 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM 1:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM 3:2 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_ELSE_B 5:4 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_ELSE_B_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_ELSE_B_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_ELSE_B_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_ELSE_B_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW 9:8 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBI 11:10 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBI_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBI_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBI_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBI_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBX 13:12 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBX_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBX_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBX_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_PRBX_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_RS 15:14 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_RS_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_RS_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_RS_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_RMW_RS_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_LL 17:16 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_LL_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_LL_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_LL_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_STATUS_1_MISS_LL_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL 0x001404cc /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_MIN_LIMIT 5:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_MIN_LIMIT_INIT 0x05 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_ARB_SPARE 7:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_ARB_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_LIMIT_HIT 14:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_LIMIT_HIT_INIT 0x10 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_LIMIT_ALL_WRS 22:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_LIMIT_ALL_WRS_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_LIMIT_SYSRD 30:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_IMMREQ_CTRL_LIMIT_SYSRD_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0 0x001404d0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS 8:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS_INIT 0x010 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS_MIN 0x008 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB_SEPARATELY 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB_WITH_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO 18:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO_INIT 0x060 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO_MIN 0x008 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW_SEPARATELY 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW_WITH_EE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE 29:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE_INIT 0x040 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE_MIN 0x010 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE_WITH_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE_WITH_HUB 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST_AS_NEEDED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST_CONTINUOUSLY 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1 0x001404d4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED 9:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_MIN 0x010 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_CTRL_DISABLED 0x3ff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SYSMEM_HUB 18:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SYSMEM_HUB_INIT 0x000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT_THROUGH_MISS 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT_THROUGH_HIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED 21:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED 23:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW 29:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW_INIT 0x02 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_0 0x001404d8 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_0_MISS_FIFO_DEPTH 10:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_0_NUM_AWPS 20:11 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_0_ISO_RDAT_FIFO_DEPTH 31:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_1 0x0014058c /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_1_SLICE_SIZE_IN_KB 15:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_1_SLICES_PER_L2 20:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_1_SLICES_PER_L2_1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_1_SLICES_PER_L2_2 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_1_SLICES_PER_L2_3 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_INFO_1_SLICES_PER_L2_4 0x04 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN 0x001404dc /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_TIMEOUT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_TIMEOUT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_TIMEOUT_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_TIMEOUT_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_TIMEOUT_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_ECC_SCRUB_0 0x0014050c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_ECC_SCRUB_0_XBAR_RAW_PADR 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_ECC_SCRUB_0_XBAR_RAW_PADR_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_ECC_SCRUB_1 0x00140510 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_ECC_SCRUB_1_WRITE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_ECC_SCRUB_1_WRITE_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_ECC_SCRUB_1_WRITE_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY 0x00140514 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MASTER 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MASTER_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MASTER_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_READ_THLD 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_READ_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_READ_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_INUSE_THLD 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_INUSE_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_INUSE_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ATOMIC_THLD 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ATOMIC_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ATOMIC_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_AWP_THLD 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_AWP_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_AWP_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM2INUSE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_RMW2INUSE 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_RMW2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_RMW2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_FB_READ_CREDIT 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_FB_READ_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_FB_READ_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_FULL 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_FULL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_FULL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_INTERLOCK 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_INTERLOCK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_INTERLOCK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_REF_COUNT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_REF_COUNT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_TSTG_REDUCE_REPLAY_ICC_REF_COUNT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0 0x001404e0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0__PRIV_LEVEL_MASK 0x00140598 /* */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CLEAN_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CLEAN_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_COHERENCY 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_COHERENCY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_COHERENCY_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_COHERENCY_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_LRU_DEALLOC 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_LRU_DEALLOC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_LRU_DEALLOC_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_LRU_DEALLOC_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_EVICTION_HWM 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_EVICTION_HWM_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_EVICTION_HWM_MIN 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SET_SWIZZLE 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SET_SWIZZLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SET_SWIZZLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SET_SWIZZLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CROSS_VC_CONFLICT 13:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CROSS_VC_CONFLICT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CROSS_VC_CONFLICT_FASTTRACK_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CROSS_VC_CONFLICT_FASTTRACK_MOST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CROSS_VC_CONFLICT_STALL 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_CROSS_VC_CONFLICT_RETRY 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_ACTIVE_SETS 15:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_ACTIVE_SETS_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_ACTIVE_SETS_ALL 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_ACTIVE_SETS_HALF 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_ACTIVE_SETS_QUARTER 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_ACTIVE_SETS_EIGHTH 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_NUM_ACTIVE_WAYS 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_NUM_ACTIVE_WAYS_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_NUM_ACTIVE_WAYS_MAX 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SPARE_20 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SPARE_20_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SPARE_21 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SPARE_21_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SPARE_22 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_SPARE_22_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_I 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_I_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_I_MO_N 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_I_MO 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_X 26:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_X_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_X_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROBE_X_ALIGNED_ONLY_ENABLE 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROMOTE_PROBE_X 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROMOTE_PROBE_X_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROMOTE_PROBE_X_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_PROMOTE_PROBE_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT 31:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_3 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0 0x00140518 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0__PRIV_LEVEL_MASK 0x001405d4 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ECC 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ECC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ECC_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_CHECKBIT_WR_SUPPRESS 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_CHECKBIT_WR_SUPPRESS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_CHECKBIT_WR_SUPPRESS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE_ACTIVE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_FBFILL_BESTATE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_FBFILL_BESTATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_FBFILL_BESTATE_ACTIVE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_DRAM_ECC 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_DRAM_ECC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_DRAM_ECC_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_XBAR_RW_ILOCK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_XBAR_RW_ILOCK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_XBAR_RW_ILOCK_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_0 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_STATUS_SELECT_31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_NB_CREDIT_TTHRESHOLD 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_NB_CREDIT_TTHRESHOLD_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_RMW_VC 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_RMW_VC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_RMW_VC_ISO 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_RMW_VC_NOTISO 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_RESERVE_DECOMP 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_RESERVE_DECOMP_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_RESERVE_DECOMP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_DB2DCMP_SCND_ENABLE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_DB2DCMP_SCND_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_DB2DCMP_SCND_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_DB2DCMP_SCND_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_NB_CREDIT_DTHRESHOLD 27:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_NB_CREDIT_DTHRESHOLD_INIT 0x8 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_NB_CREDIT_DTHRESHOLD_INF 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2 0x001405a0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2__PRIV_LEVEL_MASK 0x001405d4 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_NB_HUB_CREDIT_TTHRESHOLD 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_NB_HUB_CREDIT_TTHRESHOLD_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD_INIT 0x8 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD_INF 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_BYPASS 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_BYPASS_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_BYPASS_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_DC 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_DC_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_DC_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_AC 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_AC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_DBI_AC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_STITCH 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_STITCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_STITCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_MULTI_CATOM 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_MULTI_CATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_COMPRET_MULTI_CATOM_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0 0x00140508 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0__PRIV_LEVEL_MASK 0x001405d0 /* */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_VDC_DISABLE 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_VDC_DISABLE_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_VDC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_DISABLE 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_DISABLE_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_VDC_FORCE_SUCCESS 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_VDC_FORCE_SUCCESS_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_VDC_FORCE_SUCCESS_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_UGO_FOR_ALL 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_UGO_FOR_ALL_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_UGO_FOR_ALL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_PULL_LIMIT 10:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_PULL_LIMIT_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_PULL_LIMIT_1QUARTER 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_PULL_LIMIT_HALF 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_PULL_LIMIT_3QUARTER 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_1B_DETECT_DISABLE 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_1B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_1B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_2B_DETECT_DISABLE 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_2B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_2B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_4B_DETECT_DISABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_4B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_SDC_4B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_CC_DISABLE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_CC_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_CC_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_ZBC_DISABLE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_ZBC_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_ZBC_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_UCOMP_MIXED_DISABLE 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_UCOMP_MIXED_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_UCOMP_MIXED_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_DISABLE_PARTIAL_PLC 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_DISABLE_PARTIAL_PLC_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_PLC_CFG0_DISABLE_PARTIAL_PLC_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT 0x0014051c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT_SEC_COUNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT_SEC_COUNT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT_DED_COUNT 23:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_REPORT_DED_COUNT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS 0x00140520 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS_INFO 22:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS_INFO_BIT 2:0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS_INFO_LINE 19:8 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS_INFO_BANK 21:20 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS_INFO_RAM 22:22 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS_INFO_RAM_0_BYTE 7:3 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ECC_ADDRESS_INFO_RAM_1_BYTE 7:6 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0 0x00140524 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_IDQ_DATA_COUNT 7:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_IDQ_WR_THREAD 8:8 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_IDQ_WR_THREAD_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_IDQ_WR_THREAD_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_DDRQ_DATA 9:9 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_DDRQ_DATA_EMPTY 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_DDRQ_DATA_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_DCRQ_CMD 10:10 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_DCRQ_CMD_EMPTY 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_DCRQ_CMD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_SEQUENCER_STATUS 11:11 /* R-IVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_SEQUENCER_STATUS_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_STATUS_0_SEQUENCER_STATUS_BUSY 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ 0x00140528 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_CWR_DATI_CTRL_LIMIT 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_CWR_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_CWR_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_OLD_DATI_CTRL_LIMIT 21:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_OLD_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_OLD_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_SHARED_DATI_CTRL_LIMIT 29:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_WDQ_SHARED_DATI_CTRL_LIMIT_INIT 0x28 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO 0x0014052c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_VIDMEM_LIMIT 9:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_VIDMEM_LIMIT_INIT 0x004 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_SYSMEM_LIMIT 19:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_SYSMEM_LIMIT_INIT 0x004 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT 29:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT_CTRL_DISABLED 0x3ff /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_SPARE 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_GATOM_SRC_FIFO_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_INDEX 0x00140538 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_INDEX_ADDRESS 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_INDEX_ADDRESS_RESERVED 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_INDEX_RDI_SOURCE 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_INDEX_RDI_SOURCE_DSTG 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_INDEX_RDI_SOURCE_GC 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x0014053c+(i)*4) /* RW-4A */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 /* */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_COLOR_CLEAR_VALUE_FIELD 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x0014054c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_STENCIL_CLEAR_VALUE 0x00140404 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_DSTG_ZBC_STENCIL_CLEAR_VALUE_FIELD 7:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM 0x00140550 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_ENABLE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_ENABLE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT 4:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP0 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP2 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP3 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP4 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP5 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP6 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP7 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP8 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP9 0x9 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP10 0xa /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP11 0xb /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP12 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP13 0xd /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP14 0xe /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP15 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT 10:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_STATIC_PATTERN_5555_16_GROUP 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_STATIC_PATTERN_AAAA_16_GROUP 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP41 0x29 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP42 0x2a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP43 0x2b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP44 0x2c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP45 0x2d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP46 0x2e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP47 0x2f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP48 0x30 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP49 0x31 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP50 0x32 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP51 0x33 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP52 0x34 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP53 0x35 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP54 0x36 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP55 0x37 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP56 0x38 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP57 0x39 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP58 0x3a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP59 0x3b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP60 0x3c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP61 0x3d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP62 0x3e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_GRP63 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT 16:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE 22:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_STATIC_PATTERN_5555_16_GROUP 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_STATIC_PATTERN_AAAA_16_GROUP 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP41 0x29 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP42 0x2a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP43 0x2b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP44 0x2c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP45 0x2d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP46 0x2e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP47 0x2f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP48 0x30 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP49 0x31 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP50 0x32 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP51 0x33 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP52 0x34 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP53 0x35 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP54 0x36 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP55 0x37 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP56 0x38 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP57 0x39 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP58 0x3a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP59 0x3b /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP60 0x3c /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP61 0x3d /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP62 0x3e /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_SELECT_CLONE_GRP63 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC 0x00140530 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_LAT_SCALE 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_LAT_SCALE_INIT 0x27 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_LAT_SCALE 11:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_LAT_SCALE_INIT 0x27 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE 23:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_INIT 0xb /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_128TH 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_64TH 0xe /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_32ND 0xd /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_16TH 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_8TH 0xb /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_4TH 0xa /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_2ND 0x9 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X1 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X2 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X4 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X8 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X16 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X32 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X64 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X128 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X256 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE 27:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_INIT 0xb /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_128TH 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_64TH 0xe /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_32ND 0xd /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_16TH 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_8TH 0xb /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_4TH 0xa /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_2ND 0x9 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X1 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X2 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X4 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X8 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X16 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X32 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X64 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X128 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X256 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL 29:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_10 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_100 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_1000 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_10000 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_10 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_100 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_1000 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_10000 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR 0x00140554 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_NAN_VALUE 22:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_NAN_VALUE_INIT 0x7fffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_RND 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_RND_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_DAZ_ENABLE 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_DAZ_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_DAZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_DAZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_FTZ_ENABLE 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_FTZ_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_FTZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_FTZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_NAN_ENABLE 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_NAN_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_NAN_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_FPADDR_NAN_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC 0x00140558 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_A_MISC__PRIV_LEVEL_MASK 0x001405c0 /* */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_REQ_LIMIT 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_REQ_LIMIT_INIT 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16ADDR_NAN_VALUE 13:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16ADDR_NAN_VALUE_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16ADDR_NAN_ENABLE 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16ADDR_NAN_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16ADDR_NAN_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16ADDR_NAN_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16_DAZ_ENABLE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16_DAZ_ENABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16_DAZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_A_MISC_FP16_DAZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CG1 0x0014055c /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_CG1__PRIV_LEVEL_MASK 0x001405dc /* */
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#define NV_PLTCG_LTC0_LTS0_CG1_SLCG 31:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_CG1_SLCG_DISABLED 0x7fffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00140580 /* RWB4R */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX 0x00140560 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX__PRIV_LEVEL_MASK 0x00140580 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_INDEX 7:0 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_INDEX_ZERO 0x00 /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_INDEX_MAX 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_INDEX_MAX_AVAIL 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_BLKACTIVITY_ENABLE 16:16 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_INIT 0x0 /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_DATA 0x00140564 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_DATA__PRIV_LEVEL_MASK 0x00140580 /* */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_DATA_DATA 31:0 /* RWBVF */
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#define NV_PLTCG_LTC0_LTS0_BLK_ACT_DATA_DATA_INIT 0x00000000 /* RWB-V */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS 0x00140568 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_KIND 7:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_COMPBITS 9:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_ZDCMP_STATE 12:10 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_IDLE 13:13 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_ARB_IDLE 14:14 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_CDCMP_IDLE 15:15 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_RDAT_FIFO_IDLE 16:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_REQ_FIFO_IDLE 17:17 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_WDAT_FIFO_IDLE 18:18 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_WREQ_FIFO_IDLE 19:19 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_ZDCMP_IDLE 20:20 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_CDCMP_REQ_PVLD 21:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_CDCMP_DATA_PVLD 22:22 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_CDCMP_IS_RMW 23:23 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_CDCMP_IS_P2P 24:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_CDCMP_IS_TEX 25:25 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_ZDCMP_REQ_PVLD 26:26 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_ZDCMP_DATA_PVLD 27:27 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_ZDCMP_IS_RMW 28:28 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_ZDCMP_IS_P2P 29:29 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS_CDCMP_STATE 30:30 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS1 0x0014056c /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS1_INPUT_MASK 7:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_DCMP_STATUS1_ROLLING_MASK 15:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG 0x001405e0 /* RWI4R */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG__PRIV_LEVEL_MASK 0x001405dc /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG1 0x001405e4 /* RWI4R */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG1__PRIV_LEVEL_MASK 0x001405dc /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_CBC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG 0x001405f8 /* RWI4R */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG__PRIV_LEVEL_MASK 0x001405dc /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_BLPG_EN 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DIS_EARLY_WUP 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DEEP_ELPG_EN 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_ELPG_EN 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DIDT_DELAY 23:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_DIDT_DELAY_HWINIT 0xa /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_RESET_DURATION 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_RESET_DURATION_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_CLAMP_DELAY 29:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_CLAMP_DELAY_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_ZONE_OFF_MASK 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_SOFT_GATING_EN 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG1 0x001405fc /* RWI4R */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG1__PRIV_LEVEL_MASK 0x001405dc /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG1_ZONE_SEQ 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG1_ZONE_MASK 31:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_LTS_PG1_ZONE_MASK_HWINIT 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG 0x001405c8 /* RWI4R */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG__PRIV_LEVEL_MASK 0x001405dc /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG1 0x001405cc /* RWI4R */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG1__PRIV_LEVEL_MASK 0x001405dc /* */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS0_G_PRI_IQ_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2 0x001405f4 /* R--4R */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE 15:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_4 0x0004 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_5 0x0005 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_6 0x0006 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_7 0x0007 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_8 0x0008 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_10 0x000a /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_11 0x000b /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_13 0x000d /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_16 0x0010 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_22 0x0016 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_32 0x0020 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_64 0x0040 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_128 0x0080 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_NUM_CACHE_LINES 23:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_NUM_CACHE_LINES_16 0x10 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_NUM_CACHE_LINES_20 0x14 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_NUM_CACHE_LINES_32 0x20 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_NUM_CACHE_LINES_40 0x28 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_NUM_CACHE_LINES_64 0x40 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE 27:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_512 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_1K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_2K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_4K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_8K 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_16K 0x5 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_32K 0x6 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_CACHE_LINE_SIZE_64K 0x7 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_SLICES_PER_LTC 31:28 /* R--VF */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_SLICES_PER_LTC_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_SLICES_PER_LTC_2 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_CBC_PARAM2_SLICES_PER_LTC_4 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTS0_MISC_CFG 0x00140500 /* RW-4R */
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#define NV_PLTCG_LTC0_LTS0_MISC_CFG__PRIV_LEVEL_MASK 0x00140598 /* */
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#define NV_PLTCG_LTC0_LTS0_MISC_CFG_SPARE 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTS0_MISC_CFG_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTS1 0x00140600 /* RW--L */
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#define NV_PLTCG_LTC0_LTS2 0x00140800 /* RW--L */
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#define NV_PLTCG_LTC0_LTS3 0x00140a00 /* RW--L */
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#define NV_PLTCG_LTC0_LTSS 0x00140200 /* RW--L */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK 0x00140218 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_iq" /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK 0x001403a8 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cbc" /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK 0x001403d8 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_vpr_leakage" /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK 0x001403d4 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_dstg" /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK 0x001403c4 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya_ecc" /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK 0x00140390 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK 0x001403c0 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya" /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK 0x001403d0 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_tstg" /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK 0x001403bc /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK 0x00140384 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK 0x001403dc /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cgate" /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK 0x00140394 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK 0x00140398 /* RWE4R */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya_coh" /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTC0_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL 0x001402e4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL__PRIV_LEVEL_MASK 0x001403d8 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_MIN 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_MAX 0x001c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CONFIG 0x0000 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TRIGGER_CTL 0x0001 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_1 0x0002 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_2 0x0003 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_3 0x0004 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_4 0x0005 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_MASK_LO 0x0006 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_MASK_HI 0x0007 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_VAL_LO 0x0008 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_VAL_HI 0x0009 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_1 0x000a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_2 0x000b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_3 0x000c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_4 0x000d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_MASK_LO 0x000e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_MASK_HI 0x000f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_VAL_LO 0x0010 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_VAL_HI 0x0011 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DIN_TRIGGER_CTL 0x0012 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DOUT_TRIGGER_CTL 0x0013 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DATA_TRIGGER_VAL_LO 0x0014 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DATA_TRIGGER_VAL_HI 0x0015 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DIN_SAMPLE_CTL 0x0016 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DOUT_SAMPLE_CTL 0x0017 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_CTL 0x0018 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_BUFFER_DEPTH 0x0019 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_STATUS 0x001a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_STATUS_2 0x001b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILA_BUFFER_READ 0x001c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_CBC_DEBUG 0x0100 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_TG_DEBUG 0x0101 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE1_INFO0 0x0102 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE1_INFO1 0x0103 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE2_INFO0 0x0104 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE2_INFO1 0x0105 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_READINCR 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_READINCR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_READINCR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_WRITEINCR 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_WRITEINCR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_CTRL_WRITEINCR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE 0x001402e8 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE__PRIV_LEVEL_MASK 0x001403d8 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_VAL 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA 1:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_USECBC_PARTIAL 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_USECBC_FULL 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_TRIGGER_ONLY 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE 5:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_A 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_C 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TSTAMP_TRIG_BIT 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TSTAMP_TRIG_BIT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC 15:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_ZERO 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_12_5 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_25_0 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_37_5 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_50_0 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_62_5 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_75_0 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_87_5 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_EV_CNT 31:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_EV_CNT_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK 15:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_ALL_ENABLE 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK 30:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_ALL_ENABLE 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_RESERVED 31:31 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_RESERVED_VAL 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_ID 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK_EXACT 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_ID 22:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK 30:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK_EXACT 0x7f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE_INCLUSIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE_EXCLUSIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MASK 31:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MASK_ALL_ADDRESSES 0x0000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_HI_MASK 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_HI_MASK_ALL_ADDRESSES 0x000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_VAL_LO_PADR 31:7 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_VAL_HI_PADR 23:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK 15:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_ALL_ENABLE 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK 30:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_ALL_ENABLE 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_ID 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK_EXACT 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_ID 22:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK 30:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK_EXACT 0x7f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE_INCLUSIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE_EXCLUSIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MASK 31:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MASK_ALL_ADDRESSES 0x0000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_HI_MASK 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_HI_MASK_ALL_ADDRESSES 0x000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_VAL_LO_PADR 31:7 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_VAL_HI_PADR 23:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_BYTE_MASK 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_BYTE_MASK_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_QWORD_SEL 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_QWORD_SEL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_SPKT_MASK 25:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_SPKT_MASK_ALL_ENABLE 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_BYTE_MASK 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_BYTE_MASK_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_QWORD_SEL 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_QWORD_SEL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_SPKT_MASK 23:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_SPKT_MASK_ALL_ENABLE 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DATA_TRIGGER_VAL_LO_DATA 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DATA_TRIGGER_VAL_HI_DATA 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_DATA_SEL 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_DATA_SEL_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SPKT_MASK 17:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SPKT_MASK_ALL_ENABLE 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_DATA_SEL 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_DATA_SEL_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SPKT_MASK 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SPKT_MASK_ALL_ENABLE 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE_TRIGGER 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE_PMON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_CNT 15:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_CNT_INIT 0x0000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE 31:31 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE_128BIT 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE_256BIT 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INDEX 11:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED 14:14 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE 15:15 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_LAST_INDEX 27:16 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_LAST_INDEX_INIT 0x000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY 30:30 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY_FALSE 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY_TRUE 0x1 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED 31:31 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON 5:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG 0:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN 1:1 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT 2:2 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP 3:3 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON 4:4 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL 5:5 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_READ 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_CBC_DEBUG 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_TG_DEBUG 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE1_INFO0 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE1_INFO1 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE2_INFO0 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE2_INFO1 31:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL 0x001402ec /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL__PRIV_LEVEL_MASK 0x00140390 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS 0x001402f0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_RESET 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_RESET_TASK 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_STATUS_RESET_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT 0x001402f4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x001402f8 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS 0x001402fc /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_INDEX 31:0 /* R-XVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_LOCATION 21:0 /* R-XVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM 29:22 /* R-XVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM0 0x00 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM2 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM3 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO0 0x00 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM0 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM1 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM2 0x04 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM3 0x05 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM4 0x06 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM5 0x07 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM6 0x08 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM7 0x09 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM0 0x0a /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM1 0x0b /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM2 0x0c /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM3 0x0d /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM4 0x0e /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM5 0x0f /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM6 0x10 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM7 0x11 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM0 0x12 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM1 0x13 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM2 0x14 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM3 0x15 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM4 0x16 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM5 0x17 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM6 0x18 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM7 0x19 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRA_RAM 0x1a /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_LRU_RAM 0x1b /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM 0x1c /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM 0x1d /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_COPY_RAM 0x1e /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_STATE 0x1f /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_PAIR 0x20 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_INFO 0x21 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_RAM 0x22 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_LRU_RAM 0x23 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO2 0x24 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_LCN_COMP_STAT 0x25 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS 0x26 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM0 0x00 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM2 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM3 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM4 0x04 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM5 0x05 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM6 0x06 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM7 0x07 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK0 0x08 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK1 0x09 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK2 0x0a /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK3 0x0b /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT 31:30 /* R-XVF */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_RSTG 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_TSTG 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_DSTG 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_CLIENT_POISON_RETURNED 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM0_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM1_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM2_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM3_ROW 9:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO0_ROW 8:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO1_ROW 8:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRA_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_LRU_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM_SLICE 3:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM_ROW 11:4 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM_SLICE 3:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM_ROW 11:4 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_LRU_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO2_ROW 8:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_LCN_COMP_STAT_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS_SLICE 3:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS_ROW 11:4 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK0_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK1_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK2_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK3_ROW 11:0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CST_RDI_INDEX 0x00140200 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CST_RDI_INDEX_ADDRESS 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CST_RDI_INDEX_ADDRESS_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CST_RDI_INDEX_ADDRESS_MAX 0xffff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CST_RDI_DATA(i) (0x001403ac+(i)*4) /* R--4A */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CST_RDI_DATA__SIZE_1 4 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CST_RDI_DATA_FIELD 31:0 /* R-XVF */
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#define NV_PLTCG_LTC0_LTSS_INTR 0x0014020c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_IQ 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_IQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_IQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_IQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_CBC 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_CBC_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_CBC_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_CBC_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_TSTG 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_TSTG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_TSTG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_TSTG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_DSTG 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_DSTG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_DSTG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_IDLE_ERROR_DSTG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_EVICTED_CB 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EVICTED_CB_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EVICTED_CB_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EVICTED_CB_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLOCKLINEAR_CB 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLOCKLINEAR_CB_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLOCKLINEAR_CB_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLOCKLINEAR_CB_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_SEC_ERROR 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_SEC_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_SEC_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_SEC_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_DED_ERROR 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_DED_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_DED_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ECC_DED_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_DEBUG 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_DEBUG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_DEBUG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_DEBUG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_ATOMIC_TO_Z 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_ATOMIC_TO_Z_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ATOMIC_TO_Z_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ATOMIC_TO_Z_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_ATOMIC 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_ATOMIC_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_ATOMIC_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_ATOMIC_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLKACTIVITY_ERR 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLKACTIVITY_ERR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLKACTIVITY_ERR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_BLKACTIVITY_ERR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_IQ 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_IQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_IQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_CBC 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_CBC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_CBC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_TSTG 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_TSTG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_TSTG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_DSTG 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_DSTG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_IDLE_ERROR_DSTG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_EVICTED_CB 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_EVICTED_CB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_EVICTED_CB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_COMPSTAT 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_COMPSTAT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_BLOCKLINEAR_CB 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_BLOCKLINEAR_CB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_BLOCKLINEAR_CB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ECC_SEC_ERROR 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ECC_SEC_ERROR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ECC_SEC_ERROR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ECC_DED_ERROR 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ECC_DED_ERROR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ECC_DED_ERROR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_DEBUG 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_DEBUG_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_DEBUG_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ATOMIC_TO_Z 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ATOMIC_TO_Z_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ATOMIC_TO_Z_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_ATOMIC 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_ATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_ATOMIC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_BLKACTIVITY_ERR 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_BLKACTIVITY_ERR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_BLKACTIVITY_ERR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2 0x00140208 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_INVALID_TDTAG 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_INVALID_TDTAG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_INVALID_TDTAG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_INVALID_TDTAG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_TRDONE 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_TRDONE_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_TRDONE_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_TRDONE_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_INVALID_SUBID 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_PRBRS 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_MISSING_DATA 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_MISSING_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_MISSING_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_MISSING_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_UNEXPECTED_DATA 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_UNEXPECTED_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_UNEXPECTED_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBX_UNEXPECTED_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_UNEXPECTED_PA7 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_UNEXPECTED_PA7_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_UNEXPECTED_PA7_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_PRBRS_UNEXPECTED_PA7_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_UNEXPECTED_PA7 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_UNEXPECTED_PA7_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_UNEXPECTED_PA7_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_TRDONE_UNEXPECTED_PA7_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_TRDONE_INVALID_TDTAG 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_TRDONE_INVALID_TDTAG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_TRDONE_INVALID_TDTAG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_TRDONE 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_TRDONE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_TRDONE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBRS_INVALID_SUBID 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBRS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBRS_INVALID_SUBID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_PRBRS 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBIN_UNEXPECTED_PRBRS 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBIN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBIN_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBX_MISSING_DATA 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBX_MISSING_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBX_MISSING_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBX_UNEXPECTED_DATA 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBX_UNEXPECTED_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBX_UNEXPECTED_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBRS_UNEXPECTED_PA7 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBRS_UNEXPECTED_PA7_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_PRBRS_UNEXPECTED_PA7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_TRDONE_UNEXPECTED_PA7 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_TRDONE_UNEXPECTED_PA7_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_TRDONE_UNEXPECTED_PA7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3 0x00140388 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_RMWRS_INVALID_SUBID 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_RMWRS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_RMWRS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_RMWRS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_UNEXPECTED_RMWRS 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_UNEXPECTED_RMWRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_UNEXPECTED_RMWRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_UNEXPECTED_RMWRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ECC_CORRECTED 7:7 /* R-XVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ECC_CORRECTED_NOT_PENDING 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ECC_CORRECTED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ECC_UNCORRECTED 8:8 /* R-XVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ECC_UNCORRECTED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_VOLATILE_TO_COMPRESSED 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_VOLATILE_TO_COMPRESSED_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_VOLATILE_TO_COMPRESSED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_VOLATILE_TO_COMPRESSED_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_KIND_INVALID 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_KIND_INVALID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_KIND_INVALID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_KIND_INVALID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_COMPTAG_INVALID 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_COMPTAG_INVALID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_COMPTAG_INVALID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_DTM_COMPTAG_INVALID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CDCMP_IP_ERROR 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CDCMP_IP_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CDCMP_IP_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_CDCMP_IP_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_RMWRS_INVALID_SUBID 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_RMWRS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_RMWRS_INVALID_SUBID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_UNEXPECTED_RMWRS 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_UNEXPECTED_RMWRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_UNEXPECTED_RMWRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_VOLATILE_TO_COMPRESSED 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_VOLATILE_TO_COMPRESSED_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_VOLATILE_TO_COMPRESSED_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_DTM_KIND_INVALID 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_DTM_KIND_INVALID_ENABLED 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_DTM_KIND_INVALID_DISABLED 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_DTM_COMPTAG_INVALID 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_DTM_COMPTAG_INVALID_ENABLED 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_DTM_COMPTAG_INVALID_DISABLED 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CDCMP_IP_ERROR 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CDCMP_IP_ERROR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_INTR3_EN_CDCMP_IP_ERROR_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS 0x00140210 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_LTC_STOP 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_LTC_STOP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_LTC_STOP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_RSTG_BUSY 8:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_TSTG_BUSY 9:9 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_DSTG_BUSY 10:10 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_A_BUSY 11:11 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_WAITING_FOR_XBAR_CMD_CREDITS 20:20 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_WAITING_FOR_XBAR_DATA_CREDITS 21:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_STATUS_WAITING_FOR_SYSMEM_FILL_DATA 22:22 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG 0x00140214 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH_ABORT 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH_ABORT_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_FLUSH_ABORT_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_STATUS_CBC_NOT_READY 8:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_ELPG_STATUS_TSTG_NOT_READY 9:9 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0 0x0014021c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0__PRIV_LEVEL_MASK 0x001403c4 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_TO_GENERIC 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_TO_GENERIC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_TO_GENERIC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_TO_GENERIC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_STATUS_SELECT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_STATUS_SELECT_INIT 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_STATUS_SELECT_DISABLED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_SPARE 31:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_SPARE_UCREQ_LIVELOCK_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_CFG_0_SPARE_UCREQ_LIVELOCK_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_XBAR_STATUS_0 0x00140220 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_XBAR_STATUS_0_VALUE 31:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_XBAR_STATUS_0_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0 0x0014023c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0__PRIV_LEVEL_MASK 0x00140218 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_ISO_WEIGHT 2:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_ISO_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_NISO_NB_WEIGHT 6:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_NISO_NB_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_PLC_WEIGHT 10:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_PLC_WEIGHT_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_NB_WEIGHT 14:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_NB_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_B_WEIGHT 18:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_B_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_RESP_WEIGHT 22:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_RESP_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_CREQ_WEIGHT 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_WRR_CREQ_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1 0x00140240 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1__PRIV_LEVEL_MASK 0x00140218 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1_WRR_LL_WEIGHT 6:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1_WRR_LL_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3 0x00140244 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3__PRIV_LEVEL_MASK 0x00140218 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG_INIT 0xa /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG 10:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG_MAX 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG 14:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG_MAX 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE_AFTER_DRAINING_PENDING 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE_IMMEDIATELY 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_SPARE_25 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_SPARE_25_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG 31:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_MIN 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0 0x00140248 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0__PRIV_LEVEL_MASK 0x00140218 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_B 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_B_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_B_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_B_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0 0x00140260 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_MODE_TIMEOUT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_MODE_TIMEOUT_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_FNIC2LTC_FILL 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_LTC2FNIC_REQ 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_TIMEOUT 27:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_BALANCE_TIMEOUT_INIT 0xf80 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_REQUEST_BASED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_SUBPACKET_BASED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0 0x00140264 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_ECO_CYA 2:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_ECO_CYA_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS 10:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_UNLIMITED 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0 0x00140268 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_MAX 0x36 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_UNALLOC_VC_INTERLOCK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_UNALLOC_VC_INTERLOCK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_UNALLOC_VC_INTERLOCK_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_MIN_LIMIT 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_MIN_LIMIT_INIT 0x6 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_NUM_ACTIVE_LINES 19:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_NUM_ACTIVE_LINES_INIT 0x40 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_NUM_ACTIVE_LINES_ALL 0x40 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1 0x0014026c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_CLEAN_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_INVALIDATE 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_INVALIDATE_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_CLEAR 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_CLEAR_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_ACTIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_2 0x00140270 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 19:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND_INIT 0x00000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_3 0x00140274 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 19:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0xfffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_BASE 0x00140278 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_BASE__PRIV_LEVEL_MASK 0x001403a8 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_BASE_ALIGNMENT_SHIFT 0x0000000b /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_BASE_ADDRESS 25:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_BASE_HUB_SAFE 31:31 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS 0x0014027c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK 0x00140394 /* */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM 0x00140280 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE 9:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_4 0x004 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_5 0x005 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_6 0x006 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_7 0x007 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_8 0x008 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_10 0x00a /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_11 0x00b /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_12 0x00c /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_13 0x00d /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_14 0x00e /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_16 0x010 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_20 0x014 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_22 0x016 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_24 0x018 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_26 0x01a /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_28 0x01c /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_32 0x020 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_44 0x02c /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_64 0x040 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_128 0x080 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING 11:10 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_2K 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_4K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_8K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_16K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING 13:12 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_64K 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_128K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_256K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_512K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_NUM_CACHE_LINES 23:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_NUM_CACHE_LINES_16 0x10 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_NUM_CACHE_LINES_20 0x14 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_NUM_CACHE_LINES_32 0x20 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_NUM_CACHE_LINES_40 0x28 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_NUM_CACHE_LINES_64 0x40 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_512 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_1K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_2K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_4K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_8K 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_16K 0x5 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_32K 0x6 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_CACHE_LINE_SIZE_64K 0x7 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_SLICES_PER_LTC 31:28 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_SLICES_PER_LTC_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_SLICES_PER_LTC_2 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_SLICES_PER_LTC_3 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM_SLICES_PER_LTC_4 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CLEAR_GOB_VALUE 0x001403a4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_CLEAR_GOB_VALUE_COMPBITS 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CBC_CLEAR_GOB_VALUE_COMPBITS_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CBC_CLEAR_GOB_VALUE_COMPBITS_UNCOMPRESSED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS 0x0014028c /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_FILL_CMD_STATE 2:1 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_CLEAN_CMD_STATE 5:3 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_EVICT_DATA_STATE 7:6 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_CLEAR_CMD_STATE 11:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_NUM_WRITEBUFF_REQ 15:12 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_PIPE_VLD 16:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_WRITEBUFF_COMMIT_VLD 17:17 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_AVAIL_LRU_TAG_VLD 18:18 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_AVAIL_DIRTY_TAG_VLD 19:19 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_FILL_PEND 20:20 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_CLEAN_PEND 21:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_STATUS_DIRTY_PEND 22:22 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0 0x00140290 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0__PRIV_LEVEL_MASK 0x001403d0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK_TO_CROP 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK_STALL 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_CROP_RDWR 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_CROP_RDWR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_CROP_RDWR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_ZROP_RDWR 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_ZROP_RDWR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_ZROP_RDWR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_NISO_NB_WR 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_NISO_NB_WR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_NISO_NB_WR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_HOLD_INUSE 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_HOLD_INUSE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_HOLD_INUSE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_FORCE_LDST_TO_ATM 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_FORCE_LDST_TO_ATM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_FORCE_LDST_TO_ATM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_TEST_WITHOUT_FB 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_TEST_WITHOUT_FB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_TEST_WITHOUT_FB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_VOLATILE_READ 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_VOLATILE_READ_PER_SECTOR 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_VOLATILE_READ_PER_LINE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_VOLATILE_PART_CLR_FULL 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_VOLATILE_PART_CLR_FULL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_RMW 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_RMW_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_RMW_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_ISO_RD 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_ISO_RD_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_INTERLOCK_ISO_RD_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_SAME_SET 20:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_SAME_SET_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_SAME_SET_ONE_CYCLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_SAME_SET_TWO_CYCLES 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_SAME_SET_ONE_AND_TWO_CYCLES 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_ISO_WITHOUT_ICC 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_ISO_WITHOUT_ICC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_ISO_WITHOUT_ICC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_SPARE 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_SPARE_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_L2_ECC_FILL_ON_WR 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_L2_ECC_FILL_ON_WR_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_0_L2_ECC_FILL_ON_WR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4 0x00140334 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4__PRIV_LEVEL_MASK 0x00140384 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_VOL_BYPASS_GATOM 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_VOL_BYPASS_GATOM_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_VOL_BYPASS_GATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FORCE_ISO_MISS 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FORCE_ISO_MISS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FORCE_ISO_MISS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_RD_CACHING 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_RD_CACHING_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_RD_CACHING_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHING 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHING_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHING_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_VOLBYPASS 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_VOLBYPASS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_VOLBYPASS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FAIL_GC_COND_RD 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FAIL_GC_COND_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FAIL_GC_COND_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_LC_PROMOTION 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_LC_PROMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_LC_PROMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_PREFETCH 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_PREFETCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_PREFETCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_256B_PROMOTE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_256B_PROMOTE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_256B_PROMOTE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_ISO_CBC_RD 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_ISO_CBC_RD_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SAME_SET_ISO_CBC_RD_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_CMGMT_PLC_INVALID 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_CMGMT_PLC_INVALID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_CMGMT_PLC_INVALID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_CMGMT_PLC_INFLIGHT 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_CMGMT_PLC_INFLIGHT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_CMGMT_PLC_INFLIGHT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_GMK_COLOR_128B_RMW 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_GMK_COLOR_128B_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_GMK_COLOR_128B_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SEND_CR_ON_MISS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SEND_CR_ON_MISS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_SEND_CR_ON_MISS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_NISO_NB_TO_VC_LL 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_NISO_NB_TO_VC_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_NISO_NB_TO_VC_LL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FAIL_GMK_COND_RD 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FAIL_GMK_COND_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_4_FAIL_GMK_COND_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5 0x00140304 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5__PRIV_LEVEL_MASK 0x001403a8 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_ROP_DATA 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_ROP_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_ROP_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_RAST_DATA 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_RAST_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_RAST_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_PE_DATA 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_PE_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_PE_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_SCC_DATA 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_SCC_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_SCC_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_TEX_DATA 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_TEX_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_TEX_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_ALL_DATA 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_ALL_DATA_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_ALL_DATA_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_COMPRESSED_DATA 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_COMPRESSED_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_5_DISCARD_COMPRESSED_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1 0x00140294 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_WAYS 15:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_WAYS_INIT 0xffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_WAYS_GF100_1 0x0001 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_WAYS_GF100_ALL 0xffff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_SETS 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_SETS_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_SETS_HALF 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_SETS_QUARTER 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES 22:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_7_8TH 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_6_8TH 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_5_8TH 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_4_8TH 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_3_8TH 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_2_8TH 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_1_8TH 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD 27:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_MIN 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_1 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_2 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_4 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_8 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_16 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_32 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_64 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_128 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_256 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_MAX 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ECC_HUB_RMW_DISABLE 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ECC_HUB_RMW_DISABLE_CE_ONLY 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_ECC_HUB_RMW_DISABLE_ALL 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_CACHE_HUB_WEAK_VOL 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_CACHE_HUB_WEAK_VOL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_1_CACHE_HUB_WEAK_VOL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2 0x00140298 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE 1:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE 3:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE 5:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE 7:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE 11:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE 13:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE 15:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_ON_128B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_ON_SECT0 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE 19:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE 21:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE 23:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE 25:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE 27:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE 29:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_ON_128B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_ON_SECT0 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3 0x0014029c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE 1:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE 3:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE 5:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE 7:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE 11:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE 13:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PROMOTE 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PROMOTE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PROMOTE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE 19:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE 21:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE 23:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE 25:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE 27:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE 29:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM_32B 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0 0x001402a0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0__PRIV_LEVEL_MASK 0x001403bc /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_ACTIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1 0x001402a4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1__PRIV_LEVEL_MASK 0x001403bc /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS 0x001402a8 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_DIRTY 1:1 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_INUSE 2:2 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_FULL 3:3 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_ISO_RDAT_CREDIT_IDLE 4:4 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_WRCOUNT_IDLE 5:5 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_ISO_LOCKED_WITHOUT_ICC 6:6 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_ACTIVE_ATOM 7:7 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_PENDING_FB_MISS_REQ 16:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_STALLED_ON_CLEAN_IF 17:17 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_STALLED_ON_READ_IF 18:18 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_STALLED_ON_ICC 19:19 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_STATUS_CACHELINES_PINNED 24:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0 0x001402ac /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0__PRIV_LEVEL_MASK 0x001403bc /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_RD_PINNED 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_RD_PINNED_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_SYSMEM_RD_PINNED 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_SYSMEM_RD_PINNED_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST_INIT 0x03 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_ATOMIC 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_ATOMIC_INIT 0x0b /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1 0x0014039c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1__PRIV_LEVEL_MASK 0x001403bc /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_EVICT_FIRST 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_EVICT_FIRST_INIT 0x10 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_MIN_WAYS_EVICT_NORMAL_DIRTY 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_MIN_WAYS_EVICT_NORMAL_DIRTY_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE_NORMAL 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD 22:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD_DISABLED 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD_0 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD_INIT 0x05 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_PROBING 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_PROBING_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_ATOMIC_COH_RMW 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_ATOMIC_COH_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_ATOMIC_COH_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2 0x001402b0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2__PRIV_LEVEL_MASK 0x001403d0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_INIT 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_ONE 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_INIT 0x0e /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_ONE 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3 0x001402b4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3__PRIV_LEVEL_MASK 0x001403d0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_STOP 9:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_STOP_INIT 0x030 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES 13:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_7_8TH 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_6_8TH 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_5_8TH 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_4_8TH 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_3_8TH 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_2_8TH 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_1_8TH 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES 15:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_NONE 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_2_3RD 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_1_3RD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_SYSMEM_WB_THRESHOLD 28:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_SYSMEM_WB_THRESHOLD_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4 0x001402b8 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD_INIT 0x02 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD 9:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD_INIT 0x04 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK_STRICT 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL_FULL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL_FULL_NON_READ 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS 15:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD 17:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_25PCT 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_50PCT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_75PCT 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_100PCT 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE 19:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_0PCT 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_25PCT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_50PCT 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_100PCT 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT 22:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_ANY 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_ALLOCATION 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_NON_EF_ALLOCATION 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_VERIF 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD 26:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_MIN 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5 0x001402bc /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5__PRIV_LEVEL_MASK 0x001403bc /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_TIER1_CLEAN_THRESHOLD 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_TIER1_CLEAN_THRESHOLD_INIT 0x07 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_TIER2_CLEAN_THRESHOLD 12:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_TIER2_CLEAN_THRESHOLD_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST 20:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST_INIT 0x0d /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST_FOR_COMPUTE 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD1 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD2 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD3 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC 29:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD1 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD2 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD3 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE 0x001402c0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_BUCKET_SIZE_INIT 0x020 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_LEAK_COUNT_DISABLE 0x000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_LEAK_SIZE_32B 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_LEAK_SIZE_64B 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_LEAK_SIZE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_THROTTLE_LEAK_SIZE_256B 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0 0x001402c4 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_STATE 10:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_STATE_IDLE 0x000 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE 13:12 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_HIT 15:14 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD 17:16 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ISO 19:18 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE 21:20 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD 23:22 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1 0x001402c8 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM 1:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM 3:2 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B 5:4 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW 9:8 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI 11:10 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX 13:12 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS 15:14 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_LL 17:16 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_LL_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_LL_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_LL_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_STATUS_1_MISS_LL_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL 0x001402cc /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_MIN_LIMIT 5:0 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_MIN_LIMIT_INIT 0x05 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_ARB_SPARE 7:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_ARB_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_HIT 14:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_HIT_INIT 0x10 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_ALL_WRS 22:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_ALL_WRS_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_SYSRD 30:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_SYSRD_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0 0x001402d0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS 8:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS_INIT 0x010 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS_MIN 0x008 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB_SEPARATELY 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB_WITH_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO 18:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO_INIT 0x060 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO_MIN 0x008 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW_SEPARATELY 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW_WITH_EE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE 29:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE_INIT 0x040 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE_MIN 0x010 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE_WITH_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE_WITH_HUB 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST_AS_NEEDED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST_CONTINUOUSLY 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1 0x001402d4 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED 9:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_MIN 0x010 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_CTRL_DISABLED 0x3ff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SYSMEM_HUB 18:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SYSMEM_HUB_INIT 0x000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT_THROUGH_MISS 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT_THROUGH_HIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED 21:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED 23:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW 29:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW_INIT 0x02 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_0 0x001402d8 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_0_MISS_FIFO_DEPTH 10:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_0_NUM_AWPS 20:11 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_0_ISO_RDAT_FIFO_DEPTH 31:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_1 0x0014038c /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_1_SLICE_SIZE_IN_KB 15:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_1_SLICES_PER_L2 20:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_1_SLICES_PER_L2_1 0x01 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_1_SLICES_PER_L2_2 0x02 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_1_SLICES_PER_L2_3 0x03 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_INFO_1_SLICES_PER_L2_4 0x04 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN 0x001402dc /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_TIMEOUT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_TIMEOUT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_TIMEOUT_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_TIMEOUT_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_TIMEOUT_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_ECC_SCRUB_0 0x0014030c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_ECC_SCRUB_0_XBAR_RAW_PADR 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_ECC_SCRUB_0_XBAR_RAW_PADR_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_ECC_SCRUB_1 0x00140310 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_ECC_SCRUB_1_WRITE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_ECC_SCRUB_1_WRITE_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_ECC_SCRUB_1_WRITE_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY 0x00140314 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MASTER 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MASTER_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MASTER_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_READ_THLD 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_READ_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_READ_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_INUSE_THLD 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_INUSE_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_INUSE_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ATOMIC_THLD 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ATOMIC_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ATOMIC_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_AWP_THLD 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_AWP_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_AWP_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM2INUSE 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_RMW2INUSE 9:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_RMW2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_RMW2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE 10:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_FB_READ_CREDIT 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_FB_READ_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_FB_READ_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_FULL 25:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_FULL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_FULL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_INTERLOCK 26:26 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_INTERLOCK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_INTERLOCK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_REF_COUNT 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_REF_COUNT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_TSTG_REDUCE_REPLAY_ICC_REF_COUNT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0 0x001402e0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0__PRIV_LEVEL_MASK 0x00140398 /* */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CLEAN_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CLEAN_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_COHERENCY 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_COHERENCY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_COHERENCY_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_COHERENCY_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_LRU_DEALLOC 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_LRU_DEALLOC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_LRU_DEALLOC_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_LRU_DEALLOC_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_EVICTION_HWM 9:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_EVICTION_HWM_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_EVICTION_HWM_MIN 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SET_SWIZZLE 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SET_SWIZZLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SET_SWIZZLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SET_SWIZZLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CROSS_VC_CONFLICT 13:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CROSS_VC_CONFLICT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CROSS_VC_CONFLICT_FASTTRACK_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CROSS_VC_CONFLICT_FASTTRACK_MOST 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CROSS_VC_CONFLICT_STALL 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_CROSS_VC_CONFLICT_RETRY 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_ACTIVE_SETS 15:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_ACTIVE_SETS_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_ACTIVE_SETS_ALL 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_ACTIVE_SETS_HALF 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_ACTIVE_SETS_QUARTER 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_ACTIVE_SETS_EIGHTH 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_NUM_ACTIVE_WAYS 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_NUM_ACTIVE_WAYS_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_NUM_ACTIVE_WAYS_MAX 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SPARE_20 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SPARE_20_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SPARE_21 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SPARE_21_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SPARE_22 22:22 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_SPARE_22_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_I 24:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_I_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_I_MO_N 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_I_MO 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_X 26:25 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_X_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_X_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROBE_X_ALIGNED_ONLY_ENABLE 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROMOTE_PROBE_X 27:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROMOTE_PROBE_X_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROMOTE_PROBE_X_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_PROMOTE_PROBE_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT 31:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_3 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0 0x00140318 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0__PRIV_LEVEL_MASK 0x001403d4 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ECC 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ECC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ECC_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_CHECKBIT_WR_SUPPRESS 1:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_CHECKBIT_WR_SUPPRESS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_CHECKBIT_WR_SUPPRESS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE 2:2 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE_ACTIVE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_FBFILL_BESTATE 3:3 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_FBFILL_BESTATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_FBFILL_BESTATE_ACTIVE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_DRAM_ECC 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_DRAM_ECC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_DRAM_ECC_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_XBAR_RW_ILOCK 7:7 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_XBAR_RW_ILOCK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_XBAR_RW_ILOCK_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_0 0x00 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_STATUS_SELECT_31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_NB_CREDIT_TTHRESHOLD 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_NB_CREDIT_TTHRESHOLD_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_RMW_VC 20:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_RMW_VC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_RMW_VC_ISO 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_RMW_VC_NOTISO 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_RESERVE_DECOMP 21:21 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_RESERVE_DECOMP_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_RESERVE_DECOMP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE 23:23 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_NB_CREDIT_DTHRESHOLD 27:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_NB_CREDIT_DTHRESHOLD_INIT 0x8 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_NB_CREDIT_DTHRESHOLD_INF 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2 0x001403a0 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2__PRIV_LEVEL_MASK 0x001403d4 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_NB_HUB_CREDIT_TTHRESHOLD 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_NB_HUB_CREDIT_TTHRESHOLD_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD 7:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD_INIT 0x8 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD_INF 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_BYPASS 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_BYPASS_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_BYPASS_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_DC 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_DC_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_DC_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_AC 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_AC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_DBI_AC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_STITCH 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_STITCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_STITCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_MULTI_CATOM 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_MULTI_CATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_COMPRET_MULTI_CATOM_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0 0x00140308 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0__PRIV_LEVEL_MASK 0x001403d0 /* */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_VDC_DISABLE 4:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_VDC_DISABLE_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_VDC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_DISABLE 5:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_DISABLE_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_VDC_FORCE_SUCCESS 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_VDC_FORCE_SUCCESS_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_VDC_FORCE_SUCCESS_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_UGO_FOR_ALL 8:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_UGO_FOR_ALL_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_UGO_FOR_ALL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_PULL_LIMIT 10:9 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_PULL_LIMIT_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_PULL_LIMIT_1QUARTER 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_PULL_LIMIT_HALF 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_PULL_LIMIT_3QUARTER 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_1B_DETECT_DISABLE 11:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_1B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_1B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_2B_DETECT_DISABLE 12:12 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_2B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_2B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_4B_DETECT_DISABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_4B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_SDC_4B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_CC_DISABLE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_CC_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_CC_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_ZBC_DISABLE 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_ZBC_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_ZBC_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_UCOMP_MIXED_DISABLE 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_UCOMP_MIXED_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_UCOMP_MIXED_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_DISABLE_PARTIAL_PLC 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_DISABLE_PARTIAL_PLC_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_PLC_CFG0_DISABLE_PARTIAL_PLC_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_REPORT 0x0014031c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_REPORT_SEC_COUNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_REPORT_SEC_COUNT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_REPORT_DED_COUNT 23:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_REPORT_DED_COUNT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS 0x00140320 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS_INFO 22:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS_INFO_BIT 2:0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS_INFO_LINE 19:8 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS_INFO_BANK 21:20 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS_INFO_RAM 22:22 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS_INFO_RAM_0_BYTE 7:3 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ECC_ADDRESS_INFO_RAM_1_BYTE 7:6 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0 0x00140324 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_IDQ_DATA_COUNT 7:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_IDQ_WR_THREAD 8:8 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_IDQ_WR_THREAD_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_IDQ_WR_THREAD_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_DDRQ_DATA 9:9 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_DDRQ_DATA_EMPTY 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_DDRQ_DATA_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_DCRQ_CMD 10:10 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_DCRQ_CMD_EMPTY 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_DCRQ_CMD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_SEQUENCER_STATUS 11:11 /* R-IVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_SEQUENCER_STATUS_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_STATUS_0_SEQUENCER_STATUS_BUSY 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ 0x00140328 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_CWR_DATI_CTRL_LIMIT 13:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_CWR_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_CWR_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_OLD_DATI_CTRL_LIMIT 21:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_OLD_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_OLD_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_SHARED_DATI_CTRL_LIMIT 29:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_WDQ_SHARED_DATI_CTRL_LIMIT_INIT 0x28 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO 0x0014032c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_VIDMEM_LIMIT 9:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_VIDMEM_LIMIT_INIT 0x004 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_SYSMEM_LIMIT 19:10 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_SYSMEM_LIMIT_INIT 0x004 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT 29:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT_CTRL_DISABLED 0x3ff /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_SPARE 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_GATOM_SRC_FIFO_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_INDEX 0x00140338 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_INDEX_ADDRESS 4:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_INDEX_ADDRESS_RESERVED 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_INDEX_RDI_SOURCE 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_INDEX_RDI_SOURCE_DSTG 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_INDEX_RDI_SOURCE_GC 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x0014033c+(i)*4) /* RW-4A */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 /* */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE_FIELD 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x0014034c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_STENCIL_CLEAR_VALUE 0x00140204 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_DSTG_ZBC_STENCIL_CLEAR_VALUE_FIELD 7:0 /* RWXVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM 0x00140350 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_ENABLE 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_ENABLE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT 4:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP0 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP1 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP2 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP3 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP4 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP5 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP6 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP7 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP8 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP9 0x9 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP10 0xa /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP11 0xb /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP12 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP13 0xd /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP14 0xe /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP15 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT 10:5 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_STATIC_PATTERN_5555_16_GROUP 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_STATIC_PATTERN_AAAA_16_GROUP 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP41 0x29 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP42 0x2a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP43 0x2b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP44 0x2c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP45 0x2d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP46 0x2e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP47 0x2f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP48 0x30 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP49 0x31 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP50 0x32 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP51 0x33 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP52 0x34 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP53 0x35 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP54 0x36 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP55 0x37 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP56 0x38 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP57 0x39 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP58 0x3a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP59 0x3b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP60 0x3c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP61 0x3d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP62 0x3e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_GRP63 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT 16:11 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE 22:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_STATIC_PATTERN_5555_16_GROUP 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_STATIC_PATTERN_AAAA_16_GROUP 0x1d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP41 0x29 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP42 0x2a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP43 0x2b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP44 0x2c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP45 0x2d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP46 0x2e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP47 0x2f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP48 0x30 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP49 0x31 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP50 0x32 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP51 0x33 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP52 0x34 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP53 0x35 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP54 0x36 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP55 0x37 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP56 0x38 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP57 0x39 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP58 0x3a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP59 0x3b /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP60 0x3c /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP61 0x3d /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP62 0x3e /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP63 0x3f /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC 0x00140330 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_LAT_SCALE 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_LAT_SCALE_INIT 0x27 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_LAT_SCALE 11:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_LAT_SCALE_INIT 0x27 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE 23:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_INIT 0xb /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_128TH 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_64TH 0xe /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_32ND 0xd /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_16TH 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_8TH 0xb /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_4TH 0xa /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_2ND 0x9 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X1 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X2 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X4 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X8 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X16 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X32 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X64 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X128 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X256 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE 27:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_INIT 0xb /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_128TH 0xf /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_64TH 0xe /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_32ND 0xd /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_16TH 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_8TH 0xb /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_4TH 0xa /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_2ND 0x9 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X1 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X2 0x7 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X4 0x6 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X8 0x5 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X16 0x4 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X32 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X64 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X128 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X256 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL 29:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_10 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_100 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_1000 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_10000 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL 31:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_10 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_100 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_1000 0x2 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_10000 0x3 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR 0x00140354 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_NAN_VALUE 22:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_NAN_VALUE_INIT 0x7fffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_RND 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_RND_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_DAZ_ENABLE 28:28 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_DAZ_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_DAZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_DAZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_FTZ_ENABLE 29:29 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_FTZ_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_FTZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_FTZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_NAN_ENABLE 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_NAN_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_NAN_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_FPADDR_NAN_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC 0x00140358 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_A_MISC__PRIV_LEVEL_MASK 0x001403c0 /* */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_REQ_LIMIT 3:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_REQ_LIMIT_INIT 0xf /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16ADDR_NAN_VALUE 13:4 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16ADDR_NAN_VALUE_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16ADDR_NAN_ENABLE 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16ADDR_NAN_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16ADDR_NAN_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16ADDR_NAN_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16_DAZ_ENABLE 15:15 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16_DAZ_ENABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16_DAZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_A_MISC_FP16_DAZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CG1 0x0014035c /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_CG1__PRIV_LEVEL_MASK 0x001403dc /* */
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#define NV_PLTCG_LTC0_LTSS_CG1_SLCG 31:1 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_CG1_SLCG_DISABLED 0x7fffffff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00140380 /* RWB4R */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX 0x00140360 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX__PRIV_LEVEL_MASK 0x00140380 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_INDEX 7:0 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_INDEX_ZERO 0x00 /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_INDEX_MAX 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_INDEX_MAX_AVAIL 0x1a /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE 16:16 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_INIT 0x0 /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_DATA 0x00140364 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_DATA__PRIV_LEVEL_MASK 0x00140380 /* */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_DATA_DATA 31:0 /* RWBVF */
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#define NV_PLTCG_LTC0_LTSS_BLK_ACT_DATA_DATA_INIT 0x00000000 /* RWB-V */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS 0x00140368 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_KIND 7:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_COMPBITS 9:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_ZDCMP_STATE 12:10 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_IDLE 13:13 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_ARB_IDLE 14:14 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_CDCMP_IDLE 15:15 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_RDAT_FIFO_IDLE 16:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_REQ_FIFO_IDLE 17:17 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_WDAT_FIFO_IDLE 18:18 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_WREQ_FIFO_IDLE 19:19 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_ZDCMP_IDLE 20:20 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_CDCMP_REQ_PVLD 21:21 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_CDCMP_DATA_PVLD 22:22 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_CDCMP_IS_RMW 23:23 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_CDCMP_IS_P2P 24:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_CDCMP_IS_TEX 25:25 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_ZDCMP_REQ_PVLD 26:26 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_ZDCMP_DATA_PVLD 27:27 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_ZDCMP_IS_RMW 28:28 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_ZDCMP_IS_P2P 29:29 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS_CDCMP_STATE 30:30 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS1 0x0014036c /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS1_INPUT_MASK 7:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_DCMP_STATUS1_ROLLING_MASK 15:8 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG 0x001403e0 /* RWI4R */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG__PRIV_LEVEL_MASK 0x001403dc /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG1 0x001403e4 /* RWI4R */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG1__PRIV_LEVEL_MASK 0x001403dc /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG 0x001403f8 /* RWI4R */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG__PRIV_LEVEL_MASK 0x001403dc /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_BLPG_EN 16:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DIS_EARLY_WUP 17:17 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DEEP_ELPG_EN 18:18 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_ELPG_EN 19:19 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DIDT_DELAY 23:20 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_DIDT_DELAY_HWINIT 0xa /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_RESET_DURATION 26:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_RESET_DURATION_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_CLAMP_DELAY 29:27 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_CLAMP_DELAY_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_ZONE_OFF_MASK 30:30 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_SOFT_GATING_EN 31:31 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG1 0x001403fc /* RWI4R */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG1__PRIV_LEVEL_MASK 0x001403dc /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG1_ZONE_SEQ 23:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG1_ZONE_MASK 31:24 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_LTS_PG1_ZONE_MASK_HWINIT 0xff /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG 0x001403c8 /* RWI4R */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG__PRIV_LEVEL_MASK 0x001403dc /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG1 0x001403cc /* RWI4R */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG1__PRIV_LEVEL_MASK 0x001403dc /* */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTC0_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2 0x001403f4 /* R--4R */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE 15:0 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_4 0x0004 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_5 0x0005 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_6 0x0006 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_7 0x0007 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_8 0x0008 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_10 0x000a /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_11 0x000b /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_13 0x000d /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_16 0x0010 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_22 0x0016 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_32 0x0020 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_64 0x0040 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_128 0x0080 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_NUM_CACHE_LINES 23:16 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_NUM_CACHE_LINES_16 0x10 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_NUM_CACHE_LINES_20 0x14 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_NUM_CACHE_LINES_32 0x20 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_NUM_CACHE_LINES_40 0x28 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_NUM_CACHE_LINES_64 0x40 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE 27:24 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_512 0x0 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_1K 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_2K 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_4K 0x3 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_8K 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_16K 0x5 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_32K 0x6 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_64K 0x7 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_SLICES_PER_LTC 31:28 /* R--VF */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_SLICES_PER_LTC_1 0x1 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_SLICES_PER_LTC_2 0x2 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_CBC_PARAM2_SLICES_PER_LTC_4 0x4 /* R---V */
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#define NV_PLTCG_LTC0_LTSS_MISC_CFG 0x00140300 /* RW-4R */
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#define NV_PLTCG_LTC0_LTSS_MISC_CFG__PRIV_LEVEL_MASK 0x00140398 /* */
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#define NV_PLTCG_LTC0_LTSS_MISC_CFG_SPARE 31:0 /* RWIVF */
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#define NV_PLTCG_LTC0_LTSS_MISC_CFG_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTC1 0x00142000 /* RW--L */
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#define NV_PLTCG_LTC1_MISC_LTC_PM 0x00142028 /* RW-4R */
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#define NV_PLTCG_LTC1_LTS0_G_PRI_CBC_CG 0x001425e0 /* RWI4R */
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#define NV_PLTCG_LTC1_LTS1_G_PRI_CBC_CG 0x001427e0 /* RWI4R */
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#define NV_PLTCG_LTC2 0x00144000 /* RW--L */
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#define NV_PLTCG_LTC2_LTS0_G_PRI_CBC_CG 0x001445e0 /* RWI4R */
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#define NV_PLTCG_LTC2_LTS1_G_PRI_CBC_CG 0x001447e0 /* RWI4R */
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#define NV_PLTCG_LTC3 0x00146000 /* RW--L */
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#define NV_PLTCG_LTC3_LTS0_G_PRI_CBC_CG 0x001465e0 /* RWI4R */
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#define NV_PLTCG_LTC3_LTS1_G_PRI_CBC_CG 0x001467e0 /* RWI4R */
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#define NV_PLTCG_LTC4 0x00148000 /* RW--L */
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#define NV_PLTCG_LTC4_LTS0_G_PRI_CBC_CG 0x001485e0 /* RWI4R */
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#define NV_PLTCG_LTC4_LTS1_G_PRI_CBC_CG 0x001487e0 /* RWI4R */
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#define NV_PLTCG_LTC5 0x0014a000 /* RW--L */
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#define NV_PLTCG_LTC5_LTS0_G_PRI_CBC_CG 0x0014a5e0 /* RWI4R */
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#define NV_PLTCG_LTC5_LTS1_G_PRI_CBC_CG 0x0014a7e0 /* RWI4R */
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#define NV_PLTCG_LTC6 0x0014c000 /* RW--L */
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#define NV_PLTCG_LTC6_LTS0_G_PRI_CBC_CG 0x0014c5e0 /* RWI4R */
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#define NV_PLTCG_LTC6_LTS1_G_PRI_CBC_CG 0x0014c7e0 /* RWI4R */
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#define NV_PLTCG_LTC7 0x0014e000 /* RW--L */
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#define NV_PLTCG_LTC7_LTS0_G_PRI_CBC_CG 0x0014e5e0 /* RWI4R */
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#define NV_PLTCG_LTC7_LTS1_G_PRI_CBC_CG 0x0014e7e0 /* RWI4R */
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#define NV_PLTCG_LTC8 0x00150000 /* RW--L */
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#define NV_PLTCG_LTC8_LTS0_G_PRI_CBC_CG 0x001505e0 /* RWI4R */
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#define NV_PLTCG_LTC8_LTS1_G_PRI_CBC_CG 0x001507e0 /* RWI4R */
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#define NV_PLTCG_LTC9 0x00152000 /* RW--L */
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#define NV_PLTCG_LTC9_LTS0_G_PRI_CBC_CG 0x001525e0 /* RWI4R */
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#define NV_PLTCG_LTC9_LTS1_G_PRI_CBC_CG 0x001527e0 /* RWI4R */
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#define NV_PLTCG_LTC10 0x00154000 /* RW--L */
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#define NV_PLTCG_LTC11 0x00156000 /* RW--L */
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#define NV_PLTCG_LTCS 0x0017e000 /* RW--L */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK 0x0017e064 /* RWE4R */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cgate" /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_MISC_LTC_NUM_ACTIVE_LTCS 0x0017e000 /* RW-4R */
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#define NV_PLTCG_LTCS_MISC_LTC_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_LTC_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_FB_ID 0x0017e018 /* R--4R */
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#define NV_PLTCG_LTCS_MISC_FB_ID_VAL 7:0 /* R-XVF */
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#define NV_PLTCG_LTCS_MISC_LTC_PM 0x0017e028 /* RW-4R */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_ENABLE 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_ENABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT 3:1 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_GRP0 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_GRP1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_GRP2 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_GRP3 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_GRP4 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_GRP5 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_GRP6 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SELECT_STATIC_PATTERN_AA_8_GROUP 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT 6:4 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_0 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_2 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_3 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_4 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_5 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_6 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_VC_SELECT_ALL 0x7 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SECTOR_COUNT_SELECT 8:7 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SECTOR_COUNT_SELECT_REQUEST 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SECTOR_COUNT_SELECT_MISS 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_PM_SECTOR_COUNT_SELECT_HIT 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG 0x0017e02c /* RW-4R */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_NUM_ACTIVE_LTS_PER_LTC 2:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_NUM_ACTIVE_LTS_PER_LTC_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_NUM_ACTIVE_LTS_PER_LTC_MAX 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION 6:4 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION_MIN 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_NUM_LTS_PER_SUBPARTITION_MAX 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_LOWER_LTS_PAIR 8:8 /* R-XVF */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_LOWER_LTS_PAIR_DISABLED 0x1 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_LOWER_LTS_PAIR_ENABLED 0x0 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_UPPER_LTS_PAIR 9:9 /* R-XVF */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_UPPER_LTS_PAIR_DISABLED 0x1 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_UPPER_LTS_PAIR_ENABLED 0x0 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_SLICE_DISABLE 13:10 /* R-XVF */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_SLICE_DISABLE_ALL_ENABLED 0x0 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE0_DISABLED 0x1 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE1_DISABLED 0x2 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE2_DISABLED 0x4 /* R---V */
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#define NV_PLTCG_LTCS_MISC_LTC_CFG_FS_SLICE_DISABLE_SLICE3_DISABLED 0x8 /* R---V */
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#define NV_PLTCG_LTCS_MISC_CG1 0x0017e050 /* RW-4R */
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#define NV_PLTCG_LTCS_MISC_CG1__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_CG1_SLCG 31:1 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_CG1_SLCG_DISABLED 0x7fffffff /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG 0x0017e030 /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG1 0x0017e034 /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG1__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG 0x0017e038 /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_EN 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DIS_EARLY_WUP 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DEEP_ELPG_EN 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_ELPG_EN 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DIDT_DELAY 23:20 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_DIDT_DELAY_HWINIT 0xa /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_RESET_DURATION 26:24 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_RESET_DURATION_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_CLAMP_DELAY 29:27 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_CLAMP_DELAY_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_ZONE_OFF_MASK 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_SOFT_GATING_EN 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG1 0x0017e03c /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG1__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG1_ZONE_SEQ 23:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG1_ZONE_MASK 31:24 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_DCMP_PRI_DCMP_PG1_ZONE_MASK_HWINIT 0xff /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG 0x0017e040 /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG1 0x0017e044 /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG1__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG 0x0017e048 /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_BLPG_EN 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DIS_EARLY_WUP 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DEEP_ELPG_EN 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_ELPG_EN 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DIDT_DELAY 23:20 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_DIDT_DELAY_HWINIT 0xa /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_RESET_DURATION 26:24 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_RESET_DURATION_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_CLAMP_DELAY 29:27 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_CLAMP_DELAY_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_ZONE_OFF_MASK 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_SOFT_GATING_EN 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG1 0x0017e04c /* RWI4R */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG1__PRIV_LEVEL_MASK 0x0017e064 /* */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG1_ZONE_SEQ 23:0 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWI-V */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG1_ZONE_MASK 31:24 /* RWIVF */
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#define NV_PLTCG_LTCS_MISC_PRI_LTC_PG1_ZONE_MASK_HWINIT 0xff /* RWI-V */
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#define NV_PLTCG_LTCS_LTS0 0x0017e400 /* RW--L */
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#define NV_PLTCG_LTCS_LTS1 0x0017e600 /* RW--L */
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#define NV_PLTCG_LTCS_LTS2 0x0017e800 /* RW--L */
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#define NV_PLTCG_LTCS_LTS3 0x0017ea00 /* RW--L */
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#define NV_PLTCG_LTCS_LTSS 0x0017e200 /* RW--L */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK 0x0017e218 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_iq" /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK 0x0017e3a8 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cbc" /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK 0x0017e3d8 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_vpr_leakage" /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_VPR_LEAKAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK 0x0017e3d4 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_dstg" /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK 0x0017e3c4 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya_ecc" /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK 0x0017e390 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_SRAM_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK 0x0017e3c0 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya" /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK 0x0017e3d0 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_tstg" /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK 0x0017e3bc /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK 0x0017e384 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK 0x0017e3dc /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cgate" /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CGATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK 0x0017e394 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK 0x0017e398 /* RWE4R */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "plts_cya_coh" /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PLTCG_LTCS_LTSS_CYA_COH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL 0x0017e2e4 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL__PRIV_LEVEL_MASK 0x0017e3d8 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX 15:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_MIN 0x0000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_MAX 0x001c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CONFIG 0x0000 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TRIGGER_CTL 0x0001 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_1 0x0002 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_2 0x0003 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_3 0x0004 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_CTL_4 0x0005 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_MASK_LO 0x0006 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_MASK_HI 0x0007 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_VAL_LO 0x0008 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_TRIGGER_PADR_VAL_HI 0x0009 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_1 0x000a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_2 0x000b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_3 0x000c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_CTL_4 0x000d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_MASK_LO 0x000e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_MASK_HI 0x000f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_VAL_LO 0x0010 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_TAG_SAMPLE_PADR_VAL_HI 0x0011 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DIN_TRIGGER_CTL 0x0012 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DOUT_TRIGGER_CTL 0x0013 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DATA_TRIGGER_VAL_LO 0x0014 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DATA_TRIGGER_VAL_HI 0x0015 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DIN_SAMPLE_CTL 0x0016 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_DOUT_SAMPLE_CTL 0x0017 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_CTL 0x0018 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_BUFFER_DEPTH 0x0019 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_STATUS 0x001a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_CAPTURE_STATUS_2 0x001b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILA_BUFFER_READ 0x001c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_CBC_DEBUG 0x0100 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_TG_DEBUG 0x0101 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE1_INFO0 0x0102 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE1_INFO1 0x0103 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE2_INFO0 0x0104 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_INDEX_ILLEGAL_ACCESS_KIND_TYPE2_INFO1 0x0105 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_READINCR 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_READINCR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_READINCR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_WRITEINCR 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_WRITEINCR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_CTRL_WRITEINCR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE 0x0017e2e8 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE__PRIV_LEVEL_MASK 0x0017e3d8 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_VAL 31:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA 1:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_USECBC_PARTIAL 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_USECBC_FULL 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_ILA_TRIGGER_ONLY 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE 5:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_A 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CONFIG_SAMPLEMODE_C 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TAG_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DIN_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_DOUT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_TSTAMP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_PMON_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_GLOBAL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TSTAMP_TRIG_BIT 12:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TSTAMP_TRIG_BIT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC 15:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_ZERO 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_12_5 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_25_0 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_37_5 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_50_0 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_62_5 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_75_0 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_POST_STORE_PERC_87_5 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_EV_CNT 31:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TRIGGER_CTL_TRIGGER_EV_CNT_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK 3:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S0_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S1_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S2_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SECTOR_MASK_S3_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK 7:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_LOCAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_PEER_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_COH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_APERTURE_MASK_SYS_NCOH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK 11:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_NONE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_N_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_I_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_SENT_PRB_TYPE_MASK_X_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK 15:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_I_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_X_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_E_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_REQ_STATE_MASK_M_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK 17:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_ALL_ENABLE 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_NO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_PROBING_MASK_YES_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK 30:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_ALL_ENABLE 0x7 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_COMMIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_RESERVED 31:31 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_1_RESERVED_VAL 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_ISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NISO_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_BLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESP_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PF_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED7_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED8_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED9_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED10_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED11_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED12_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_CBC_NISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_PLC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_LL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_UCTRL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED20_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED21_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED22_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED23_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED25_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED26_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED27_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED28_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED29_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_2_VC_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_PREFETCH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RD_RWC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DOWNGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_RMW_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_TRANSDONE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_CLEAN_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GATOMIC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GRED_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_EVICTION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_UPROBE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PF_FLUSH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_SYSMEM_WT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_PLC_WB_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_3_CMD_MASK_DEMOTE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_ID 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK 13:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_NODE_MASK_EXACT 0x3f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_ID 22:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK 30:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_CTL_4_UNIT_MASK_EXACT 0x7f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE_INCLUSIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MATCH_MODE_EXCLUSIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_ADDRESS_OF_INTEREST_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MASK 31:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_LO_MASK_ALL_ADDRESSES 0x0000000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_HI_MASK 23:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_MASK_HI_MASK_ALL_ADDRESSES 0x000000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_VAL_LO_PADR 31:7 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_TRIGGER_PADR_VAL_HI_PADR 23:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK 3:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S0_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S1_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S2_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SECTOR_MASK_S3_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK 7:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_LOCAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_PEER_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_COH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_APERTURE_MASK_SYS_NCOH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK 11:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_NONE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_N_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_I_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SENT_PRB_TYPE_MASK_X_MO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK 15:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_ALL_ENABLE 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_I_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_X_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_E_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_REQ_STATE_MASK_M_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK 17:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_ALL_ENABLE 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_NO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_PROBING_MASK_YES_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK 30:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_ALL_ENABLE 0x7 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_COMMIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_ALLOC_MASK_REPL_NOT_HEAD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_1_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_ISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NISO_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_NONBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_BLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESP_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_PF_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED7_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED8_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED9_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED10_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED11_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED12_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_NISO_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_CBC_PLC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_LL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCREQ_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UBLOCKING_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_UCTRL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED20_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED21_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED22_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED23_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED25_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED26_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED27_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED28_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED29_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_2_VC_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK 31:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ALL_ENABLE 0xffffffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_PREFETCH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RD_RWC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_UPGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_NORMAL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_WR_EVICT_LAST_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_DOWNGRADE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RMW_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_TRANSDONE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_NO_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_MEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_CLEAN_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_INVALIDATE_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GATOMIC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GRED_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PROBE_RESPONSE_DATA_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_EVICTION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_GMEMBAR_WITH_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED24_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ZBC_2X_WR_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PF_FLUSH_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_SYSMEM_WT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_PLC_WB_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_ECC_DIRTY_GENERATION_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED30_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_3_CMD_MASK_RESERVED31_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_ID 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK 13:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_NODE_MASK_EXACT 0x3f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_ID 22:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_ID_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK 30:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK_ALL 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_CTL_4_UNIT_MASK_EXACT 0x7f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE_INCLUSIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MATCH_MODE_EXCLUSIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_ADDRESS_OF_INTEREST_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MASK 31:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_LO_MASK_ALL_ADDRESSES 0x0000000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_HI_MASK 23:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_MASK_HI_MASK_ALL_ADDRESSES 0x000000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_VAL_LO_PADR 31:7 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TAG_SAMPLE_PADR_VAL_HI_PADR 23:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_BYTE_MASK 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_BYTE_MASK_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_QWORD_SEL 9:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_QWORD_SEL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_SPKT_MASK 25:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_SPKT_MASK_ALL_ENABLE 0x3ff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_TRIGGER_CTL_INVERT_MATCH_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_BYTE_MASK 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_BYTE_MASK_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_QWORD_SEL 9:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_QWORD_SEL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_SPKT_MASK 23:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_SPKT_MASK_ALL_ENABLE 0xff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_TRIGGER_CTL_INVERT_MATCH_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DATA_TRIGGER_VAL_LO_DATA 31:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DATA_TRIGGER_VAL_HI_DATA 31:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_DATA_SEL 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_DATA_SEL_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SPKT_MASK 17:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SPKT_MASK_ALL_ENABLE 0x3ff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DIN_SAMPLE_CTL_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_DATA_SEL 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_DATA_SEL_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SPKT_MASK 15:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SPKT_MASK_ALL_ENABLE 0xff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_DOUT_SAMPLE_CTL_SAMPLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_ARM_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE_TRIGGER 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_CTL_CAPTURE_MODE_PMON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_CNT 15:0 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_CNT_INIT 0x0000 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE 31:31 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE_128BIT 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_DEPTH_SAMPLE_SIZE_256BIT 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INDEX 11:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED 14:14 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGERED_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE 15:15 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_TRIGGER_INCL_SAMPLE_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_LAST_INDEX 27:16 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_LAST_INDEX_INIT 0x000 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY 30:30 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY_FALSE 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_EMPTY_TRUE 0x1 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED 31:31 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_BUF_WRAPPED_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON 5:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG 0:0 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TAG_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN 1:1 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DIN_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT 2:2 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_DOUT_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP 3:3 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_TIMESTAMP_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON 4:4 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_PMON_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL 5:5 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CAPTURE_STATUS_2_TRIGGER_REASON_GLOBAL_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_BUFFER_READ 31:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_CBC_DEBUG 31:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_TG_DEBUG 31:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE1_INFO0 31:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE1_INFO1 31:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE2_INFO0 31:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_DFD_APERTURE_ILA_ILLEGAL_ACCESS_KIND_TYPE2_INFO1 31:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL 0x0017e2ec /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL__PRIV_LEVEL_MASK 0x0017e390 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_RSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_RSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_TSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_DSTG__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_DSTG__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_CORRECTED_ERR_CLIENT_POISON_RETURNED__NOP 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_TASK 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CONTROL_INJECT_UNCORRECTED_ERR_CLIENT_POISON_RETURNED__NOP 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS 0x0017e2f0 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_RSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_RSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_DSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_DSTG_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_CLIENT_POISON_RETURNED_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_CLIENT_POISON_RETURNED_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_RESET 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_RESET_TASK 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_STATUS_RESET_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT 0x0017e2f4 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT 0x0017e2f8 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS 0x0017e2fc /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_INDEX 31:0 /* R-XVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_LOCATION 21:0 /* R-XVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM 29:22 /* R-XVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM0 0x00 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM1 0x01 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM2 0x02 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM3 0x03 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO0 0x00 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO1 0x01 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM0 0x02 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM1 0x03 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM2 0x04 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM3 0x05 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM4 0x06 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM5 0x07 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM6 0x08 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM7 0x09 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM0 0x0a /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM1 0x0b /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM2 0x0c /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM3 0x0d /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM4 0x0e /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM5 0x0f /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM6 0x10 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM7 0x11 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM0 0x12 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM1 0x13 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM2 0x14 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM3 0x15 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM4 0x16 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM5 0x17 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM6 0x18 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM7 0x19 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRA_RAM 0x1a /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_LRU_RAM 0x1b /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM 0x1c /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM 0x1d /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_COPY_RAM 0x1e /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_STATE 0x1f /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_PAIR 0x20 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_PLC_INFO 0x21 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_RAM 0x22 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_LRU_RAM 0x23 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO2 0x24 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_LCN_COMP_STAT 0x25 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS 0x26 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM0 0x00 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM1 0x01 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM2 0x02 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM3 0x03 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM4 0x04 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM5 0x05 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM6 0x06 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM7 0x07 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK0 0x08 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK1 0x09 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK2 0x0a /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK3 0x0b /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT 31:30 /* R-XVF */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_RSTG 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_TSTG 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_DSTG 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_SUBUNIT_CLIENT_POISON_RETURNED 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM0_ROW 9:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM1_ROW 9:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM2_ROW 9:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_RSTG_CBC_RAM3_ROW 9:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO0_ROW 8:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO1_ROW 8:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_TRLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_FULLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_CST_DIRTYRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRA_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_LRU_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM_SLICE 3:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_NO_LRU_RAM_ROW 11:4 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM_SLICE 3:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRL_NO_SECTOR_RAM_ROW 11:4 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_PF_LRU_RAM_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_RR_FREE_FIFO2_ROW 8:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_SRV_LCN_COMP_STAT_ROW 11:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS_SLICE 3:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_TSTG_TG_TRC_PRECIOUS_ROW 11:4 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM0_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM1_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM2_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM3_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM4_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM5_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM6_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_CLRBE_TRLRAM7_ROW 7:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK0_ROW 11:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK1_ROW 11:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK2_ROW 11:0 /* */
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#define NV_PLTCG_LTCS_LTSS_L2_CACHE_ECC_ADDRESS_RAM_DSTG_DB_BANK3_ROW 11:0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CST_RDI_INDEX 0x0017e200 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CST_RDI_INDEX_ADDRESS 15:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CST_RDI_INDEX_ADDRESS_INIT 0x0000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CST_RDI_INDEX_ADDRESS_MAX 0xffff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CST_RDI_DATA(i) (0x0017e3ac+(i)*4) /* R--4A */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CST_RDI_DATA__SIZE_1 4 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CST_RDI_DATA_FIELD 31:0 /* R-XVF */
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#define NV_PLTCG_LTCS_LTSS_INTR 0x0017e20c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_IQ 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_IQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_IQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_IQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_CBC 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_CBC_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_CBC_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_CBC_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_TSTG 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_TSTG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_TSTG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_TSTG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_DSTG 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_DSTG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_DSTG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_IDLE_ERROR_DSTG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_EVICTED_CB 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EVICTED_CB_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EVICTED_CB_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EVICTED_CB_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLOCKLINEAR_CB 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLOCKLINEAR_CB_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLOCKLINEAR_CB_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLOCKLINEAR_CB_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_SEC_ERROR 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_SEC_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_SEC_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_SEC_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_DED_ERROR 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_DED_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_DED_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ECC_DED_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_DEBUG 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_DEBUG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_DEBUG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_DEBUG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_ATOMIC_TO_Z 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_ATOMIC_TO_Z_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ATOMIC_TO_Z_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ATOMIC_TO_Z_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_ATOMIC 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_ATOMIC_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_ATOMIC_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_ATOMIC_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLKACTIVITY_ERR 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLKACTIVITY_ERR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLKACTIVITY_ERR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_BLKACTIVITY_ERR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR_ILLEGAL_COMPSTAT_ACCESS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_IQ 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_IQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_IQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_CBC 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_CBC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_CBC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_TSTG 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_TSTG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_TSTG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_DSTG 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_DSTG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_IDLE_ERROR_DSTG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_EVICTED_CB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_BLOCKLINEAR_CB 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_BLOCKLINEAR_CB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_BLOCKLINEAR_CB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ECC_SEC_ERROR 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ECC_SEC_ERROR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ECC_SEC_ERROR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ECC_DED_ERROR 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ECC_DED_ERROR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ECC_DED_ERROR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_DEBUG 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_DEBUG_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_DEBUG_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ATOMIC_TO_Z 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ATOMIC_TO_Z_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ATOMIC_TO_Z_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_ATOMIC 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_ATOMIC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_ATOMIC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_BLKACTIVITY_ERR 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_BLKACTIVITY_ERR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_BLKACTIVITY_ERR_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR_EN_ILLEGAL_COMPSTAT_ACCESS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2 0x0017e208 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_INVALID_TDTAG 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_INVALID_TDTAG_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_INVALID_TDTAG_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_INVALID_TDTAG_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_TRDONE 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_TRDONE_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_TRDONE_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_TRDONE_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_INVALID_SUBID 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_PRBRS 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIN_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBIMO_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_MISSING_DATA 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_MISSING_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_MISSING_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_MISSING_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_UNEXPECTED_DATA 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_UNEXPECTED_DATA_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_UNEXPECTED_DATA_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBX_UNEXPECTED_DATA_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_UNEXPECTED_PA7 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_UNEXPECTED_PA7_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_UNEXPECTED_PA7_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_PRBRS_UNEXPECTED_PA7_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_UNEXPECTED_PA7 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_UNEXPECTED_PA7_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_UNEXPECTED_PA7_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_TRDONE_UNEXPECTED_PA7_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_SYSFILL_BYPASS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_UNEXPECTED_SYSFILL_BYPASS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_PRBRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_CHECKEDIN_UNEXPECTED_TRDONE_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_TRDONE_INVALID_TDTAG 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_TRDONE_INVALID_TDTAG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_TRDONE_INVALID_TDTAG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_TRDONE 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_TRDONE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_TRDONE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_RWC_UPG_UNEXPECTED_TRDONE_CANCEL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBRS_INVALID_SUBID 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBRS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBRS_INVALID_SUBID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_PRBRS 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBIN_UNEXPECTED_PRBRS 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBIN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBIN_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBIMO_UNEXPECTED_PRBRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBX_MISSING_DATA 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBX_MISSING_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBX_MISSING_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBX_UNEXPECTED_DATA 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBX_UNEXPECTED_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBX_UNEXPECTED_DATA_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBRS_UNEXPECTED_PA7 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBRS_UNEXPECTED_PA7_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_PRBRS_UNEXPECTED_PA7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_TRDONE_UNEXPECTED_PA7 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_TRDONE_UNEXPECTED_PA7_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_TRDONE_UNEXPECTED_PA7_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_SYSFILL_BYPASS_INVALID_SUBID_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_UNEXPECTED_SYSFILL_BYPASS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_PRBRS_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR2_EN_CHECKEDIN_UNEXPECTED_TRDONE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3 0x0017e388 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_NINB_NCNP_REQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CHECKEDOUT_CREQ_NCNP_REQ_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_RMWRS_INVALID_SUBID 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_RMWRS_INVALID_SUBID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_RMWRS_INVALID_SUBID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_RMWRS_INVALID_SUBID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_UNEXPECTED_RMWRS 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_UNEXPECTED_RMWRS_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_UNEXPECTED_RMWRS_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_UNEXPECTED_RMWRS_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ECC_CORRECTED 7:7 /* R-XVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ECC_CORRECTED_NOT_PENDING 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ECC_CORRECTED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ECC_UNCORRECTED 8:8 /* R-XVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ECC_UNCORRECTED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_VOLATILE_TO_COMPRESSED 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_VOLATILE_TO_COMPRESSED_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_VOLATILE_TO_COMPRESSED_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_VOLATILE_TO_COMPRESSED_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE1_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_ILLEGAL_ACCESS_KIND_TYPE2_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_KIND_INVALID 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_KIND_INVALID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_KIND_INVALID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_KIND_INVALID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_COMPTAG_INVALID 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_COMPTAG_INVALID_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_COMPTAG_INVALID_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_DTM_COMPTAG_INVALID_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CDCMP_IP_ERROR 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CDCMP_IP_ERROR_NOT_PENDING 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CDCMP_IP_ERROR_PENDING 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_CDCMP_IP_ERROR_RESET 0x1 /* -W--C */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_RWC_UPG_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_TRDONE_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_PRBRS_UNEXPECTED_NVPORT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_NINB_NCNP_REQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CHECKEDOUT_CREQ_NCNP_REQ_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_RMWRS_INVALID_SUBID 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_RMWRS_INVALID_SUBID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_RMWRS_INVALID_SUBID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_UNEXPECTED_RMWRS 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_UNEXPECTED_RMWRS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_UNEXPECTED_RMWRS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_VOLATILE_TO_COMPRESSED 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_VOLATILE_TO_COMPRESSED_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_VOLATILE_TO_COMPRESSED_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE1_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_ILLEGAL_ACCESS_KIND_TYPE2_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_DTM_KIND_INVALID 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_DTM_KIND_INVALID_ENABLED 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_DTM_KIND_INVALID_DISABLED 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_DTM_COMPTAG_INVALID 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_DTM_COMPTAG_INVALID_ENABLED 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_DTM_COMPTAG_INVALID_DISABLED 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CDCMP_IP_ERROR 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CDCMP_IP_ERROR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_INTR3_EN_CDCMP_IP_ERROR_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS 0x0017e210 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_LTC_STOP 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_LTC_STOP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_LTC_STOP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_RSTG_BUSY 8:8 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_TSTG_BUSY 9:9 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_DSTG_BUSY 10:10 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_A_BUSY 11:11 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_WAITING_FOR_XBAR_CMD_CREDITS 20:20 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_WAITING_FOR_XBAR_DATA_CREDITS 21:21 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_STATUS_WAITING_FOR_SYSMEM_FILL_DATA 22:22 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG 0x0017e214 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH_ABORT 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH_ABORT_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_FLUSH_ABORT_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_STATUS_CBC_NOT_READY 8:8 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_ELPG_STATUS_TSTG_NOT_READY 9:9 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0 0x0017e21c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0__PRIV_LEVEL_MASK 0x0017e3c4 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_OVERRIDE_SYSMEM_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_PITCH_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_COLOR_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_DEPTH_ECC_MISS_MASK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_USE_CMGMT_PER_LINE_CLASS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_EVICT_NORMAL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_TO_GENERIC 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_TO_GENERIC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_TO_GENERIC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_TO_GENERIC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_REMAP_COMPRESSIBLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_STATUS_SELECT 19:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_STATUS_SELECT_INIT 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_STATUS_SELECT_DISABLED 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_FORCE_CREQ_RD_NCP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_SPARE 31:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_SPARE_UCREQ_LIVELOCK_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_CFG_0_SPARE_UCREQ_LIVELOCK_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_XBAR_STATUS_0 0x0017e220 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_XBAR_STATUS_0_VALUE 31:0 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_XBAR_STATUS_0_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0 0x0017e23c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0__PRIV_LEVEL_MASK 0x0017e218 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_ISO_WEIGHT 2:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_ISO_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_NISO_NB_WEIGHT 6:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_NISO_NB_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_NISO_NB_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_PLC_WEIGHT 10:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_PLC_WEIGHT_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_PLC_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_NB_WEIGHT 14:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_NB_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_B_WEIGHT 18:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_B_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_RESP_WEIGHT 22:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_RESP_WEIGHT_INIT 0x7 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_RESP_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_CREQ_WEIGHT 26:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_WRR_CREQ_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_RESP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_0_LIVELOCK_CREQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1 0x0017e240 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1__PRIV_LEVEL_MASK 0x0017e218 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1_WRR_LL_WEIGHT 6:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1_WRR_LL_WEIGHT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY_LOW 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY_HI 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_1_LL_PRIORITY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3 0x0017e244 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3__PRIV_LEVEL_MASK 0x0017e218 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG 3:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_TIMEOUT_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG 7:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG_INIT 0xa /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_END_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG 10:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_START_LOG_MAX 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_LFSR_OFFSET_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG 14:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_DELAY_RATE_LOG_MAX 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_ISO_NACK_CTRL_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE_AFTER_DRAINING_PENDING 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_RECIRCULATE_IMMEDIATELY 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NISO_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ISO_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_B_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_SPARE_25 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_SPARE_25_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_SINGLE_STEP_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_REPEAT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG 31:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_MIN 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_GENERAL_3_LIVELOCK_ABORT_LOG_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0 0x0017e248 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0__PRIV_LEVEL_MASK 0x0017e218 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_COUNT_MULT64_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_B 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_B_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_B_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_B_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_NISO_NB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_RESP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_ARB_VERIF_0_THROTTLE_CREQ_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0 0x0017e260 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_MODE_TIMEOUT 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_MODE_TIMEOUT_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_GPC_SYSWR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_HUB_SYSWR_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_FNIC2LTC_FILL 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_BALANCE_LTC2FNIC_REQ 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_TIMEOUT 27:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_BALANCE_TIMEOUT_INIT 0xf80 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_REQUEST_BASED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_IQ_SYSWR_CTRL_0_COUNTER_MECHANISM_SUBPACKET_BASED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0 0x0017e264 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_ECO_CYA 2:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_ECO_CYA_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_PLC_128B_OPTIMIZATION__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS 10:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CFG_0_MAX_CYCLES_BETWEEN_CLEARS_UNLIMITED 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0 0x0017e268 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_MAX 0x36 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_UNALLOC_VC_INTERLOCK 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_UNALLOC_VC_INTERLOCK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_UNALLOC_VC_INTERLOCK_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_MIN_LIMIT 11:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_MIN_LIMIT_INIT 0x6 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_NUM_ACTIVE_LINES 19:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_NUM_ACTIVE_LINES_INIT 0x40 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_NUM_ACTIVE_LINES_ALL 0x40 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_LRU_LINE_ON_MISS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_CLEAN_THRESHOLD_INCLUDES_FILLS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_ILLEGAL_COMPSTAT_SCRUBBER_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_0_IGNORE_FILL_HELD_UNTIL_HIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1 0x0017e26c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAN_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_INVALIDATE_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_CLEAR_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_ACTIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_1_DISABLE_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2 0x0017e270 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND 19:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_2_CLEAR_LOWER_BOUND_INIT 0x00000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3 0x0017e274 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND 19:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CTRL_3_CLEAR_UPPER_BOUND_INIT 0xfffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_BASE 0x0017e278 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_BASE__PRIV_LEVEL_MASK 0x0017e3a8 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ALIGNMENT_SHIFT 0x0000000b /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_BASE_ADDRESS 25:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_BASE_HUB_SAFE 31:31 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS 0x0017e27c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS__PRIV_LEVEL_MASK 0x0017e394 /* */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_V_INIT 0x01 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_OVERRIDE_PEER_VOL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_SERIALIZE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_COMPTAG_AS_ADR_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_OFF 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_NUM_ACTIVE_LTCS_PEER_NEW_ADR_COMPARE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM 0x0017e280 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE 9:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_4 0x004 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_5 0x005 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_6 0x006 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_7 0x007 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_8 0x008 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_10 0x00a /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_11 0x00b /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_12 0x00c /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_13 0x00d /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_14 0x00e /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_16 0x010 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_20 0x014 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_22 0x016 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_24 0x018 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_26 0x01a /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_28 0x01c /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_32 0x020 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_44 0x02c /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_64 0x040 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_BYTES_PER_COMPTAGLINE_PER_SLICE_128 0x080 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING 11:10 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_2K 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_4K 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_8K 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_DIVIDE_ROUNDING_16K 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING 13:12 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_64K 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_128K 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_256K 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_AMAP_SWIZZLE_ROUNDING_512K 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_NUM_CACHE_LINES 23:16 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_NUM_CACHE_LINES_16 0x10 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_NUM_CACHE_LINES_20 0x14 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_NUM_CACHE_LINES_32 0x20 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_NUM_CACHE_LINES_40 0x28 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_NUM_CACHE_LINES_64 0x40 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE 27:24 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_512 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_1K 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_2K 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_4K 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_8K 0x4 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_16K 0x5 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_32K 0x6 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_CACHE_LINE_SIZE_64K 0x7 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC 31:28 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC_2 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC_3 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM_SLICES_PER_LTC_4 0x4 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CLEAR_GOB_VALUE 0x0017e3a4 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_CLEAR_GOB_VALUE_COMPBITS 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CBC_CLEAR_GOB_VALUE_COMPBITS_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CBC_CLEAR_GOB_VALUE_COMPBITS_UNCOMPRESSED 0x00 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS 0x0017e28c /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_FILL_CMD_STATE 2:1 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_CLEAN_CMD_STATE 5:3 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_EVICT_DATA_STATE 7:6 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_CLEAR_CMD_STATE 11:8 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_NUM_WRITEBUFF_REQ 15:12 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_PIPE_VLD 16:16 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_WRITEBUFF_COMMIT_VLD 17:17 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_AVAIL_LRU_TAG_VLD 18:18 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_AVAIL_DIRTY_TAG_VLD 19:19 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_FILL_PEND 20:20 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_CLEAN_PEND 21:21 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_STATUS_DIRTY_PEND 22:22 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0 0x0017e290 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0__PRIV_LEVEL_MASK 0x0017e3d0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK_TO_CROP 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_LDST_ON_ATOMIC_LOCK_STALL 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_CROP_RDWR 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_CROP_RDWR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_CROP_RDWR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_ZROP_RDWR 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_ZROP_RDWR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_ZROP_RDWR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_NISO_NB_WR 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_NISO_NB_WR_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_NISO_NB_WR_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_HOLD_INUSE 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_HOLD_INUSE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_HOLD_INUSE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_FORCE_LDST_TO_ATM 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_FORCE_LDST_TO_ATM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_FORCE_LDST_TO_ATM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_FORCE_MEMBAR_TO_ATM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_TEST_WITHOUT_FB 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_TEST_WITHOUT_FB_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_TEST_WITHOUT_FB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_VOLATILE_READ 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_VOLATILE_READ_PER_SECTOR 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_VOLATILE_READ_PER_LINE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_VOLATILE_PART_CLR_FULL 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_VOLATILE_PART_CLR_FULL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_RESERVE_COUNT_FOR_ISO_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_RMW 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_RMW_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_RMW_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_ISO_RD 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_ISO_RD_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_INTERLOCK_ISO_RD_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_SAME_SET 20:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_SAME_SET_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_SAME_SET_ONE_CYCLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_SAME_SET_TWO_CYCLES 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_SAME_SET_ONE_AND_TWO_CYCLES 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_NISO_NB_READ_SET_TRSHLD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_ISO_WITHOUT_ICC 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_ISO_WITHOUT_ICC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_ISO_WITHOUT_ICC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_SPARE 28:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_SPARE_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_L2_ECC_ACCUMULATE_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_L2_ECC_FILL_ON_WR 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_L2_ECC_FILL_ON_WR_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_0_L2_ECC_FILL_ON_WR_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4 0x0017e334 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4__PRIV_LEVEL_MASK 0x0017e384 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_NISO_NB_VID_WR_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_VOL_BYPASS_GATOM 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_VOL_BYPASS_GATOM_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_VOL_BYPASS_GATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FORCE_ISO_MISS 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FORCE_ISO_MISS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FORCE_ISO_MISS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_RD_CACHING 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_RD_CACHING_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_RD_CACHING_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHING 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHING_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHING_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_VOLBYPASS 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_VOLBYPASS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_VOLBYPASS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_WR_CACHE_PARTIAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_LC_PROMOTION_MISS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_CACHE_STRONG_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_COMPREQ_PROMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_POC_FORCE_EVICT_FIRST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_LCN_FORCE_EVICT_FIRST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_FASTTRACK_LCN_CACHEABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_UGPU_INTLCK_VCWR_VCUWR_BYPASS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FAIL_GC_COND_RD 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FAIL_GC_COND_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FAIL_GC_COND_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_LC_PROMOTION 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_LC_PROMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_LC_PROMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_MMU_NISO_NB_TO_VC_LL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_PREFETCH_AS_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_DGDTD_PRBXNXRSP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_INTERLOCK_DGD_UPGRWC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_PREFETCH 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_PREFETCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_PREFETCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_SOFT_PREFETCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_256B_PROMOTE 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_256B_PROMOTE_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_256B_PROMOTE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_ISO_CBC_RD 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_ISO_CBC_RD_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SAME_SET_ISO_CBC_RD_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_CMGMT_PLC_INVALID 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_CMGMT_PLC_INVALID_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_CMGMT_PLC_INVALID_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_CMGMT_PLC_INFLIGHT 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_CMGMT_PLC_INFLIGHT_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_CMGMT_PLC_INFLIGHT_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SPKT_FULL_SETS_RDREQ_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_GMK_COLOR_128B_RMW 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_GMK_COLOR_128B_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_GMK_COLOR_128B_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SEND_CR_ON_MISS 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SEND_CR_ON_MISS_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_SEND_CR_ON_MISS_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_NISO_NB_TO_VC_LL 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_NISO_NB_TO_VC_LL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_NISO_NB_TO_VC_LL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FAIL_GMK_COND_RD 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FAIL_GMK_COND_RD_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_4_FAIL_GMK_COND_RD_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5 0x0017e304 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5__PRIV_LEVEL_MASK 0x0017e3a8 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_ROP_DATA 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_ROP_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_ROP_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_RAST_DATA 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_RAST_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_RAST_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_PE_DATA 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_PE_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_PE_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_SCC_DATA 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_SCC_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_SCC_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_TEX_DATA 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_TEX_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_TEX_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_TEX_ALL_DATA__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_ALL_DATA 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_ALL_DATA_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_ALL_DATA_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_COMPRESSED_DATA 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_COMPRESSED_DATA_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_5_DISCARD_COMPRESSED_DATA_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1 0x0017e294 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_WAYS 15:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_WAYS_INIT 0xffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_WAYS_GF100_1 0x0001 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_WAYS_GF100_ALL 0xffff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_SETS 17:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_SETS_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_SETS_HALF 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_SETS_QUARTER 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES 22:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_7_8TH 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_6_8TH 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_5_8TH 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_4_8TH 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_3_8TH 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_2_8TH 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ACTIVE_ICC_ENTRIES_1_8TH 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD 27:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_MIN 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_1 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_2 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_4 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_8 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_16 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_32 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_64 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_128 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_256 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ISO_RDAT_FIFO_FREE_THRESHOLD_MAX 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_RESERVE_ISO_COUNT_SYSMEM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ECC_HUB_RMW_DISABLE 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ECC_HUB_RMW_DISABLE_CE_ONLY 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_ECC_HUB_RMW_DISABLE_ALL 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_CACHE_HUB_WEAK_VOL 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_CACHE_HUB_WEAK_VOL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_1_CACHE_HUB_WEAK_VOL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2 0x0017e298 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE 1:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ALL_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE 3:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_HUB_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE 5:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE 7:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_FE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE 9:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PD_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE 11:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_CTX_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE 13:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE 15:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_ON_128B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_SP2_256B_PROMOTE_ON_SECT0 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE 17:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE 19:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_T1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE 21:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_PE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE 23:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_RAST_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE 25:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_ROP_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE 27:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE 29:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_GPCCS_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE 31:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_ON_128B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_2_VIDMEM_L2_256B_PROMOTE_ON_SECT0 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3 0x0017e29c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE 1:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ALL_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE 3:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_HUB_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE 5:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE 7:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_FE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE 9:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PD_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE 11:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_CTX_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE 13:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_SCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PROMOTE 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PROMOTE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PROMOTE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE 17:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_L1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE 19:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_T1_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE 21:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_PE_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE 23:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_RAST_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE 25:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_ROP_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE 27:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GCC_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE 29:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_NONE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_SYSMEM_GPCCS_PROMOTE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM 31:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM_64B 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CFG_3_FETCH_PARTIAL_CATOM_32B 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0 0x0017e2a0 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0__PRIV_LEVEL_MASK 0x0017e3bc /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES 11:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_0 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_MAX_CYCLES_BETWEEN_INVALIDATES_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_LAST_CLASS_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_NORMAL_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_INVALIDATE_EVICT_FIRST_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_ACTIVE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_0_DISABLE_INVALIDATE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1 0x0017e2a4 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1__PRIV_LEVEL_MASK 0x0017e3bc /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_NOT_PENDING 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_PENDING 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS 11:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_MAX_CYCLES_BETWEEN_CLEANS_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_WAIT_FOR_FB_TO_PULL_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_LAST_CLASS_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_NORMAL_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_CMGMT_1_CLEAN_EVICT_FIRST_CLASS_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS 0x0017e2a8 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_IDLE 0:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_DIRTY 1:1 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_INUSE 2:2 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_FULL 3:3 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_ISO_RDAT_CREDIT_IDLE 4:4 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_WRCOUNT_IDLE 5:5 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_ISO_LOCKED_WITHOUT_ICC 6:6 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_ACTIVE_ATOM 7:7 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_PENDING_FB_MISS_REQ 16:16 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_STALLED_ON_CLEAN_IF 17:17 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_STALLED_ON_READ_IF 18:18 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_STALLED_ON_ICC 19:19 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_STATUS_CACHELINES_PINNED 24:24 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0 0x0017e2ac /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0__PRIV_LEVEL_MASK 0x0017e3bc /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_RD_PINNED 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_RD_PINNED_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_SYSMEM_RD_PINNED 12:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_SYSMEM_RD_PINNED_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST 20:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_EVICT_LAST_INIT 0x03 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_ATOMIC 28:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_0_MAX_WAYS_ATOMIC_INIT 0x0b /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1 0x0017e39c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1__PRIV_LEVEL_MASK 0x0017e3bc /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_EVICT_FIRST 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_EVICT_FIRST_INIT 0x10 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_GPC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_BASED_ON_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_PLC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_MIN_WAYS_EVICT_NORMAL_DIRTY 12:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_MIN_WAYS_EVICT_NORMAL_DIRTY_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE_NORMAL 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_CROP__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_HUB_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_EVICT_NORMAL_DIRTY_PANIC_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_SERIALIZE_AND_CACHE_VOL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD 22:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD_DISABLED 0x10 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD_0 0x00 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_THRESHOLD_INIT 0x05 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_PE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_PROBING 28:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_MAX_WAYS_PROBING_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_RECOMPRESS_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_ATOMIC_COH_RMW 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_ATOMIC_COH_RMW_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_ATOMIC_COH_RMW_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_1_PLC_EXCLUDE_TEX_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2 0x0017e2b0 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2__PRIV_LEVEL_MASK 0x0017e3d0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_INIT 0xff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_ONE 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_RD_MISS_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS 15:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_INIT 0x0e /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_ONE 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_MAX_GPC_SYSMEM_WR_MISS_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_COMPR_WR_INVAL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_DB2CST_RMW_WRITE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_WRITE_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_UPDATE_LRU_ON_PREFETCH_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ONLY_ALLOW_WRITES_TO_CLEAN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_ISSUE_DIRTY_ON_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_BYPASS_MODE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_PADR_HIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_L2_FASTTRACK_ACROSS_VC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_2_PLC_INVALIDATE_ON_ZBC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3 0x0017e2b4 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3__PRIV_LEVEL_MASK 0x0017e3d0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_STOP 9:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_STOP_INIT 0x030 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES 13:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_7_8TH 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_6_8TH 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_5_8TH 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_4_8TH 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_3_8TH 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_2_8TH 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_CLEAN_FIFO_ENTRIES_1_8TH 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES 15:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_NONE 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_2_3RD 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_SRV_CAM_ENTRIES_1_3RD 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_SAME_SET_PREFETCH_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DONT_CLEAN_OLDEST_DIRTY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_DIRTY_PM_USE_PADR_BITS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DRAM_ECC_FILL_EVICT_LAST_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_VOL_GATOM_CLRBE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_FCLR_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CBC_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_DISALLOW_CLEAN_CE_IMM_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_SYSMEM_WB_THRESHOLD 28:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_SYSMEM_WB_THRESHOLD_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_3_WRITE_THRESHOLD_CTRL_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4 0x0017e2b8 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD_INIT 0x02 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_PARTIAL_FILL_THRESHOLD_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD 9:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD_INIT 0x04 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_PARTIAL_THRESHOLD_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_INTERLOCK_STRICT 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL_FULL_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_RESET_PARTIAL_FULL_NON_READ 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS 15:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_0 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_3 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_DRAM_ECC_MAX_CYCLES_BETWEEN_FILLS_UNLIMITED 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD 17:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_25PCT 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_50PCT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_75PCT 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_THRESHOLD_100PCT 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE 19:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_0PCT 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_25PCT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_50PCT 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BANK_STALL_DUTY_CYCLE_100PCT 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST_TRUE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_TEST_OLDEST_FALSE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT 22:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_ANY 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_ALLOCATION 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_NON_EF_ALLOCATION 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_EVENT_VERIF 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD 26:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_MIN 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_PERIOD_MAX 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_4_BG_DEMOTION_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5 0x0017e2bc /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5__PRIV_LEVEL_MASK 0x0017e3bc /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_TIER1_CLEAN_THRESHOLD 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_TIER1_CLEAN_THRESHOLD_INIT 0x07 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_TIER2_CLEAN_THRESHOLD 12:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_TIER2_CLEAN_THRESHOLD_INIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST 20:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST_INIT 0x0d /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_MAX_WAYS_INUSE_NOT_EVICT_LAST_FOR_COMPUTE 0x10 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO 26:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD1 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD2 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_THLD3 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC 29:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD1 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD2 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_THLD3 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_ISO_NISONB_CBC_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_NONE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_THLD0 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SET_MGMT_5_ICC_RESERVED_NISONB_CBC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE 0x0017e2c0 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_BUCKET_SIZE_INIT 0x020 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_LEAK_COUNT_DISABLE 0x000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_LEAK_SIZE_32B 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_LEAK_SIZE_64B 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_LEAK_SIZE_128B 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_THROTTLE_LEAK_SIZE_256B 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0 0x0017e2c4 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_STATE 10:0 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_STATE_IDLE 0x000 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE 13:12 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_WRITE_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_HIT 15:14 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_HIT_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD 17:16 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_IMM_SYSRD_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ISO 19:18 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ISO_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE 21:20 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_ELSE_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD 23:22 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_0_MISS_SYSRD_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1 0x0017e2c8 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM 1:0 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM 3:2 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_GATOM_SYSMEM_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B 5:4 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_ELSE_B_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW 9:8 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI 11:10 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBI_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX 13:12 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_PRBX_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS 15:14 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_RMW_RS_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_LL 17:16 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_LL_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_LL_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_LL_AT_LEAST_4 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_STATUS_1_MISS_LL_FULL 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL 0x0017e2cc /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_MIN_LIMIT 5:0 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_MIN_LIMIT_INIT 0x05 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_ARB_SPARE 7:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_ARB_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_HIT 14:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_HIT_INIT 0x10 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_ALL_WRS 22:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_ALL_WRS_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_SYSRD 30:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_IMMREQ_CTRL_LIMIT_SYSRD_INIT 0x20 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0 0x0017e2d0 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS 8:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS_INIT 0x010 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_SYSMISS_MIN 0x008 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB_SEPARATELY 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_HUB_WITH_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO 18:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO_INIT 0x060 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_ISO_MIN 0x008 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW_SEPARATELY 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_RMW_WITH_EE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE 29:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE_INIT 0x040 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_LIMIT_EVERYTHING_ELSE_MIN 0x010 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE_WITH_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_THREAD_CE_WITH_HUB 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST_AS_NEEDED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_0_POLL_CST_CONTINUOUSLY 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1 0x0017e2d4 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED 9:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_MIN 0x010 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SHARED_CTRL_DISABLED 0x3ff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SYSMEM_HUB 18:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_SYSMEM_HUB_INIT 0x000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT_THROUGH_MISS 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_HUB_HIT_THROUGH_HIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED 21:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_HUB_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED 23:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_SYSMISS_GPC_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW 29:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW_INIT 0x02 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_LIMIT_RMW_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED 31:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_NEVER 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_FIRST 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_SRV_MISSREQ_CTRL_1_RMW_SHARED_LAST 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_0 0x0017e2d8 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_0_MISS_FIFO_DEPTH 10:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_0_NUM_AWPS 20:11 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_0_ISO_RDAT_FIFO_DEPTH 31:21 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_1 0x0017e38c /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_1_SLICE_SIZE_IN_KB 15:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_1_SLICES_PER_L2 20:16 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_1_SLICES_PER_L2_1 0x01 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_1_SLICES_PER_L2_2 0x02 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_1_SLICES_PER_L2_3 0x03 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_INFO_1_SLICES_PER_L2_4 0x04 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN 0x0017e2dc /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_TIMEOUT 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_TIMEOUT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_TIMEOUT_DISABLED 0x00 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_TIMEOUT_MIN 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_TIMEOUT_MAX 0xff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY_FALSE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_AUTOCLEAN_DRAM_ECC_PARTIAL_ONLY_TRUE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_ECC_SCRUB_0 0x0017e30c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_ECC_SCRUB_0_XBAR_RAW_PADR 31:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_ECC_SCRUB_0_XBAR_RAW_PADR_INIT 0x00000000 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_ECC_SCRUB_1 0x0017e310 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_ECC_SCRUB_1_WRITE 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_ECC_SCRUB_1_WRITE_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_ECC_SCRUB_1_WRITE_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY 0x0017e314 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MASTER 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MASTER_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MASTER_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_READ_THLD 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_READ_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_READ_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_READ_SYSMEM_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_INUSE_THLD 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_INUSE_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_INUSE_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ATOMIC_THLD 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ATOMIC_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ATOMIC_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_AWP_THLD 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_AWP_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_AWP_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_EVICT_LAST_THLD_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NO_REALLOCATABLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM2INUSE 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_RMW2INUSE 9:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_RMW2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_RMW2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE 10:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_CLR2WR_INVAL2INUSE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_WR_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_HIT_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_IMM_SYSRD_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MISS_SYSMEM_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_MISS_EE_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM_SRC_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GATOM_SYSSRC_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_FB_READ_CREDIT 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_FB_READ_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_FB_READ_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_FB_CLEAN_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_GPC_SYSMEM_RD_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ISO_RDAT_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NISO_NB_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_BLOCKING_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_NON_BLOCKING_CREDIT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_FULL 25:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_FULL_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_FULL_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_INTERLOCK 26:26 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_INTERLOCK_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_INTERLOCK_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_REF_COUNT 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_REF_COUNT_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_TSTG_REDUCE_REPLAY_ICC_REF_COUNT_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0 0x0017e2e0 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0__PRIV_LEVEL_MASK 0x0017e398 /* */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CLEAN 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CLEAN_ACTIVE 0x1 /* -W--T */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CLEAN_INACTIVE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_COHERENCY 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_COHERENCY_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_COHERENCY_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_COHERENCY_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_LRU_DEALLOC 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_LRU_DEALLOC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_LRU_DEALLOC_ENABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_LRU_DEALLOC_DISABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_EVICTION_HWM 9:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_EVICTION_HWM_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_EVICTION_HWM_MIN 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SET_SWIZZLE 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SET_SWIZZLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SET_SWIZZLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SET_SWIZZLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CROSS_VC_CONFLICT 13:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CROSS_VC_CONFLICT_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CROSS_VC_CONFLICT_FASTTRACK_GPC 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CROSS_VC_CONFLICT_FASTTRACK_MOST 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CROSS_VC_CONFLICT_STALL 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_CROSS_VC_CONFLICT_RETRY 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_ACTIVE_SETS 15:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_ACTIVE_SETS_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_ACTIVE_SETS_ALL 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_ACTIVE_SETS_HALF 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_ACTIVE_SETS_QUARTER 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_ACTIVE_SETS_EIGHTH 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_NUM_ACTIVE_WAYS 19:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_NUM_ACTIVE_WAYS_INIT 0x4 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_NUM_ACTIVE_WAYS_MAX 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SPARE_20 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SPARE_20_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SPARE_21 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SPARE_21_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SPARE_22 22:22 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_SPARE_22_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_I 24:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_I_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_I_MO_N 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_I_MO 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_X 26:25 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_X_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_X_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROBE_X_ALIGNED_ONLY_ENABLE 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROMOTE_PROBE_X 27:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROMOTE_PROBE_X_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROMOTE_PROBE_X_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_PROMOTE_PROBE_X_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT 31:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_INIT 0x3 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PRBF_0_MAX_CYCLES_BETWEEN_PF_EVICT_3 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0 0x0017e318 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0__PRIV_LEVEL_MASK 0x0017e3d4 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ECC 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ECC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ECC_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_CHECKBIT_WR_SUPPRESS 1:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_CHECKBIT_WR_SUPPRESS_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_CHECKBIT_WR_SUPPRESS_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE 2:2 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ECC_SYSMEMFILL_BESTATE_ACTIVE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_FBFILL_BESTATE 3:3 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_FBFILL_BESTATE_INACTIVE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_FBFILL_BESTATE_ACTIVE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_DRAM_ECC 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_DRAM_ECC_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_DRAM_ECC_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_ISO_4TO1_8TO1_REDUCED_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_XBAR_RW_ILOCK 7:7 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_XBAR_RW_ILOCK_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_XBAR_RW_ILOCK_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT 13:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_0 0x00 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_1 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_2 0x02 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_3 0x03 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_4 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_5 0x05 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_6 0x06 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_7 0x07 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_8 0x08 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_9 0x09 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_10 0x0a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_11 0x0b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_12 0x0c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_13 0x0d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_14 0x0e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_15 0x0f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_16 0x10 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_17 0x11 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_18 0x12 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_19 0x13 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_20 0x14 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_21 0x15 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_22 0x16 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_23 0x17 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_24 0x18 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_25 0x19 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_26 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_27 0x1b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_28 0x1c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_29 0x1d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_30 0x1e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_STATUS_SELECT_31 0x1f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_NB_CREDIT_TTHRESHOLD 19:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_NB_CREDIT_TTHRESHOLD_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_RMW_VC 20:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_RMW_VC_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_RMW_VC_ISO 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_RMW_VC_NOTISO 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_RESERVE_DECOMP 21:21 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_RESERVE_DECOMP_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_RESERVE_DECOMP_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE 23:23 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_DB2DCMP_SCND_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_NB_CREDIT_DTHRESHOLD 27:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_NB_CREDIT_DTHRESHOLD_INIT 0x8 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_NB_CREDIT_DTHRESHOLD_INF 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA 31:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_4TO1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_8TO1 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG0_REDUCTION_RATIO_IN_1XAA_INIT 0x2 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2 0x0017e3a0 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2__PRIV_LEVEL_MASK 0x0017e3d4 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_NB_HUB_CREDIT_TTHRESHOLD 3:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_NB_HUB_CREDIT_TTHRESHOLD_INIT 0xc /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD 7:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD_INIT 0x8 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_NB_HUB_CREDIT_DTHRESHOLD_INF 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_BYPASS 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_BYPASS_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_BYPASS_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_DC 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_DC_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_DC_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_AC 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_AC_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_DBI_AC_ENABLE 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_STITCH 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_STITCH_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_STITCH_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_MULTI_CATOM 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_MULTI_CATOM_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_COMPRET_MULTI_CATOM_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_CFG2_TEX_UNCOMPRESSED_STICKY_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0 0x0017e308 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0__PRIV_LEVEL_MASK 0x0017e3d0 /* */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_VDC_DISABLE 4:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_VDC_DISABLE_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_VDC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_DISABLE 5:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_DISABLE_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_DISABLE_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_VDC_FORCE_SUCCESS 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_VDC_FORCE_SUCCESS_NORMAL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_VDC_FORCE_SUCCESS_FORCE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_UGO_FOR_ALL 8:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_UGO_FOR_ALL_DISABLE 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_UGO_FOR_ALL_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_PULL_LIMIT 10:9 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_PULL_LIMIT_ALL 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_PULL_LIMIT_1QUARTER 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_PULL_LIMIT_HALF 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_PULL_LIMIT_3QUARTER 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_1B_DETECT_DISABLE 11:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_1B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_1B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_2B_DETECT_DISABLE 12:12 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_2B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_2B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_4B_DETECT_DISABLE 13:13 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_4B_DETECT_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_SDC_4B_DETECT_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_CC_DISABLE 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_CC_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_CC_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_ZBC_DISABLE 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_ZBC_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_ZBC_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_UCOMP_MIXED_DISABLE 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_UCOMP_MIXED_DISABLE_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_UCOMP_MIXED_DISABLE_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_DISABLE_PARTIAL_PLC 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_DISABLE_PARTIAL_PLC_OFF 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_PLC_CFG0_DISABLE_PARTIAL_PLC_ON 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_REPORT 0x0017e31c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_REPORT_SEC_COUNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_REPORT_SEC_COUNT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_REPORT_DED_COUNT 23:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_REPORT_DED_COUNT_INIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS 0x0017e320 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS_INFO 22:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS_INFO_BIT 2:0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS_INFO_LINE 19:8 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS_INFO_BANK 21:20 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS_INFO_RAM 22:22 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS_INFO_RAM_0_BYTE 7:3 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ECC_ADDRESS_INFO_RAM_1_BYTE 7:6 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0 0x0017e324 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_IDQ_DATA_COUNT 7:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_IDQ_WR_THREAD 8:8 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_IDQ_WR_THREAD_FALSE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_IDQ_WR_THREAD_TRUE 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_DDRQ_DATA 9:9 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_DDRQ_DATA_EMPTY 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_DDRQ_DATA_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_DCRQ_CMD 10:10 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_DCRQ_CMD_EMPTY 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_DCRQ_CMD_AT_LEAST_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_SEQUENCER_STATUS 11:11 /* R-IVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_SEQUENCER_STATUS_IDLE 0x0 /* R-I-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_STATUS_0_SEQUENCER_STATUS_BUSY 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ 0x0017e328 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_ZWR_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_CWR_DATI_CTRL_LIMIT 13:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_CWR_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_CWR_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_OLD_DATI_CTRL_LIMIT 21:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_OLD_DATI_CTRL_LIMIT_INIT 0x0c /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_OLD_DATI_CTRL_LIMIT_MIN 0x0c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_SHARED_DATI_CTRL_LIMIT 29:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_WDQ_SHARED_DATI_CTRL_LIMIT_INIT 0x28 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO 0x0017e32c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_VIDMEM_LIMIT 9:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_VIDMEM_LIMIT_INIT 0x004 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_SYSMEM_LIMIT 19:10 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_SYSMEM_LIMIT_INIT 0x004 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT 29:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_SHARED_LIMIT_CTRL_DISABLED 0x3ff /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_SPARE 31:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_GATOM_SRC_FIFO_SPARE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX 0x0017e338 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS 4:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_ADDRESS_RESERVED 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_RDI_SOURCE 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_RDI_SOURCE_DSTG 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_INDEX_RDI_SOURCE_GC 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE(i) (0x0017e33c+(i)*4) /* RW-4A */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE__SIZE_1 4 /* */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_COLOR_CLEAR_VALUE_FIELD 31:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE 0x0017e34c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_DEPTH_CLEAR_VALUE_FIELD 31:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_STENCIL_CLEAR_VALUE 0x0017e204 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_DSTG_ZBC_STENCIL_CLEAR_VALUE_FIELD 7:0 /* RWXVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM 0x0017e350 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_ENABLE 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_ENABLE_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT 4:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP0 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP1 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP2 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP3 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP4 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP5 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP6 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP7 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP8 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP9 0x9 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP10 0xa /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP11 0xb /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP12 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP13 0xd /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP14 0xe /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SECTOR_MUX_SELECT_GRP15 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT 10:5 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_STATIC_PATTERN_5555_16_GROUP 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_STATIC_PATTERN_AAAA_16_GROUP 0x1d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP41 0x29 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP42 0x2a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP43 0x2b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP44 0x2c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP45 0x2d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP46 0x2e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP47 0x2f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP48 0x30 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP49 0x31 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP50 0x32 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP51 0x33 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP52 0x34 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP53 0x35 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP54 0x36 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP55 0x37 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP56 0x38 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP57 0x39 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP58 0x3a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP59 0x3b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP60 0x3c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP61 0x3d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP62 0x3e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_GRP63 0x3f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT 16:11 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SRCUNIT_MUX_SELECT_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE 22:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP0 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP1 0x01 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP2 0x02 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP3 0x03 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP4 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP5 0x05 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP6 0x06 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP7 0x07 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP8 0x08 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP9 0x09 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP10 0x0a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP11 0x0b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP12 0x0c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP13 0x0d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP14 0x0e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP15 0x0f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP16 0x10 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP17 0x11 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP18 0x12 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP19 0x13 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP20 0x14 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP21 0x15 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP22 0x16 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP23 0x17 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP24 0x18 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP25 0x19 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP26 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP27 0x1b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP28 0x1c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP29 0x1d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP30 0x1e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP31 0x1f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_STATIC_PATTERN_5555_16_GROUP 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_STATIC_PATTERN_AAAA_16_GROUP 0x1d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP32 0x20 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP33 0x21 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP34 0x22 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP35 0x23 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP36 0x24 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP37 0x25 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP38 0x26 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP39 0x27 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP40 0x28 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP41 0x29 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP42 0x2a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP43 0x2b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP44 0x2c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP45 0x2d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP46 0x2e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP47 0x2f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP48 0x30 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP49 0x31 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP50 0x32 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP51 0x33 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP52 0x34 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP53 0x35 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP54 0x36 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP55 0x37 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP56 0x38 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP57 0x39 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP58 0x3a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP59 0x3b /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP60 0x3c /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP61 0x3d /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP62 0x3e /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_SELECT_CLONE_GRP63 0x3f /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC 0x0017e330 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_LAT_SCALE 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_LAT_SCALE_INIT 0x27 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_LAT_SCALE 11:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_LAT_SCALE_INIT 0x27 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE 23:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_INIT 0xb /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_128TH 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_64TH 0xe /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_32ND 0xd /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_16TH 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_8TH 0xb /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_4TH 0xa /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_2ND 0x9 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X1 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X2 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X4 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X8 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X16 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X32 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X64 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X128 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SCALE_X256 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE 27:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_INIT 0xb /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_128TH 0xf /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_64TH 0xe /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_32ND 0xd /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_16TH 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_8TH 0xb /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_4TH 0xa /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_2ND 0x9 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X1 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X2 0x7 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X4 0x6 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X8 0x5 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X16 0x4 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X32 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X64 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X128 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SCALE_X256 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL 29:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_10 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_100 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_1000 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_RDAT_SAMP_SEL_10000 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL 31:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_10 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_100 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_1000 0x2 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_MISC_LTC_LTS_PM_OCC_DIRTY_SAMP_SEL_10000 0x3 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR 0x0017e354 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_NAN_VALUE 22:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_NAN_VALUE_INIT 0x7fffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_RND 26:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_RND_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_DAZ_ENABLE 28:28 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_DAZ_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_DAZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_DAZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_FTZ_ENABLE 29:29 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_FTZ_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_FTZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_FTZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_NAN_ENABLE 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_NAN_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_NAN_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_FPADDR_NAN_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC 0x0017e358 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_A_MISC__PRIV_LEVEL_MASK 0x0017e3c0 /* */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_REQ_LIMIT 3:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_REQ_LIMIT_INIT 0xf /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16ADDR_NAN_VALUE 13:4 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16ADDR_NAN_VALUE_INIT 0x3ff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16ADDR_NAN_ENABLE 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16ADDR_NAN_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16ADDR_NAN_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16ADDR_NAN_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16_DAZ_ENABLE 15:15 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16_DAZ_ENABLE_INIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16_DAZ_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_A_MISC_FP16_DAZ_ENABLE_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CG1 0x0017e35c /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_CG1__PRIV_LEVEL_MASK 0x0017e3dc /* */
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#define NV_PLTCG_LTCS_LTSS_CG1_SLCG 31:1 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_CG1_SLCG_DISABLED 0x7fffffff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x0017e380 /* RWB4R */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0xc /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX 0x0017e360 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX__PRIV_LEVEL_MASK 0x0017e380 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_INDEX 7:0 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_INDEX_ZERO 0x00 /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_INDEX_MAX 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_INDEX_MAX_AVAIL 0x1a /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE 16:16 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_DISABLE 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_ENABLE 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_INDEX_BLKACTIVITY_ENABLE_INIT 0x0 /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_DATA 0x0017e364 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_DATA__PRIV_LEVEL_MASK 0x0017e380 /* */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_DATA_DATA 31:0 /* RWBVF */
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#define NV_PLTCG_LTCS_LTSS_BLK_ACT_DATA_DATA_INIT 0x00000000 /* RWB-V */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS 0x0017e368 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_KIND 7:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_COMPBITS 9:8 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_ZDCMP_STATE 12:10 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_IDLE 13:13 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_ARB_IDLE 14:14 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_CDCMP_IDLE 15:15 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_RDAT_FIFO_IDLE 16:16 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_REQ_FIFO_IDLE 17:17 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_WDAT_FIFO_IDLE 18:18 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_WREQ_FIFO_IDLE 19:19 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_ZDCMP_IDLE 20:20 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_CDCMP_REQ_PVLD 21:21 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_CDCMP_DATA_PVLD 22:22 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_CDCMP_IS_RMW 23:23 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_CDCMP_IS_P2P 24:24 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_CDCMP_IS_TEX 25:25 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_ZDCMP_REQ_PVLD 26:26 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_ZDCMP_DATA_PVLD 27:27 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_ZDCMP_IS_RMW 28:28 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_ZDCMP_IS_P2P 29:29 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS_CDCMP_STATE 30:30 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS1 0x0017e36c /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS1_INPUT_MASK 7:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_DCMP_STATUS1_ROLLING_MASK 15:8 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG 0x0017e3e0 /* RWI4R */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG__PRIV_LEVEL_MASK 0x0017e3dc /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG1 0x0017e3e4 /* RWI4R */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG1__PRIV_LEVEL_MASK 0x0017e3dc /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_CBC_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG 0x0017e3f8 /* RWI4R */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG__PRIV_LEVEL_MASK 0x0017e3dc /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0a /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_BLPG_EN 16:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_BLPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_BLPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DIS_EARLY_WUP 17:17 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DIS_EARLY_WUP_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DIS_EARLY_WUP_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DEEP_ELPG_EN 18:18 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DEEP_ELPG_EN_ENABLED 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DEEP_ELPG_EN_DISABLED 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_ELPG_EN 19:19 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_ELPG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_IDLE_ELPG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DIDT_DELAY 23:20 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_DIDT_DELAY_HWINIT 0xa /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_RESET_DURATION 26:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_RESET_DURATION_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_CLAMP_DELAY 29:27 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_CLAMP_DELAY_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_ZONE_OFF_MASK 30:30 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_ZONE_OFF_MASK_HWINIT 0x1 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_SOFT_GATING_EN 31:31 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_SOFT_GATING_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG_SOFT_GATING_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG1 0x0017e3fc /* RWI4R */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG1__PRIV_LEVEL_MASK 0x0017e3dc /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG1_ZONE_SEQ 23:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG1_ZONE_SEQ_HWINIT 0x053977 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG1_ZONE_MASK 31:24 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_LTS_PG1_ZONE_MASK_HWINIT 0xff /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG 0x0017e3c8 /* RWI4R */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG__PRIV_LEVEL_MASK 0x0017e3dc /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_IDLE_CG_DLY_CNT__PROD 0x04 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_IDLE_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STATE_CG_EN 7:7 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STALL_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_STALL_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_QUIESCENT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_WAKEUP_DLY_CNT__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_HALT_CG_EN 31:31 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG1 0x0017e3cc /* RWI4R */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG1__PRIV_LEVEL_MASK 0x0017e3dc /* */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN_DISABLED 0x0 /* RWI-V */
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#define NV_PLTCG_LTCS_LTSS_G_PRI_IQ_CG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2 0x0017e3f4 /* R--4R */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE 15:0 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_4 0x0004 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_5 0x0005 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_6 0x0006 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_7 0x0007 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_8 0x0008 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_10 0x000a /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_11 0x000b /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_13 0x000d /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_16 0x0010 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_22 0x0016 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_32 0x0020 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_64 0x0040 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE_128 0x0080 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_NUM_CACHE_LINES 23:16 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_NUM_CACHE_LINES_16 0x10 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_NUM_CACHE_LINES_20 0x14 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_NUM_CACHE_LINES_32 0x20 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_NUM_CACHE_LINES_40 0x28 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_NUM_CACHE_LINES_64 0x40 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE 27:24 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_512 0x0 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_1K 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_2K 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_4K 0x3 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_8K 0x4 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_16K 0x5 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_32K 0x6 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_CACHE_LINE_SIZE_64K 0x7 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_SLICES_PER_LTC 31:28 /* R--VF */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_SLICES_PER_LTC_1 0x1 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_SLICES_PER_LTC_2 0x2 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_CBC_PARAM2_SLICES_PER_LTC_4 0x4 /* R---V */
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#define NV_PLTCG_LTCS_LTSS_MISC_CFG 0x0017e300 /* RW-4R */
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#define NV_PLTCG_LTCS_LTSS_MISC_CFG__PRIV_LEVEL_MASK 0x0017e398 /* */
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#define NV_PLTCG_LTCS_LTSS_MISC_CFG_SPARE 31:0 /* RWIVF */
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#define NV_PLTCG_LTCS_LTSS_MISC_CFG_SPARE_INIT 0x00000000 /* RWI-V */
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#endif // __ga102_dev_ltc_h__
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