5052 lines
467 KiB
C
5052 lines
467 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_nv_xp_h__
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#define __ga102_dev_nv_xp_h__
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/* This file is autogenerated. Do not edit */
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#define NV_XP 0x0008EFFF:0x0008B000 /* RW--D */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK 0x0008E1B0 /* RWI4R */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT 0x0000000F /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_a_bit0" /* */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PEX_PAD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK 0x0008E1B4 /* RW-4R */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xp_protect_dropoff_others" /* */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_OTHER_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK 0x0008E1B8 /* RW-4R */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xp_protect_dropoff_cya_grp" /* */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK 0x0008E1BC /* RW-4R */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xp_protect_dropoff_non_cya_grp" /* */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_NON_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK 0x0008E1C0 /* RW-4R */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit5" /* */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_CLKCTRL_BLKCG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK 0x0008E1C4 /* RW-4R */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit6" /* */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_DL_MGR_TIMING_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK 0x0008E1C8 /* RW-4R */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit7" /* */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK 0x0008E1CC /* RW-4R */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit8" /* */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_UPHY_CFG_IF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK 0x0008E1D0 /* RW-4R */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit9" /* */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PAD_ECTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK 0x0008E1D4 /* RW-4R */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit10" /* */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK 0x0008E1D8 /* RW-4R */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit11" /* */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK 0x0008E1DC /* RW-4R */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit12" /* */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PEX_PLL_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK 0x0008E1E0 /* RW-4R */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit13" /* */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PL_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK 0x0008E1E4 /* RW-4R */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit14" /* */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PL_LCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK 0x0008E1E8 /* RW-4R */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit15" /* */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PL_NFTS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK 0x0008E1EC /* RW-4R */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pcie_magic_bits_c_bit16" /* */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PL_PAD_PWRDN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK 0x0008E1F0 /* RW-4R */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PL_LINK_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK 0x0008E1F4 /* RW-4R */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_XP_PROTECT_PAD_CTL1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_XP_DL_MGR_TIMING_1(i) (0x0008B000+(i)*4) /* RW-4A */
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#define NV_XP_DL_MGR_TIMING_1__SIZE_1 256 /* */
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#define NV_XP_DL_MGR_TIMING_1__PRIV_LEVEL_MASK 0x0008E1C4 /* */
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#define NV_XP_DL_MGR_TIMING_1_UPDATE_FC_THRESHOLD 10:0 /* RWXVF */
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#define NV_XP_DL_MGR_TIMING_1_ACK_TIMER_LIMIT 26:16 /* RWXVF */
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#define NV_XP_DL_MGR_TIMING_2(i) (0x0008B400+(i)*4) /* RW-4A */
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#define NV_XP_DL_MGR_TIMING_2__SIZE_1 256 /* */
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#define NV_XP_DL_MGR_TIMING_2__PRIV_LEVEL_MASK 0x0008E1C4 /* */
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#define NV_XP_DL_MGR_TIMING_2_REPLAY_TIMER_LIMIT 12:0 /* RWXVF */
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#define NV_XP_DL_TX_0(i) (0x0008B800+(i)*4) /* RW-4A */
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#define NV_XP_DL_TX_0__SIZE_1 1 /* */
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#define NV_XP_DL_TX_0__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_DL_TX_0_TXBUF_BEGIN_PTR 8:0 /* RWIVF */
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#define NV_XP_DL_TX_0_TXBUF_BEGIN_PTR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_TX_0_TXBUF_END_PTR 20:12 /* RWIVF */
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#define NV_XP_DL_TX_0_TXBUF_END_PTR_INIT 0x000001FF /* RWI-V */
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#define NV_XP_DL_TX_0_TXBUF_MODE 26:26 /* RWIVF */
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#define NV_XP_DL_TX_0_TXBUF_MODE_STORE_AND_FORWARD 0x00000001 /* RW--V */
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#define NV_XP_DL_TX_0_TXBUF_MODE_CUT_THROUGH 0x00000000 /* RW--V */
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#define NV_XP_DL_TX_0_TXBUF_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_TX_0_TXBUF_MAX_UNSENT_ENTRIES 31:27 /* RWIVF */
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#define NV_XP_DL_TX_0_TXBUF_MAX_UNSENT_ENTRIES_INIT 0x0000001A /* RWI-V */
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#define NV_XP_DL_TX_0_TXBUF_MAX_UNSENT_ENTRIES_MAX_VAL 0x0000001F /* RW--V */
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#define NV_XP_DL_TX_1(i) (0x0008B840+(i)*4) /* RW-4A */
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#define NV_XP_DL_TX_1__SIZE_1 1 /* */
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#define NV_XP_DL_TX_1_BANK_OVERFLOW_ERR 1:0 /* RWIVF */
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#define NV_XP_DL_TX_1_BANK_OVERFLOW_ERR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_TX_1_BANK_OVERFLOW_ERR_BANK0_OK 0x00000000 /* RW--V */
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#define NV_XP_DL_TX_1_BANK_OVERFLOW_ERR_BANK0_ERROR 0x00000001 /* RW--V */
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#define NV_XP_DL_TX_1_BANK_OVERFLOW_ERR_BANK1_OK 0x00000000 /* RW--V */
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#define NV_XP_DL_TX_1_BANK_OVERFLOW_ERR_BANK1_ERROR 0x00000002 /* RW--V */
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#define NV_XP_DL_TX_1_BANK_PARITY_ERR 3:2 /* RWIVF */
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#define NV_XP_DL_TX_1_BANK_PARITY_ERR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_TX_1_BANK_PARITY_ERR_INIT_BANK0_OK 0x00000000 /* RW--V */
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#define NV_XP_DL_TX_1_BANK_PARITY_ERR_INIT_BANK0_ERROR 0x00000001 /* RW--V */
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#define NV_XP_DL_TX_1_BANK_PARITY_ERR_INIT_BANK1_OK 0x00000000 /* RW--V */
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#define NV_XP_DL_TX_1_BANK_PARITY_ERR_INIT_BANK1_ERROR 0x00000002 /* RW--V */
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#define NV_XP_DL_TX_1_SUBCH_ILLEGAL_COMB_ERR 4:4 /* RWIVF */
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#define NV_XP_DL_TX_1_SUBCH_ILLEGAL_COMB_ERR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_TX_1_SUBCH_ILLEGAL_COMB_ERR_OK 0x00000000 /* RW--V */
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#define NV_XP_DL_TX_1_SUBCH_ILLEGAL_COMB_ERR_ERROR 0x00000001 /* RW--V */
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#define NV_XP_DL_TX_1_SUBCH_PROTOCOL_ERR 5:5 /* RWIVF */
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#define NV_XP_DL_TX_1_SUBCH_PROTOCOL_ERR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_TX_1_SUBCH_PROTOCOL_ERR_OK 0x00000000 /* RW--V */
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#define NV_XP_DL_TX_1_SUBCH_PROTOCOL_ERR_ERROR 0x00000001 /* RW--V */
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#define NV_XP_DL_TX_1_TXBUF_NUM_ENTRIES 29:20 /* R-IVF */
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#define NV_XP_DL_TX_1_TXBUF_NUM_ENTRIES_INIT 0x200 /* R-I-V */
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#define NV_XP_DL_RX_0(i) (0x0008B880+(i)*4) /* RW-4A */
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#define NV_XP_DL_RX_0__SIZE_1 1 /* */
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#define NV_XP_DL_RX_0__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_DL_RX_0_EXAMPLE_MODE 3:0 /* RWIVF */
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#define NV_XP_DL_RX_0_EXAMPLE_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_RX_0_EXAMPLE_STATUS 11:8 /* R-IVF */
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#define NV_XP_DL_RX_0_EXAMPLE_STATUS_INIT 0x00000001 /* R-I-V */
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#define NV_XP_DL_MGR_0(i) (0x0008B8C0+(i)*4) /* RW-4A */
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#define NV_XP_DL_MGR_0__SIZE_1 1 /* */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_ACK 0:0 /* RWIVF */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_ACK_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_ACK_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_ACK_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_UPDATE_FC 1:1 /* RWIVF */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_UPDATE_FC_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_UPDATE_FC_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_DL_MGR_0_OPPORTUNISTIC_UPDATE_FC_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_DL_MGR_0_SAFE_TIMING 2:2 /* RWIVF */
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#define NV_XP_DL_MGR_0_SAFE_TIMING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_MGR_0_SAFE_TIMING__PROD 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_MGR_0_SAFE_TIMING_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_MGR_0_SAFE_TIMING_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_MGR_0_L1_THRESHOLD_FRAC 5:3 /* RWIVF */
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|
#define NV_XP_DL_MGR_0_L1_THRESHOLD_FRAC_INIT 0x00000000 /* RWI-V */
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|
#define NV_XP_DL_MGR_0_L1_THRESHOLD_FRAC_MIN 0x00000000 /* RW--V */
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|
#define NV_XP_DL_MGR_0_L1_THRESHOLD_FRAC_MAX 0x00000007 /* RW--V */
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#define NV_XP_DL_MGR_0_UNUSED 15:6 /* RWIVF */
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|
#define NV_XP_DL_MGR_0_UNUSED_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_MGR_0_L1_HOLDOFF_LIMIT 25:16 /* RWIVF */
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|
#define NV_XP_DL_MGR_0_L1_HOLDOFF_LIMIT_INIT 0x00000064 /* RWI-V */
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|
#define NV_XP_DL_MGR_0_L1_HOLDOFF_LIMIT_MIN 0x00000023 /* RW--V */
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|
#define NV_XP_DL_MGR_0_L1_HOLDOFF_LIMIT_MAX 0x000000FF /* RW--V */
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|
#define NV_XP_DL_MGR_1(i) (0x0008B900+(i)*4) /* RW-4A */
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|
#define NV_XP_DL_MGR_1__SIZE_1 1 /* */
|
|
#define NV_XP_DL_MGR_1_L0S_ACK_WAKE 7:0 /* RWIVF */
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#define NV_XP_DL_MGR_1_L0S_ACK_WAKE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_MGR_1_L0S_ACK_WAKE_MIN 0x00000000 /* RW--V */
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#define NV_XP_DL_MGR_1_L0S_ACK_WAKE_MAX 0x000000FF /* RW--V */
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#define NV_XP_DL_MGR_1_L0S_UPDATE_WAKE 15:8 /* RWIVF */
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#define NV_XP_DL_MGR_1_L0S_UPDATE_WAKE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_MGR_1_L0S_UPDATE_WAKE_MIN 0x00000000 /* RW--V */
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#define NV_XP_DL_MGR_1_L0S_UPDATE_WAKE_MAX 0x000000FF /* RW--V */
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#define NV_XP_DL_MGR_1_L0S_THRESHOLD 25:16 /* RWIVF */
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#define NV_XP_DL_MGR_1_L0S_THRESHOLD_INIT 0x000003FF /* RWI-V */
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#define NV_XP_DL_MGR_1_L0S_THRESHOLD_REMOTE_NFTS 0x000003FF /* RW--V */
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#define NV_XP_DL_MGR_1_L0S_THRESHOLD_MIN 0x00000064 /* RW--V */
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#define NV_XP_DL_MGR_1_L0S_THRESHOLD_MAX 0x000003FF /* RW--V */
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#define NV_XP_DL_MGR_1_UNUSED 27:26 /* RWIVF */
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|
#define NV_XP_DL_MGR_1_UNUSED_UNUSED_INIT 0x00000000 /* RWI-V */
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|
#define NV_XP_DL_MGR_1_L1_THRESHOLD 31:28 /* RWIVF */
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#define NV_XP_DL_MGR_1_L1_THRESHOLD_INIT 0x00000003 /* RWI-V */
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#define NV_XP_DL_MGR_1_L1_THRESHOLD_MIN 0x00000000 /* RW--V */
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#define NV_XP_DL_MGR_1_L1_THRESHOLD_MAX 0x0000000D /* RW--V */
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#define NV_XP_DL_CYA_0(i) (0x0008B940+(i)*4) /* RW-4A */
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|
#define NV_XP_DL_CYA_0__SIZE_1 1 /* */
|
|
#define NV_XP_DL_CYA_0__PRIV_LEVEL_MASK 0x0008E1B8 /* */
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|
#define NV_XP_DL_CYA_0_RETIMING_STAGES 4:0 /* RWIUF */
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#define NV_XP_DL_CYA_0_RETIMING_STAGES_INIT 0x00000002 /* RWI-V */
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#define NV_XP_DL_CYA_0_RETIMING_STAGES__PROD 0x00000002 /* RW--V */
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#define NV_XP_DL_CYA_0_RETIMING_STAGES_MIN 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_RETIMING_STAGES_MAX 0x0000000D /* RW--V */
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|
#define NV_XP_DL_CYA_0_L0S_WAKE_ACK_CALC 6:6 /* RWIUF */
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|
#define NV_XP_DL_CYA_0_L0S_WAKE_ACK_CALC_INIT 0x00000001 /* RWI-V */
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|
#define NV_XP_DL_CYA_0_L0S_WAKE_ACK_CALC_OLD 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_L0S_WAKE_ACK_CALC_NEW 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_0_L0S_WAKE_UPDATE_CALC 7:7 /* RWIUF */
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|
#define NV_XP_DL_CYA_0_L0S_WAKE_UPDATE_CALC_INIT 0x00000001 /* RWI-V */
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|
#define NV_XP_DL_CYA_0_L0S_WAKE_UPDATE_CALC_OLD 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_0_L0S_WAKE_UPDATE_CALC_NEW 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_0_TRIGGER_EXTERNAL_LA 12:12 /* RWIVF */
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#define NV_XP_DL_CYA_0_TRIGGER_EXTERNAL_LA_INIT 0x00000000 /* RWI-V */
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|
#define NV_XP_DL_CYA_0_TRIGGER_EXTERNAL_LA_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_TRIGGER_EXTERNAL_LA_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_0_REPLAY_TIMEOUT_BEFORE_ACK_N_NAK 13:13 /* RWIVF */
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|
#define NV_XP_DL_CYA_0_REPLAY_TIMEOUT_BEFORE_ACK_N_NAK_INIT 0x00000000 /* RWI-V */
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|
#define NV_XP_DL_CYA_0_REPLAY_TIMEOUT_BEFORE_ACK_N_NAK_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_REPLAY_TIMEOUT_BEFORE_ACK_N_NAK_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_0_X16_DLLP_PACKING 14:14 /* RWIVF */
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|
#define NV_XP_DL_CYA_0_X16_DLLP_PACKING_INIT 0x00000000 /* RWI-V */
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|
#define NV_XP_DL_CYA_0_X16_DLLP_PACKING_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_X16_DLLP_PACKING_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_0_REFLECTED_WRITE_BAILOUT 15:15 /* RWIVF */
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|
#define NV_XP_DL_CYA_0_REFLECTED_WRITE_BAILOUT_INIT 0x00000001 /* RWI-V */
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|
#define NV_XP_DL_CYA_0_REFLECTED_WRITE_BAILOUT_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_REFLECTED_WRITE_BAILOUT_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER 19:16 /* RWIVF */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_INIT 0x0000000F /* RWI-V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_ENTER_L1_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_ENTER_L1_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_ENTER_L23_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_ENTER_L23_ENABLE 0x00000002 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_AS_REQ_L1_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_AS_REQ_L1_ENABLE 0x00000004 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_REQ_ACK_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_REQ_ACK_ENABLE 0x00000008 /* RW--V */
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#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_NONE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_0_PM_DLLP_FILTER_ALL 0x0000000F /* RW--V */
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#define NV_XP_DL_CYA_0_REMOTE_EXTENDED_SYNC 21:20 /* RWIVF */
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|
#define NV_XP_DL_CYA_0_REMOTE_EXTENDED_SYNC_INIT 0x00000002 /* RWI-V */
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|
#define NV_XP_DL_CYA_0_REMOTE_EXTENDED_SYNC_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_0_REMOTE_EXTENDED_SYNC_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_0_REMOTE_EXTENDED_SYNC_SYMMETRIC 0x00000002 /* RW--V */
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|
#define NV_XP_DL_CYA_0_REPLAY_L0S_TIMING 22:22 /* RWIVF */
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#define NV_XP_DL_CYA_0_REPLAY_L0S_TIMING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_CYA_0_REPLAY_L0S_TIMING_STATIC 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_0_REPLAY_L0S_TIMING_DYNAMIC 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_0_USE_REPLAY_DUE_TO_TIMEOUT_PENDING 23:23 /* RWIVF */
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#define NV_XP_DL_CYA_0_USE_REPLAY_DUE_TO_TIMEOUT_PENDING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_CYA_0_USE_REPLAY_DUE_TO_TIMEOUT_PENDING_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_0_USE_REPLAY_DUE_TO_TIMEOUT_PENDING_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_0_REPLAY_TIMER_STYLE 24:24 /* RWIVF */
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#define NV_XP_DL_CYA_0_REPLAY_TIMER_STYLE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_CYA_0_REPLAY_TIMER_STYLE_OLD 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_0_REPLAY_TIMER_STYLE_SIMPLIFIED 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_1(i) (0x0008B980+(i)*4) /* RW-4A */
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#define NV_XP_DL_CYA_1__SIZE_1 1 /* */
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#define NV_XP_DL_CYA_1__PRIV_LEVEL_MASK 0x0008E1B8 /* */
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#define NV_XP_DL_CYA_1_ACK_L1_NO_WAIT 0:0 /* RWIVF */
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#define NV_XP_DL_CYA_1_ACK_L1_NO_WAIT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_CYA_1_ACK_L1_NO_WAIT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_1_ACK_L1_NO_WAIT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_1_L2_L3_READY_STATE 1:1 /* RWIVF */
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#define NV_XP_DL_CYA_1_L2_L3_READY_STATE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_DL_CYA_1_L2_L3_READY_STATE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_1_L2_L3_READY_STATE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_1_L1_ASPM_SUPPORT 2:2 /* RWIVF */
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#define NV_XP_DL_CYA_1_L1_ASPM_SUPPORT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_CYA_1_L1_ASPM_SUPPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_1_L1_ASPM_SUPPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_1_NAK_EACH_ASL1_REQ 3:3 /* RWIVF */
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#define NV_XP_DL_CYA_1_NAK_EACH_ASL1_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_CYA_1_NAK_EACH_ASL1_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_DL_CYA_1_NAK_EACH_ASL1_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_1_ACK_BEFORE_L0S 4:4 /* RWIVF */
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#define NV_XP_DL_CYA_1_ACK_BEFORE_L0S_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_CYA_1_ACK_BEFORE_L0S_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_1_ACK_BEFORE_L0S_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_1_L0S_ASPM_SUPPORT 5:5 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_L0S_ASPM_SUPPORT_INIT 0x00000000 /* RWI-V */
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|
#define NV_XP_DL_CYA_1_L0S_ASPM_SUPPORT_DISABLE 0x00000000 /* RW--V */
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|
#define NV_XP_DL_CYA_1_L0S_ASPM_SUPPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_DL_CYA_1_DLLP_AWAIT_EQUALIZATION 6:6 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_DLLP_AWAIT_EQUALIZATION_INIT 0x00000001 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_DLLP_AWAIT_EQUALIZATION_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_DLLP_AWAIT_EQUALIZATION_ENABLE 0x00000001 /* RW--V */
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|
#define NV_XP_DL_CYA_1_RECOVERY_TRUMPS_ACK 7:7 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_RECOVERY_TRUMPS_ACK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_RECOVERY_TRUMPS_ACK_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_RECOVERY_TRUMPS_ACK_ENALBE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_UNUSED_7_TO_10 10:8 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_UNUSED_7_TO_10_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_ASPM_TEST 12:11 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_ASPM_TEST_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_ASPM_TEST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_TEST_L0S_ONCE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_TEST_L1_ONCE 0x00000002 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_TEST_DONE 0x00000003 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_FLUSH_BEFORE_L0S 13:13 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_FLUSH_BEFORE_L0S_INIT 0x00000001 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_FLUSH_BEFORE_L0S_DISABLE 0x00000000 /* RW--V */
|
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#define NV_XP_DL_CYA_1_FLUSH_BEFORE_L0S_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_SPEED_CHANGE_HOLDOFF 14:14 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_ASPM_SPEED_CHANGE_HOLDOFF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_ASPM_SPEED_CHANGE_HOLDOFF_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_SPEED_CHANGE_HOLDOFF_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_IGNORE_UNCHANGED_UPDATE_FC 15:15 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_ASPM_IGNORE_UNCHANGED_UPDATE_FC_INIT 0x00000001 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_ASPM_IGNORE_UNCHANGED_UPDATE_FC_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_IGNORE_UNCHANGED_UPDATE_FC_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE 23:16 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_INIT 0x000000FF /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_DISABLE_ALL 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN1_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN1_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN1_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN1_ENABLE 0x00000002 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN2_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN2_ENABLE 0x00000004 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN2_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN2_ENABLE 0x00000008 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN3_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN3_ENABLE 0x00000010 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN3_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN3_ENABLE 0x00000020 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN4_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L0S_GEN4_ENABLE 0x00000040 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN4_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_ASPM_WINIDLE_L1_GEN4_ENABLE 0x00000080 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_RESTART_ASPM_L1_AFTER_RECOVERY 24:24 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_RESTART_ASPM_L1_AFTER_RECOVERY_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_RESTART_ASPM_L1_AFTER_RECOVERY_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_RESTART_ASPM_L1_AFTER_RECOVERY_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_BUG1042979FIX 25:25 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_BUG1042979FIX_INIT 0x00000001 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_BUG1042979FIX_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_BUG1042979FIX_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_BUG200544245FIX 26:26 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_BUG200544245FIX_INIT 0x00000001 /* RWI-V */
|
|
#define NV_XP_DL_CYA_1_BUG200544245FIX_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_BUG200544245FIX_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_XP_DL_CYA_1_UNUSED 31:27 /* RWIVF */
|
|
#define NV_XP_DL_CYA_1_UNUSED_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_2(i) (0x0008B9C0+(i)*4) /* RW-4A */
|
|
#define NV_XP_DL_CYA_2__SIZE_1 1 /* */
|
|
#define NV_XP_DL_CYA_2__PRIV_LEVEL_MASK 0x0008E1B8 /* */
|
|
#define NV_XP_DL_CYA_2_FORCE_SM_STATE_VAL 4:0 /* RWIVF */
|
|
#define NV_XP_DL_CYA_2_FORCE_SM_STATE_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_2_FORCE_SM_STATE_LD 5:5 /* RWIVF */
|
|
#define NV_XP_DL_CYA_2_FORCE_SM_STATE_LD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_2_RSVD_0 6:6 /* RWIVF */
|
|
#define NV_XP_DL_CYA_2_RSVD_0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_2_RSVD_1 7:7 /* RWIVF */
|
|
#define NV_XP_DL_CYA_2_RSVD_1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_2_RSVD_2 8:8 /* RWIVF */
|
|
#define NV_XP_DL_CYA_2_RSVD_2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_2_RSVD_3 9:9 /* RWIVF */
|
|
#define NV_XP_DL_CYA_2_RSVD_3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_XP_DL_CYA_2_RSVD_4 10:10 /* RWIVF */
|
|
#define NV_XP_DL_CYA_2_RSVD_4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_CYA_2_RSVD_5 31:11 /* RWIVF */
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#define NV_XP_DL_CYA_2_RSVD_5_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_REPLAY_TIMER_1(i) (0x0008BA00+(i)*4) /* RW-4A */
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#define NV_XP_DL_REPLAY_TIMER_1__SIZE_1 1 /* */
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#define NV_XP_DL_REPLAY_TIMER_1__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_DL_REPLAY_TIMER_1_SIMPLIFIED_ES_OFF 16:0 /* RWIVF */
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#define NV_XP_DL_REPLAY_TIMER_1_SIMPLIFIED_ES_OFF_INIT 0x00005DC0 /* RWI-V */
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#define NV_XP_DL_REPLAY_TIMER_1_SIMPLIFIED_ES_OFF_MIN 0x00005DC0 /* RW--V */
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#define NV_XP_DL_REPLAY_TIMER_1_SIMPLIFIED_ES_OFF_MAX 0x00007918 /* RW--V */
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#define NV_XP_DL_REPLAY_TIMER_2(i) (0x0008BA40+(i)*4) /* RW-4A */
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#define NV_XP_DL_REPLAY_TIMER_2__SIZE_1 1 /* */
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#define NV_XP_DL_REPLAY_TIMER_2__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_DL_REPLAY_TIMER_2_SIMPLIFIED_ES_ON 16:0 /* RWIVF */
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#define NV_XP_DL_REPLAY_TIMER_2_SIMPLIFIED_ES_ON_INIT 0x00013880 /* RWI-V */
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#define NV_XP_DL_REPLAY_TIMER_2_SIMPLIFIED_ES_ON_MIN 0x00013880 /* RW--V */
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#define NV_XP_DL_REPLAY_TIMER_2_SIMPLIFIED_ES_ON_MAX 0x000186A0 /* RW--V */
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#define NV_XP_DL_ACK_LATENCY_TIMER(i) (0x0008BA80+(i)*4) /* RW-4A */
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#define NV_XP_DL_ACK_LATENCY_TIMER__SIZE_1 1 /* */
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#define NV_XP_DL_ACK_LATENCY_TIMER_VALUE 18:0 /* R--VF */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN4 26:26 /* RWIVF */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN4_INIT 0x00000000 /* */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN4_DONE 0x00000000 /* RWI-V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN4_PENDING 0x00000001 /* -W--T */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN3 27:27 /* RWIVF */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN3_INIT 0x00000000 /* */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN3_DONE 0x00000000 /* RWI-V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN3_PENDING 0x00000001 /* -W--T */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN2 28:28 /* RWIVF */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN2_INIT 0x00000000 /* */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN2_DONE 0x00000000 /* RWI-V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN2_PENDING 0x00000001 /* -W--T */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN1 29:29 /* RWIVF */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN1_INIT 0x00000000 /* */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN1_DONE 0x00000000 /* RWI-V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_RESET_GEN1_PENDING 0x00000001 /* -W--T */
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#define NV_XP_DL_ACK_LATENCY_TIMER_SPEED_SEL 31:30 /* RWIVF */
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#define NV_XP_DL_ACK_LATENCY_TIMER_SPEED_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_SPEED_SEL_GEN1 0x00000000 /* RW--V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_SPEED_SEL_GEN2 0x00000001 /* RW--V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_SPEED_SEL_GEN3 0x00000002 /* RW--V */
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#define NV_XP_DL_ACK_LATENCY_TIMER_SPEED_SEL_GEN4 0x00000003 /* RW--V */
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#define NV_XP_PL_LINK_PRESENT 0x0008C000 /* R--4R */
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#define NV_XP_PL_LINK_PRESENT_15 15:15 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_14 14:14 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_13 13:13 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_12 12:12 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_11 11:11 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_10 10:10 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_09 9:9 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_08 8:8 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_07 7:7 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_06 6:6 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_05 5:5 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_04 4:4 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_03 3:3 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_02 2:2 /* R--VF */
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#define NV_XP_PL_LINK_PRESENT_01 1:1 /* R-IVF */
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#define NV_XP_PL_LINK_PRESENT_01_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LINK_PRESENT_00 0:0 /* R--VF */
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#define NV_XP_PL_LANE_PRESENT 0x0008C004 /* R--4R */
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#define NV_XP_PL_LANE_PRESENT_15 15:15 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_15_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_14 14:14 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_14_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_13 13:13 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_13_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_12 12:12 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_12_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_11 11:11 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_11_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_10 10:10 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_10_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_09 9:9 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_09_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_08 8:8 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_08_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_07 7:7 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_07_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_06 6:6 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_06_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_05 5:5 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_05_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_04 4:4 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_04_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_03 3:3 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_03_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_02 2:2 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_02_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_01 1:1 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_01_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LANE_PRESENT_00 0:0 /* R-IVF */
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#define NV_XP_PL_LANE_PRESENT_00_INIT 0x1 /* R-I-V */
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#define NV_XP_PL_LINK_CONFIG_0(i) (0x0008C040+(i)*4) /* RW-4A */
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#define NV_XP_PL_LINK_CONFIG_0__SIZE_1 1 /* */
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#define NV_XP_PL_LINK_CONFIG_0__PRIV_LEVEL_MASK 0x0008E1F0 /* */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER 31:27 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_INIT 0x00000010 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_NULL 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_00_00 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_01_01 0x00000003 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_02_02 0x00000005 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_03_03 0x00000007 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_04_04 0x00000009 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_05_05 0x0000000B /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_06_06 0x0000000D /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_07_07 0x0000000F /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_08_08 0x00000011 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_09_09 0x00000013 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_10_10 0x00000015 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_11_11 0x00000017 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_12_12 0x00000019 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_13_13 0x0000001B /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_14_14 0x0000001D /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_15_15 0x0000001F /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_01_00 0x00000002 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_03_02 0x00000006 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_05_04 0x0000000A /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_07_06 0x0000000E /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_09_08 0x00000012 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_11_10 0x00000016 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_13_12 0x0000001A /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_15_14 0x0000001E /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_03_00 0x00000004 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_07_04 0x0000000C /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_11_08 0x00000014 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_15_12 0x0000001C /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_07_00 0x00000008 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_15_08 0x00000018 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_SPECIFIER_15_00 0x00000010 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_ENCODING_OVERRIDE 26:25 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_ENCODING_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_ENCODING_OVERRIDE_OFF 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_ENCODING_OVERRIDE_GEN2 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_ENCODING_OVERRIDE_GEN3 0x00000002 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LINK_ENCODING_OVERRIDE_GEN4 0x00000003 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_EXTENDED_CONFIG_ENBL 24:24 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_EXTENDED_CONFIG_ENBL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_EXTENDED_CONFIG_ENBL_OFF 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_EXTENDED_CONFIG_ENBL_ON 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_ASYM_LINK_WIDTH_ENBL 23:23 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_ASYM_LINK_WIDTH_ENBL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_ASYM_LINK_WIDTH_ENBL_OFF 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_ASYM_LINK_WIDTH_ENBL_ON 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_TARGET_TX_WIDTH 22:20 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_TARGET_TX_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_TARGET_TX_WIDTH_x16 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_TARGET_TX_WIDTH_x8 0x00000004 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_TARGET_TX_WIDTH_x4 0x00000005 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_TARGET_TX_WIDTH_x2 0x00000006 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_TARGET_TX_WIDTH_x1 0x00000007 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_MAX_LINK_RATE 19:18 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_MAX_LINK_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_MAX_LINK_RATE_16000_MTPS 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_MAX_LINK_RATE_8000_MTPS 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_MAX_LINK_RATE_5000_MTPS 0x00000002 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_MAX_LINK_RATE_2500_MTPS 0x00000003 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_XCLK_FREQ_SLCT 15:14 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_XCLK_FREQ_SLCT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_XCLK_FREQ_SLCT_RSVD_0 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_XCLK_FREQ_SLCT_250_MHZ 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_XCLK_FREQ_SLCT_500_MHZ 0x00000002 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_XCLK_FREQ_SLCT_RSVD_1 0x00000003 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_XCLK_FREQ_SLCT 13:12 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_XCLK_FREQ_SLCT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_XCLK_FREQ_SLCT_125_MHZ 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_XCLK_FREQ_SLCT_250_MHZ 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_XCLK_FREQ_SLCT_500_MHZ 0x00000002 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_XCLK_FREQ_SLCT_RSVD 0x00000003 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_SERDES_INTERFACE_MODE 11:11 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_SERDES_INTERFACE_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_SERDES_INTERFACE_MODE_FAST 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN2_SERDES_INTERFACE_MODE_WIDE 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_SERDES_INTERFACE_MODE 10:10 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_SERDES_INTERFACE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_SERDES_INTERFACE_MODE_FAST 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_GEN1_SERDES_INTERFACE_MODE_WIDE 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_SKIP_TX_RCVR_DETECT 9:9 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_SKIP_TX_RCVR_DETECT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_SKIP_TX_RCVR_DETECT_OFF 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_SKIP_TX_RCVR_DETECT_ON 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_POLLING_THRESHOLD 8:8 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_POLLING_THRESHOLD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_POLLING_THRESHOLD_ONE_LANE 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_POLLING_THRESHOLD_ALL_LANES 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_DISABLE_SCRAMBLING 7:7 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_DISABLE_SCRAMBLING_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_DISABLE_SCRAMBLING_OFF 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_DISABLE_SCRAMBLING_ON 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_STATUS 4:4 /* R--VF */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_STATUS_IDLE 0x00000000 /* R---V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_STATUS_BUSY 0x00000001 /* R---V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE 3:0 /* RWIVF */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_NORMAL_OPERATIONS 0x00000000 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_CHANGE_SPEED 0x00000001 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_CHANGE_WIDTH 0x00000002 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_CHANGE_SPEED_WIDTH 0x00000003 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_GOTO_DETECT 0x00000004 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_LOOPBACK_IDLE_DATA 0x00000005 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_LOOPBACK_COMPLIANCE 0x00000006 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_LOOPBACK_MOD_COMPLI 0x00000007 /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_GOTO_RECOVERY 0x0000000C /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_HOT_RESET_AND_DETECT 0x0000000E /* RW--V */
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#define NV_XP_PL_LINK_CONFIG_0_LTSSM_DIRECTIVE_HOT_RESET_AND_HOLD 0x0000000F /* RW--V */
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#define NV_XP_PL_LINK_STATUS_0(i) (0x0008C080+(i)*4) /* R--4A */
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#define NV_XP_PL_LINK_STATUS_0__SIZE_1 1 /* */
|
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES 12:8 /* R--VF */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_NULL 0x00000000 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_00_00 0x00000001 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_01_01 0x00000003 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_02_02 0x00000005 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_03_03 0x00000007 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_04_04 0x00000009 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_05_05 0x0000000B /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_06_06 0x0000000D /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_07_07 0x0000000F /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_08_08 0x00000011 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_09_09 0x00000013 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_10_10 0x00000015 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_11_11 0x00000017 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_12_12 0x00000019 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_13_13 0x0000001B /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_14_14 0x0000001D /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_15_15 0x0000001F /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_01_00 0x00000002 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_03_02 0x00000006 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_05_04 0x0000000A /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_07_06 0x0000000E /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_09_08 0x00000012 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_11_10 0x00000016 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_13_12 0x0000001A /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_15_14 0x0000001E /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_03_00 0x00000004 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_07_04 0x0000000C /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_11_08 0x00000014 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_15_12 0x0000001C /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_07_00 0x00000008 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_15_08 0x00000018 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_TX_LANES_15_00 0x00000010 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES 4:0 /* R--VF */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_NULL 0x00000000 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_00_00 0x00000001 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_01_01 0x00000003 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_02_02 0x00000005 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_03_03 0x00000007 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_04_04 0x00000009 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_05_05 0x0000000B /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_06_06 0x0000000D /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_07_07 0x0000000F /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_08_08 0x00000011 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_09_09 0x00000013 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_10_10 0x00000015 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_11_11 0x00000017 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_12_12 0x00000019 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_13_13 0x0000001B /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_14_14 0x0000001D /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_15_15 0x0000001F /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_01_00 0x00000002 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_03_02 0x00000006 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_05_04 0x0000000A /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_07_06 0x0000000E /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_09_08 0x00000012 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_11_10 0x00000016 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_13_12 0x0000001A /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_15_14 0x0000001E /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_03_00 0x00000004 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_07_04 0x0000000C /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_11_08 0x00000014 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_15_12 0x0000001C /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_07_00 0x00000008 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_15_08 0x00000018 /* R---V */
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#define NV_XP_PL_LINK_STATUS_0_ACTIVE_RX_LANES_15_00 0x00000010 /* R---V */
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#define NV_XP_PL_N_FTS_LOCAL(i) (0x0008C100+(i)*4) /* RW-4A */
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#define NV_XP_PL_N_FTS_LOCAL__SIZE_1 1 /* */
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#define NV_XP_PL_N_FTS_LOCAL__PRIV_LEVEL_MASK 0x0008E1E8 /* */
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#define NV_XP_PL_N_FTS_LOCAL_GEN1 7:0 /* RWIVF */
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#define NV_XP_PL_N_FTS_LOCAL_GEN1_INIT 0x0000001F /* RWI-V */
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#define NV_XP_PL_N_FTS_LOCAL_GEN2 15:8 /* RWIVF */
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#define NV_XP_PL_N_FTS_LOCAL_GEN2_INIT 0x0000002C /* RWI-V */
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#define NV_XP_PL_N_FTS_LOCAL_GEN3 23:16 /* RWIVF */
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#define NV_XP_PL_N_FTS_LOCAL_GEN3_INIT 0x0000002C /* RWI-V */
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#define NV_XP_PL_N_FTS_LOCAL_GEN4 31:24 /* RWIVF */
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#define NV_XP_PL_N_FTS_LOCAL_GEN4_INIT 0x0000002C /* RWI-V */
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#define NV_XP_PL_N_FTS_REMOTE(i) (0x0008C140+(i)*4) /* R--4A */
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#define NV_XP_PL_N_FTS_REMOTE__SIZE_1 1 /* */
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#define NV_XP_PL_N_FTS_REMOTE_GEN1 7:0 /* R--VF */
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#define NV_XP_PL_N_FTS_REMOTE_GEN2 15:8 /* R--VF */
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#define NV_XP_PL_N_FTS_REMOTE_GEN3 23:16 /* R--VF */
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#define NV_XP_PL_N_FTS_REMOTE_GEN4 31:24 /* R--VF */
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#define NV_XP_PL_FTS_DETECT_START(i) (0x0008C180+(i)*4) /* RW-4A */
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#define NV_XP_PL_FTS_DETECT_START__SIZE_1 1 /* */
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#define NV_XP_PL_FTS_DETECT_START__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_FTS_DETECT_START_GEN1 7:0 /* RWIVF */
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#define NV_XP_PL_FTS_DETECT_START_GEN1_INIT 0x00000050 /* RWI-V */
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#define NV_XP_PL_FTS_DETECT_START_GEN2 15:8 /* RWIVF */
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#define NV_XP_PL_FTS_DETECT_START_GEN2_INIT 0x00000040 /* RWI-V */
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#define NV_XP_PL_FTS_DETECT_START_GEN3 23:16 /* RWIVF */
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#define NV_XP_PL_FTS_DETECT_START_GEN3_INIT 0x00000040 /* RWI-V */
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#define NV_XP_PL_FTS_DETECT_START_GEN4 31:24 /* RWIVF */
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#define NV_XP_PL_FTS_DETECT_START_GEN4_INIT 0x00000040 /* RWI-V */
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#define NV_XP_PL_LCTRL_2(i) (0x0008C1C0+(i)*4) /* RW-4A */
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#define NV_XP_PL_LCTRL_2__SIZE_1 1 /* */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED 19:16 /* RWIVF */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_2P5 0x00000001 /* RW--V */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_5P0_2P5 0x00000002 /* RW--V */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_8P0_5P0_2P5 0x00000003 /* RW--V */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_16P0_8P0_5P0_2P5 0x00000004 /* RWI-V */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE 23:20 /* R-IVF */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_2P5 0x00000003 /* R-I-V */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_5P0_2P5 0x00000002 /* R---V */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_8P0_5P0_2P5 0x00000001 /* R---V */
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#define NV_XP_PL_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_16P0_8P0_5P0_2P5 0x00000000 /* R---V */
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#define NV_XP_PL_LCTRL_3(i) (0x0008C1D0+(i)*4) /* RW-4A */
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#define NV_XP_PL_LCTRL_3__SIZE_1 1 /* */
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#define NV_XP_PL_LCTRL_3__PRIV_LEVEL_MASK 0x0008E1E4 /* */
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#define NV_XP_PL_LCTRL_3_AUTONOMOUS_CHANGE 1:1 /* RWIVF */
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#define NV_XP_PL_LCTRL_3_AUTONOMOUS_CHANGE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_LCTRL_3_UPCONFIGURE_CAPABLE 2:2 /* R--VF */
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#define NV_XP_PL_LCTRL_3_N_EIE_SYMBOLS 6:3 /* RWIVF */
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#define NV_XP_PL_LCTRL_3_N_EIE_SYMBOLS_INIT 0x00000006 /* RWI-V */
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#define NV_XP_PL_LCTRL_3_N_EIE_SYMBOLS_MAX 0x00000008 /* RW--V */
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#define NV_XP_PL_LCTRL_3_CYA_TX_MARGIN_OVERRIDE 8:8 /* RWIVF */
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#define NV_XP_PL_LCTRL_3_CYA_TX_MARGIN_OVERRIDE_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_PL_LCTRL_3_CYA_TX_MARGIN_OVERRIDE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_LCTRL_3_LTSSM_TIMER_OVERRIDE 12:10 /* RWIVF */
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#define NV_XP_PL_LCTRL_3_LTSSM_TIMER_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LCTRL_3_LTSSM_TIMER_OVERRIDE_NONE 0x00000000 /* RW--V */
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#define NV_XP_PL_LCTRL_3_LTSSM_TIMER_OVERRIDE_DETECT 0x00000001 /* RW--V */
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#define NV_XP_PL_LCTRL_3_LTSSM_TIMER_OVERRIDE_ALL 0x00000003 /* RW--V */
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#define NV_XP_PL_LCTRL_3_LTSSM_TIMER_OVERRIDE_ACCEL 0x00000004 /* RW--V */
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#define NV_XP_PL_LCTRL_3_LTSSM_PERIODIC_EQ_TIMER_OVERRIDE 13:13 /* RWIVF */
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#define NV_XP_PL_LCTRL_3_LTSSM_PERIODIC_EQ_TIMER_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_LCTRL_3_LTSSM_PERIODIC_EQ_TIMER_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_LCTRL_3_RECOVERY_SPEED_TIMEOUT_ADJ 26:24 /* RWIVF */
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#define NV_XP_PL_LCTRL_3_RECOVERY_SPEED_TIMEOUT_ADJ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_INIT_RECOVERY(i) (0x0008C200+(i)*4) /* RW-4A */
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#define NV_XP_PL_INIT_RECOVERY__SIZE_1 1 /* */
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#define NV_XP_PL_INIT_RECOVERY__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_THRESHOLD 19:0 /* RWIVF */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_THRESHOLD_2500 0x000009C4 /* RWI-V */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_WINDOW 30:20 /* RWIVF */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_WINDOW_100US 0x00000064 /* RWI-V */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_ENABLE 31:31 /* RWIVF */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_ENABLE_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_INIT_RECOVERY_8B10B_ERROR_ENABLE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0 0x0008C2C0 /* RW-4R */
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#define NV_XP_PL_CYA_0_AUTO_DISABLE_GEN3_SPEED 0:0 /* RWIVF */
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#define NV_XP_PL_CYA_0_AUTO_DISABLE_GEN3_SPEED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_AUTO_DISABLE_GEN3_SPEED_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_AUTO_DISABLE_GEN3_SPEED_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN2_SPEED 2:2 /* RWIVF */
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#define NV_XP_PL_CYA_0_DISABLE_GEN2_SPEED_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN2_SPEED_FALSE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN2_SPEED_TRUE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN4_SPEED 13:13 /* RWIVF */
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#define NV_XP_PL_CYA_0_DISABLE_GEN4_SPEED_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN4_SPEED_FALSE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN4_SPEED_TRUE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_POST_EQZN_LINK_SPEED 21:19 /* RWIVF */
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#define NV_XP_PL_CYA_0_POST_EQZN_LINK_SPEED_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_POST_EQZN_LINK_SPEED_NOCHANGE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_POST_EQZN_LINK_SPEED_GEN1 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_POST_EQZN_LINK_SPEED_GEN2 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_0_POST_EQZN_LINK_SPEED_GEN3 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_0_POST_EQZN_LINK_SPEED_GEN4 0x00000004 /* RW--V */
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#define NV_XP_PL_CYA_0_POST_EQZN_DOWNTRAIN 22:22 /* RWIVF */
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#define NV_XP_PL_CYA_0_POST_EQZN_DOWNTRAIN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_POST_EQZN_DOWNTRAIN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_POST_EQZN_DOWNTRAIN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN3_SPEED 23:23 /* RWIVF */
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#define NV_XP_PL_CYA_0_DISABLE_GEN3_SPEED_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN3_SPEED_FALSE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_DISABLE_GEN3_SPEED_TRUE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1 0x0008C2C4 /* RW-4R */
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#define NV_XP_PL_CYA_0_1__PRIV_LEVEL_MASK 0x0008E1E0 /* */
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#define NV_XP_PL_CYA_0_1_REUSE_EQ_TS2_PRESETS 1:1 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_REUSE_EQ_TS2_PRESETS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_REUSE_EQ_TS2_PRESETS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_REUSE_EQ_TS2_PRESETS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_IGNORE_EQZN_TIMEOUTS 3:3 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_IGNORE_EQZN_TIMEOUTS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_IGNORE_EQZN_TIMEOUTS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_IGNORE_EQZN_TIMEOUTS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE0_DFE_TRAINING 4:4 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_PHASE0_DFE_TRAINING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_PHASE0_DFE_TRAINING_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE0_DFE_TRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAINING 5:5 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAINING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAINING_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAIN_DLY 7:6 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAIN_DLY_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAIN_DLY_001_US 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAIN_DLY_006_US 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAIN_DLY_010_US 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_0_1_PHASE2_DFE_TRAIN_DLY_020_US 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_0_1_BACKUP_PRESET 11:8 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_BACKUP_PRESET_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_SEND_SKP_BEFORE_MCOMP 12:12 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_SEND_SKP_BEFORE_MCOMP_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_SEND_SKP_BEFORE_MCOMP_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_SEND_SKP_BEFORE_MCOMP_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_QUIESCE_GUARANTEE 14:14 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_QUIESCE_GUARANTEE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_QUIESCE_GUARANTEE_FALSE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_QUIESCE_GUARANTEE_TRUE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_REQUEST_EQUALIZATION 15:15 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_REQUEST_EQUALIZATION_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_REQUEST_EQUALIZATION_DONE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_REQUEST_EQUALIZATION_PENDING 0x00000001 /* -W--T */
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#define NV_XP_PL_CYA_0_1_SET_POLARITY_AT_COM3 16:16 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_SET_POLARITY_AT_COM3_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_SET_POLARITY_AT_COM3_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_SET_POLARITY_AT_COM3_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_RESET_IDLE_CTR_ON_NON_IDL_SKP 17:17 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_RESET_IDLE_CTR_ON_NON_IDL_SKP_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_RESET_IDLE_CTR_ON_NON_IDL_SKP_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_RESET_IDLE_CTR_ON_NON_IDL_SKP_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_IGNORE_LTSSMHOLD_FROM_HOST 18:18 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_IGNORE_LTSSMHOLD_FROM_HOST_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_LTSSM_COUNT_ONLY_7_TSX 24:24 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_LTSSM_COUNT_ONLY_7_TSX_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_LTSSM_COUNT_ONLY_7_TSX_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_LTSSM_COUNT_ONLY_7_TSX_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_LOOPBACK_DFE_TRAINING 25:25 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_LOOPBACK_DFE_TRAINING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_LOOPBACK_DFE_TRAINING_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_LOOPBACK_DFE_TRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_COMPLIANCE_DFE_TRAINING 26:26 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_COMPLIANCE_DFE_TRAINING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_COMPLIANCE_DFE_TRAINING_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_0_1_COMPLIANCE_DFE_TRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_0_1_EXTRA_TX_FTS 31:27 /* RWIVF */
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#define NV_XP_PL_CYA_0_1_EXTRA_TX_FTS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_0_1_EXTRA_TX_FTS_10 0x0000000a /* RW--V */
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#define NV_XP_PL_CYA_0_1_EXTRA_TX_FTS_20 0x00000014 /* RW--V */
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#define NV_XP_PL_CYA_1(i) (0x0008C300+(i)*4) /* RW-4A */
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#define NV_XP_PL_CYA_1__SIZE_1 1 /* */
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#define NV_XP_PL_CYA_1__PRIV_LEVEL_MASK 0x0008E1E0 /* */
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#define NV_XP_PL_CYA_1_IDLE_TO_L0_DELAY 3:0 /* RWIVF */
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#define NV_XP_PL_CYA_1_IDLE_TO_L0_DELAY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM 4:4 /* RWIVF */
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#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_BLOCK_HOST2XP_HOLD_LTSSM_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_WAIT_FOR_HOSTCLK_RDY 5:5 /* RWIVF */
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#define NV_XP_PL_CYA_1_WAIT_FOR_HOSTCLK_RDY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_TRIAL_LOW_SHORT_TIMEOUT 6:6 /* RWIVF */
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#define NV_XP_PL_CYA_1_TRIAL_LOW_SHORT_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_1_CONFIG_ROBUST_MODE 7:7 /* RWIVF */
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#define NV_XP_PL_CYA_1_CONFIG_ROBUST_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_1_CONFIG_ROBUST_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_CONFIG_ROBUST_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_LOOPBACK_EXIT_THRESHOLD 15:8 /* RWIVF */
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#define NV_XP_PL_CYA_1_LOOPBACK_EXIT_THRESHOLD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_STICKY_TX_IDLE 16:16 /* RWIVF */
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#define NV_XP_PL_CYA_1_STICKY_TX_IDLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_STICKY_TX_IDLE_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_STICKY_TX_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_WAIT_FOR_DESKEW 17:17 /* RWIVF */
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#define NV_XP_PL_CYA_1_WAIT_FOR_DESKEW_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_1_WAIT_FOR_DESKEW_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_WAIT_FOR_DESKEW_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN 18:18 /* RWIVF */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN_ANY 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN_ALL 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_HOST2XP_HOLD_LTSSM_IN_NULL 19:19 /* RWIVF */
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#define NV_XP_PL_CYA_1_HOST2XP_HOLD_LTSSM_IN_NULL_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_1_HOST2XP_HOLD_LTSSM_IN_NULL_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_HOST2XP_HOLD_LTSSM_IN_NULL_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_CLK_CHG_B_SHORT_TIMEOUT 20:20 /* RWIVF */
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#define NV_XP_PL_CYA_1_CLK_CHG_B_SHORT_TIMEOUT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_CLK_CHG_B_SHORT_TIMEOUT_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_CLK_CHG_B_SHORT_TIMEOUT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN_FOR_DISABLED_STATE 21:21 /* RWIVF */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN_FOR_DISABLED_STATE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN_FOR_DISABLED_STATE_ALL 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_1_RCVR_EIDLE_CDN_FOR_DISABLED_STATE_ANY 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_CLK_CHG_C_MIN_TIME 23:22 /* RWIVF */
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#define NV_XP_PL_CYA_1_CLK_CHG_C_MIN_TIME_500NS 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_1_CLK_CHG_C_MIN_TIME_800NS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_1_CLK_CHG_C_MIN_TIME_001US 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_1_CLK_CHG_C_MIN_TIME_004US 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_1_SPARE 31:24 /* RWIVF */
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#define NV_XP_PL_CYA_1_SPARE_INIT 0x00000020 /* RWI-V */
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#define NV_XP_PL_CYA_2 0x0008C340 /* RW-4R */
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#define NV_XP_PL_CYA_2__PRIV_LEVEL_MASK 0x0008E1E0 /* */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY 3:0 /* RWIVF */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_INIT 0x00000004 /* RWI-V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_004_US 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_008_US 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_012_US 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_016_US 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_020_US 0x00000004 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_024_US 0x00000005 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_028_US 0x00000006 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_032_US 0x00000007 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_036_US 0x00000008 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_040_US 0x00000009 /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_070_US 0x0000000A /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_100_US 0x0000000B /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_125_US 0x0000000C /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_250_US 0x0000000D /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_500_US 0x0000000E /* RW--V */
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#define NV_XP_PL_CYA_2_RECOVERY_DFE_TRAIN_DLY_001_MS 0x0000000F /* RW--V */
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#define NV_XP_PL_CYA_2_RSVD_1 7:4 /* RWIVF */
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#define NV_XP_PL_CYA_2_RSVD_1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_2_PHASE2_TIMEOUT 12:8 /* RWIVF */
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#define NV_XP_PL_CYA_2_PHASE2_TIMEOUT_INIT 0x00000018 /* RWI-V */
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#define NV_XP_PL_CYA_2_SPARE_1 15:13 /* RWIVF */
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#define NV_XP_PL_CYA_2_SPARE_1_INIT 0x00000004 /* RWI-V */
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#define NV_XP_PL_CYA_2_EQUALIZATION_REQUEST_DATA_RATE 16:16 /* RWIVF */
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#define NV_XP_PL_CYA_2_EQUALIZATION_REQUEST_DATA_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_2_EQUALIZATION_REQUEST_DATA_RATE_GEN3 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_2_EQUALIZATION_REQUEST_DATA_RATE_GEN4 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_2_SEND_EXTRA_TSX 22:22 /* RWIVF */
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#define NV_XP_PL_CYA_2_SEND_EXTRA_TSX_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_2_SEND_EXTRA_TSX_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_2_SEND_EXTRA_TSX_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_2_FG_EXPLR_MODE 23:23 /* RWIVF */
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#define NV_XP_PL_CYA_2_FG_EXPLR_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_2_FG_EXPLR_MODE_FOUR_DIR 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_2_FG_EXPLR_MODE_EIGHT_DIR 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_2_LPBK_SLAVE_TIMEOUT 24:24 /* RWIVF */
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#define NV_XP_PL_CYA_2_LPBK_SLAVE_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_2_LPBK_SLAVE_TIMEOUT_1_MS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_2_LPBK_SLAVE_TIMEOUT_2_MS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_2_RX_QEYE_HYSTERESIS 27:25 /* RWIVF */
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#define NV_XP_PL_CYA_2_RX_QEYE_HYSTERESIS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_2_RSVD_2 29:28 /* RWIVF */
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#define NV_XP_PL_CYA_2_RSVD_2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_EN 30:30 /* RWIVF */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_VAL 31:31 /* RWIVF */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_VAL_ZERO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_2_STRAP_PCIE_CFG_OVERRIDE_VAL_ONE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_3 0x0008C380 /* RW-4R */
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#define NV_XP_PL_CYA_3__PRIV_LEVEL_MASK 0x0008E1E0 /* */
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#define NV_XP_PL_CYA_3_RX_EOM_THRESHOLD 15:0 /* RWIVF */
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#define NV_XP_PL_CYA_3_RX_EOM_THRESHOLD_INIT 0x0000003E /* RWI-V */
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#define NV_XP_PL_CYA_3_RX_EOM_THRESHOLD_MIN 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_3_RX_EOM_THRESHOLD_MAX 0x0000003F /* RW--V */
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#define NV_XP_PL_CYA_3_LTSSM_ESCAPE_TO_EXT_EVNT 31:16 /* RWIVF */
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#define NV_XP_PL_CYA_3_LTSSM_ESCAPE_TO_EXT_EVNT_INIT 0x000003E8 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN 0x0008C384 /* RW-4R */
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#define NV_XP_PL_PAD_PWRDN__PRIV_LEVEL_MASK 0x0008E1EC /* */
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#define NV_XP_PL_PAD_PWRDN_L1 0:0 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_L1_EN 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_L1_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_DISABLED 2:2 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_DISABLED_L0 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_DISABLED_L1 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_DISABLED__PROD 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_L1_LANE0 4:4 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_L1_LANE0_ENABLED 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_L1_LANE0_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_L1 5:5 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_L1_ENABLED 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_L1_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_DYNAMIC 6:6 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_DYNAMIC_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_IDLE_EN_DYNAMIC_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_LANE0 27:26 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_LANE0_L0 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_LANE0_L1 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_LANE0_L1P 0x00000002 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_LANE0_L1PP 0x00000003 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1 29:28 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_L0 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_L1 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_L1P 0x00000002 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_L1_L1PP 0x00000003 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_DYNAMIC 31:30 /* RWIVF */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L0 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1P 0x00000002 /* RW--V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP 0x00000003 /* RWI-V */
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#define NV_XP_PL_PAD_PWRDN_SLEEP_MODE_DYNAMIC__PROD 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_4 0x0008C388 /* RW-4R */
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#define NV_XP_PL_CYA_4__PRIV_LEVEL_MASK 0x0008E1B8 /* */
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#define NV_XP_PL_CYA_4_DELAY_RXLANE_DATA_EN 0:0 /* RWIVF */
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#define NV_XP_PL_CYA_4_DELAY_RXLANE_DATA_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_DELAY_RXLANE_DATA_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_DELAY_RXLANE_DATA_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_NO_TSX 1:1 /* RWIVF */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_NO_TSX_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_NO_TSX_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_NO_TSX_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_ON_ERR 2:2 /* RWIVF */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_ON_ERR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_ON_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_REDO_ALIGNMENT_ON_ERR_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_RSVD_1 12:3 /* RWIVF */
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#define NV_XP_PL_CYA_4_RSVD_1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_ALIGN_ON_SECOND_EIEOS 13:13 /* RWIVF */
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#define NV_XP_PL_CYA_4_ALIGN_ON_SECOND_EIEOS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_ALIGN_ON_SECOND_EIEOS_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_ALIGN_ON_SECOND_EIEOS_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_BEFORE_EQZN 14:14 /* RWIVF */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_BEFORE_EQZN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_BEFORE_EQZN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_BEFORE_EQZN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_AFTER_EQZN 15:15 /* RWIVF */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_AFTER_EQZN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_AFTER_EQZN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_SLCT_TRGT_IN_CFG_CMPLT_AFTER_EQZN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_POST_EQZN_LINK_SPEED_STICKY 16:16 /* RWIVF */
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#define NV_XP_PL_CYA_4_POST_EQZN_LINK_SPEED_STICKY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_POST_EQZN_LINK_SPEED_STICKY_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_POST_EQZN_LINK_SPEED_STICKY_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_EQZN_DOWNTRAIN_AFTER_L0 18:17 /* RWIVF */
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#define NV_XP_PL_CYA_4_EQZN_DOWNTRAIN_AFTER_L0_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_EQZN_DOWNTRAIN_AFTER_L0_0_MS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_EQZN_DOWNTRAIN_AFTER_L0_10_MS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_EQZN_DOWNTRAIN_AFTER_L0_50_MS 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_4_EQZN_DOWNTRAIN_AFTER_L0_100_MS 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_4_IGNORE_TARGET_LINK_SPEED 19:19 /* RWIVF */
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#define NV_XP_PL_CYA_4_IGNORE_TARGET_LINK_SPEED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_IGNORE_TARGET_LINK_SPEED_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_IGNORE_TARGET_LINK_SPEED_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM14 20:20 /* RWIVF */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM14_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM14_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM14_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM15 21:21 /* RWIVF */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM15_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM15_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_DISABLE_DC_BALANCE_SYM15_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_RSVD_2 22:22 /* RWIVF */
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#define NV_XP_PL_CYA_4_RSVD_2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_RST_GEN3_TS_CNTR_ON_INVLD_TS_ID 23:23 /* RWIVF */
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#define NV_XP_PL_CYA_4_RST_GEN3_TS_CNTR_ON_INVLD_TS_ID_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_RST_GEN3_TS_CNTR_ON_INVLD_TS_ID_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_RST_GEN3_TS_CNTR_ON_INVLD_TS_ID_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_MATCH_SYM_6 24:24 /* RWIVF */
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#define NV_XP_PL_CYA_4_MATCH_SYM_6_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_MATCH_SYM_6_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_MATCH_SYM_6_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_INFER_EIDLE_ON_NO_VLD_RXCLK_FIFO_DATA 25:25 /* RWIVF */
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#define NV_XP_PL_CYA_4_INFER_EIDLE_ON_NO_VLD_RXCLK_FIFO_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_INFER_EIDLE_ON_NO_VLD_RXCLK_FIFO_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_INFER_EIDLE_ON_NO_VLD_RXCLK_FIFO_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_RST_TS1_CNT_WHEN_RCV_TS2 26:26 /* RWIVF */
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#define NV_XP_PL_CYA_4_RST_TS1_CNT_WHEN_RCV_TS2_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_RST_TS1_CNT_WHEN_RCV_TS2_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_RST_TS1_CNT_WHEN_RCV_TS2_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_WAKE_NONOP_FROM_IDDQ 27:27 /* RWIVF */
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#define NV_XP_PL_CYA_4_WAKE_NONOP_FROM_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_WAKE_NONOP_FROM_IDDQ_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_WAKE_NONOP_FROM_IDDQ_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_RSVD_3 28:28 /* RWIVF */
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#define NV_XP_PL_CYA_4_RSVD_3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_SEND_SKPOS_WITH_LEADING_LANE 29:29 /* RWIVF */
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#define NV_XP_PL_CYA_4_SEND_SKPOS_WITH_LEADING_LANE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_SEND_SKPOS_WITH_LEADING_LANE_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_SEND_SKPOS_WITH_LEADING_LANE_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_RD_SYM4_IN_ALL_STATES 30:30 /* RWIVF */
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#define NV_XP_PL_CYA_4_RD_SYM4_IN_ALL_STATES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_4_RD_SYM4_IN_ALL_STATES_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_RD_SYM4_IN_ALL_STATES_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_4_RD_SYM5_IN_ALL_STATES 31:31 /* RWIVF */
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#define NV_XP_PL_CYA_4_RD_SYM5_IN_ALL_STATES_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_4_RD_SYM5_IN_ALL_STATES_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_4_RD_SYM5_IN_ALL_STATES_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_COUNTERS 0x0008C38C /* RW-4R */
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#define NV_XP_PL_REALIGN_COUNTERS__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_REALIGN_COUNTERS_RSVD 11:0 /* RWIVF */
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#define NV_XP_PL_REALIGN_COUNTERS_RSVD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_REALIGN_COUNTERS_GEN3_SYNC_HDR_ERR_THRESHOLD_VAL 17:14 /* RWIVF */
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#define NV_XP_PL_REALIGN_COUNTERS_GEN3_SYNC_HDR_ERR_THRESHOLD_VAL_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PL_REALIGN_COUNTERS_GEN2_8B10B_ERR_THRESHOLD_IN_ALIGN_VAL 27:18 /* RWIVF */
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#define NV_XP_PL_REALIGN_COUNTERS_GEN2_8B10B_ERR_THRESHOLD_IN_ALIGN_VAL_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PL_REALIGN_COUNTERS_SPARE 31:28 /* RWIVF */
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#define NV_XP_PL_REALIGN_COUNTERS_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_REALIGN_TSX_WAIT 0x0008C390 /* RW-4R */
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#define NV_XP_PL_REALIGN_TSX_WAIT_VAL_GEN1 9:0 /* RWIVF */
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#define NV_XP_PL_REALIGN_TSX_WAIT_VAL_GEN1_INIT 0x00000200 /* RWI-V */
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#define NV_XP_PL_REALIGN_TSX_WAIT_VAL_GEN2 19:10 /* RWIVF */
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#define NV_XP_PL_REALIGN_TSX_WAIT_VAL_GEN2_INIT 0x00000100 /* RWI-V */
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#define NV_XP_PL_REALIGN_TSX_WAIT_VAL_GEN3 30:20 /* RWIVF */
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#define NV_XP_PL_REALIGN_TSX_WAIT_VAL_GEN3_INIT 0x00000250 /* RWI-V */
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#define NV_XP_PL_REALIGN_TSX_WAIT_1 0x0008C398 /* RW-4R */
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#define NV_XP_PL_REALIGN_TSX_WAIT_1__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_REALIGN_TSX_WAIT_1_VAL_GEN4 10:0 /* RWIVF */
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#define NV_XP_PL_REALIGN_TSX_WAIT_1_VAL_GEN4_INIT 0x00000128 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES 0x0008C394 /* RW-4R */
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#define NV_XP_PL_REALIGN_STATES__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_REALIGN_STATES_DETECT 0:0 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_DETECT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_DETECT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_DETECT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_POLLING 1:1 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_POLLING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_POLLING_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_POLLING_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN1 2:2 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN1_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN1_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN2 3:3 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN2_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN2_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN3 4:4 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN3_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN3_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN1 5:5 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN1_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN2 6:6 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN2_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN3 7:7 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN3_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN1 9:9 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN1_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN1_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN2 10:10 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN2_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN2_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN3 11:11 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN3_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN3_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN1 12:12 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN1_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN1_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN2 13:13 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN2_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN2_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN3 14:14 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN3_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN3_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN1 15:15 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN1_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN1_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN2 16:16 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN2_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN2_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN3 17:17 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN3_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN3_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_EQZN 18:18 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_EQZN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_EQZN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_EQZN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_DFE_TRAIN 19:19 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_DFE_TRAIN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_DFE_TRAIN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_DFE_TRAIN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN4 20:20 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN4_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN4_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRLOCK_GEN4_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN4 21:21 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN4_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_RCVRCFG_GEN4_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN4 22:22 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN4_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN4_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_HOTRESET_GEN4_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN4 23:23 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN4_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN4_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_LOOPBACK_GEN4_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN4 24:24 /* RWIVF */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN4_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN4_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_REALIGN_STATES_CONFIG_GEN4_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE(i) (0x0008C3C0+(i)*4) /* RW-4A */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE__SIZE_1 16 /* */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_VAL 8:0 /* RWIVF */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_0_VAL_DEFAULT 0x0000001F /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_1_VAL_DEFAULT 0x0000003E /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_2_VAL_DEFAULT 0x0000005D /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_3_VAL_DEFAULT 0x0000007C /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_4_VAL_DEFAULT 0x0000009B /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_5_VAL_DEFAULT 0x000000BA /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_6_VAL_DEFAULT 0x000000D9 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_7_VAL_DEFAULT 0x000000F8 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_8_VAL_DEFAULT 0x00000117 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_9_VAL_DEFAULT 0x00000136 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_10_VAL_DEFAULT 0x00000155 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_11_VAL_DEFAULT 0x00000174 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_12_VAL_DEFAULT 0x00000193 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_13_VAL_DEFAULT 0x000001B2 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_14_VAL_DEFAULT 0x000001D1 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_SLEEP_STAGGER_VALUE_LANE_15_VAL_DEFAULT 0x000001F0 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE(i) (0x0008C400+(i)*4) /* RW-4A */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE__SIZE_1 16 /* */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_VAL 5:0 /* RWIVF */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_0_VAL_DEFAULT 0x00000004 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_1_VAL_DEFAULT 0x00000008 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_2_VAL_DEFAULT 0x0000000C /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_3_VAL_DEFAULT 0x00000010 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_4_VAL_DEFAULT 0x00000004 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_5_VAL_DEFAULT 0x00000008 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_6_VAL_DEFAULT 0x0000000C /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_7_VAL_DEFAULT 0x00000010 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_8_VAL_DEFAULT 0x00000004 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_9_VAL_DEFAULT 0x00000008 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_10_VAL_DEFAULT 0x0000000C /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_11_VAL_DEFAULT 0x00000010 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_12_VAL_DEFAULT 0x00000004 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_13_VAL_DEFAULT 0x00000008 /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_14_VAL_DEFAULT 0x0000000C /* RWI-V */
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#define NV_XP_PL_LANE_STAGGER_TIMER_DATA_RDY_STAGGER_VALUE_LANE_15_VAL_DEFAULT 0x00000010 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_IDDQ_STATE_BEFORE_SLEEP 0x0008C440 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_IDDQ_STATE_BEFORE_SLEEP__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_IDDQ_STATE_BEFORE_SLEEP_VAL 7:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_IDDQ_STATE_BEFORE_SLEEP_VAL_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_IDDQ 0x0008C444 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_IDDQ__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_IDDQ_VAL 7:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_IDDQ_VAL_INIT 0x00000019 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_SLEEP_STAGGER 0x0008C448 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_SLEEP_STAGGER__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_SLEEP_STAGGER_VAL 7:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_SLEEP_STATE_BEFORE_SLEEP_STAGGER_VAL_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_SLEEP_STAGGER_TIME 0x0008C44C /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_SLEEP_STAGGER_TIME__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_SLEEP_STAGGER_TIME_VAL 9:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_SLEEP_STAGGER_TIME_VAL_INIT 0x00000210 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_SLEEP_BEFORE_DATA_EN 0x0008C450 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_SLEEP_BEFORE_DATA_EN__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_SLEEP_BEFORE_DATA_EN_VAL 15:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_SLEEP_BEFORE_DATA_EN_VAL_INIT 0x000000FA /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_DATA_EN_BEFORE_DATA_EN 0x0008C454 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_DATA_EN_BEFORE_DATA_EN__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_DATA_EN_BEFORE_DATA_EN_VAL 7:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_AFTER_DATA_EN_BEFORE_DATA_EN_VAL_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_BEFORE_SLEEP 0x0008C458 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_BEFORE_SLEEP__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_BEFORE_SLEEP_VAL 7:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_DIS_STATE_BEFORE_SLEEP_VAL_INIT 0x00000005 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_DATA_RDY_STAGGER_TIME 0x0008C45C /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_DATA_RDY_STAGGER_TIME__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_DATA_RDY_STAGGER_TIME_VAL 5:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_DATA_RDY_STAGGER_TIME_VAL_INIT 0x00000018 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN1 0x0008C460 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN1__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN1_VAL 15:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN1_VAL_INIT 0x00000060 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN2 0x0008C464 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN2__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN2_VAL 15:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN2_VAL_INIT 0x00000040 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN3 0x0008C468 /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN3__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN3_VAL 15:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN3_VAL_INIT 0x00000040 /* RWI-V */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN4 0x0008C46C /* RW-4R */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN4__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN4_VAL 15:0 /* RWIVF */
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#define NV_XP_PL_PAD_CTL_TIMER_MIN_TIME_DATA_EN_STATE_BEFORE_DATA_EN_RXLANE_GEN4_VAL_INIT 0x00000040 /* RWI-V */
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#define NV_XP_PL_DC_BALANCE_THRESHOLD 0x0008C470 /* RW-4R */
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#define NV_XP_PL_DC_BALANCE_THRESHOLD_SYM15_VAL 8:0 /* RWIVF */
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#define NV_XP_PL_DC_BALANCE_THRESHOLD_SYM15_VAL_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PL_DC_BALANCE_THRESHOLD_SYM14_VAL 17:9 /* RWIVF */
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#define NV_XP_PL_DC_BALANCE_THRESHOLD_SYM14_VAL_INIT 0x0000001F /* RWI-V */
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#define NV_XP_PL_CYA_5 0x0008C478 /* RW-4R */
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#define NV_XP_PL_CYA_5__PRIV_LEVEL_MASK 0x0008E1B8 /* */
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#define NV_XP_PL_CYA_5_REENABLE_GEN4_IN_L0 0:0 /* RWIVF */
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#define NV_XP_PL_CYA_5_REENABLE_GEN4_IN_L0_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_REENABLE_GEN4_IN_L0_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_REENABLE_GEN4_IN_L0_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_RSVD 5:1 /* RWIVF */
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#define NV_XP_PL_CYA_5_RSVD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_5_STOP_TXLANE_TS_CTR_AT_MAX 6:6 /* RWIVF */
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#define NV_XP_PL_CYA_5_STOP_TXLANE_TS_CTR_AT_MAX_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_STOP_TXLANE_TS_CTR_AT_MAX_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_STOP_TXLANE_TS_CTR_AT_MAX_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_SEND_SKPOS_IN_LPBKS_AS_PER_SPEC 7:7 /* RWIVF */
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#define NV_XP_PL_CYA_5_SEND_SKPOS_IN_LPBKS_AS_PER_SPEC_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_SEND_SKPOS_IN_LPBKS_AS_PER_SPEC_YES 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_SEND_SKPOS_IN_LPBKS_AS_PER_SPEC_NO 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_FIX_RX_STAT_IDL_DET 8:8 /* RWIVF */
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#define NV_XP_PL_CYA_5_FIX_RX_STAT_IDL_DET_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_5_FIX_RX_STAT_IDL_DET_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_FIX_RX_STAT_IDL_DET_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_RESET_IDL_STATUS_IN_RCVY_SPD 9:9 /* RWIVF */
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#define NV_XP_PL_CYA_5_RESET_IDL_STATUS_IN_RCVY_SPD_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_RESET_IDL_STATUS_IN_RCVY_SPD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_RESET_IDL_STATUS_IN_RCVY_SPD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_RX_TGL_ON_PCOMP_SPD_CHG 10:10 /* RWIVF */
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#define NV_XP_PL_CYA_5_RX_TGL_ON_PCOMP_SPD_CHG_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_5_RX_TGL_ON_PCOMP_SPD_CHG_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_RX_TGL_ON_PCOMP_SPD_CHG_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_PCOMPLIANCE_EXIT_IGNORE_RCVR_IN_EIDLE 12:12 /* RWIVF */
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#define NV_XP_PL_CYA_5_PCOMPLIANCE_EXIT_IGNORE_RCVR_IN_EIDLE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_PCOMPLIANCE_EXIT_IGNORE_RCVR_IN_EIDLE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_PCOMPLIANCE_EXIT_IGNORE_RCVR_IN_EIDLE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_RCVY_EQ_PH3_FIX_1 14:14 /* RWIVF */
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#define NV_XP_PL_CYA_5_RCVY_EQ_PH3_FIX_1_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_RCVY_EQ_PH3_FIX_1_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_RCVY_EQ_PH3_FIX_1_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT6_IN_ALL_STATES 17:17 /* RWIVF */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT6_IN_ALL_STATES_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT6_IN_ALL_STATES_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT6_IN_ALL_STATES_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT5_IN_ALL_STATES 18:18 /* RWIVF */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT5_IN_ALL_STATES_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT5_IN_ALL_STATES_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_RD_SYM9_BIT5_IN_ALL_STATES_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_REENABLE_GEN3_IN_L0 19:19 /* RWIVF */
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#define NV_XP_PL_CYA_5_REENABLE_GEN3_IN_L0_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_REENABLE_GEN3_IN_L0_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_REENABLE_GEN3_IN_L0_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_2_TS1_CONFIG_RULE 20:20 /* RWIVF */
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#define NV_XP_PL_CYA_5_2_TS1_CONFIG_RULE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_2_TS1_CONFIG_RULE_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_2_TS1_CONFIG_RULE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_COMPLT_EIOS_IN_GEN1_LPBK 21:21 /* RWIVF */
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#define NV_XP_PL_CYA_5_COMPLT_EIOS_IN_GEN1_LPBK_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_COMPLT_EIOS_IN_GEN1_LPBK_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_COMPLT_EIOS_IN_GEN1_LPBK_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_LONG_DETECT_QUIET 22:22 /* RWIVF */
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#define NV_XP_PL_CYA_5_LONG_DETECT_QUIET_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_LONG_DETECT_QUIET_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_LONG_DETECT_QUIET_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_INFER_EIDLE_RSPDONE 23:23 /* RWIVF */
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#define NV_XP_PL_CYA_5_INFER_EIDLE_RSPDONE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_5_INFER_EIDLE_RSPDONE_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_INFER_EIDLE_RSPDONE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_RCVY_ON_SYNC_HDR_CODING_ERR 24:24 /* RWIVF */
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#define NV_XP_PL_CYA_5_RCVY_ON_SYNC_HDR_CODING_ERR_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_RCVY_ON_SYNC_HDR_CODING_ERR_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_RCVY_ON_SYNC_HDR_CODING_ERR_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_TIMER_GEN1_WM 25:25 /* RWIVF */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_TIMER_GEN1_WM_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_TIMER_GEN1_WM_128_NS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_TIMER_GEN1_WM_020_NS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_EARLY 26:26 /* RWIVF */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_EARLY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_EARLY_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_UPDT_SLPG_LANES_EARLY_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_POWER_UP_SLPG_LANES_EARLY 27:27 /* RWIVF */
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#define NV_XP_PL_CYA_5_POWER_UP_SLPG_LANES_EARLY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_5_POWER_UP_SLPG_LANES_EARLY_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_POWER_UP_SLPG_LANES_EARLY_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_REFLECT_COMP_RCV_IN_POLLING 28:28 /* RWIVF */
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#define NV_XP_PL_CYA_5_REFLECT_COMP_RCV_IN_POLLING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_REFLECT_COMP_RCV_IN_POLLING_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_REFLECT_COMP_RCV_IN_POLLING_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_ERR_IN_EQZN 29:29 /* RWIVF */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_ERR_IN_EQZN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_ERR_IN_EQZN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_ERR_IN_EQZN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_DATA_SYNC_HDR_IN_EQZN 30:30 /* RWIVF */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_DATA_SYNC_HDR_IN_EQZN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_DATA_SYNC_HDR_IN_EQZN_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_REDO_ALIGNMENT_ON_DATA_SYNC_HDR_IN_EQZN_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_5_SEND_THROWAWAY_SYMBOLS 31:31 /* RWIVF */
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#define NV_XP_PL_CYA_5_SEND_THROWAWAY_SYMBOLS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_5_SEND_THROWAWAY_SYMBOLS_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_5_SEND_THROWAWAY_SYMBOLS_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6 0x0008C47C /* RW-4R */
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#define NV_XP_PL_CYA_6_COARSE_GRAIN_TIMEOUT 4:0 /* RWIVF */
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#define NV_XP_PL_CYA_6_COARSE_GRAIN_TIMEOUT_INIT 0x00000016 /* RWI-V */
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#define NV_XP_PL_CYA_6_COARSE_GRAIN_TIMEOUT_22MS 0x00000016 /* RW--V */
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#define NV_XP_PL_CYA_6_COARSE_GRAIN_TIMEOUT_16MS 0x00000010 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_COARSE_GRAIN_ALGO 5:5 /* RWIVF */
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#define NV_XP_PL_CYA_6_ENABLE_COARSE_GRAIN_ALGO_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_6_ENABLE_COARSE_GRAIN_ALGO_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_COARSE_GRAIN_ALGO_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_FINE_GRAIN_ALGO 6:6 /* RWIVF */
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#define NV_XP_PL_CYA_6_ENABLE_FINE_GRAIN_ALGO_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_6_ENABLE_FINE_GRAIN_ALGO_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_FINE_GRAIN_ALGO_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_SBIOS_PRESET_REQ 7:7 /* RWIVF */
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#define NV_XP_PL_CYA_6_ENABLE_SBIOS_PRESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_6_ENABLE_SBIOS_PRESET_REQ_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_SBIOS_PRESET_REQ_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_SW_SPEC_COEFF_REQ 8:8 /* RWIVF */
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#define NV_XP_PL_CYA_6_ENABLE_SW_SPEC_COEFF_REQ_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_6_ENABLE_SW_SPEC_COEFF_REQ_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_SW_SPEC_COEFF_REQ_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_PREV_BEST_SETTINGS 9:9 /* RWIVF */
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#define NV_XP_PL_CYA_6_ENABLE_PREV_BEST_SETTINGS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_6_ENABLE_PREV_BEST_SETTINGS_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_ENABLE_PREV_BEST_SETTINGS_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_SEQUENCE_CONFIG 11:10 /* RWIVF */
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#define NV_XP_PL_CYA_6_CG_SEQUENCE_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_6_CG_SEQ2_STARTING_POINT 13:12 /* RWIVF */
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#define NV_XP_PL_CYA_6_CG_SEQ2_STARTING_POINT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_6_CG_SEQ2_STARTING_POINT_0_0 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_SEQ2_STARTING_POINT_1_1 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_SEQ2_STARTING_POINT_0_1 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_SEQ2_STARTING_POINT_1_0 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_POSTCUR_STEP_SIZE 15:14 /* RWIVF */
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#define NV_XP_PL_CYA_6_CG_POSTCUR_STEP_SIZE_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_6_CG_POSTCUR_STEP_SIZE_FOUR 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_POSTCUR_STEP_SIZE_ONE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_POSTCUR_STEP_SIZE_TWO 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_POSTCUR_STEP_SIZE_THREE 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_PRECUR_STEP_SIZE 17:16 /* RWIVF */
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#define NV_XP_PL_CYA_6_CG_PRECUR_STEP_SIZE_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_6_CG_PRECUR_STEP_SIZE_FOUR 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_PRECUR_STEP_SIZE_ONE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_PRECUR_STEP_SIZE_TWO 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_6_CG_PRECUR_STEP_SIZE_THREE 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_REQ_COEFF_TIMEOUT 19:18 /* RWIVF */
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#define NV_XP_PL_CYA_6_PHASE2_REQ_COEFF_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_6_PHASE2_REQ_COEFF_TIMEOUT_006_US 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_REQ_COEFF_TIMEOUT_010_US 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_REQ_COEFF_TIMEOUT_020_US 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_REQ_COEFF_TIMEOUT_070_US 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_DFE_TRAIN_TIMEOUT 21:20 /* RWIVF */
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#define NV_XP_PL_CYA_6_PHASE2_DFE_TRAIN_TIMEOUT_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_6_PHASE2_DFE_TRAIN_TIMEOUT_001_MS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_DFE_TRAIN_TIMEOUT_002_MS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_DFE_TRAIN_TIMEOUT_004_MS 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_6_PHASE2_DFE_TRAIN_TIMEOUT_012_MS 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_6_NUM_PHASE2_TUNING_ATTEMPTS 30:22 /* RWIVF */
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#define NV_XP_PL_CYA_6_NUM_PHASE2_TUNING_ATTEMPTS_INIT 0x000001FF /* RWI-V */
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#define NV_XP_PL_CYA_6_NUM_PHASE2_TUNING_ATTEMPTS_MIN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_6_NUM_PHASE2_TUNING_ATTEMPTS_NORMAL 0x000000FF /* RW--V */
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#define NV_XP_PL_CYA_6_NUM_PHASE2_TUNING_ATTEMPTS_MAX 0x000001FF /* RW--V */
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#define NV_XP_PL_CYA_6_OPTIMIZE_FOR_BAD_COEFFS 31:31 /* RWIVF */
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#define NV_XP_PL_CYA_6_OPTIMIZE_FOR_BAD_COEFFS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_6_OPTIMIZE_FOR_BAD_COEFFS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_6_OPTIMIZE_FOR_BAD_COEFFS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7 0x0008C480 /* RW-4R */
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#define NV_XP_PL_CYA_7_LPBK_ENTRY_SLV_TIMEOUT 1:0 /* RWIVF */
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#define NV_XP_PL_CYA_7_LPBK_ENTRY_SLV_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_LPBK_ENTRY_SLV_TIMEOUT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_LPBK_ENTRY_SLV_TIMEOUT_001_MS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_LPBK_ENTRY_SLV_TIMEOUT_002_MS 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_7_LPBK_ENTRY_SLV_TIMEOUT_012_MS 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_7_SAME_LEADING_LANE_ON_LINK_UP_SIZE 2:2 /* RWIVF */
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#define NV_XP_PL_CYA_7_SAME_LEADING_LANE_ON_LINK_UP_SIZE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_SAME_LEADING_LANE_ON_LINK_UP_SIZE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_SAME_LEADING_LANE_ON_LINK_UP_SIZE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT 3:3 /* RWIVF */
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#define NV_XP_PL_CYA_7_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_7_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_FIX_GEN2_DEEMPHASIS_LTSSM_STATES 4:4 /* RWIVF */
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#define NV_XP_PL_CYA_7_FIX_GEN2_DEEMPHASIS_LTSSM_STATES_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_FIX_GEN2_DEEMPHASIS_LTSSM_STATES_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_FIX_GEN2_DEEMPHASIS_LTSSM_STATES_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_FIX_ENTER_COMPLIANCE_USE_PRESET 5:5 /* RWIVF */
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#define NV_XP_PL_CYA_7_FIX_ENTER_COMPLIANCE_USE_PRESET_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_FIX_ENTER_COMPLIANCE_USE_PRESET_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_FIX_ENTER_COMPLIANCE_USE_PRESET_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_UP 6:6 /* RWIVF */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_UP_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_UP_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_UP_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_DOWN 7:7 /* RWIVF */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_DOWN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_DOWN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_FULL_LINK_WIDTH_STATUS_IN_LOOPBACK_MASTER_LINK_DOWN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_LANE_REVERSAL_IN_PCOMP_AND_LPBK_MSTR 8:8 /* RWIVF */
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#define NV_XP_PL_CYA_7_LANE_REVERSAL_IN_PCOMP_AND_LPBK_MSTR_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_LANE_REVERSAL_IN_PCOMP_AND_LPBK_MSTR_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_LANE_REVERSAL_IN_PCOMP_AND_LPBK_MSTR_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_HOT_RESET_LESS_STICKY 9:9 /* RWIVF */
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#define NV_XP_PL_CYA_7_HOT_RESET_LESS_STICKY_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_HOT_RESET_LESS_STICKY_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_HOT_RESET_LESS_STICKY_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_UPDATE_PRESET_IN_PCOMPL_CLB 10:10 /* RWIVF */
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#define NV_XP_PL_CYA_7_UPDATE_PRESET_IN_PCOMPL_CLB_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_UPDATE_PRESET_IN_PCOMPL_CLB_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_UPDATE_PRESET_IN_PCOMPL_CLB_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_EXPLR_ON_REQ_COEFF_TIMEOUT 11:11 /* RWIVF */
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#define NV_XP_PL_CYA_7_EXPLR_ON_REQ_COEFF_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_EXPLR_ON_REQ_COEFF_TIMEOUT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_EXPLR_ON_REQ_COEFF_TIMEOUT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_MATCH_GEN3_COMPLIANCE_LANE_NUM 12:12 /* RWIVF */
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#define NV_XP_PL_CYA_7_MATCH_GEN3_COMPLIANCE_LANE_NUM_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_MATCH_GEN3_COMPLIANCE_LANE_NUM_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_MATCH_GEN3_COMPLIANCE_LANE_NUM_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_LOOPBK_SPD_CHG_DONE_MSTR_TIMEOUT 14:13 /* RWIVF */
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#define NV_XP_PL_CYA_7_LOOPBK_SPD_CHG_DONE_MSTR_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_LOOPBK_SPD_CHG_DONE_MSTR_TIMEOUT_0_MS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_LOOPBK_SPD_CHG_DONE_MSTR_TIMEOUT_001_MS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_LOOPBK_SPD_CHG_DONE_MSTR_TIMEOUT_002_MS 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_7_LOOPBK_SPD_CHG_DONE_MSTR_TIMEOUT_012_MS 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN3_LOOPBACK 15:15 /* RWIVF */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN3_LOOPBACK_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN3_LOOPBACK_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN3_LOOPBACK_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_LOOPBACK_EXIT_MASTER_2MS 16:16 /* RWIVF */
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#define NV_XP_PL_CYA_7_LOOPBACK_EXIT_MASTER_2MS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_LOOPBACK_EXIT_MASTER_2MS_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_LOOPBACK_EXIT_MASTER_2MS_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_POLLING_IGNORE_EIDLE_EXIT_2MS 17:17 /* RWIVF */
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#define NV_XP_PL_CYA_7_POLLING_IGNORE_EIDLE_EXIT_2MS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_POLLING_IGNORE_EIDLE_EXIT_2MS_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_POLLING_IGNORE_EIDLE_EXIT_2MS_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_DETECT 18:18 /* RWIVF */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_DETECT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_DETECT_RESET 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_DETECT_NO_RESET 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_POLLING_ACTIVE_REMEMBER_EIDLE_EXIT 19:19 /* RWIVF */
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#define NV_XP_PL_CYA_7_POLLING_ACTIVE_REMEMBER_EIDLE_EXIT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_POLLING_ACTIVE_REMEMBER_EIDLE_EXIT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_POLLING_ACTIVE_REMEMBER_EIDLE_EXIT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_SPEED_INFER_EIDLE 20:20 /* RWIVF */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_SPEED_INFER_EIDLE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_SPEED_INFER_EIDLE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_SPEED_INFER_EIDLE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_RCVRCFG_INFER_EIDLE 21:21 /* RWIVF */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_RCVRCFG_INFER_EIDLE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_RCVRCFG_INFER_EIDLE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_DELAY_GEN1_RCVRY_RCVRCFG_INFER_EIDLE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_NO_MANDATORY_SKPOS_ON_L0_ENTRY 22:22 /* RWIVF */
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#define NV_XP_PL_CYA_7_NO_MANDATORY_SKPOS_ON_L0_ENTRY_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_NO_MANDATORY_SKPOS_ON_L0_ENTRY_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_NO_MANDATORY_SKPOS_ON_L0_ENTRY_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_NO_DUPLICATE_SKPOS_ON_L0_ENTRY 23:23 /* RWIVF */
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#define NV_XP_PL_CYA_7_NO_DUPLICATE_SKPOS_ON_L0_ENTRY_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_NO_DUPLICATE_SKPOS_ON_L0_ENTRY_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_NO_DUPLICATE_SKPOS_ON_L0_ENTRY_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN4_LOOPBACK 24:24 /* RWIVF */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN4_LOOPBACK_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN4_LOOPBACK_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_USE_EQ_TS1_PRESETS_IN_GEN4_LOOPBACK_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_POLLING_CONFIG 25:25 /* RWIVF */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_POLLING_CONFIG_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_POLLING_CONFIG_RESET 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_7_RESET_COMPLIANCE_COUNT_ON_POLLING_CONFIG_NO_RESET 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_7_MIN_NUM_CYCLES_BTW_2_SKPS 31:26 /* RWIVF */
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#define NV_XP_PL_CYA_7_MIN_NUM_CYCLES_BTW_2_SKPS_INIT 0x00000014 /* RWI-V */
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#define NV_XP_PL_CYA_7_MIN_NUM_CYCLES_BTW_2_SKPS_RESET 0x00000014 /* RW--V */
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#define NV_XP_PL_CYA_7_MIN_NUM_CYCLES_BTW_2_SKPS_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_8 0x0008C484 /* RW-4R */
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#define NV_XP_PL_CYA_8__PRIV_LEVEL_MASK 0x0008E1B8 /* */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_THRESHOLD 19:0 /* RWIVF */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_THRESHOLD_INIT 0x00000400 /* RWI-V */
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#define NV_XP_PL_CYA_8_FILTER_BY_RX_STAT_IDLE 20:20 /* RWIVF */
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#define NV_XP_PL_CYA_8_FILTER_BY_RX_STAT_IDLE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_8_FILTER_BY_RX_STAT_IDLE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_8_FILTER_BY_RX_STAT_IDLE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_RCVRY_RCVRLOCK 21:21 /* RWIVF */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_RCVRY_RCVRLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_RCVRY_RCVRLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_RCVRY_RCVRLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_POLLING_COMP 22:22 /* RWIVF */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_POLLING_COMP_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_POLLING_COMP_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_POLLING_COMP_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_LOOPBACK_ENTRY 23:23 /* RWIVF */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_LOOPBACK_ENTRY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_LOOPBACK_ENTRY_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_LOOPBACK_ENTRY_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_HOT_RESET 24:24 /* RWIVF */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_HOT_RESET_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_HOT_RESET_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_8_RX_STAT_IDLE_IN_HOT_RESET_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_8_SPARE 31:25 /* RWIVF */
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#define NV_XP_PL_CYA_8_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST 0x0008C488 /* RW-4R */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN1 7:0 /* RWIVF */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN1_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN2 15:8 /* RWIVF */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN2_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN3 23:16 /* RWIVF */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN3_INIT 0x00000012 /* RWI-V */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN4 31:24 /* RWIVF */
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#define NV_XP_PL_N_FTS_TIMEOUT_ADJUST_GEN4_INIT 0x00000012 /* RWI-V */
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#define NV_XP_PL_CYA_9 0x0008C48C /* RW-4R */
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#define NV_XP_PL_CYA_9_DELAY_RXLANE_DATA_EN_DEASSERT 3:0 /* RWIVF */
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#define NV_XP_PL_CYA_9_DELAY_RXLANE_DATA_EN_DEASSERT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_L2 4:4 /* RWIVF */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_L2_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_L2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_L2_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_DISABLED 5:5 /* RWIVF */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_DISABLED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_DISABLED_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_9_FORCE_ELECTRICAL_IDLE_BASED_ON_LTSSM_FOR_DISABLED_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_9_RSVD_0 31:6 /* RWIVF */
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#define NV_XP_PL_CYA_9_RSVD_0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10 0x0008C490 /* RW-4R */
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#define NV_XP_PL_CYA_10_GEN4_COARSE_GRAIN_TIMEOUT 4:0 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_COARSE_GRAIN_TIMEOUT_INIT 0x00000016 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_COARSE_GRAIN_TIMEOUT_22MS 0x00000016 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_COARSE_GRAIN_TIMEOUT_16MS 0x00000010 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_COARSE_GRAIN_ALGO 5:5 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_COARSE_GRAIN_ALGO_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_COARSE_GRAIN_ALGO_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_COARSE_GRAIN_ALGO_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_FINE_GRAIN_ALGO 6:6 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_FINE_GRAIN_ALGO_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_FINE_GRAIN_ALGO_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_FINE_GRAIN_ALGO_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SBIOS_PRESET_REQ 7:7 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SBIOS_PRESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SBIOS_PRESET_REQ_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SBIOS_PRESET_REQ_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SW_SPEC_COEFF_REQ 8:8 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SW_SPEC_COEFF_REQ_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SW_SPEC_COEFF_REQ_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_SW_SPEC_COEFF_REQ_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_PREV_BEST_SETTINGS 9:9 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_PREV_BEST_SETTINGS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_PREV_BEST_SETTINGS_EN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_ENABLE_PREV_BEST_SETTINGS_DIS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQUENCE_CONFIG 11:10 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQUENCE_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQ2_STARTING_POINT 13:12 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQ2_STARTING_POINT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQ2_STARTING_POINT_0_0 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQ2_STARTING_POINT_1_1 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQ2_STARTING_POINT_0_1 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_SEQ2_STARTING_POINT_1_0 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_POSTCUR_STEP_SIZE 15:14 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_CG_POSTCUR_STEP_SIZE_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_CG_POSTCUR_STEP_SIZE_FOUR 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_POSTCUR_STEP_SIZE_ONE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_POSTCUR_STEP_SIZE_TWO 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_POSTCUR_STEP_SIZE_THREE 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_PRECUR_STEP_SIZE 17:16 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_CG_PRECUR_STEP_SIZE_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_CG_PRECUR_STEP_SIZE_FOUR 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_PRECUR_STEP_SIZE_ONE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_PRECUR_STEP_SIZE_TWO 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_CG_PRECUR_STEP_SIZE_THREE 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_REQ_COEFF_TIMEOUT 19:18 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_REQ_COEFF_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_REQ_COEFF_TIMEOUT_006_US 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_REQ_COEFF_TIMEOUT_010_US 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_REQ_COEFF_TIMEOUT_020_US 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_REQ_COEFF_TIMEOUT_070_US 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_DFE_TRAIN_TIMEOUT 21:20 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_DFE_TRAIN_TIMEOUT_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_DFE_TRAIN_TIMEOUT_001_MS 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_DFE_TRAIN_TIMEOUT_002_MS 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_DFE_TRAIN_TIMEOUT_004_MS 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_PHASE2_DFE_TRAIN_TIMEOUT_012_MS 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_NUM_PHASE2_TUNING_ATTEMPTS 30:22 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_NUM_PHASE2_TUNING_ATTEMPTS_INIT 0x000001FF /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_NUM_PHASE2_TUNING_ATTEMPTS_MIN 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_NUM_PHASE2_TUNING_ATTEMPTS_NORMAL 0x000000FF /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_NUM_PHASE2_TUNING_ATTEMPTS_MAX 0x000001FF /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_OPTIMIZE_FOR_BAD_COEFFS 31:31 /* RWIVF */
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#define NV_XP_PL_CYA_10_GEN4_OPTIMIZE_FOR_BAD_COEFFS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_10_GEN4_OPTIMIZE_FOR_BAD_COEFFS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_10_GEN4_OPTIMIZE_FOR_BAD_COEFFS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_11 0x0008C494 /* RW-4R */
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#define NV_XP_PL_CYA_11_GEN4_RX_EOM_THRESHOLD 15:0 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_RX_EOM_THRESHOLD_INIT 0x0000003E /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_RX_EOM_THRESHOLD_MIN 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_RX_EOM_THRESHOLD_MAX 0x0000003F /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_RX_QEYE_HYSTERESIS 18:16 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_RX_QEYE_HYSTERESIS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAINING 19:19 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAINING_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAINING_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_FG_EXPLR_MODE 20:20 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_FG_EXPLR_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_FG_EXPLR_MODE_FOUR_DIR 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_FG_EXPLR_MODE_EIGHT_DIR 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT 21:21 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_SKIP_DFE_TRAIN_ON_PH2_TIMEOUT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_EXPLR_ON_REQ_COEFF_TIMEOUT 22:22 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_EXPLR_ON_REQ_COEFF_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_EXPLR_ON_REQ_COEFF_TIMEOUT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_EXPLR_ON_REQ_COEFF_TIMEOUT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_BACKUP_PRESET 27:24 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_BACKUP_PRESET_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_REUSE_EQ_TS2_PRESETS 28:28 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_REUSE_EQ_TS2_PRESETS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_REUSE_EQ_TS2_PRESETS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_REUSE_EQ_TS2_PRESETS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAIN_DLY 30:29 /* RWIVF */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAIN_DLY_INIT 0x00000002 /* RWI-V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAIN_DLY_001_US 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAIN_DLY_006_US 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAIN_DLY_010_US 0x00000002 /* RW--V */
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#define NV_XP_PL_CYA_11_GEN4_PHASE2_DFE_TRAIN_DLY_020_US 0x00000003 /* RW--V */
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#define NV_XP_PL_CYA_11_AUTO_DISABLE_GEN4_SPEED 31:31 /* RWIVF */
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#define NV_XP_PL_CYA_11_AUTO_DISABLE_GEN4_SPEED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_11_AUTO_DISABLE_GEN4_SPEED_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_11_AUTO_DISABLE_GEN4_SPEED_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_12 0x0008C4A4 /* RW-4R */
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#define NV_XP_PL_CYA_12_RX_DATA_EN_ON_RECOVERY_ENTRY 0:0 /* RWIVF */
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#define NV_XP_PL_CYA_12_RX_DATA_EN_ON_RECOVERY_ENTRY_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_12_RX_DATA_EN_ON_RECOVERY_ENTRY_REMAIN_ASSERTED 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_12_RX_DATA_EN_ON_RECOVERY_ENTRY_DEASSERT 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_12_ABORT_MARGINING_STYLE 1:1 /* RWIVF */
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#define NV_XP_PL_CYA_12_ABORT_MARGINING_STYLE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_CYA_12_ABORT_MARGINING_STYLE_IND_SMPLR 0x00000001 /* RW--V */
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#define NV_XP_PL_CYA_12_ABORT_MARGINING_STYLE_NON_IND_SMPLR 0x00000000 /* RW--V */
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#define NV_XP_PL_CYA_12_DFE_TRAIN_LTSSM_ESCAPE_TO_EXT_EVNT 31:16 /* RWIVF */
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#define NV_XP_PL_CYA_12_DFE_TRAIN_LTSSM_ESCAPE_TO_EXT_EVNT_INIT 0x00000FA0 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_0 0x0008C498 /* RW-4R */
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#define NV_XP_PL_EQUALIZATION_0_LANE_NUM_SEL 3:0 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_0_LANE_NUM_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_0_LOCAL_PRESET 7:4 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_0_LOCAL_PRECUR 13:8 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_0_LOCAL_MAINCUR 19:14 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_0_LOCAL_POSTCUR 25:20 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_0_LOCAL_USE_PRESET 26:26 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_0_SPEED_SEL 31:31 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_0_SPEED_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_0_SPEED_SEL_GEN3 0x00000000 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_0_SPEED_SEL_GEN4 0x00000001 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_1 0x0008C49C /* R--4R */
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#define NV_XP_PL_EQUALIZATION_1_REMOTE_PRESET 3:0 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_1_REMOTE_PRECUR 9:4 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_1_REMOTE_MAINCUR 15:10 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_1_REMOTE_POSTCUR 21:16 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_1_REMOTE_USE_PRESET 22:22 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_2 0x0008C4A0 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_2_REMOTE_FS 5:0 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_2_REMOTE_LF 11:6 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_2_LOCAL_FS 17:12 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_2_LOCAL_FS_INIT 0x3C /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_2_LOCAL_LF 23:18 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_3(i) (0x0008C4B0+(i)*4) /* RW-4A */
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#define NV_XP_PL_EQUALIZATION_3__SIZE_1 16 /* */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_TX_PRECUR 5:0 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_TX_PRECUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_3_RSVD_1 14:6 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_3_RSVD_1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_TX_POSTCUR 21:16 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_TX_POSTCUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_3_RSVD_2 22:22 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_3_RSVD_2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_TX_PRESET 27:24 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_TX_PRESET_INIT 0x00000005 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_3_RSVD_3 28:28 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_3_RSVD_3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_FORCE_PRESETS 29:29 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_FORCE_PRESETS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_FORCE_PRESETS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_3_REMOTE_FORCE_PRESETS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3(i) (0x0008C8B0+(i)*4) /* RW-4A */
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#define NV_XP_PL_GEN4_EQUALIZATION_3__SIZE_1 16 /* */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_TX_PRECUR 5:0 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_TX_PRECUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_RSVD_1 14:6 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_RSVD_1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_TX_POSTCUR 21:16 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_TX_POSTCUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_RSVD_2 22:22 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_RSVD_2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_TX_PRESET 27:24 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_TX_PRESET_INIT 0x00000005 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_RSVD_3 28:28 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_RSVD_3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_FORCE_PRESETS 29:29 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_FORCE_PRESETS_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_FORCE_PRESETS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_3_REMOTE_FORCE_PRESETS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4(i) (0x0008E170+(i)*4) /* RW-4A */
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#define NV_XP_PL_GEN4_EQUALIZATION_4__SIZE_1 16 /* */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_PRECUR 5:0 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_PRECUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_MAINCUR 13:8 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_MAINCUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_POSTCUR 21:16 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_POSTCUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_FORCE_PRESETS 23:23 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_FORCE_PRESETS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_FORCE_PRESETS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_FORCE_PRESETS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_PRESET 27:24 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_LOCAL_TX_PRESET_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3 29:29 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3 30:30 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK 31:31 /* RWIVF */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_GEN4_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_CLOCKS 0x0008C4F0 /* R--4R */
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#define NV_XP_PL_CLOCKS_HOSTCLK 3:0 /* R-IVF */
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#define NV_XP_PL_CLOCKS_HOSTCLK_NONE 0x00000000 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_ALT 0x00000001 /* R-I-V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_REFCLK 0x00000002 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_277 0x00000003 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_417 0x00000004 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_500 0x00000005 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_GEN3 0x00000006 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_1000 0x00000007 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_1142 0x00000008 /* R---V */
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#define NV_XP_PL_CLOCKS_HOSTCLK_NAFLL 0x00000009 /* R---V */
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#define NV_XP_PL_CLOCKS_XCLK 6:4 /* R-IVF */
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#define NV_XP_PL_CLOCKS_XCLK_NONE 0x00000000 /* R---V */
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#define NV_XP_PL_CLOCKS_XCLK_ALT 0x00000001 /* R-I-V */
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#define NV_XP_PL_CLOCKS_XCLK_REFCLK 0x00000002 /* R---V */
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#define NV_XP_PL_CLOCKS_XCLK_125 0x00000003 /* R---V */
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#define NV_XP_PL_CLOCKS_XCLK_250 0x00000004 /* R---V */
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#define NV_XP_PL_CLOCKS_XCLK_500 0x00000005 /* R---V */
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#define NV_XP_PL_CLOCKS_XCLK_1000 0x00000006 /* R---V */
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#define NV_XP_PL_CLOCKS_TXCLK 10:8 /* R-IVF */
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#define NV_XP_PL_CLOCKS_TXCLK_NONE 0x00000000 /* R---V */
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#define NV_XP_PL_CLOCKS_TXCLK_ALT 0x00000001 /* R-I-V */
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#define NV_XP_PL_CLOCKS_TXCLK_REFCLK 0x00000002 /* R---V */
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#define NV_XP_PL_CLOCKS_TXCLK_125 0x00000003 /* R---V */
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#define NV_XP_PL_CLOCKS_TXCLK_250 0x00000004 /* R---V */
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#define NV_XP_PL_CLOCKS_TXCLK_500 0x00000005 /* R---V */
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#define NV_XP_PL_CLOCKS_TXCLK_1000 0x00000006 /* R---V */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY(i) (0x0008C500+(i)*4) /* RW-4A */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY__SIZE_1 1 /* */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN1 7:0 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN1_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN2 15:8 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN2_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN3 23:16 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN3_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN4 31:24 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_DLY_GEN4_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN(i) (0x0008C540+(i)*4) /* RW-4A */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN__SIZE_1 1 /* */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN1 7:0 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN2 15:8 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN3 23:16 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN4 31:24 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_TX_L0S_MIN_GEN4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN(i) (0x0008C580+(i)*4) /* RW-4A */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN__SIZE_1 1 /* */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN1 7:0 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN2 15:8 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN3 23:16 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN4 31:24 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_L1_MIN_GEN4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_SKP_TIMEOUT_GEN1(i) (0x0008C5C0+(i)*4) /* RW-4A */
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#define NV_XP_PL_SKP_TIMEOUT_GEN1__SIZE_1 1 /* */
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#define NV_XP_PL_SKP_TIMEOUT_GEN1__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_SKP_TIMEOUT_GEN1_THRESHOLD 15:0 /* RWIVF */
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#define NV_XP_PL_SKP_TIMEOUT_GEN1_THRESHOLD_INIT 0x000005DC /* RWI-V */
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#define NV_XP_PL_SKP_TIMEOUT_GEN2(i) (0x0008C600+(i)*4) /* RW-4A */
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#define NV_XP_PL_SKP_TIMEOUT_GEN2__SIZE_1 1 /* */
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#define NV_XP_PL_SKP_TIMEOUT_GEN2__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_SKP_TIMEOUT_GEN2_THRESHOLD 15:0 /* RWIVF */
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#define NV_XP_PL_SKP_TIMEOUT_GEN2_THRESHOLD_INIT 0x000005DC /* RWI-V */
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#define NV_XP_PL_SKP_TIMEOUT_GEN3(i) (0x0008C640+(i)*4) /* RW-4A */
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#define NV_XP_PL_SKP_TIMEOUT_GEN3__SIZE_1 1 /* */
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#define NV_XP_PL_SKP_TIMEOUT_GEN3__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_SKP_TIMEOUT_GEN3_THRESHOLD 15:0 /* RWIVF */
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#define NV_XP_PL_SKP_TIMEOUT_GEN3_THRESHOLD_INIT 0x00001738 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN1(i) (0x0008C680+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN1__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN1__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN1_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN1_THRESHOLD_INIT 0x000001CC /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN2(i) (0x0008C6C0+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN2__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN2_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN2_THRESHOLD_INIT 0x000000E6 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN3(i) (0x0008C700+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN3__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN3_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN3_THRESHOLD_INIT 0x0000033D /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN4(i) (0x0008CBC0+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN4__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN4_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_SUC_GEN4_THRESHOLD_INIT 0x0000019F /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN1(i) (0x0008C740+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN1__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN1__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN1_THRESHOLD 12:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN1_THRESHOLD_INIT 0x00000190 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN2(i) (0x0008C780+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN2__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN2_THRESHOLD 12:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN2_THRESHOLD_INIT 0x00000640 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN3(i) (0x0008C7C0+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN3__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN3_THRESHOLD 12:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN3_THRESHOLD_INIT 0x000003E8 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN4(i) (0x0008CC00+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN4__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN4_THRESHOLD 12:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_SPEED_UNSUC_GEN4_THRESHOLD_INIT 0x000001F4 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN1(i) (0x0008C800+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN1__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN1__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN1_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN1_THRESHOLD_INIT 0x000001CC /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN2(i) (0x0008C840+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN2__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN2_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN2_THRESHOLD_INIT 0x000000E6 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN3(i) (0x0008C880+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN3__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN3_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN3_THRESHOLD_INIT 0x001E8698 /* RWI-V */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN4(i) (0x0008CB80+(i)*4) /* RW-4A */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN4__SIZE_1 1 /* */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN4_THRESHOLD 23:0 /* RWIVF */
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#define NV_XP_PL_EIDLE_INFER_TO_RCVRY_RCVRCFG_GEN4_THRESHOLD_INIT 0x001E858C /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0(i) (0x0008C900+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_DETECT_QUIET_TIMEOUT_12MS 4:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_DETECT_QUIET_TIMEOUT_12MS_INIT 0x016 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_DETECT_ACTIVE_TIMEOUT_12MS 9:5 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_DETECT_ACTIVE_TIMEOUT_12MS_INIT 0x016 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_DETECT_STAY_MIN_1MS 14:10 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_DETECT_STAY_MIN_1MS_INIT 0x011 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_POLLING_ACTIVE_TIMEOUT_24MS 19:15 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_POLLING_ACTIVE_TIMEOUT_24MS_INIT 0x018 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_POLLING_COMPLIANCE_MIN_EIDLE_1MS 24:20 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_POLLING_COMPLIANCE_MIN_EIDLE_1MS_INIT 0x011 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_POLLING_CONFIGURATION_TIMEOUT_48MS 29:25 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_0_POLLING_CONFIGURATION_TIMEOUT_48MS_INIT 0x01A /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1(i) (0x0008C940+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_LINKWIDTH_START_TIMEOUT_24MS 4:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_LINKWIDTH_START_TIMEOUT_24MS_INIT 0x018 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_LINKWIDTH_ACCEPT_TIMEOUT_2MS 9:5 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_LINKWIDTH_ACCEPT_TIMEOUT_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_LANENUM_WAIT_TIMEOUT_2MS 14:10 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_LANENUM_WAIT_TIMEOUT_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_COMPLETE_TIMEOUT_2MS 19:15 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_COMPLETE_TIMEOUT_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_IDLE_TIMEOUT_2MS 24:20 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_IDLE_TIMEOUT_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_MAX_LANE_SETTLING_1MS 29:25 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_1_CONFIGURATION_MAX_LANE_SETTLING_1MS_INIT 0x011 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2(i) (0x0008C980+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_RCVRLOCK_TIMEOUT_24MS 4:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_RCVRLOCK_TIMEOUT_24MS_INIT 0x018 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_TIMEOUT_48MS 9:5 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_TIMEOUT_48MS_INIT 0x01A /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_MAX_EIDLE_1MS 14:10 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_MAX_EIDLE_1MS_INIT 0x011 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_MIN_ACK_EIDLE_800NS 19:15 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_MIN_ACK_EIDLE_800NS_INIT 0x006 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_MIN_NAK_EIDLE_6US 24:20 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_SPEED_MIN_NAK_EIDLE_6US_INIT 0x00A /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_RCVRCFG_TIMEOUT_48MS 29:25 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_2_RECOVERY_RCVRCFG_TIMEOUT_48MS_INIT 0x01A /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3(i) (0x0008C9C0+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_RCVRCFG_RCVD_TS2_EQ_1MS 4:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_RCVRCFG_RCVD_TS2_EQ_1MS_INIT 0x011 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_IDLE_TIMEOUT_2MS 9:5 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_IDLE_TIMEOUT_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE0_TIMEOUT_12MS 14:10 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE0_TIMEOUT_12MS_INIT 0x016 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE1_TIMEOUT_12MS 19:15 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE1_TIMEOUT_12MS_INIT 0x016 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE2_TIMEOUT_24MS 24:20 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE2_TIMEOUT_24MS_INIT 0x018 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE3_TIMEOUT_32MS 29:25 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_3_RECOVERY_EQUALIZATION_PHASE3_TIMEOUT_32MS_INIT 0x019 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4(i) (0x0008CA00+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_RECOVERY_EQUALIZATION_MIN_EVAL_1US 4:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_RECOVERY_EQUALIZATION_MIN_EVAL_1US_INIT 0x07 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_RECOVERY_EQUALIZATION_MAX_EVAL_2MS 9:5 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_RECOVERY_EQUALIZATION_MAX_EVAL_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_DISABLED_TIMEOUT_2MS 14:10 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_DISABLED_TIMEOUT_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_HOT_RESET_TIMEOUT_2MS 19:15 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_HOT_RESET_TIMEOUT_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_LOOPBACK_ENTRY_MASTER_EIDLE_1MS 24:20 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_LOOPBACK_ENTRY_MASTER_EIDLE_1MS_INIT 0x011 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_LOOPBACK_ENTRY_SLAVE_EIDLE_2MS 29:25 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_4_LOOPBACK_ENTRY_SLAVE_EIDLE_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5(i) (0x0008CA40+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5_LOOPBACK_ENTRY_MASTER_STAY_MIN_2MS 4:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5_LOOPBACK_ENTRY_MASTER_STAY_MIN_2MS_INIT 0x13 /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5_LOOPBACK_ENTRY_MASTER_TIMEOUT 9:5 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5_LOOPBACK_ENTRY_MASTER_TIMEOUT_INIT 0x01A /* RWI-V */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5_LOOPBACK_EXIT_EIDLE_2MS 14:10 /* RWIVF */
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#define NV_XP_PL_LTSSM_CTRL_TIMER_5_LOOPBACK_EXIT_EIDLE_2MS_INIT 0x013 /* RWI-V */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_0(i) (0x0008CA80+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_0__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_0_LIMIT 26:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_0_LIMIT_INIT 0x0000000 /* RWI-V */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_1(i) (0x0008CAC0+(i)*4) /* RW-4A */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_1__SIZE_1 1 /* */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_1_LIMIT 26:0 /* RWIVF */
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#define NV_XP_PL_LTSSM_PROGRAMMABLE_TIMER_1_LIMIT_INIT 0x0000000 /* RWI-V */
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#define NV_XP_PEX_PAD_DUMMY0_0(i) (0x0008D100+(i)*4) /* RW-4A */
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#define NV_XP_PEX_PAD_DUMMY0_0__SIZE_1 8 /* */
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#define NV_XP_PEX_PAD_DUMMY0_0__PRIV_LEVEL_MASK 0x0008E1C8 /* */
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#define NV_XP_PEX_PAD_DUMMY0_0_DATA 31:0 /* RWIVF */
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#define NV_XP_PEX_PAD_DUMMY0_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_DUMMY0_1(i) (0x0008D120+(i)*4) /* RW-4A */
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#define NV_XP_PEX_PAD_DUMMY0_1__SIZE_1 20 /* */
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#define NV_XP_PEX_PAD_DUMMY0_1__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_DUMMY0_1_DATA 31:0 /* RWIVF */
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#define NV_XP_PEX_PAD_DUMMY0_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_DUMMY0_2(i) (0x0008D170+(i)*4) /* RW-4A */
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#define NV_XP_PEX_PAD_DUMMY0_2__SIZE_1 4 /* */
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#define NV_XP_PEX_PAD_DUMMY0_2__PRIV_LEVEL_MASK 0x0008E1CC /* */
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#define NV_XP_PEX_PAD_DUMMY0_2_DATA 31:0 /* RWIVF */
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#define NV_XP_PEX_PAD_DUMMY0_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_DUMMY0_3(i) (0x0008D180+(i)*4) /* RW-4A */
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#define NV_XP_PEX_PAD_DUMMY0_3__SIZE_1 8 /* */
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#define NV_XP_PEX_PAD_DUMMY0_3__PRIV_LEVEL_MASK 0x0008E1F4 /* */
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#define NV_XP_PEX_PAD_DUMMY0_3_DATA 31:0 /* RWIVF */
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#define NV_XP_PEX_PAD_DUMMY0_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_SEL 0x0008D180 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_SEL__PRIV_LEVEL_MASK 0x0008E1F4 /* */
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#define NV_XP_PEX_PAD_CTL_SEL_LANE_SELECT 15:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_SEL_LANE_SELECT_INIT 0x0000FFFF /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_SEL_LANE_SELECT_NO_LANES 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_SEL_LANE_SELECT_LANES_15_0 0x0000FFFF /* RW--V */
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#define NV_XP_PEX_PAD_CTL_SEL_FORCE_RATE_UPDATE 31:31 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_SEL_FORCE_RATE_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_SEL_FORCE_RATE_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_SEL_FORCE_RATE_UPDATE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1 0x0008D104 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_1__PRIV_LEVEL_MASK 0x0008E1C8 /* */
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#define NV_XP_PEX_PAD_CTL_1_TX_SLEEP 5:4 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_SLEEP_INIT 0x00000003 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_SLEEP_ACTIVE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_SLEEP_L1 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_SLEEP_L1P 0x00000002 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_SLEEP_L1PP 0x00000003 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_READY 6:6 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_READY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_READY_NOT_READY 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_READY_READY 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_EN 7:7 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_DATA_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_SLEEP 9:8 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_SLEEP_INIT 0x00000003 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_SLEEP_ACTIVE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_SLEEP_L1 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_SLEEP_L1P 0x00000002 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_SLEEP_L1PP 0x00000003 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_DATA_EN 11:11 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_DATA_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_DATA_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_DATA_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_ID_OVRD 12:12 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_ID_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_ID_OVRD 13:13 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_ID_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_ID 18:16 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_ID_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_ID 21:19 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_ID_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_PDIV 23:22 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_PDIV_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_PDIV_10_BIT 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_PDIV_20_BIT 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_PDIV_08_BIT 0x00000002 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_RATE_PDIV_16_BIT 0x00000003 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_PDIV 25:24 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_PDIV_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_PDIV_10_BIT 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_PDIV_20_BIT 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_PDIV_08_BIT 0x00000002 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_RATE_PDIV_16_BIT 0x00000003 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_PWR_OVRD 26:26 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_PWR_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_PWR_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_PWR_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_PWR_OVRD 27:27 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_PWR_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_PWR_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_PWR_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ 28:28 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ_OVRD 29:29 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_TX_IDDQ_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ 30:30 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ_OVRD 31:31 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_1_RX_IDDQ_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2 0x0008D108 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_2__PRIV_LEVEL_MASK 0x0008E1C8 /* */
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#define NV_XP_PEX_PAD_CTL_2_RX_TERM_EN 0:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_RX_TERM_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_RX_TERM_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RX_TERM_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC_OVRD 8:8 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_OVRD 9:9 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC 12:12 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_TX_SYNC_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_RESET 13:13 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_RESET_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_RESET_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_EN 14:14 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RX_CDR_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OVRD 16:16 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OFF 17:17 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OFF_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OFF_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_LOOP_OFF_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RESET 20:20 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_2_RESET_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_2_RESET_DISABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_2_RESET_ENABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3 0x0008D10C /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_3__PRIV_LEVEL_MASK 0x0008E1C8 /* */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_DATA 9:8 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_MODE 11:10 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_EN 12:12 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_DATA 14:13 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_MODE 16:15 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_EN 17:17 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_OVRD 18:18 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_READY 19:19 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_READY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_READY_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_TX_BYP_READY_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_REF_CLK_EN 20:20 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_REF_CLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_REF_CLK_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_3_RX_BYP_REF_CLK_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4 0x0008D110 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_4__PRIV_LEVEL_MASK 0x0008E1C8 /* */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_OVRD 7:7 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_STAT_IDLE 9:8 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH 11:10 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH__70_MVPPD 0x00000002 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH_120_MVPPD 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH_100_MVPPD 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH_STRAP_LUT0 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH_STRAP_LUT1 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH_STRAP_LUT2 0x00000002 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_TH_STRAP_LUT3 0x00000003 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_BYP 12:12 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_BYP_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_BYP_BYPASS 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_BYP_NORMAL 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_BYP 13:13 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_BYP_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_BYP_BYPASS 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_BYP_NORMAL 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ 14:14 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ_OVRD 15:15 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDDQ_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_EN 16:16 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN_OVRD 18:18 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE_OVRD 19:19 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ 20:20 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ_OVRD 21:21 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_IDDQ_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_TERM_EN 24:24 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_TERM_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_TERM_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_TERM_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_EN 25:25 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_CLK_EN 26:26 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_CLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_CLK_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_RDET_CLK_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_TX_STAT_PRESENT 27:27 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN 29:29 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE 31:30 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_4_AUX_RX_IDLE_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5 0x0008D184 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_5__PRIV_LEVEL_MASK 0x0008E1F4 /* */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_TRAIN_EN 0:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_TRAIN_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_TRAIN_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_TRAIN_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_TRAIN_DONE 1:1 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_RESET 3:3 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_RESET_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_RESET_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_EN 4:4 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_DONE 5:5 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_EN 7:7 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_DONE 8:8 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_OVRD 12:12 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EQ_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_OVRD 13:13 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_CAL_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_OVRD 14:14 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_CYA_RX_CAL_4PT_BYP 15:15 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_5_CYA_RX_CAL_4PT_BYP_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_5_CYA_RX_CAL_4PT_BYP_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_CYA_RX_CAL_4PT_BYP_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_5_RX_EOM_STATUS 31:16 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_6 0x0008D118 /* R--4P */
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#define NV_XP_PEX_PAD_CTL_6__PRIV_LEVEL_MASK 0x0008E1C8 /* */
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#define NV_XP_PEX_PAD_CTL_6_MISC_OUT 31:24 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_8 0x0008D170 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_8__PRIV_LEVEL_MASK 0x0008E1CC /* */
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#define NV_XP_PEX_PAD_CTL_8_CFG_WDATA 15:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_8_CFG_WDATA_INIT 0x0 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_8_CFG_ADDR 23:16 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_8_CFG_ADDR_INIT 0x0 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_8_CFG_WDS 24:24 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_8_CFG_WDS_INIT 0x0 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_8_CFG_RDS 25:25 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_8_CFG_RDS_INIT 0x0 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_8_CFG_RESET 27:27 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_8_CFG_RESET_INIT 0x1 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_9 0x0008D174 /* R--4P */
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#define NV_XP_PEX_PAD_CTL_9__PRIV_LEVEL_MASK 0x0008E1CC /* */
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#define NV_XP_PEX_PAD_CTL_9_CFG_RDATA 15:0 /* R--VF */
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#define NV_XP_PEX_PAD_CTL_10 0x0008D178 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_10__PRIV_LEVEL_MASK 0x0008E1CC /* */
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#define NV_XP_PEX_PAD_CTL_10_CFG_SETUP 7:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_10_CFG_SETUP_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_10_CFG_HOLD 15:8 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_10_CFG_HOLD_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_10_CFG_STROBE_PULSE 23:16 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_10_CFG_STROBE_PULSE_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_10_CFG_READ_DELAY 31:24 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_10_CFG_READ_DELAY_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_1_R1 0x0008D120 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_1_R1__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_INIT 0x00000027 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_1150_MVPPD 0x00000026 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_1000_MVPPD 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP__500_MVPPD 0x0000001A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP__200_MVPPD 0x00000007 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT0 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT1 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT2 0x00000011 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT3 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT4 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT5 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT6 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R1_TX_DRV_AMP_LUT7 0x0000001F /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1 0x0008D124 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R1__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_35DB 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_37DB 0x0000000E /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_60DB 0x00000014 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT0 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT1 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT2 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT3 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT4 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT5 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT6 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_POST_LUT7 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_PRE 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R1_TX_DRV_PRE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_1_R2 0x0008D128 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_1_R2__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_INIT 0x00000027 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_1150_MVPPD 0x00000026 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_1000_MVPPD 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP__500_MVPPD 0x0000001A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP__200_MVPPD 0x00000007 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT0 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT1 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT2 0x00000011 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT3 0x00000015 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT4 0x00000017 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT5 0x00000019 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT6 0x0000001B /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R2_TX_DRV_AMP_LUT7 0x0000001F /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2 0x0008D12C /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R2__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_35DB 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_60DB 0x0000000F /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT0 0x0000000F /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT1 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT2 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT3 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT4 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT5 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT6 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL0_LUT7 0x0000000F /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_PRE_SEL0 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_PRE_SEL0_35DB 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_PRE_SEL0_60DB 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_PRE_SEL0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT0 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT1 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT2 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT3 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT4 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT5 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT6 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_POST_SEL1_LUT7 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_PRE_SEL1 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R2_TX_DRV_PRE_SEL1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_1_R3 0x0008D130 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_1_R3__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_INIT 0x00000027 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_1150_MVPPD 0x00000026 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_1000_MVPPD 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP__500_MVPPD 0x0000001A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP__200_MVPPD 0x00000007 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT0 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_ALT_LUT0 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT1 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT2 0x00000011 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT3 0x00000015 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT4 0x00000017 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT5 0x00000019 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT6 0x0000001B /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R3_TX_DRV_AMP_LUT7 0x0000001F /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_1_R4 0x0008D134 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_1_R4__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_1_R4_TX_DRV_AMP 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_1_R4_TX_DRV_AMP_INIT 0x00000027 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_1_R4_TX_DRV_AMP_LUT0 0x00000027 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0 0x0008D138 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_POST_SEL0 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_POST_SEL0_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_POST_SEL0_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_PRE_SEL0 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_PRE_SEL0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_POST_SEL1 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_POST_SEL1_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_PRE_SEL1 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_0_TX_DRV_PRE_SEL1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1 0x0008D13C /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_POST_SEL2 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_POST_SEL2_INIT 0x0000000C /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_PRE_SEL2 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_PRE_SEL2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_POST_SEL3 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_POST_SEL3_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_PRE_SEL3 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_1_TX_DRV_PRE_SEL3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2 0x0008D140 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_POST_SEL4 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_POST_SEL4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_PRE_SEL4 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_PRE_SEL4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_POST_SEL5 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_POST_SEL5_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_PRE_SEL5 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_2_TX_DRV_PRE_SEL5_INIT 0x00000006 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3 0x0008D144 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_POST_SEL6 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_POST_SEL6_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_PRE_SEL6 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_PRE_SEL6_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_POST_SEL7 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_POST_SEL7_INIT 0x0000000C /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_PRE_SEL7 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_3_TX_DRV_PRE_SEL7_INIT 0x00000006 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4 0x0008D148 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_POST_SEL8 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_POST_SEL8_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_PRE_SEL8 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_PRE_SEL8_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_POST_SEL9 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_POST_SEL9_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_PRE_SEL9 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_4_TX_DRV_PRE_SEL9_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5 0x0008D14C /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_INIT 0x0000000E /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT0 0x00000014 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT1 0x0000000C /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT2 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT3 0x0000000E /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT4 0x00000010 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT5 0x00000011 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT6 0x00000012 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_POST_SEL10_LUT7 0x00000013 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_PRE_SEL10 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_5_TX_DRV_PRE_SEL10_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_6 0x0008D150 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R3_6__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R3_6_TX_DRV_POST_FS 5:0 /* R--VF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_6_TX_DRV_POST_FS_INIT 0x0000003C /* R---V */
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#define NV_XP_PEX_PAD_ECTL_4_R3_6_TX_DRV_POST_LF 13:8 /* R--VF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_6_TX_DRV_PRE_LIMIT 19:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R3_6_TX_DRV_PRE_LIMIT_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0 0x0008D154 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_POST_SEL0 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_POST_SEL0_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_POST_SEL0_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_PRE_SEL0 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_PRE_SEL0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_POST_SEL1 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_POST_SEL1_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_PRE_SEL1 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_0_TX_DRV_PRE_SEL1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1 0x0008D158 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_POST_SEL2 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_POST_SEL2_INIT 0x0000000C /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_PRE_SEL2 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_PRE_SEL2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_POST_SEL3 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_POST_SEL3_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_PRE_SEL3 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_1_TX_DRV_PRE_SEL3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2 0x0008D15C /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_POST_SEL4 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_POST_SEL4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_PRE_SEL4 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_PRE_SEL4_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_POST_SEL5 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_POST_SEL5_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_PRE_SEL5 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_2_TX_DRV_PRE_SEL5_INIT 0x00000006 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3 0x0008D160 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_POST_SEL6 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_POST_SEL6_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_PRE_SEL6 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_PRE_SEL6_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_POST_SEL7 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_POST_SEL7_INIT 0x0000000C /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_PRE_SEL7 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_3_TX_DRV_PRE_SEL7_INIT 0x00000006 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4 0x0008D164 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_POST_SEL8 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_POST_SEL8_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_PRE_SEL8 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_PRE_SEL8_INIT 0x00000008 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_POST_SEL9 21:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_POST_SEL9_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_PRE_SEL9 29:24 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_4_TX_DRV_PRE_SEL9_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_5 0x0008D168 /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R4_5__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R4_5_TX_DRV_POST_SEL10 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_5_TX_DRV_POST_SEL10_INIT 0x0000000E /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_5_TX_DRV_POST_SEL10_LUT0 0x00000014 /* RW--V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_5_TX_DRV_PRE_SEL10 13:8 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_5_TX_DRV_PRE_SEL10_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_6 0x0008D16C /* RW-4P */
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#define NV_XP_PEX_PAD_ECTL_4_R4_6__PRIV_LEVEL_MASK 0x0008E1D0 /* */
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#define NV_XP_PEX_PAD_ECTL_4_R4_6_TX_DRV_POST_FS 5:0 /* R--VF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_6_TX_DRV_POST_FS_INIT 0x0000003C /* R---V */
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#define NV_XP_PEX_PAD_ECTL_4_R4_6_TX_DRV_POST_LF 13:8 /* R--VF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_6_TX_DRV_PRE_LIMIT 19:16 /* RWIVF */
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#define NV_XP_PEX_PAD_ECTL_4_R4_6_TX_DRV_PRE_LIMIT_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PEX_PAD_DUMMY_2(i) (0x0008D1A0+(i)*4) /* RW-4A */
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#define NV_XP_PEX_PAD_DUMMY_2__SIZE_1 8 /* */
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#define NV_XP_PEX_PAD_DUMMY_2__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PEX_PAD_DUMMY_2_DATA 31:0 /* RWIVF */
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#define NV_XP_PEX_PAD_DUMMY_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0 0x0008D1A0 /* RW-4P */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE0 5:0 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE0_INIT 0x00000027 /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE0_DESKTOP 0x00000027 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE0_MOBILE 0x00000027 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE1 13:8 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE1_INIT 0x00000023 /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE1_DESKTOP 0x00000023 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE1_MOBILE 0x00000023 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE2 21:16 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE2_INIT 0x0000001F /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE2_DESKTOP 0x0000001F /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE2_MOBILE 0x0000001F /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE3 29:24 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE3_INIT 0x0000001B /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE3_DESKTOP 0x0000001B /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP0_CODE3_MOBILE 0x0000001B /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1 0x0008D1A4 /* RW-4P */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE4 5:0 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE4_INIT 0x00000017 /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE4_DESKTOP 0x00000017 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE4_MOBILE 0x00000017 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE5 13:8 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE5_INIT 0x00000013 /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE5_DESKTOP 0x00000013 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE5_MOBILE 0x00000013 /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE6 21:16 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE6_INIT 0x0000000F /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE6_DESKTOP 0x0000000F /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE6_MOBILE 0x0000000F /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE7 29:24 /* RWIVF */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE7_INIT 0x0000000B /* RWI-V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE7_DESKTOP 0x0000000B /* RW--V */
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#define NV_XP_PL_PAD_TX_MARGIN_MAP1_CODE7_MOBILE 0x0000000B /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7 0x0008D1A8 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_7__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY 5:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_0_INIT 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_1_INIT 0x00000008 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_2_INIT 0x00000010 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_3_INIT 0x00000018 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_4_INIT 0x00000002 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_5_INIT 0x0000000A /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_6_INIT 0x00000012 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_7_INIT 0x0000001A /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_8_INIT 0x00000004 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_9_INIT 0x0000000C /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_10_INIT 0x00000014 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_11_INIT 0x0000001C /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_12_INIT 0x00000006 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_13_INIT 0x0000000E /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_14_INIT 0x00000016 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_7_STAGGER_DLY_LANE_15_INIT 0x0000001E /* RW--V */
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#define NV_XP_PEX_PAD_CTL_12 0x0008D1B0 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_12__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PEX_PAD_CTL_12_EQ_EOM_ABORT_TIME 11:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_12_EQ_EOM_ABORT_TIME_1us 0x0000007D /* RWI-V */
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#define NV_XP_PEX_PAD_DUMMY_1(i) (0x0008D1C0+(i)*4) /* RW-4A */
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#define NV_XP_PEX_PAD_DUMMY_1__SIZE_1 16 /* */
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#define NV_XP_PEX_PAD_DUMMY_1__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_PEX_PAD_DUMMY_1_DATA 31:0 /* RWIVF */
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#define NV_XP_PEX_PAD_DUMMY_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_16 0x0008D1C0 /* RW-4P */
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#define NV_XP_PEX_PAD_CTL_16_MISC_CTRL 7:0 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_16_MISC_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_MODE 28:28 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_16_CYA_AUX_RX_TERM_EN 29:29 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_16_CYA_AUX_RX_TERM_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_16_CYA_AUX_RX_TERM_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_16_CYA_AUX_RX_TERM_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN_OVRD 30:30 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN 31:31 /* RWIVF */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PAD_CTL_16_AUX_RX_TERM_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1 0x0008D200 /* RW-4R */
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#define NV_XP_PEX_PLL_CTL1__PRIV_LEVEL_MASK 0x0008E1DC /* */
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#define NV_XP_PEX_PLL_CTL1_PLL_IDDQ 0:0 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL1_PLL_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL1_PLL_IDDQ_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_IDDQ_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RSTN 1:1 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL1_PLL_RSTN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RSTN_ENABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RSTN_DISABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_PWR_OVRD 3:3 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL1_PLL_PWR_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL1_PLL_PWR_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_PWR_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_SLEEP 5:4 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL1_PLL_SLEEP_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL1_PLL_SLEEP_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_SLEEP_ENABLE 0x00000003 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID 7:6 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID_GEN12 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID_GEN3 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID_OVRD 8:8 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID_OVRD_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_RATE_ID_OVRD_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_ENABLE 9:9 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL1_PLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL1_PLL_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL1_PLL0_LOCKDET 19:19 /* R--VF */
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#define NV_XP_PEX_PLL_CTL1_PLL0_LOCKDET_NOT_LOCKED 0x00000000 /* R---V */
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#define NV_XP_PEX_PLL_CTL1_PLL0_LOCKDET_LOCKED 0x00000001 /* R---V */
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#define NV_XP_PEX_PLL_CTL2 0x0008D204 /* RW-4R */
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#define NV_XP_PEX_PLL_CTL2__PRIV_LEVEL_MASK 0x0008E1DC /* */
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#define NV_XP_PEX_PLL_CTL2_PLL_TCLKOUT_EN 12:12 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL2_PLL_TCLKOUT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL2_PLL_TCLKOUT_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL2_PLL_TCLKOUT_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL2_PLL_BYPASS_EN 15:15 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL2_PLL_BYPASS_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL2_PLL_BYPASS_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL2_PLL_BYPASS_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL2_PLL_MISC_OUT 31:16 /* R--VF */
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#define NV_XP_PEX_PLL_CTL3 0x0008D208 /* RW-4R */
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#define NV_XP_PEX_PLL_CTL3__PRIV_LEVEL_MASK 0x0008E1DC /* */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_CODE 4:0 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_CODE_INIT 0x0000000E /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_CODE_MAX_R 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_CODE_NOMINAL_R 0x0000000E /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_CODE_MIN_R 0x0000001F /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_CLK_EN 5:5 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_CLK_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_CLK_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_CLK_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_EN 6:6 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_EN 7:7 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_VAL 12:8 /* R--VF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_VAL_MAX_R 0x00000000 /* R---V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_VAL_MIN_R 0x0000001F /* R---V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_OVRD 13:13 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_OVRD_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_BYP_OVRD_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_OVRD 14:14 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_OVRD_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_OVRD_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_DONE 15:15 /* R--VF */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_DONE_FALSE 0x00000000 /* R---V */
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#define NV_XP_PEX_PLL_CTL3_PLL_RCAL_DONE_TRUE 0x00000001 /* R---V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_EN 16:16 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_DONE 17:17 /* R--VF */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_DONE_FALSE 0x00000000 /* R---V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_DONE_TRUE 0x00000001 /* R---V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_RESET 18:18 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_RESET_INIT 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_RESET_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_RESET_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_OVRD 19:19 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_OVRD_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_OVRD_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL3_PLL_CAL_OVRD_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL4_PLL 0x0008D20C /* RW-4R */
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#define NV_XP_PEX_PLL_CTL4_PLL__PRIV_LEVEL_MASK 0x0008E1DC /* */
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#define NV_XP_PEX_PLL_CTL4_PLL_MISC_CTRL 15:0 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL4_PLL_MISC_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL4_PLL_SLEEP_STATE 17:16 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL4_PLL_SLEEP_STATE_INIT 0x00000003 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL4_PLL_IDDQ_STATE 20:20 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL4_PLL_IDDQ_STATE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL4_PLL_IDDQ_STATE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CTL4_PLL_IDDQ_STATE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PEX_PLL_CTL4_PLL_REFCLK_CFG_SEL 21:21 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL4_PLL_REFCLK_CFG_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL5 0x0008D214 /* RW-4R */
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#define NV_XP_PEX_PLL_CTL5__PRIV_LEVEL_MASK 0x0008E1CC /* */
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#define NV_XP_PEX_PLL_CTL5_CFG_WDATA 15:0 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL5_CFG_WDATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL5_CFG_ADDR 23:16 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL5_CFG_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL5_CFG_WDS 24:24 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL5_CFG_WDS_INIT 0x00000000 /* */
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#define NV_XP_PEX_PLL_CTL5_CFG_WDS_DONE 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL5_CFG_WDS_PENDING 0x00000001 /* -W--T */
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#define NV_XP_PEX_PLL_CTL5_CFG_RDS 25:25 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL5_CFG_RDS_INIT 0x00000000 /* */
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#define NV_XP_PEX_PLL_CTL5_CFG_RDS_DONE 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL5_CFG_RDS_PENDING 0x00000001 /* -W--T */
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#define NV_XP_PEX_PLL_CTL5_CFG_RESET 27:27 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL5_CFG_RESET_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PLL_CTL6 0x0008D218 /* R--4R */
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#define NV_XP_PEX_PLL_CTL6__PRIV_LEVEL_MASK 0x0008E1CC /* */
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#define NV_XP_PEX_PLL_CTL6_CFG_RDATA 15:0 /* R--VF */
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#define NV_XP_PEX_PLL_CTL7 0x0008D21C /* RW-4R */
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#define NV_XP_PEX_PLL_CTL7__PRIV_LEVEL_MASK 0x0008E1CC /* */
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#define NV_XP_PEX_PLL_CTL7_CFG_SETUP 7:0 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL7_CFG_SETUP_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PLL_CTL7_CFG_HOLD 15:8 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL7_CFG_HOLD_INIT 0x0000000A /* RWI-V */
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#define NV_XP_PEX_PLL_CTL7_CFG_STROBE_PULSE 23:16 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL7_CFG_STROBE_PULSE_INIT 0x0000001E /* RWI-V */
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#define NV_XP_PEX_PLL_CTL7_CFG_READ_DELAY 31:24 /* RWIVF */
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#define NV_XP_PEX_PLL_CTL7_CFG_READ_DELAY_INIT 0x00000010 /* RWI-V */
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#define NV_XP_PL_PAD_CFG 0x0008D210 /* RW-4R */
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#define NV_XP_PL_PAD_CFG__PRIV_LEVEL_MASK 0x0008E1B4 /* */
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#define NV_XP_PL_PAD_CFG_DFE_RESET_DETECT 0:0 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_DFE_RESET_DETECT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_DFE_RESET_DETECT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_DFE_RESET_DETECT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN1 16:16 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN1_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN2 17:17 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN2_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN2_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN2_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN3 18:18 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN3_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN3_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN3_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_EVERYTIME 19:19 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_EVERYTIME_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_EVERYTIME_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_EVERYTIME_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_RECOVERY_EOM_TRAIN 20:20 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_RECOVERY_EOM_TRAIN_DONE 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_RECOVERY_EOM_TRAIN_PENDING 0x00000001 /* -W--T */
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#define NV_XP_PL_PAD_CFG_RECOVERY_DFE_TRAIN 21:21 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_RECOVERY_DFE_TRAIN_DONE 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_RECOVERY_DFE_TRAIN_PENDING 0x00000001 /* -W--T */
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#define NV_XP_PL_PAD_CFG_TRAIN_PCOMPLIANCE 22:22 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_PCOMPLIANCE_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_PCOMPLIANCE_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_PCOMPLIANCE_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_LOOPBACK 23:23 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_LOOPBACK_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_LOOPBACK_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_LOOPBACK_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_DETECT 24:24 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_DETECT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_DETECT_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_DETECT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_EOM_TRAIN 25:25 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_EOM_TRAIN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_EOM_TRAIN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_EOM_TRAIN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_DFE_TRAIN 26:26 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_DFE_TRAIN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_DFE_TRAIN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN3_DFE_TRAIN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_EOM_TRAIN 27:27 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_EOM_TRAIN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_EOM_TRAIN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_EOM_TRAIN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_DFE_TRAIN 28:28 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_DFE_TRAIN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_DFE_TRAIN_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_CFG_L1_EXIT_GEN4_DFE_TRAIN_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN4 29:29 /* RWIVF */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN4_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN4_DISABLE 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_CFG_TRAIN_GEN4_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_PL_PAD_PERIODIC_EQ 0x0008D240 /* RW-4R */
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#define NV_XP_PL_PAD_PERIODIC_EQ_TIME 19:0 /* RWIVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_TIME_100us 0x00000190 /* RW--V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_TIME_10ms 0x00009C40 /* RWI-V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_COUNT_RESET 29:29 /* RWIVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_COUNT_RESET_INIT 0x00000000 /* */
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#define NV_XP_PL_PAD_PERIODIC_EQ_COUNT_RESET_DONE 0x00000000 /* RWI-V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_COUNT_RESET_PENDING 0x00000001 /* -W--T */
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#define NV_XP_PL_PAD_PERIODIC_EQ_GEN4_EN 30:30 /* RWIVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_GEN4_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_GEN3_EN 31:31 /* RWIVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_GEN3_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_CTL1 0x0008D244 /* RW-4R */
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#define NV_XP_PL_PAD_PERIODIC_EQ_CTL1_TIMEOUT 15:0 /* RWIVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_CTL1_TIMEOUT_INIT 0x000001E0 /* RWI-V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_CTL1_CDR_LOCK_TIME 25:16 /* RWIVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_CTL1_CDR_LOCK_TIME_INIT 0x00000014 /* RWI-V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_CTL1_CDR_LOCK_TIME_ZERO 0x00000000 /* RW--V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_STAT_1 0x0008D248 /* R--4R */
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#define NV_XP_PL_PAD_PERIODIC_EQ_STAT_1_EQ_COUNTER 31:0 /* R-IVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_STAT_1_EQ_COUNTER_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_PAD_PERIODIC_EQ_STAT_2 0x0008D24C /* R--4R */
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#define NV_XP_PL_PAD_PERIODIC_EQ_STAT_2_ABORT_COUNTER 31:0 /* R-IVF */
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#define NV_XP_PL_PAD_PERIODIC_EQ_STAT_2_ABORT_COUNTER_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PEX_PLL 0x0008D324 /* RW-4R */
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#define NV_XP_PEX_PLL__PRIV_LEVEL_MASK 0x0008E1D4 /* */
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#define NV_XP_PEX_PLL_PWRDN_D0_EN 0:0 /* RWIVF */
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#define NV_XP_PEX_PLL_PWRDN_D0_EN_DISBLED 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_PWRDN_D0_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_PWRDN_D1_EN 1:1 /* RWIVF */
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#define NV_XP_PEX_PLL_PWRDN_D1_EN_DISBLED 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_PWRDN_D1_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_PWRDN_D2_EN 2:2 /* RWIVF */
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#define NV_XP_PEX_PLL_PWRDN_D2_EN_DISBLED 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_PWRDN_D2_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_PWRDN_D3_EN 3:3 /* RWIVF */
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#define NV_XP_PEX_PLL_PWRDN_D3_EN_DISBLED 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_PWRDN_D3_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_CLK_REQ_EN 6:6 /* RWIVF */
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#define NV_XP_PEX_PLL_CLK_REQ_EN_DISBLED 0x00000000 /* RWI-V */
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#define NV_XP_PEX_PLL_CLK_REQ_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PEX_PLL_PWRDN_SEQ_START_XCLK_DLY 31:8 /* RWIVF */
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#define NV_XP_PEX_PLL_PWRDN_SEQ_START_XCLK_DLY_INIT 0x00004000 /* RWI-V */
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#define NV_XP_PEX_PLL2 0x0008D328 /* RW-4R */
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#define NV_XP_PEX_PLL2__PRIV_LEVEL_MASK 0x0008E1D8 /* */
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#define NV_XP_PEX_PLL2_PWRDN_MIN_INACTIVE_DLY 23:16 /* RWIVF */
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#define NV_XP_PEX_PLL2_PWRDN_MIN_INACTIVE_DLY_DEFAULT 0x00000001 /* RWI-V */
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#define NV_XP_PEX_PLL2_PWRUP_CLKREQ_TO_SWITCH_REFCLK_DLY 31:24 /* RWIVF */
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#define NV_XP_PEX_PLL2_PWRUP_CLKREQ_TO_SWITCH_REFCLK_DLY_DEFAULT 0x00000001 /* RWI-V */
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#define NV_XP_PL_LTSSM_STATE 0x0008D32C /* R--4R */
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#define NV_XP_PL_LTSSM_STATE_FULL 7:0 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_L0 8:8 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_L0_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_L0_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_L1 9:9 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_L1_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_L1_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_L2 10:10 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_L2_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_L2_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_DEEP_L1 11:11 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_DEEP_L1_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_DEEP_L1_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_TX_L0S 12:12 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_TX_L0S_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_TX_L0S_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_RX_L0S 13:13 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_RX_L0S_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_RX_L0S_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_DETECT 14:14 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_DETECT_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_DETECT_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_POLLING_COMPLIANCE 15:15 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_POLLING_COMPLIANCE_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_POLLING_COMPLIANCE_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_RECOVERY_EQZN 16:16 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_RECOVERY_EQZN_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_RECOVERY_EQZN_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_LINK_DOWN 17:17 /* R-IVF */
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#define NV_XP_PL_LTSSM_STATE_IS_LINK_DOWN_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_LINK_DOWN_TRUE 0x00000001 /* R-I-V */
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#define NV_XP_PL_LTSSM_STATE_IS_LINK_READY 18:18 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_LINK_READY_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_LINK_READY_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_DISABLED 19:19 /* R--VF */
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#define NV_XP_PL_LTSSM_STATE_IS_DISABLED_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_IS_DISABLED_TRUE 0x00000001 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_LANES_IN_SLEEP 31:31 /* R-IVF */
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#define NV_XP_PL_LTSSM_STATE_LANES_IN_SLEEP_FALSE 0x00000000 /* R---V */
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#define NV_XP_PL_LTSSM_STATE_LANES_IN_SLEEP_TRUE 0x00000001 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS 0x0008D400 /* RW-4R */
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#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR 0:0 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_CODING_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR 1:1 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_SYNC_HDR_ORDER_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR 2:2 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_OS_DATA_SEQ_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR 3:3 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_TSX_DATA_SEQ_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR 4:4 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_SKPOS_LFSR_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW 5:5 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_RX_CLK_FIFO_OVERFLOW_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW 6:6 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_ELASTIC_FIFO_OVERFLOW_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR 7:7 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_RCVD_LINK_NUM_ERR_ACTIVE 0x00000000 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR 8:8 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_RCVD_LANE_NUM_ERR_ACTIVE 0x00000000 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR 9:9 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_SKP_RCV_SYM_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR 10:10 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_SKPOS_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR 11:11 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_LOCAL_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR 12:12 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_FIRST_RETIMER_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR 13:13 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_SECOND_RETIMER_DATA_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR 14:14 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_CRC_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR 15:15 /* RWIVF */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR_NOT_ACTIVE 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERROR_STATUS_CTLSKPOS_MARGIN_PARITY_ERR_ACTIVE 0x00000001 /* R---V */
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#define NV_XP__8B10B_ERRORS_COUNT 0x0008D404 /* R--4R */
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#define NV_XP__8B10B_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
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#define NV_XP__8B10B_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_SYNC_HEADER_ERRORS_COUNT 0x0008D408 /* R--4R */
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#define NV_XP_SYNC_HEADER_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
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#define NV_XP_SYNC_HEADER_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_0 0x0008D40C /* R--4R */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_0_VALUE 7:0 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_0_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_1_VALUE 15:8 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_1_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_2_VALUE 23:16 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_2_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_3_VALUE 31:24 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_0_LANE_3_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_1 0x0008D410 /* R--4R */
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#define NV_XP_LANE_ERRORS_COUNT_1_LANE_4_VALUE 7:0 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_1_LANE_4_VALUE_INIT 0x00000000 /* R-I-V */
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|
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_5_VALUE 15:8 /* R-IVF */
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|
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_5_VALUE_INIT 0x00000000 /* R-I-V */
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|
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_6_VALUE 23:16 /* R-IVF */
|
|
#define NV_XP_LANE_ERRORS_COUNT_1_LANE_6_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_1_LANE_7_VALUE 31:24 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_1_LANE_7_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_2 0x0008D414 /* R--4R */
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|
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_8_VALUE 7:0 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_2_LANE_8_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_LANE_ERRORS_COUNT_2_LANE_9_VALUE 15:8 /* R-IVF */
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#define NV_XP_LANE_ERRORS_COUNT_2_LANE_9_VALUE_INIT 0x00000000 /* R-I-V */
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|
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_10_VALUE 23:16 /* R-IVF */
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|
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_10_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_11_VALUE 31:24 /* R-IVF */
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|
#define NV_XP_LANE_ERRORS_COUNT_2_LANE_11_VALUE_INIT 0x00000000 /* R-I-V */
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|
#define NV_XP_LANE_ERRORS_COUNT_3 0x0008D418 /* R--4R */
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|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_12_VALUE 7:0 /* R-IVF */
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|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_12_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_13_VALUE 15:8 /* R-IVF */
|
|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_13_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_14_VALUE 23:16 /* R-IVF */
|
|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_14_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_15_VALUE 31:24 /* R-IVF */
|
|
#define NV_XP_LANE_ERRORS_COUNT_3_LANE_15_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_RECEIVER_ERRORS_COUNT(i) (0x0008D440+(i)*4) /* R--4A */
|
|
#define NV_XP_RECEIVER_ERRORS_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_RECEIVER_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
|
|
#define NV_XP_RECEIVER_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_LCRC_ERRORS_COUNT(i) (0x0008D480+(i)*4) /* R--4A */
|
|
#define NV_XP_LCRC_ERRORS_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_LCRC_ERRORS_COUNT_VALUE 15:0 /* R-IVF */
|
|
#define NV_XP_LCRC_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_FAILED_L0S_EXITS_COUNT(i) (0x0008D4C0+(i)*4) /* R--4A */
|
|
#define NV_XP_FAILED_L0S_EXITS_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_FAILED_L0S_EXITS_COUNT_VALUE 15:0 /* R-IVF */
|
|
#define NV_XP_FAILED_L0S_EXITS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_NAKS_SENT_COUNT(i) (0x0008D500+(i)*4) /* R--4A */
|
|
#define NV_XP_NAKS_SENT_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_NAKS_SENT_COUNT_VALUE 15:0 /* R-IVF */
|
|
#define NV_XP_NAKS_SENT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_NAKS_RCVD_COUNT(i) (0x0008D540+(i)*4) /* R--4A */
|
|
#define NV_XP_NAKS_RCVD_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_NAKS_RCVD_COUNT_VALUE 15:0 /* R-IVF */
|
|
#define NV_XP_NAKS_RCVD_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_NAKS_RCVD_COUNT_ILLOGICAL_VALUE 23:16 /* R-IVF */
|
|
#define NV_XP_NAKS_RCVD_COUNT_ILLOGICAL_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_REPLAY_COUNT(i) (0x0008D580+(i)*4) /* R--4A */
|
|
#define NV_XP_REPLAY_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_REPLAY_COUNT_VALUE 31:0 /* R-IVF */
|
|
#define NV_XP_REPLAY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_REPLAY_ROLLOVER_COUNT(i) (0x0008D5C0+(i)*4) /* R--4A */
|
|
#define NV_XP_REPLAY_ROLLOVER_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_REPLAY_ROLLOVER_COUNT_VALUE 15:0 /* R-IVF */
|
|
#define NV_XP_REPLAY_ROLLOVER_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_L1_TO_RECOVERY_COUNT(i) (0x0008D600+(i)*4) /* R--4A */
|
|
#define NV_XP_L1_TO_RECOVERY_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_L1_TO_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
|
|
#define NV_XP_L1_TO_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_L0_TO_RECOVERY_COUNT(i) (0x0008D640+(i)*4) /* R--4A */
|
|
#define NV_XP_L0_TO_RECOVERY_COUNT__SIZE_1 1 /* */
|
|
#define NV_XP_L0_TO_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
|
|
#define NV_XP_L0_TO_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_RECOVERY_COUNT(i) (0x0008D680+(i)*4) /* R--4A */
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#define NV_XP_RECOVERY_COUNT__SIZE_1 1 /* */
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#define NV_XP_RECOVERY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_RECOVERY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_BAD_DLLP_COUNT(i) (0x0008D6C0+(i)*4) /* R--4A */
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#define NV_XP_BAD_DLLP_COUNT__SIZE_1 1 /* */
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#define NV_XP_BAD_DLLP_COUNT_VALUE 15:0 /* R-IVF */
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#define NV_XP_BAD_DLLP_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_BAD_TLP_COUNT(i) (0x0008D700+(i)*4) /* R--4A */
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#define NV_XP_BAD_TLP_COUNT__SIZE_1 1 /* */
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#define NV_XP_BAD_TLP_COUNT_VALUE 15:0 /* R-IVF */
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#define NV_XP_BAD_TLP_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT(i) (0x0008D740+(i)*4) /* R--4A */
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#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT__SIZE_1 1 /* */
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#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_CHIPSET_XMIT_L0S_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT(i) (0x0008D780+(i)*4) /* R--4A */
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#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT__SIZE_1 1 /* */
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#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_GPU_XMIT_L0S_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_L1_ENTRY_COUNT(i) (0x0008D7C0+(i)*4) /* R--4A */
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#define NV_XP_L1_ENTRY_COUNT__SIZE_1 1 /* */
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#define NV_XP_L1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_L1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_L1P_ENTRY_COUNT(i) (0x0008D800+(i)*4) /* R--4A */
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#define NV_XP_L1P_ENTRY_COUNT__SIZE_1 1 /* */
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#define NV_XP_L1P_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_L1P_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_DEEP_L1_ENTRY_COUNT(i) (0x0008D840+(i)*4) /* R--4A */
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#define NV_XP_DEEP_L1_ENTRY_COUNT__SIZE_1 1 /* */
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#define NV_XP_DEEP_L1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_DEEP_L1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_ASLM_COUNT(i) (0x0008D880+(i)*4) /* R--4A */
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#define NV_XP_ASLM_COUNT__SIZE_1 1 /* */
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#define NV_XP_ASLM_COUNT_VALUE 15:0 /* R-IVF */
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#define NV_XP_ASLM_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_SKPOS_ERRORS_COUNT(i) (0x0008D8C0+(i)*4) /* R--4A */
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#define NV_XP_SKPOS_ERRORS_COUNT__SIZE_1 1 /* */
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#define NV_XP_SKPOS_ERRORS_COUNT_VALUE 7:0 /* R-IVF */
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#define NV_XP_SKPOS_ERRORS_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_L1_1_ENTRY_COUNT(i) (0x0008D910+(i)*4) /* R--4A */
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#define NV_XP_L1_1_ENTRY_COUNT__SIZE_1 1 /* */
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#define NV_XP_L1_1_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_L1_1_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_L1_2_ENTRY_COUNT(i) (0x0008D950+(i)*4) /* R--4A */
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#define NV_XP_L1_2_ENTRY_COUNT__SIZE_1 1 /* */
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#define NV_XP_L1_2_ENTRY_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_L1_2_ENTRY_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_L1_2_ABORT_COUNT(i) (0x0008D990+(i)*4) /* R--4A */
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#define NV_XP_L1_2_ABORT_COUNT__SIZE_1 1 /* */
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#define NV_XP_L1_2_ABORT_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_L1_2_ABORT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT(i) (0x0008D9D0+(i)*4) /* R--4A */
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#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT__SIZE_1 1 /* */
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#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_L1_SHORT_DURATION_COUNT(i) (0x0008E0C4+(i)*4) /* R--4A */
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#define NV_XP_L1_SHORT_DURATION_COUNT__SIZE_1 1 /* */
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#define NV_XP_L1_SHORT_DURATION_COUNT_VALUE 31:0 /* R-IVF */
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#define NV_XP_L1_SHORT_DURATION_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_XP_ERROR_COUNTER_RESET 0x0008D900 /* RWI4R */
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#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT 0:0 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_8B10B_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT 1:1 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_SYNC_HEADER_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT 2:2 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_LANE_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT 3:3 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_RECEIVER_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT 4:4 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_LCRC_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT 5:5 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_FAILED_L0S_EXITS_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT 6:6 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_NAKS_SENT_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT 7:7 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_NAKS_RCVD_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT 8:8 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_REPLAY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT 9:9 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_REPLAY_ROLLOVER_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT 10:10 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1_TO_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT 11:11 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L0_TO_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT 12:12 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_RECOVERY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT 13:13 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_BAD_DLLP_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT 14:14 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_BAD_TLP_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT 15:15 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_CHIPSET_XMIT_L0S_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT 16:16 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_GPU_XMIT_L0S_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT 17:17 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT 18:18 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1P_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT 19:19 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_DEEP_L1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT 20:20 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_ASLM_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT 21:21 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_SKPOS_ERRORS_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT 22:22 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1_1_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT 23:23 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1_2_ENTRY_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT 24:24 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1_2_ABORT_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT 25:25 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT 26:26 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT_DONE 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_RESET_L1_SHORT_DURATION_COUNT_PENDING 0x00000001 /* -W--T */
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#define NV_XP_ERROR_COUNTER_FREEZE 0x0008D904 /* RWI4R */
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#define NV_XP_ERROR_COUNTER_FREEZE_8B10B_ERRORS_COUNT 0:0 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_8B10B_ERRORS_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_8B10B_ERRORS_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_SYNC_HEADER_ERRORS_COUNT 1:1 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_SYNC_HEADER_ERRORS_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_SYNC_HEADER_ERRORS_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_LANE_ERRORS_COUNT 2:2 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_LANE_ERRORS_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_LANE_ERRORS_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_RECEIVER_ERRORS_COUNT 3:3 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_RECEIVER_ERRORS_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_RECEIVER_ERRORS_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_LCRC_ERRORS_COUNT 4:4 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_LCRC_ERRORS_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_LCRC_ERRORS_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_FAILED_L0S_EXITS_COUNT 5:5 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_FAILED_L0S_EXITS_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_FAILED_L0S_EXITS_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_NAKS_SENT_COUNT 6:6 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_NAKS_SENT_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_NAKS_SENT_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_NAKS_RCVD_COUNT 7:7 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_NAKS_RCVD_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_NAKS_RCVD_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_REPLAY_COUNT 8:8 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_REPLAY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_REPLAY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_REPLAY_ROLLOVER_COUNT 9:9 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_REPLAY_ROLLOVER_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_REPLAY_ROLLOVER_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_TO_RECOVERY_COUNT 10:10 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_TO_RECOVERY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_TO_RECOVERY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L0_TO_RECOVERY_COUNT 11:11 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L0_TO_RECOVERY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L0_TO_RECOVERY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_RECOVERY_COUNT 12:12 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_RECOVERY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_RECOVERY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_BAD_DLLP_COUNT 13:13 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_BAD_DLLP_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_BAD_DLLP_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_BAD_TLP_COUNT 14:14 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_BAD_TLP_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_BAD_TLP_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_CHIPSET_XMIT_L0S_ENTRY_COUNT 15:15 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_CHIPSET_XMIT_L0S_ENTRY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_CHIPSET_XMIT_L0S_ENTRY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_GPU_XMIT_L0S_ENTRY_COUNT 16:16 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_GPU_XMIT_L0S_ENTRY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_GPU_XMIT_L0S_ENTRY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_ENTRY_COUNT 17:17 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_ENTRY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_ENTRY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1P_ENTRY_COUNT 18:18 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1P_ENTRY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1P_ENTRY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_DEEP_L1_ENTRY_COUNT 19:19 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_DEEP_L1_ENTRY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_DEEP_L1_ENTRY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_ASLM_COUNT 20:20 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_ASLM_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_ASLM_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_SKPOS_ERRORS_COUNT 21:21 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_SKPOS_ERRORS_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_SKPOS_ERRORS_COUNT_ENABLE 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_1_ENTRY_COUNT 22:22 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_1_ENTRY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_1_ENTRY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_2_ENTRY_COUNT 23:23 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_2_ENTRY_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_2_ENTRY_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_2_ABORT_COUNT 24:24 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_2_ABORT_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_2_ABORT_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT 25:25 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_SUBSTATE_TO_DEEP_L1_TIMEOUT_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_SHORT_DURATION_COUNT 26:26 /* RWIVF */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_SHORT_DURATION_COUNT_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_ERROR_COUNTER_FREEZE_L1_SHORT_DURATION_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_LANES_DETECTED 0x0008D90C /* R--4R */
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#define NV_XP_PL_LANES_DETECTED_IN_DETECT 15:0 /* R--VF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN 0x0008D908 /* RWI4R */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN1 7:0 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN1_INIT 0x00000010 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN2 15:8 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN2_INIT 0x00000010 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN3 23:16 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN3_INIT 0x00000010 /* RWI-V */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN4 31:24 /* RWIVF */
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#define NV_XP_PL_IDLE_TIMER_RX_L0S_MIN_GEN4_INIT 0x00000010 /* RWI-V */
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#define NV_XP_LA_CR_1 0x0008DA00 /* RW-4R */
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#define NV_XP_LA_CR_1_MASTER_EN 0:0 /* RWIVF */
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#define NV_XP_LA_CR_1_MASTER_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_1_MASTER_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_CR_1_MASTER_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_CR_1_RELATIVE_TIMESTAMP_SIZE 4:1 /* RWIVF */
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#define NV_XP_LA_CR_1_RELATIVE_TIMESTAMP_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIMESTAMPS_EN 5:5 /* RWIVF */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIMESTAMPS_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIMESTAMPS_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIMESTAMPS_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET 6:6 /* RWIVF */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET_INIT 0x00000000 /* */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET_DONE 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET_PENDING 0x00000001 /* -W--T */
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#define NV_XP_LA_CR_1_START_LOGGING 7:7 /* RWIVF */
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#define NV_XP_LA_CR_1_START_LOGGING_DONE 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_1_START_LOGGING_PENDING 0x00000001 /* -W--T */
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#define NV_XP_LA_CR_1_STOP_LOGGING 8:8 /* RWIVF */
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#define NV_XP_LA_CR_1_STOP_LOGGING_DONE 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_1_STOP_LOGGING_PENDING 0x00000001 /* -W--T */
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#define NV_XP_LA_CR_1_PROLOGUE_MAX_SIZE 18:9 /* RWIVF */
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#define NV_XP_LA_CR_1_PROLOGUE_MAX_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_1_PROLOGUE_WRAP_AROUND_MODE 19:19 /* RWIVF */
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#define NV_XP_LA_CR_1_PROLOGUE_WRAP_AROUND_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_1_PROLOGUE_WRAP_AROUND_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_CR_1_PROLOGUE_WRAP_AROUND_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_CR_2 0x0008DA04 /* RW-4R */
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#define NV_XP_LA_CR_2_RAM_WRAP_AROUND_MODE 0:0 /* RWIVF */
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#define NV_XP_LA_CR_2_RAM_WRAP_AROUND_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_2_RAM_WRAP_AROUND_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_CR_2_RAM_WRAP_AROUND_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_CR_2_RAM_FULL 1:1 /* R--VF */
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#define NV_XP_LA_CR_2_RAM_READ_ADDRESS 11:2 /* RWIVF */
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#define NV_XP_LA_CR_2_RAM_READ_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_2_RAM_WRITE_POINTER 21:12 /* R--VF */
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#define NV_XP_LA_CR_2_RAM_READ_MODE 22:22 /* RWIVF */
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#define NV_XP_LA_CR_2_RAM_READ_MODE_TRACE 0x00000000 /* RWI-V */
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#define NV_XP_LA_CR_2_RAM_READ_MODE_SAMPLE_INTERVALS 0x00000001 /* RW--V */
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#define NV_XP_LA_CR_2_LA_STATUS 24:24 /* R-IVF */
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#define NV_XP_LA_CR_2_LA_STATUS_STOPPED 0x00000000 /* R-I-V */
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#define NV_XP_LA_CR_2_LA_STATUS_RUNNING 0x00000001 /* R---V */
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#define NV_XP_LA_CR_2_PROLOGUE_FULL 26:26 /* R--VF */
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#define NV_XP_LA_CR_3 0x0008DA08 /* R--4R */
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#define NV_XP_LA_CR_3_PROLOGUE_WRITE_POINTER 9:0 /* R--VF */
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#define NV_XP_LA_EVENT_LOG_DW0 0x0008DA10 /* R--4R */
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#define NV_XP_LA_EVENT_LOG_DW0_0 31:0 /* R--VF */
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#define NV_XP_LA_EVENT_LOG_DW1 0x0008DA14 /* R--4R */
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#define NV_XP_LA_EVENT_LOG_DW1_1 31:0 /* R--VF */
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#define NV_XP_LA_EVENT_LOG_DW2 0x0008DA18 /* R--4R */
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#define NV_XP_LA_EVENT_LOG_DW2_2 15:0 /* R--VF */
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#define NV_XP_LA_LTSSM_DET_CTRL 0x0008DA20 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_CTRL_EN 0:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_LTSSM_DET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_LTSSM_DET_CTRL_CONFIG_SETTINGS 11:1 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_RPT_EN 15:12 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2 0x0008DA24 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_EVENT_REPORT_SIZE 31:30 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_2_EVENT_REPORT_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_3 0x0008DB30 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX0_SLCT 3:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX0_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX1_SLCT 7:4 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX1_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX2_SLCT 11:8 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX2_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX3_SLCT 15:12 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_MUX3_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_FUNCTION 31:16 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_CTRL_3_STYLE3_FUNCTION_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_0 0x0008DA28 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_0 0x0008DA2C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_1 0x0008DA30 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_1 0x0008DA34 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_2 0x0008DA38 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_2 0x0008DA3C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_3 0x0008DA40 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_MATCH_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_3 0x0008DA44 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE0_DONTCARE_MASK_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_0 0x0008DA48 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_0 0x0008DA4C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_1 0x0008DB90 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_1 0x0008DB94 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_2 0x0008DB98 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE1_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_2 0x0008DB9C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE1_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_0 0x0008DA50 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_0 0x0008DA54 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_1 0x0008DB34 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_1 0x0008DB38 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_2 0x0008DB3C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_2 0x0008DB40 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_3 0x0008DB44 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_3 0x0008DB48 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_4 0x0008DB18 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_4_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_MATCH_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_4 0x0008DB1C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_4_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE2_DONTCARE_MASK_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_0 0x0008DB4C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_0 0x0008DB50 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_1 0x0008DB54 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_1 0x0008DB58 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_2 0x0008DB5C /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE3_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_2 0x0008DB60 /* RW-4R */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_LTSSM_DET_STYLE3_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL 0x0008DA60 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_CTRL_EN 0:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_CONFIG_SETTINGS 11:1 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_RPT_EN 15:12 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2 0x0008DA64 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3 0x0008DB64 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX0_SLCT 3:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX0_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX1_SLCT 7:4 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX1_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX2_SLCT 11:8 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX2_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX3_SLCT 15:12 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_MUX3_SLCT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_FUNCTION 31:16 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_CTRL_3_STYLE3_FUNCTION_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_0 0x0008DA68 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_0 0x0008DA6C /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_1 0x0008DA70 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_1 0x0008DA74 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_2 0x0008DA78 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_2 0x0008DA7C /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_3 0x0008DBA0 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_MATCH_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_3 0x0008DBA4 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE0_DONTCARE_MASK_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_MATCH_0 0x0008DA80 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_DONTCARE_MASK_0 0x0008DA84 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_MATCH_1 0x0008DA88 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_DONTCARE_MASK_1 0x0008DA8C /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE1_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE2_MATCH_0 0x0008DA90 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE2_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE2_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE2_DONTCARE_MASK_0 0x0008DA94 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE2_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE2_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_0 0x0008DA98 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_0 0x0008DA9C /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_1 0x0008DB68 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_1 0x0008DB6C /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_2 0x0008DB70 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_2 0x0008DB74 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_3 0x0008DB78 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_3 0x0008DB7C /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_4 0x0008DB80 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_4_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_MATCH_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_4 0x0008DB84 /* RW-4R */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_4_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_PL_LANE_DET_STYLE3_DONTCARE_MASK_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL 0x0008DAA0 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_CTRL_EN 0:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_CONFIG_SETTINGS 11:1 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_RPT_EN 15:12 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2 0x0008DAA4 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_EVENT_REPORT_SIZE 31:30 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_CTRL_2_EVENT_REPORT_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_0 0x0008DAA8 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_0 0x0008DAAC /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_1 0x0008DAB0 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_1 0x0008DAB4 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_2 0x0008DAB8 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_2 0x0008DABC /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_3 0x0008DBA8 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_MATCH_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_3 0x0008DBAC /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_3_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE0_DONTCARE_MASK_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_0 0x0008DAC0 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_0 0x0008DAC4 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_1 0x0008DAC8 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_1 0x0008DACC /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_2 0x0008DBB0 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_2 0x0008DBB4 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE1_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_0 0x0008DAD0 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_0 0x0008DAD4 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_1 0x0008DAD8 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_1 0x0008DADC /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_2 0x0008DBB8 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_MATCH_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_2 0x0008DBBC /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_2_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE2_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_MATCH_0 0x0008DAE0 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_DONTCARE_MASK_0 0x0008DAE4 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_MATCH_1 0x0008DAE8 /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_DONTCARE_MASK_1 0x0008DAEC /* RW-4R */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_MGR_DET_STYLE3_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL 0x0008DAF0 /* RW-4R */
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#define NV_XP_LA_DL_DET_CTRL_EN 0:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_LA_DL_DET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_LA_DL_DET_CTRL_CONFIG_SETTINGS 11:1 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_RPT_EN 15:12 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2 0x0008DAF4 /* RW-4R */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWIVF */
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#define NV_XP_LA_DL_DET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE0_MATCH_0 0x0008DAF8 /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE0_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE0_DONTCARE_MASK_0 0x0008DAFC /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE0_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE1_MATCH_0 0x0008DB10 /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE1_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE1_DONTCARE_MASK_0 0x0008DB14 /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE1_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE2_MATCH_0 0x0008DB20 /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE2_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE2_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE2_DONTCARE_MASK_0 0x0008DB24 /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE2_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE2_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE2_MATCH_1 0x0008DB28 /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE2_MATCH_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE2_MATCH_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE2_DONTCARE_MASK_1 0x0008DB2C /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE2_DONTCARE_MASK_1_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE2_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE3_MATCH_0 0x0008DB88 /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE3_MATCH_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE3_MATCH_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_LA_DL_DET_STYLE3_DONTCARE_MASK_0 0x0008DB8C /* RW-4R */
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#define NV_XP_LA_DL_DET_STYLE3_DONTCARE_MASK_0_DATA 31:0 /* RWIVF */
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#define NV_XP_LA_DL_DET_STYLE3_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PRI_XP3G_CG 0x0008E000 /* RWI4R */
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#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
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#define NV_XP_PRI_XP3G_CG_IDLE_CG_DLY_CNT__PROD 0x0000000B /* RW--V */
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#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_PRI_XP3G_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
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#define NV_XP_PRI_XP3G_CG_STATE_CG_EN 7:7 /* */
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#define NV_XP_PRI_XP3G_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
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#define NV_XP_PRI_XP3G_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_STATE_CG_EN__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_XP_PRI_XP3G_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PRI_XP3G_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_PRI_XP3G_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
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#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
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#define NV_XP_PRI_XP3G_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN 28:28 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_EN__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
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#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_HALT_CG_EN 31:31 /* */
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#define NV_XP_PRI_XP3G_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
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#define NV_XP_PRI_XP3G_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG_HALT_CG_EN__PROD 0x00000000 /* */
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#define NV_XP_PRI_XP3G_CG1 0x0008E004 /* RWI4R */
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#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_XP_PRI_XP3G_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2 0x0008E008 /* RW-4R */
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#define NV_XP_CLKCTRL_BLKCG2__PRIV_LEVEL_MASK 0x0008E1C0 /* */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_XVE3G_IDLE_WAKE_EN 0:0 /* RWIVF */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_XVE3G_IDLE_WAKE_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_XVE3G_IDLE_WAKE_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_XVE3G_IDLE_WAKE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_TLP_PENDING_WAKE_EN 1:1 /* RWIVF */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_TLP_PENDING_WAKE_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_TLP_PENDING_WAKE_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_TLP_PENDING_WAKE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_DL_TX_NONIDLE_WAKE_EN 2:2 /* RWIVF */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_DL_TX_NONIDLE_WAKE_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_DL_TX_NONIDLE_WAKE_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_XV2XP_DL_TX_NONIDLE_WAKE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_XP_PAD_IDLE_WAKE_EN 3:3 /* RWIVF */
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#define NV_XP_CLKCTRL_BLKCG2_XP_PAD_IDLE_WAKE_EN_INIT 0x00000001 /* RWI-V */
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#define NV_XP_CLKCTRL_BLKCG2_XP_PAD_IDLE_WAKE_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_XP_PAD_IDLE_WAKE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_HOST2XV_FORCE_CLK_ON_WAKE_EN 4:4 /* RWIVF */
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#define NV_XP_CLKCTRL_BLKCG2_HOST2XV_FORCE_CLK_ON_WAKE_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_CLKCTRL_BLKCG2_HOST2XV_FORCE_CLK_ON_WAKE_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_HOST2XV_FORCE_CLK_ON_WAKE_EN_DISALED 0x00000000 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_L1 8:8 /* RWIVF */
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#define NV_XP_CLKCTRL_BLKCG2_L1_INIT 0x00000001 /* RWI-V */
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#define NV_XP_CLKCTRL_BLKCG2_L1_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_L1_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_GATE_IN_DEEP_L1 9:9 /* RWIVF */
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#define NV_XP_CLKCTRL_BLKCG2_GATE_IN_DEEP_L1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_CLKCTRL_BLKCG2_GATE_IN_DEEP_L1_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_CLKCTRL_BLKCG2_GATE_IN_DEEP_L1_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PM_CTRL 0x0008E00C /* RW-4R */
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#define NV_XP_PM_CTRL_SEL0 7:0 /* RWIVF */
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#define NV_XP_PM_CTRL_SEL0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PM_CTRL_SEL0_GRP0 0x00000000 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP1 0x00000001 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP2 0x00000002 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP3 0x00000003 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP4 0x00000004 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP5 0x00000005 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP6 0x00000006 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP7 0x00000007 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP8 0x00000008 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP9 0x00000009 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP10 0x0000000a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP11 0x0000000b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP12 0x0000000c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP13 0x0000000d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP14 0x0000000e /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP15 0x0000000f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP16 0x00000010 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP17 0x00000011 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP18 0x00000012 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP19 0x00000013 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP20 0x00000014 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP21 0x00000015 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP22 0x00000016 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP23 0x00000017 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP24 0x00000018 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP25 0x00000019 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP26 0x0000001a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP27 0x0000001b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP28 0x0000001c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP29 0x0000001d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP30 0x0000001e /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP31 0x0000001f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP32 0x00000020 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP33 0x00000021 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP34 0x00000022 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP35 0x00000023 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP36 0x00000024 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP37 0x00000025 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP38 0x00000026 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP39 0x00000027 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP40 0x00000028 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP41 0x00000029 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP42 0x0000002a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP43 0x0000002b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP44 0x0000002c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP45 0x0000002d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP46 0x0000002e /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP47 0x0000002f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP48 0x00000030 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP49 0x00000031 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP50 0x00000032 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP51 0x00000033 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP52 0x00000034 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP53 0x00000035 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP54 0x00000036 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP55 0x00000037 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP56 0x00000038 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP57 0x00000039 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP58 0x0000003a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP59 0x0000003b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP60 0x0000003c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP61 0x0000003d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP62 0x0000003e /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP63 0x0000003f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP64 0x00000040 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP65 0x00000041 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP66 0x00000042 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP67 0x00000043 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP68 0x00000044 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP69 0x00000045 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP70 0x00000046 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP71 0x00000047 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP72 0x00000048 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP73 0x00000049 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP74 0x0000004a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP75 0x0000004b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP76 0x0000004c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP77 0x0000004d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP78 0x0000004e /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP79 0x0000004f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP80 0x00000050 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP81 0x00000051 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP82 0x00000052 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP83 0x00000053 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP84 0x00000054 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP85 0x00000055 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP86 0x00000056 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP87 0x00000057 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP88 0x00000058 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP89 0x00000059 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP90 0x0000005a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP91 0x0000005b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP92 0x0000005c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP93 0x0000005d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP94 0x0000005e /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP95 0x0000005f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP96 0x00000060 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP97 0x00000061 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP98 0x00000062 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP99 0x00000063 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP100 0x00000064 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP101 0x00000065 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP102 0x00000066 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP103 0x00000067 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP104 0x00000068 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP105 0x00000069 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP106 0x0000006a /* RW--V */
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|
#define NV_XP_PM_CTRL_SEL0_GRP107 0x0000006b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP108 0x0000006c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP109 0x0000006d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP110 0x0000006e /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL0_GRP111 0x0000006f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP112 0x00000070 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP113 0x00000071 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP114 0x00000072 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP115 0x00000073 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP116 0x00000074 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL0_GRP117 0x00000075 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL0_GRP118 0x00000076 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP119 0x00000077 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP120 0x00000078 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP121 0x00000079 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP122 0x0000007a /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP123 0x0000007b /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP124 0x0000007c /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP125 0x0000007d /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP126 0x0000007e /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP127 0x0000007f /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP128 0x00000080 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP129 0x00000081 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP130 0x00000082 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP131 0x00000083 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP132 0x00000084 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP133 0x00000085 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP134 0x00000086 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP135 0x00000087 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP136 0x00000088 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP137 0x00000089 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP138 0x0000008a /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP139 0x0000008b /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP140 0x0000008c /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP141 0x0000008d /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP142 0x0000008e /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP143 0x0000008f /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP144 0x00000090 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP145 0x00000091 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP146 0x00000092 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP147 0x00000093 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP148 0x00000094 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP149 0x00000095 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP150 0x00000096 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP151 0x00000097 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP152 0x00000098 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL0_GRP153 0x00000099 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL0_GRP154 0x0000009a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP155 0x0000009b /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP156 0x0000009c /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP157 0x0000009d /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP158 0x0000009e /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP159 0x0000009f /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP160 0x000000a0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP161 0x000000a1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP162 0x000000a2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP163 0x000000a3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP164 0x000000a4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP165 0x000000a5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP166 0x000000a6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP167 0x000000a7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP168 0x000000a8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP169 0x000000a9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP170 0x000000aa /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP171 0x000000ab /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP172 0x000000ac /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP173 0x000000ad /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP174 0x000000ae /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP175 0x000000af /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP176 0x000000b0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP177 0x000000b1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP178 0x000000b2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP179 0x000000b3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP180 0x000000b4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP181 0x000000b5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP182 0x000000b6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP183 0x000000b7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP184 0x000000b8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP185 0x000000b9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP186 0x000000ba /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP187 0x000000bb /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP188 0x000000bc /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP189 0x000000bd /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP190 0x000000be /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP191 0x000000bf /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP192 0x000000c0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP193 0x000000c1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP194 0x000000c2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP195 0x000000c3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP196 0x000000c4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP197 0x000000c5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP198 0x000000c6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP199 0x000000c7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP200 0x000000c8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP201 0x000000c9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP202 0x000000ca /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP203 0x000000cb /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP204 0x000000cc /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP205 0x000000cd /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP206 0x000000ce /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP207 0x000000cf /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP208 0x000000d0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP209 0x000000d1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP210 0x000000d2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP211 0x000000d3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP212 0x000000d4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP213 0x000000d5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP214 0x000000d6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP215 0x000000d7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP216 0x000000d8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP217 0x000000d9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP218 0x000000da /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP219 0x000000db /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP220 0x000000dc /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP221 0x000000dd /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP222 0x000000de /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP223 0x000000df /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP224 0x000000e0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP225 0x000000e1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP226 0x000000e2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP227 0x000000e3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP228 0x000000e4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP229 0x000000e5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP230 0x000000e6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP231 0x000000e7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP232 0x000000e8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP233 0x000000e9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP234 0x000000ea /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP235 0x000000eb /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP236 0x000000ec /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP237 0x000000ed /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP238 0x000000ee /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP239 0x000000ef /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP240 0x000000f0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP241 0x000000f1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP242 0x000000f2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP243 0x000000f3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP244 0x000000f4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP245 0x000000f5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP246 0x000000f6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP247 0x000000f7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP248 0x000000f8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP249 0x000000f9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP250 0x000000fa /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP251 0x000000fb /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP252 0x000000fc /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP253 0x000000fd /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP254 0x000000fe /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_GRP255 0x000000ff /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_STATIC_PATTERN_55_8_GROUP 0x0000009a /* RW--V */
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#define NV_XP_PM_CTRL_SEL0_STATIC_PATTERN_AA_8_GROUP 0x0000009b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1 15:8 /* RWIVF */
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#define NV_XP_PM_CTRL_SEL1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PM_CTRL_SEL1_GRP0 0x00000000 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP1 0x00000001 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP2 0x00000002 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP3 0x00000003 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP4 0x00000004 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP5 0x00000005 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP6 0x00000006 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP7 0x00000007 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP8 0x00000008 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP9 0x00000009 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP10 0x0000000a /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP11 0x0000000b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP12 0x0000000c /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP13 0x0000000d /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP14 0x0000000e /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP15 0x0000000f /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP16 0x00000010 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP17 0x00000011 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP18 0x00000012 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP19 0x00000013 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP20 0x00000014 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP21 0x00000015 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP22 0x00000016 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP23 0x00000017 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP24 0x00000018 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP25 0x00000019 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP26 0x0000001a /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP27 0x0000001b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP28 0x0000001c /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP29 0x0000001d /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP30 0x0000001e /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP31 0x0000001f /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP32 0x00000020 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP33 0x00000021 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP34 0x00000022 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP35 0x00000023 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP36 0x00000024 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP37 0x00000025 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP38 0x00000026 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP39 0x00000027 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP40 0x00000028 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP41 0x00000029 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP42 0x0000002a /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP43 0x0000002b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP44 0x0000002c /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP45 0x0000002d /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP46 0x0000002e /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP47 0x0000002f /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP48 0x00000030 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP49 0x00000031 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP50 0x00000032 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP51 0x00000033 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP52 0x00000034 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP53 0x00000035 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP54 0x00000036 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP55 0x00000037 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP56 0x00000038 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP57 0x00000039 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP58 0x0000003a /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP59 0x0000003b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP60 0x0000003c /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP61 0x0000003d /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP62 0x0000003e /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP63 0x0000003f /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP64 0x00000040 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP65 0x00000041 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP66 0x00000042 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP67 0x00000043 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP68 0x00000044 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP69 0x00000045 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP70 0x00000046 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP71 0x00000047 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP72 0x00000048 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP73 0x00000049 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP74 0x0000004a /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP75 0x0000004b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP76 0x0000004c /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP77 0x0000004d /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP78 0x0000004e /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP79 0x0000004f /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP80 0x00000050 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP81 0x00000051 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP82 0x00000052 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP83 0x00000053 /* RW--V */
|
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#define NV_XP_PM_CTRL_SEL1_GRP84 0x00000054 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP85 0x00000055 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP86 0x00000056 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP87 0x00000057 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP88 0x00000058 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP89 0x00000059 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP90 0x0000005a /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP91 0x0000005b /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP92 0x0000005c /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP93 0x0000005d /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP94 0x0000005e /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP95 0x0000005f /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP96 0x00000060 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP97 0x00000061 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP98 0x00000062 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP99 0x00000063 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP100 0x00000064 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP101 0x00000065 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP102 0x00000066 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP103 0x00000067 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP104 0x00000068 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP105 0x00000069 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP106 0x0000006a /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP107 0x0000006b /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP108 0x0000006c /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP109 0x0000006d /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP110 0x0000006e /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP111 0x0000006f /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP112 0x00000070 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP113 0x00000071 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP114 0x00000072 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP115 0x00000073 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP116 0x00000074 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP117 0x00000075 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP118 0x00000076 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP119 0x00000077 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP120 0x00000078 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP121 0x00000079 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP122 0x0000007a /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP123 0x0000007b /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP124 0x0000007c /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP125 0x0000007d /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP126 0x0000007e /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP127 0x0000007f /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP128 0x00000080 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP129 0x00000081 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP130 0x00000082 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP131 0x00000083 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP132 0x00000084 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP133 0x00000085 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP134 0x00000086 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP135 0x00000087 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP136 0x00000088 /* RW--V */
|
|
#define NV_XP_PM_CTRL_SEL1_GRP137 0x00000089 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP138 0x0000008a /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP139 0x0000008b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP140 0x0000008c /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP141 0x0000008d /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP142 0x0000008e /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP143 0x0000008f /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP144 0x00000090 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP145 0x00000091 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP146 0x00000092 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP147 0x00000093 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP148 0x00000094 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP149 0x00000095 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP150 0x00000096 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP151 0x00000097 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP152 0x00000098 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP153 0x00000099 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP154 0x0000009a /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP155 0x0000009b /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP156 0x0000009c /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP157 0x0000009d /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP158 0x0000009e /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP159 0x0000009f /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP160 0x000000a0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP161 0x000000a1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP162 0x000000a2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP163 0x000000a3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP164 0x000000a4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP165 0x000000a5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP166 0x000000a6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP167 0x000000a7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP168 0x000000a8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP169 0x000000a9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP170 0x000000aa /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP171 0x000000ab /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP172 0x000000ac /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP173 0x000000ad /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP174 0x000000ae /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP175 0x000000af /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP176 0x000000b0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP177 0x000000b1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP178 0x000000b2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP179 0x000000b3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP180 0x000000b4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP181 0x000000b5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP182 0x000000b6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP183 0x000000b7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP184 0x000000b8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP185 0x000000b9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP186 0x000000ba /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP187 0x000000bb /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP188 0x000000bc /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP189 0x000000bd /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP190 0x000000be /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP191 0x000000bf /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP192 0x000000c0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP193 0x000000c1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP194 0x000000c2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP195 0x000000c3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP196 0x000000c4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP197 0x000000c5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP198 0x000000c6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP199 0x000000c7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP200 0x000000c8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP201 0x000000c9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP202 0x000000ca /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP203 0x000000cb /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP204 0x000000cc /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP205 0x000000cd /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP206 0x000000ce /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP207 0x000000cf /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP208 0x000000d0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP209 0x000000d1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP210 0x000000d2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP211 0x000000d3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP212 0x000000d4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP213 0x000000d5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP214 0x000000d6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP215 0x000000d7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP216 0x000000d8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP217 0x000000d9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP218 0x000000da /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP219 0x000000db /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP220 0x000000dc /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP221 0x000000dd /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP222 0x000000de /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP223 0x000000df /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP224 0x000000e0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP225 0x000000e1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP226 0x000000e2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP227 0x000000e3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP228 0x000000e4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP229 0x000000e5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP230 0x000000e6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP231 0x000000e7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP232 0x000000e8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP233 0x000000e9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP234 0x000000ea /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP235 0x000000eb /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP236 0x000000ec /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP237 0x000000ed /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP238 0x000000ee /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP239 0x000000ef /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP240 0x000000f0 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP241 0x000000f1 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP242 0x000000f2 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP243 0x000000f3 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP244 0x000000f4 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP245 0x000000f5 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP246 0x000000f6 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP247 0x000000f7 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP248 0x000000f8 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP249 0x000000f9 /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP250 0x000000fa /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP251 0x000000fb /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP252 0x000000fc /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP253 0x000000fd /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP254 0x000000fe /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_GRP255 0x000000ff /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_STATIC_PATTERN_99_8_GROUP 0x0000009a /* RW--V */
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#define NV_XP_PM_CTRL_SEL1_STATIC_PATTERN_66_8_GROUP 0x0000009b /* RW--V */
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#define NV_XP_PL_REALIGN_ATTEMPTS_LANE(i) (0x0008E010+(i)*4) /* R--4A */
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#define NV_XP_PL_REALIGN_ATTEMPTS_LANE__SIZE_1 16 /* */
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#define NV_XP_PL_REALIGN_ATTEMPTS_LANE_VAL 8:0 /* R--VF */
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#define NV_XP_PL_EQUALIZATION_4(i) (0x0008E050+(i)*4) /* RW-4A */
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#define NV_XP_PL_EQUALIZATION_4__SIZE_1 16 /* */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_PRECUR 5:0 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_PRECUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_MAINCUR 13:8 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_MAINCUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_POSTCUR 21:16 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_POSTCUR_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_FORCE_PRESETS 23:23 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_FORCE_PRESETS_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_FORCE_PRESETS_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_FORCE_PRESETS_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_PRESET 27:24 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_LOCAL_TX_PRESET_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3 29:29 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_DURING_PHASE3_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3 30:30 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_EXIT_PHASE3_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK 31:31 /* RWIVF */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_4_CYA_OVERRIDE_RCVRLOCK_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_PL_EQUALIZATION_5 0x0008E094 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_5_TOTAL_PHASE2_TIME 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_5_TOTAL_PHASE2_TIME_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_5_TOTAL_PHASE3_TIME 31:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_5_TOTAL_PHASE3_TIME_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_6 0x0008E098 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_6_LONGEST_DFE_TRAIN_TIME 12:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_6_LONGEST_DFE_TRAIN_TIME_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_6_TOTAL_PHASE2_ITERATIONS 24:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_6_TOTAL_PHASE2_ITERATIONS_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_7 0x0008E09C /* R--4R */
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#define NV_XP_PL_EQUALIZATION_7_MAX_EOM_OUT_LANE_0 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_7_MAX_EOM_OUT_LANE_0_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_7_MAX_EOM_OUT_LANE_1 31:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_7_MAX_EOM_OUT_LANE_1_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_8 0x0008E0A0 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_8_MAX_EOM_OUT_LANE_2 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_8_MAX_EOM_OUT_LANE_2_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_8_MAX_EOM_OUT_LANE_3 31:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_8_MAX_EOM_OUT_LANE_3_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_9 0x0008E0A4 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_9_MAX_EOM_OUT_LANE_4 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_9_MAX_EOM_OUT_LANE_4_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_9_MAX_EOM_OUT_LANE_5 31:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_9_MAX_EOM_OUT_LANE_5_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_10 0x0008E0C8 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_10_MAX_EOM_OUT_LANE_6 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_10_MAX_EOM_OUT_LANE_6_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_10_MAX_EOM_OUT_LANE_7 31:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_10_MAX_EOM_OUT_LANE_7_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_11 0x0008E0CC /* R--4R */
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#define NV_XP_PL_EQUALIZATION_11_MAX_EOM_OUT_LANE_8 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_11_MAX_EOM_OUT_LANE_8_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_11_MAX_EOM_OUT_LANE_9 31:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_11_MAX_EOM_OUT_LANE_9_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_12 0x0008E0D0 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_12_MAX_EOM_OUT_LANE_10 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_12_MAX_EOM_OUT_LANE_10_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_12_MAX_EOM_OUT_LANE_11 31:16 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_12_MAX_EOM_OUT_LANE_11_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_13 0x0008E0D4 /* R--4R */
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#define NV_XP_PL_EQUALIZATION_13_MAX_EOM_OUT_LANE_12 15:0 /* R-IVF */
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#define NV_XP_PL_EQUALIZATION_13_MAX_EOM_OUT_LANE_12_INIT 0x00000000 /* R-I-V */
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#define NV_XP_PL_EQUALIZATION_13_MAX_EOM_OUT_LANE_13 31:16 /* R-IVF */
|
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#define NV_XP_PL_EQUALIZATION_13_MAX_EOM_OUT_LANE_13_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_PL_EQUALIZATION_14 0x0008E0A8 /* R--4R */
|
|
#define NV_XP_PL_EQUALIZATION_14_MAX_EOM_OUT_LANE_14 15:0 /* R-IVF */
|
|
#define NV_XP_PL_EQUALIZATION_14_MAX_EOM_OUT_LANE_14_INIT 0x00000000 /* R-I-V */
|
|
#define NV_XP_PL_EQUALIZATION_14_MAX_EOM_OUT_LANE_15 31:16 /* R-IVF */
|
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#define NV_XP_PL_EQUALIZATION_14_MAX_EOM_OUT_LANE_15_INIT 0x00000000 /* R-I-V */
|
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#define NV_XP_L1_SUBSTATE_1 0x0008E0AC /* RW-4R */
|
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#define NV_XP_L1_SUBSTATE_1__PRIV_LEVEL_MASK 0x0008E1BC /* */
|
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#define NV_XP_L1_SUBSTATE_1_CHK_CLKREQ_DEASSERTED_DLY 12:0 /* RWIVF */
|
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#define NV_XP_L1_SUBSTATE_1_CHK_CLKREQ_DEASSERTED_DLY_INIT 0x00000051 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_1_CHK_CLKREQ_DEASSERTED_DLY_3US 0x00000051 /* RW--V */
|
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#define NV_XP_L1_SUBSTATE_1_T_PWR_OFF_DLY 22:13 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_1_T_PWR_OFF_DLY_INIT 0x00000036 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_1_T_PWR_OFF_DLY_2US 0x00000036 /* RW--V */
|
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#define NV_XP_L1_SUBSTATE_1_CHK_CLKREQ_ASSERTED_DLY 31:23 /* RWIVF */
|
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#define NV_XP_L1_SUBSTATE_1_CHK_CLKREQ_ASSERTED_DLY_INIT 0x00000008 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_1_CHK_CLKREQ_ASSERTED_DLY_300NS 0x00000008 /* RW--V */
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#define NV_XP_L1_SUBSTATE_2 0x0008E0B0 /* RW-4R */
|
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#define NV_XP_L1_SUBSTATE_2__PRIV_LEVEL_MASK 0x0008E1BC /* */
|
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#define NV_XP_L1_SUBSTATE_2_T_L1_2_DLY 12:0 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_2_T_L1_2_DLY_INIT 0x0000006C /* RWI-V */
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#define NV_XP_L1_SUBSTATE_2_T_L1_2_DLY_4US 0x0000006C /* RW--V */
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#define NV_XP_L1_SUBSTATE_2_MICROSECOND 20:13 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_2_MICROSECOND_INIT 0x0000001B /* RWI-V */
|
|
#define NV_XP_L1_SUBSTATE_2_MICROSECOND_27 0x0000001B /* RW--V */
|
|
#define NV_XP_L1_SUBSTATE_2_SPARE 31:21 /* RWIVF */
|
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#define NV_XP_L1_SUBSTATE_2_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_3 0x0008E0B4 /* RW-4R */
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#define NV_XP_L1_SUBSTATE_3_L12_WAKEUP_ELAPSED 11:0 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_3_L12_WAKEUP_ELAPSED_INIT 0x00000000 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_4 0x0008E0B8 /* RW-4R */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_1_ENABLED 0:0 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_1_ENABLED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_1_ENABLED_YES 0x00000001 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_1_ENABLED_NO 0x00000000 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_1_ENABLED 1:1 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_1_ENABLED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_1_ENABLED_YES 0x00000001 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_1_ENABLED_NO 0x00000000 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_2_ENABLED 2:2 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_2_ENABLED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_2_ENABLED_YES 0x00000001 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_CYA_ASPM_L1_2_ENABLED_NO 0x00000000 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_2_ENABLED 3:3 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_2_ENABLED_INIT 0x00000001 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_2_ENABLED_YES 0x00000001 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_CYA_PCIPM_L1_2_ENABLED_NO 0x00000000 /* RW--V */
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#define NV_XP_L1_SUBSTATE_4_SPARE 7:4 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_4_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_5 0x0008E0BC /* RW-4R */
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#define NV_XP_L1_SUBSTATE_5__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_L1_SUBSTATE_5_L12_T_REFCLK_ON 12:0 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_5_L12_T_REFCLK_ON_INIT 0x00000002 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_5_L12_T_REFCLK_ON_2US 0x00000002 /* RW--V */
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#define NV_XP_L1_SUBSTATE_5_L11_CLKREQ_TO_SWITCH_REFCLK 20:13 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_5_L11_CLKREQ_TO_SWITCH_REFCLK_INIT 0x00000003 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_5_SPARE 31:21 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_5_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_6 0x0008E0C0 /* RW-4R */
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#define NV_XP_L1_SUBSTATE_6__PRIV_LEVEL_MASK 0x0008E1BC /* */
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#define NV_XP_L1_SUBSTATE_6_CHK_CLKREQ_TIMEOUT 24:0 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_6_CHK_CLKREQ_TIMEOUT_INIT 0x00000546 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_6_CHK_CLKREQ_TIMEOUT_50US 0x00000546 /* RW--V */
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#define NV_XP_L1_SUBSTATE_6_CYA_CHK_CLKREQ_TIMEOUT 25:25 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_6_CYA_CHK_CLKREQ_TIMEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_XP_L1_SUBSTATE_6_CYA_CHK_CLKREQ_TIMEOUT_ENABLED 0x00000001 /* RW--V */
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#define NV_XP_L1_SUBSTATE_6_CYA_CHK_CLKREQ_TIMEOUT_DISABLED 0x00000000 /* RW--V */
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#define NV_XP_L1_SUBSTATE_6_SPARE 31:26 /* RWIVF */
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#define NV_XP_L1_SUBSTATE_6_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_STATUS_0 0x0008E100 /* R--4R */
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#define NV_XP_FUSE_STATUS_0_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_STATUS_1 0x0008E104 /* R--4R */
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#define NV_XP_FUSE_STATUS_1_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_STATUS_2 0x0008E108 /* R--4R */
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#define NV_XP_FUSE_STATUS_2_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_STATUS_3 0x0008E10C /* R--4R */
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#define NV_XP_FUSE_STATUS_3_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_OVERRIDE_0 0x0008E110 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_0__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_0_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_0_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_0_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_1 0x0008E114 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_1__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_1_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_1_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_1_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_2 0x0008E118 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_2__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_2_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_2_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_2_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_3 0x0008E11C /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_3__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_3_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_3_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_3_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_0 0x0008E120 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_0__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_0_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_0_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_0_VALUES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_1 0x0008E124 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_1__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_1_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_1_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_1_VALUES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_2 0x0008E128 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_2__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_2_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_2_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_2_VALUES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_3 0x0008E12C /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_3__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_3_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_3_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_3_VALUES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_STATUS_0 0x0008E130 /* R--4R */
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#define NV_XP_MISC_FUSE_STATUS_0_PADCFG_LUT_R1_0 3:0 /* R--VF */
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#define NV_XP_MISC_FUSE_STATUS_0_PADCFG_LUT_R1_1 7:4 /* R--VF */
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#define NV_XP_MISC_FUSE_STATUS_0_PADCFG_LUT_R2_0 11:8 /* R--VF */
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#define NV_XP_MISC_FUSE_STATUS_0_PADCFG_LUT_R2_1 15:12 /* R--VF */
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#define NV_XP_MISC_FUSE_STATUS_0_PADCFG_LUT_R3_0 19:16 /* R--VF */
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#define NV_XP_MISC_FUSE_STATUS_0_PADCFG_LUT_R3_1 23:20 /* R--VF */
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#define NV_XP_MISC_FUSE_STATUS_0_PEX_PLL_EN_TERM100 24:24 /* R--VF */
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#define NV_XP_MISC_FUSE_STATUS_0_PEX_PLL_EN_TERM100_DIS 0x00000000 /* R---V */
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#define NV_XP_MISC_FUSE_STATUS_0_PEX_PLL_EN_TERM100_EN 0x00000001 /* R---V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0 0x0008E134 /* RWI4R */
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#define NV_XP_MISC_FUSE_OVERRIDE_0__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_0_EN 0:0 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_0_EN_NO_OVERRIDE 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_0_EN_OVERRIDE 0x00000001 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_0_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_1_EN 4:4 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_1_EN_NO_OVERRIDE 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_1_EN_OVERRIDE 0x00000001 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R1_1_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_0_EN 8:8 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_0_EN_NO_OVERRIDE 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_0_EN_OVERRIDE 0x00000001 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_0_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_1_EN 12:12 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_1_EN_NO_OVERRIDE 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_1_EN_OVERRIDE 0x00000001 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R2_1_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_0_EN 19:16 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_0_EN_NO_OVERRIDE 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_0_EN_OVERRIDE 0x0000000f /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_0_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_1_EN 23:20 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_1_EN_NO_OVERRIDE 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_1_EN_OVERRIDE 0x0000000f /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PADCFG_LUT_R3_1_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PEX_PLL_EN_TERM100_EN 24:24 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PEX_PLL_EN_TERM100_EN_NO_OVERRIDE 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PEX_PLL_EN_TERM100_EN_OVERRIDE 0x00000001 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_0_PEX_PLL_EN_TERM100_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0 0x0008E138 /* RWI4R */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R1_0 3:0 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R1_0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R1_1 7:4 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R1_1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R2_0 11:8 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R2_0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R2_1 15:12 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R2_1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R3_0 19:16 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R3_0_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R3_1 23:20 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PADCFG_LUT_R3_1_INIT 0x00000000 /* RWI-V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PEX_PLL_EN_TERM100 24:24 /* RWIVF */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PEX_PLL_EN_TERM100_DIS 0x00000000 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PEX_PLL_EN_TERM100_EN 0x00000001 /* RW--V */
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#define NV_XP_MISC_FUSE_OVERRIDE_VAL_0_PEX_PLL_EN_TERM100_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_STATUS_4 0x0008E140 /* R--4R */
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#define NV_XP_FUSE_STATUS_4_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_STATUS_5 0x0008E144 /* R--4R */
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#define NV_XP_FUSE_STATUS_5_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_STATUS_6 0x0008E148 /* R--4R */
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#define NV_XP_FUSE_STATUS_6_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_STATUS_7 0x0008E14C /* R--4R */
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#define NV_XP_FUSE_STATUS_7_VALUE 31:0 /* R--VF */
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#define NV_XP_FUSE_OVERRIDE_4 0x0008E150 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_4__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_4_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_4_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_4_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_5 0x0008E154 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_5__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_5_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_5_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_5_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_6 0x0008E158 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_6__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_6_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_6_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_6_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_7 0x0008E15C /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_7__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_7_EN 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_7_EN_NONE 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_7_EN_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_4 0x0008E160 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_4__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_4_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_4_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_4_VALUES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_5 0x0008E164 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_5__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_5_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_5_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_5_VALUES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_6 0x0008E168 /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_6__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_6_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_6_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_6_VALUES_INIT 0x00000000 /* RWI-V */
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#define NV_XP_FUSE_OVERRIDE_VAL_7 0x0008E16C /* RWI4R */
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#define NV_XP_FUSE_OVERRIDE_VAL_7__PRIV_LEVEL_MASK 0x0008E1B0 /* */
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#define NV_XP_FUSE_OVERRIDE_VAL_7_VALUES 31:0 /* RWIVF */
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#define NV_XP_FUSE_OVERRIDE_VAL_7_VALUES_ALLZERO 0x00000000 /* RW--V */
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#define NV_XP_FUSE_OVERRIDE_VAL_7_VALUES_INIT 0x00000000 /* RWI-V */
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#endif // __ga102_dev_nv_xp_h__
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