5482 lines
490 KiB
C
5482 lines
490 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
#ifndef __ga102_dev_nvldl_ip_h__
|
|
#define __ga102_dev_nvldl_ip_h__
|
|
/* This file is autogenerated. Do not edit */
|
|
#define NV_NVLDL_TOP 0x00001FFF:0x00000000 /* RW--D */
|
|
#define NV_NVLDL_TX 0x000027FF:0x00002000 /* RW--D */
|
|
#define NV_NVLDL_TXIOBIST 0x00002FFF:0x00002E00 /* RW--D */
|
|
#define NV_NVLDL_RX 0x000037FF:0x00003000 /* RW--D */
|
|
#define NV_NVLDL_RXIOBIST 0x00003FFF:0x00003E00 /* RW--D */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0 0x00000400 /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1 0x00000404 /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2 0x00000408 /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3 0x0000040c /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4 0x00000410 /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5 0x00000414 /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6 0x00000418 /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask6" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7 0x0000041c /* RW-4R */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TOP_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_STATE 0x00000000 /* R--4R */
|
|
#define NV_NVLDL_TOP_LINK_STATE__PRIV_LEVEL_MASK 0x00000410 /* */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE 7:0 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_INIT 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_HWCFG 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_SWCFG 0x00000002 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_ACTIVE 0x00000003 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_FAULT 0x00000004 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_SLEEP 0x00000005 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_AC 0x00000008 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_RCVY_RX 0x0000000a /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_STATE_TRAIN 0x0000000b /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_STATE_AN0_BUSY 12:12 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LINK_STATE_TL_BUSY 13:13 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LINK_STATE_DBG_SUBSTATE 31:16 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN 0x00000004 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN__PRIV_LEVEL_MASK 0x00000400 /* */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_EXE_TIMEOUT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_EXE_TIMEOUT_INIT 0x00000400 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_EXE_TIMEOUT_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_EXE_TIMEOUT_DISABLE 0x000007ff /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_SAFE_TIMEOUT 21:11 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_SAFE_TIMEOUT_INIT 0x000007fe /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_SAFE_TIMEOUT_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_SAFE_TIMEOUT_DISABLE 0x000007ff /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_BASE 30:28 /* RWEUF */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_BASE_32_CLKS 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_BASE_256_CLKS 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_BASE_2048_CLKS 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_BASE_16384_CLKS 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_BASE_131072_CLKS 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_BASE_1048576_CLKS 0x00000005 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_INFINITE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_INFINITE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN_INFINITE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN2 0x00000028 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN2__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN2_FAULT_TIMEOUT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN2_FAULT_TIMEOUT_INIT 0x000007fe /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN2_FAULT_TIMEOUT_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TRAIN2_FAULT_TIMEOUT_DISABLE 0x000007ff /* RW--V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL 0x00000008 /* RW-4R */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_LINK_ACTIVE_MASK 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_LINK_ACTIVE_MASK_DEFAULT 0x00000007 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_LINK_ACTIVE_MASK_RECOVERY_BIT 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_LINK_ACTIVE_MASK_HWCFG_BIT 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_LINK_ACTIVE_MASK_SWCFG_W_DATA_BIT 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_LINK_ACTIVE_MASK_SWCFG_NO_DATA_BIT 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_SUBLINK_ACTIVE_MASK 17:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_SUBLINK_ACTIVE_MASK_DEFAULT 0x00000003 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_SUBLINK_ACTIVE_MASK_SWCFG_W_DATA_BIT 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ACTIVITY_CTRL_SUBLINK_ACTIVE_MASK_SWCFG_NO_DATA_BIT 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_ACTIVITY 0x0000000c /* R--4R */
|
|
#define NV_NVLDL_TOP_LINK_ACTIVITY_BLKACT 2:0 /* R-XVF */
|
|
#define NV_NVLDL_TOP_SUBLINK_ACTIVITY(i) (0x00000010+(i)*0x4) /* R--4A */
|
|
#define NV_NVLDL_TOP_SUBLINK_ACTIVITY__SIZE_1 1 /* */
|
|
#define NV_NVLDL_TOP_SUBLINK_ACTIVITY_0_BLKACT 2:0 /* R-XVF */
|
|
#define NV_NVLDL_TOP_SUBLINK_ACTIVITY_1_BLKACT 10:8 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG 0x00000018 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_BLKLEN 4:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_BLKLEN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_BLKLEN_128 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_ECC_MODE 27:26 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_ECC_MODE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_ECC_MODE_ECC96 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_ECC_MODE_ECC88 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_PAM4_EN 28:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_PAM4_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_PAM4_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_RECAL_FIRST_EN 29:29 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_RECAL_FIRST_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_RECAL_FIRST_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_AC_SAFE_EN 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_AC_SAFE_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_AC_SAFE_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_LINK_EN 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_LINK_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CONFIG_LINK_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A 0x0000001c /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_SAFE 7:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_SAFE_DEFAULT 0x00000010 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_HS 15:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_HS_DEFAULT 0x00000040 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_RX 23:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_RX_DEFAULT 0x0000002d /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_AC 25:24 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_AC_DEFAULT 0x00000002 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_BASE 30:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_BASE_32_CLKS 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_BASE_256_CLKS 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_BASE_2048_CLKS 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_BASE_16384_CLKS 0x00000003 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_BASE_131072_CLKS 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_BASE_1048576_CLKS 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_EN 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_EN_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_A_RCVY_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B 0x00000020 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_TICK_D4 2:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_TICK_D4_DEFAULT 0x00000002 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_CRC 15:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_CRC_DEFAULT 0x00000078 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_RCVY_ON_RXCRC 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_RCVY_ON_RXCRC_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_RCVY_ON_RXCRC_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_EN 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_EN_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TIMEOUT_B_RX_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_CLK_TIMEOUT 0x00000024 /* RW-4R */
|
|
#define NV_NVLDL_TOP_CLK_TIMEOUT__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_CLK_TIMEOUT_SWITCH_TIMEOUT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_CLK_TIMEOUT_SWITCH_TIMEOUT_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_CLK_TIMEOUT_SWITCH_TIMEOUT_SCALE 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TOP_CLK_TIMEOUT_SWITCH_TIMEOUT_SCALE_NONE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ALARM_0 0x00000030 /* RW-4R */
|
|
#define NV_NVLDL_TOP_ALARM_0__PRIV_LEVEL_MASK 0x00000400 /* */
|
|
#define NV_NVLDL_TOP_ALARM_0_VALUE 23:0 /* RWEUF */
|
|
#define NV_NVLDL_TOP_ALARM_0_VALUE_ZERO 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DIV 27:26 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ALARM_0_DIV_ONE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DIV_KILO 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR 31:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_NEVER 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_TXCLK 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_RTFLIT 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_TXFLIT 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_RXFLIT 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_TLTXFLIT 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_TLTXPKT 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_LTSSM_TICK 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_0_DECR_STATS_TICK 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1 0x00000034 /* RW-4R */
|
|
#define NV_NVLDL_TOP_ALARM_1__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_ALARM_1_VALUE 23:0 /* RWEUF */
|
|
#define NV_NVLDL_TOP_ALARM_1_VALUE_ZERO 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DIV 27:26 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ALARM_1_DIV_ONE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DIV_KILO 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR 31:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_NEVER 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_TXCLK 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_RTFLIT 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_TXFLIT 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_RXFLIT 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_TLTXFLIT 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_TLTXPKT 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_LTSSM_TICK 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_ALARM_1_DECR_STATS_TICK 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE 0x00000040 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS 1:0 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_DONE 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_FAULT 0x00000002 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_STATUS_ABORT 0x00000003 /* R---V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION 3:2 /* -WXVF */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION_LTSSM_CHANGE 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_ACTION_LTSSM_FORCE 0x00000003 /* -W--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE 7:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_HWCFG 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_SWCFG 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_ACTIVE 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_RCVY_AC 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_FAULT 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_RCVY_RX 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_SLEEP 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_NEWSTATE_TRAIN 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK 19:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_CHANGE_OLDSTATE_MASK_DONTCARE 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE 0x00000044 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS 1:0 /* R-EVF */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_DONE 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_FAULT 0x00000002 /* R---V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_STATUS_ABORT 0x00000003 /* R---V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION 3:2 /* -WEVF */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_SLSM_CHANGE 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_ACTION_SLSM_FORCE 0x00000003 /* -W--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE 7:4 /* RWEUF */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_HS 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_EIGHTH 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_TRAIN 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_SAFE 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_NEWSTATE_OFF 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK 15:12 /* RWEUF */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK_TX 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_SUBLINK_RX 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK 19:16 /* RWEUF */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_OLDSTATE_MASK_DONTCARE 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN 31:20 /* RWEUF */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_MAXIMUM 0x0000007f /* RW--V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_MINIMUM 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SUBLINK_CHANGE_COUNTDOWN_IMMEDIATE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TEST 0x00000048 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_TEST__PRIV_LEVEL_MASK 0x00000400 /* */
|
|
#define NV_NVLDL_TOP_LINK_TEST_MODE 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TEST_MODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TEST_MODE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TEST_AUTO_HWCFG_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_TEST_AUTO_NVHS_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL 0x0000004c /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON 5:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON_MINIMUM 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_LINK_CHANGE_BASE 9:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_LINK_CHANGE_BASE_1 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_LINK_CHANGE_BASE_3 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_LINK_CHANGE_BASE_7 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_LINK_CHANGE_BASE_15 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON_HS 17:12 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON_HS_DEFAULT 0x00000015 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON_HS_MINIMUM 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON_ONELANE 25:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON_ONELANE_MINIMUM 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINKCHANGE_CTRL_ACT_ON_ONELANE_DEFAULT 0x00000009 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR 0x00000050 /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_INTR_TX_REPLAY 0:0 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_TX_RECOVERY_SHORT 1:1 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_TX_FAULT_RAM 4:4 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_TX_FAULT_INTERFACE 5:5 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_RX_FAULT_DL_PROTOCOL 20:20 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_RX_SHORT_ERROR_RATE 21:21 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_RX_LONG_ERROR_RATE 22:22 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_RX_ILA_TRIGGER 23:23 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_RX_CRC_COUNTER 24:24 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_DOWN 27:27 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_LTSSM_FAULT_UP 28:28 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_LTSSM_PROTOCOL 29:29 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_REQUEST 30:30 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2 0x00000054 /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR_SW2__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_INTR_SW2_TX_REPLAY 0:0 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_TX_RECOVERY_SHORT 1:1 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_RAM 4:4 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_INTERFACE 5:5 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_RX_FAULT_DL_PROTOCOL 20:20 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_RX_SHORT_ERROR_RATE 21:21 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_RX_LONG_ERROR_RATE 22:22 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_RX_ILA_TRIGGER 23:23 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_RX_CRC_COUNTER 24:24 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_DOWN 27:27 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_FAULT_UP 28:28 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_LTSSM_PROTOCOL 29:29 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_SW2_MINION_REQUEST 30:30 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION 0x00000060 /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR_MINION__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_INTR_MINION_TX_REPLAY 0:0 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_TX_RECOVERY_SHORT 1:1 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_TX_FAULT_RAM 4:4 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_TX_FAULT_INTERFACE 5:5 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_RX_FAULT_DL_PROTOCOL 20:20 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_RX_SHORT_ERROR_RATE 21:21 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_RX_LONG_ERROR_RATE 22:22 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_RX_ILA_TRIGGER 23:23 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_RX_CRC_COUNTER 24:24 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_LTSSM_FAULT_DOWN 27:27 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_LTSSM_FAULT_UP 28:28 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_LTSSM_PROTOCOL 29:29 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_MINION_MINION_REQUEST 30:30 /* RWXVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN 0x00000058 /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_STALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN 0x0000005c /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_NONSTALL_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN 0x00000068 /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_REPLAY 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_FAULT_RAM 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_MINION_REQUEST 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONR_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN 0x0000006c /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_REPLAY 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_REPLAY_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_RECOVERY_SHORT 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_RECOVERY_SHORT_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_RECOVERY_SHORT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_RAM 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_RAM_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_RAM_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_INTERFACE 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_INTERFACE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_INTERFACE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_SUBLINK_CHANGE 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_TX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_FAULT_SUBLINK_CHANGE 16:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_FAULT_SUBLINK_CHANGE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_FAULT_SUBLINK_CHANGE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_FAULT_DL_PROTOCOL 20:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_FAULT_DL_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_FAULT_DL_PROTOCOL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_SHORT_ERROR_RATE 21:21 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_SHORT_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_SHORT_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_LONG_ERROR_RATE 22:22 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_LONG_ERROR_RATE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_LONG_ERROR_RATE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_ILA_TRIGGER 23:23 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_ILA_TRIGGER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_ILA_TRIGGER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_CRC_COUNTER 24:24 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_CRC_COUNTER_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_RX_CRC_COUNTER_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_FAULT_DOWN 27:27 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_FAULT_DOWN_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_FAULT_DOWN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_FAULT_UP 28:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_FAULT_UP_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_FAULT_UP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_PROTOCOL 29:29 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_PROTOCOL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_LTSSM_PROTOCOL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_MINION_REQUEST 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_MINION_REQUEST_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_MINIONF_EN_MINION_REQUEST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1 0x00000070 /* RW-4R */
|
|
#define NV_NVLDL_TOP_INTR_CTL1__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_INTR_STALL 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_INTR_STALL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_INTR_STALL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_INTR_NONSTALL 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_INTR_NONSTALL_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_INTR_NONSTALL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_PARITY 2:2 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_PARITY_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_FAULT_ON_PARITY_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_ALLOW_EXIT_FROM_FAULT 3:3 /* RWEVF */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_ALLOW_EXIT_FROM_FAULT_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_INTR_CTL1_LTSSM_ALLOW_EXIT_FROM_FAULT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL 0x00000080 /* -W-4R */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL__PRIV_LEVEL_MASK 0x00000410 /* */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY 2:2 /* -WXVF */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT_CTRL_CLEAR_RECOVERY_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT1 0x0000008c /* R--4R */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT1__PRIV_LEVEL_MASK 0x00000410 /* */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT1_RECOVERY_EVENTS 9:0 /* R-EUF */
|
|
#define NV_NVLDL_TOP_ERROR_COUNT1_RECOVERY_EVENTS_ZERO 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST 0x000000a0 /* R--4R */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST 7:0 /* R-XVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_NOP 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_SW 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_TXENTERPM 0x00000002 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_TXEXITPM 0x00000003 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXRECALSTRT 0x00000004 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXRECALEND 0x00000005 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXENTERPM 0x00000008 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXEXITPM 0x00000009 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXRECALDEADLINE 0x0000000b /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXRDET_FOUND 0x0000000c /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXRDET_TIMEOUT 0x0000000d /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_R4_ANY 0x00000010 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_R4_IN 0x00000011 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_R4_FM 0x00000012 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_R4_SC 0x00000013 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_R4_X3 0x00000014 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXSTATEENTRY 0x00000020 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_RXSTATEEXIT 0x00000021 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_ALARM_0 0x00000030 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_ALARM_1 0x00000031 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_HWRESERVED_F1 0x000000f1 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_HWRESERVED_F3 0x000000f3 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_HWRESERVED_F4 0x000000f4 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_HWRESERVED_F5 0x000000f5 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_HWRESERVED_F6 0x000000f6 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_REQUEST_HWRESERVED_F7 0x000000f7 /* R---V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_GENERIC 31:8 /* R-XVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_LANEDATA 15:8 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_LANEDATA_DEFAULT 0xFF /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_R4ADDR 15:8 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_R4TAG 19:16 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_R4ISWRITE 24:24 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_R4ISCOMPLETION 25:25 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_FROMSTATE 15:8 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_RD_TOSTATE 23:16 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_SWCTRL 0x000000a8 /* RW-4R */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_SWCTRL__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_SWCTRL_REQDATA 15:0 /* RWEUF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_SWCTRL_REQDATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_SWCTRL_REQUEST 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_SWCTRL_REQUEST_PENDING 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_SWCTRL_REQUEST_IDLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL 0x000000ac /* RW-4R */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_SW 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_SW_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_SW_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_TXENTERPM 2:2 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_TXENTERPM_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_TXENTERPM_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_TXEXITPM 3:3 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_TXEXITPM_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_TXEXITPM_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALSTRT 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALSTRT_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALSTRT_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALEND 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALEND_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALEND_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXENTERPM 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXENTERPM_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXENTERPM_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXEXITPM 9:9 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXEXITPM_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXEXITPM_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXSTATE_ENTRYEXIT 10:10 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXSTATE_ENTRYEXIT_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXSTATE_ENTRYEXIT_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALDEADLINE 11:11 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALDEADLINE_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRECALDEADLINE_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRDET_FOUND 12:12 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRDET_FOUND_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRDET_FOUND_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRDET_TIMEOUT 13:13 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRDET_TIMEOUT_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_RXRDET_TIMEOUT_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_ALARM_0 14:14 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_ALARM_0_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_ALARM_0_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_ALARM_1 15:15 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_ALARM_1_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_ALARM_1_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_ANY 16:16 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_ANY_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_ANY_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_IN 17:17 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_IN_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_IN_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_FM 18:18 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_FM_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_FM_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_SC 19:19 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_SC_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_SC_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_X3 20:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_X3_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_R4_X3_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_HWRESERVED_F1 25:25 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_HWRESERVED_F1_EN 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL_DISABLE_HWRESERVED_F1_DIS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL2 0x000000b0 /* RW-4R */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL2__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL2_RXSTATEENTRY_MASK 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL2_RXSTATEENTRY_MASK_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL2_RXSTATEEXIT_MASK 11:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MINION_REQUEST_CTRL2_RXSTATEEXIT_MASK_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MIN 0x00000100 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MIN__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MIN_COUNTER 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MIN_COUNTER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MAX 0x00000104 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MAX__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MAX_COUNTER 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPA_MAX_COUNTER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MIN 0x00000108 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MIN__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MIN_COUNTER 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MIN_COUNTER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MAX 0x0000010c /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MAX__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MAX_COUNTER 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPB_MAX_COUNTER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MIN 0x00000110 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MIN__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MIN_COUNTER 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MIN_COUNTER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MAX 0x00000114 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MAX__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MAX_COUNTER 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_COUNTERPC_MAX_COUNTER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0 0x00000118 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_ENABLE_HSSM 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_ENABLE_HSSM_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_RESTART_TRAINING 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_RESTART_TRAINING_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_ENABLE_LOWER 3:3 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_ENABLE_LOWER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_ENABLE_UPPER 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_ENABLE_UPPER_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_SELECT_LANE 8:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_SELECT_LANE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_SELECT_PHY 9:9 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_SELECT_PHY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_INCR_COUNT 31:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_CTRL0_INCR_COUNT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_FOM_READ_MASK 0x0000011c /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_FOM_READ_MASK__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_FOM_READ_MASK_FOM_MASK 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_FOM_READ_MASK_FOM_MASK_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS0 0x00000124 /* R--4R */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS0_DUMMY 31:0 /* R-EVF */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS0_DUMMY_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS1 0x00000128 /* R--4R */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS1_ERRORPA 0:0 /* R-EVF */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS1_ERRORPA_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS1_ERRORPB 1:1 /* R-EVF */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS1_ERRORPB_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS1_ERRORPC 2:2 /* R-EVF */
|
|
#define NV_NVLDL_TOP_HSSM_STATUS1_ERRORPC_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TOP_HSSM_WAIT_CHECK 0x0000012c /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_WAIT_CHECK__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_WAIT_CHECK_WAIT_CHECK_COUNT 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_WAIT_CHECK_WAIT_CHECK_COUNT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_LOWER 0x00000130 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_LOWER__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_LOWER_VAL 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_LOWER_VAL_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_UPPER 0x00000134 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_UPPER__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_UPPER_VAL 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_TEST_FOM_UPPER_VAL_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMA_ADDR 0x00000138 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMA_ADDR__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMA_ADDR_VAL 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMA_ADDR_VAL_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMB_ADDR 0x0000013c /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMB_ADDR__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMB_ADDR_VAL 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMB_ADDR_VAL_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMC_ADDR 0x00000140 /* RW-4R */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMC_ADDR__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMC_ADDR_VAL 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_HSSM_PARAMC_ADDR_VAL_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_PM 0x00000180 /* RW-4R */
|
|
#define NV_NVLDL_TOP_PM__PRIV_LEVEL_MASK 0x00000410 /* */
|
|
#define NV_NVLDL_TOP_PM_SEL0 7:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP00 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP01 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP02 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP03 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP04 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP05 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP06 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP07 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP08 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP09 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP10 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP11 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP12 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP13 0x0000000d /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP14 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP15 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP16 0x00000010 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP17 0x00000011 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP18 0x00000012 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP19 0x00000013 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP20 0x00000014 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP21 0x00000015 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP22 0x00000016 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP23 0x00000017 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP24 0x00000018 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP25 0x00000019 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP26 0x0000001a /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP27 0x0000001b /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP28 0x0000001c /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP29 0x0000001d /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP30 0x0000001e /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP31 0x0000001f /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL0_GRP255 0x000000ff /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1 15:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP00 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP01 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP02 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP03 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP04 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP05 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP06 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP07 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP08 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP09 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP10 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP11 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP12 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP13 0x0000000d /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP14 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP15 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP16 0x00000010 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP17 0x00000011 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP18 0x00000012 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP19 0x00000013 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP20 0x00000014 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP21 0x00000015 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP22 0x00000016 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP23 0x00000017 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP24 0x00000018 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP25 0x00000019 /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP26 0x0000001a /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP27 0x0000001b /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP28 0x0000001c /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP29 0x0000001d /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP30 0x0000001e /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP31 0x0000001f /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_SEL1_GRP255 0x000000ff /* RW--V */
|
|
#define NV_NVLDL_TOP_PM_ENABLE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_PM_ENABLE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_PM_ENABLE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL 0x00000190 /* RW-4R */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_CLEAR_ALL 0:0 /* -WEVF */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_CLEAR_ALL_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_CLEAR_ALL_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE 31:28 /* RWEUF */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_1_CLKS 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_32_CLKS 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_256_CLKS 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_2048_CLKS 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_16384_CLKS 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_131072_CLKS 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_1048576_CLKS 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_CTRL_TIMER_BASE_DISABLED 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_TOP_STATS_A 0x00000198 /* R--4R */
|
|
#define NV_NVLDL_TOP_STATS_A_COUNT_TX_STATE_NVHS 15:0 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_A_COUNT_TX_STATE_EIGHTH 31:16 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_B 0x0000019c /* R--4R */
|
|
#define NV_NVLDL_TOP_STATS_B_COUNT_TX_STATE_OTHER 15:0 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_C 0x000001a0 /* R--4R */
|
|
#define NV_NVLDL_TOP_STATS_C_DELAY_TX_LP_ENTER 7:0 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_C_DELAY_TX_LP_EXIT 15:8 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_C_DELAY_RX_LP_ENTER 23:16 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_C_DELAY_RX_LP_EXIT 31:24 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_D 0x000001a4 /* R--4R */
|
|
#define NV_NVLDL_TOP_STATS_D_NUM_TX_LP_ENTER 15:0 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_D_NUM_TX_LP_EXIT 31:16 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_E 0x000001a8 /* R--4R */
|
|
#define NV_NVLDL_TOP_STATS_E_DELAY_TX_FB_ENTER 7:0 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_E_DELAY_TX_FB_EXIT 15:8 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_E_DELAY_RX_FB_ENTER 23:16 /* R-XUF */
|
|
#define NV_NVLDL_TOP_STATS_E_DELAY_RX_FB_EXIT 31:24 /* R-XUF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY 0x000001fc /* RW-4R */
|
|
#define NV_NVLDL_TOP_LINK_RCVY__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_EN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_NOLD_ENTRY_EN 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_NOLD_ENTRY_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_NOLD_ENTRY_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_LD_ENTRY_FAULT_EN 2:2 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_LD_ENTRY_FAULT_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_LD_ENTRY_FAULT_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SURPRISE_LD_EN 3:3 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SURPRISE_LD_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SURPRISE_LD_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SQUELCH_FAULT_EN 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SQUELCH_FAULT_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SQUELCH_FAULT_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SAFE_RETRY_ON_FAULT 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SAFE_RETRY_ON_FAULT_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_SAFE_RETRY_ON_FAULT_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_PRI_UPDATE_STABLE_EN 6:6 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_PRI_UPDATE_STABLE_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LINK_RCVY_IMPRV_PRI_UPDATE_STABLE_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A 0x00000200 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SPARE_A__PRIV_LEVEL_MASK 0x00000400 /* */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ALWAYS_TICK 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ALWAYS_TICK_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RESET_RXSEQ_ON_RCVY 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RESET_RXSEQ_ON_RCVY_SURPRISE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RESET_RXSEQ_ON_RCVY_ALWAYS 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RESET_RXSEQ_ON_SLCH 2:2 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RESET_RXSEQ_ON_SLCH_FAULTS 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RESET_RXSEQ_ON_SLCH_ALWAYS 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_EXIT_FROM_SLEEP 3:3 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_EXIT_FROM_SLEEP_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_EXIT_FROM_SLEEP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_FAULT_ON_ERROR_RATE 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_FAULT_ON_ERROR_RATE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RCVY_AC_ON_ERROR_RATE 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RCVY_AC_ON_ERROR_RATE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RXCRC_DURING_FAULT_UP 6:6 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RXCRC_DURING_FAULT_UP_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RXCRC_DURING_FAULT_UP_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS 18:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_INIT 0x00000210 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_RSVD0 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_ECOCHX_UNDO_BUG1752836 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_ECOCHX_UNDO_BUG1772889 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_RSVD3 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_ECOCHX_FIX_BUG1774336 0x00000010 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_ECOCHX_UNDO_BUG1794310_B1 0x00000020 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_RSVD6 0x00000040 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_RSVD7 0x00000080 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_ECOCHX_FIX_BUG1810774_B 0x00000100 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_BITS_ECOCHX_FIX_BUG1857197 0x00000200 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ANYRCVY_IGNORED_INSWCFG_EN 19:19 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ANYRCVY_IGNORED_INSWCFG_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ANYRCVY_IGNORED_INSWCFG_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RCVYAC_IGNORED_INSWCFG_EN 20:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RCVYAC_IGNORED_INSWCFG_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RCVYAC_IGNORED_INSWCFG_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_MASK_ERRORS_IN_SLEEP 21:21 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_MASK_ERRORS_IN_SLEEP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_MASK_ERRORS_IN_SLEEP_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_INTR_MINION_HOLDOFF 23:22 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_INTR_MINION_HOLDOFF_T0 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_INTR_MINION_HOLDOFF_T7 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_INTR_MINION_HOLDOFF_T15 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_INTR_MINION_HOLDOFF_T31 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ACTIVE_SLSM_FAULTS 25:24 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ACTIVE_SLSM_FAULTS_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ACTIVE_SLSM_FAULTS_RCVY_AC 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_ACTIVE_SLSM_FAULTS_FAULT 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_EXE_TIMEOUT_PROTO_ERROR 27:27 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_EXE_TIMEOUT_PROTO_ERROR_DIS 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_EXE_TIMEOUT_PROTO_ERROR_EN 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RXCRC_DURING_RCVY 28:28 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RXCRC_DURING_RCVY_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RXCRC_DURING_RCVY_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RCVY_A_RXWAIT_STATE 29:29 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_RCVY_A_RXWAIT_STATE_ENABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_WAIT_FOR_SAFE 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_WAIT_FOR_SAFE_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_WAIT_FOR_SAFE_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_STICKIER_RECOVERY_INTR 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_A_CYA_LTSSM_STICKIER_RECOVERY_INTR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_B 0x00000204 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SPARE_B__PRIV_LEVEL_MASK 0x00000400 /* */
|
|
#define NV_NVLDL_TOP_SPARE_B_BITS 15:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_B_BITS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_B_BITS_RSVD0 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_B_BITS_RSVD1 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_B_CYA_RPLY_CNTR_EN_INRCVY_EN 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_B_CYA_RPLY_CNTR_EN_INRCVY_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_B_CYA_RPLY_CNTR_EN_INRCVY_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_SPARE_B_CYA_RPLY_CNTR_EN_INALLSTATE_EN 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SPARE_B_CYA_RPLY_CNTR_EN_INALLSTATE_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SPARE_B_CYA_RPLY_CNTR_EN_INALLSTATE_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LTSSMDBG_A 0x00000210 /* R--4R */
|
|
#define NV_NVLDL_TOP_LTSSMDBG_A__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_LTSSMDBG_A_LAST_PROTOERRID 3:0 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LTSSMDBG_A_TIMEOUTID 7:4 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LTSSMDBG_A_HOLDS 15:12 /* R-XVF */
|
|
#define NV_NVLDL_TOP_LTSSMDBG_A_DBG_SUBSTATE 31:16 /* R-XVF */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG 0x00000280 /* RW-4R */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_TIMEOUT 17:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_TIMEOUT_INIT 0x00001000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_SETUP_CLOCKS 22:20 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_SETUP_CLOCKS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_WAIT_CLOCKS 26:24 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_WAIT_CLOCKS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_HOLD_CLOCKS 29:27 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_HOLD_CLOCKS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_FS_ACTION 30:30 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_FS_ACTION_ERROR 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_FS_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_RESET_ACTION 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_RESET_ACTION_ERROR 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_MASTER_SMCONFIG_RESET_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_ASYNC_MASTER_CLOCK_GATING 0x00000284 /* RW-4R */
|
|
#define NV_NVLDL_TOP_ASYNC_MASTER_CLOCK_GATING__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_ASYNC_MASTER_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ASYNC_MASTER_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_ASYNC_MASTER_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LTSSM_DELAY 0x00000288 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LTSSM_DELAY__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_LTSSM_DELAY_RCVY_AC_SAFE2HS 7:0 /* RWEUF */
|
|
#define NV_NVLDL_TOP_LTSSM_DELAY_RCVY_AC_SAFE2HS_MINIMUM 0x00000020 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LTSSM_DELAY_RX_ACTIVE 15:8 /* RWEUF */
|
|
#define NV_NVLDL_TOP_LTSSM_DELAY_RX_ACTIVE_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_ILA_SLCG 0x0000028c /* RW-4R */
|
|
#define NV_NVLDL_TOP_ILA_SLCG__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_ILA_SLCG_ILA_SLCG 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_ILA_SLCG_ILA_SLCG_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TOP_ILA_SLCG_ILA_SLCG_DISABLED 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_WARM 0x00001fc0 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_WARM_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_COLD 0x00001fc4 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_COLD_DATA 31:0 /* RWIVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK0 0x00001fd0 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00000400 /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1 0x00001fd4 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00000404 /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK2 0x00001fd8 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00000408 /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK3 0x00001fdc /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK4 0x00001fe0 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00000410 /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK5 0x00001fe4 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00000414 /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK6 0x00001fe8 /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00000418 /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK7 0x00001fec /* RW-4R */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000041c /* */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1 0x00001000 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LA_CR_1__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_LA_CR_1_MASTER_EN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_MASTER_EN_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_MASTER_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_RELATIVE_TIMESTAMP_SIZE 4:1 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_RELATIVE_TIMESTAMP_SIZE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_ABSOLUTE_TIMESTAMPS_EN 5:5 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_ABSOLUTE_TIMESTAMPS_EN_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_ABSOLUTE_TIMESTAMPS_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET 6:6 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET_INIT 0x00000000 /* */
|
|
#define NV_NVLDL_TOP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET_DONE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_ABSOLUTE_TIME_COUNT_RESET_PENDING 0x00000001 /* -W--T */
|
|
#define NV_NVLDL_TOP_LA_CR_1_START_LOGGING 7:7 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_START_LOGGING_DONE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_START_LOGGING_PENDING 0x00000001 /* -W--T */
|
|
#define NV_NVLDL_TOP_LA_CR_1_STOP_LOGGING 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_STOP_LOGGING_DONE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_STOP_LOGGING_PENDING 0x00000001 /* -W--T */
|
|
#define NV_NVLDL_TOP_LA_CR_1_PROLOGUE_MAX_SIZE 18:9 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_PROLOGUE_MAX_SIZE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_PROLOGUE_WRAP_AROUND_MODE 19:19 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_1_PROLOGUE_WRAP_AROUND_MODE_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_1_PROLOGUE_WRAP_AROUND_MODE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LA_CR_2 0x00001004 /* RW-4R */
|
|
#define NV_NVLDL_TOP_LA_CR_2__PRIV_LEVEL_MASK 0x0000040c /* */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_WRAP_AROUND_MODE 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_WRAP_AROUND_MODE_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_WRAP_AROUND_MODE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_FULL 1:1 /* R--VF */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_READ_ADDRESS 11:2 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_READ_ADDRESS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_WRITE_POINTER 21:12 /* R--VF */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_READ_MODE 22:22 /* RWEVF */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_READ_MODE_TRACE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TOP_LA_CR_2_RAM_READ_MODE_SAMPLE_INTERVALS 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TOP_LA_CR_2_LA_STATUS 24:24 /* R-EVF */
|
|
#define NV_NVLDL_TOP_LA_CR_2_LA_STATUS_STOPPED 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TOP_LA_CR_2_LA_STATUS_RUNNING 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TOP_LA_CR_2_PROLOGUE_FULL 26:26 /* R--VF */
|
|
#define NV_NVLDL_TOP_LA_CR_3 0x00001008 /* R--4R */
|
|
#define NV_NVLDL_TOP_LA_CR_3_PROLOGUE_WRITE_POINTER 9:0 /* R--VF */
|
|
#define NV_NVLDL_TOP_LA_EVENT_LOG_DW0 0x0000100c /* R--4R */
|
|
#define NV_NVLDL_TOP_LA_EVENT_LOG_DW0_DATA 31:0 /* R--VF */
|
|
#define NV_NVLDL_TOP_LA_EVENT_LOG_DW1 0x00001010 /* R--4R */
|
|
#define NV_NVLDL_TOP_LA_EVENT_LOG_DW1_DATA 31:0 /* R--VF */
|
|
#define NV_NVLDL_TOP_LA_EVENT_LOG_DW2 0x00001014 /* R--4R */
|
|
#define NV_NVLDL_TOP_LA_EVENT_LOG_DW2_DATA 15:0 /* R--VF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0 0x00002700 /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1 0x00002704 /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2 0x00002708 /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3 0x0000270c /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4 0x00002710 /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5 0x00002714 /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6 0x00002718 /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask6" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7 0x0000271c /* RW-4R */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_TX_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX 0x00002000 /* RW-4R */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX_HOLD 15:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX_HOLD_INIT 0x00000018 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX_HOLD_MINIMUM 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX_SETUP 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX_SETUP_INIT 0x00000018 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL0_TX_SETUP_MINIMUM 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX 0x00002004 /* RW-4R */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_ALIGN_CNT 2:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_ALIGN_CNT_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_SKIP_TOGGLE_CONST 3:3 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_SKIP_TOGGLE_CONST_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_SKIP_TOGGLE_CONST_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_DEBUG_ENABLE 4:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_DEBUG_ENABLE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_DEBUG_ENABLE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_TOGGLE_MORE 15:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_TOGGLE_MORE_INIT 0x00000032 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_TOGGLE_MORE_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_TOGGLE 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_TOGGLE_INIT 0x00000014 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL1_TX_TOGGLE_MINIMUM 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL2_TX 0x00002008 /* RW-4R */
|
|
#define NV_NVLDL_TX_SAFE_CTRL2_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SAFE_CTRL2_TX_INIT_TRAIN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL2_TX_INIT_TRAIN_NOT_DONE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL2_TX_INIT_TRAIN_DONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX 0x00002010 /* RW-4R */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX_OFF2SAFE_LD_MORE 15:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX_OFF2SAFE_LD_MORE_INIT 0x00000064 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX_OFF2SAFE_LD_MORE_MINIMUM 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX_CONST_MORE 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX_CONST_MORE_INIT 0x00000064 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL4_TX_CONST_MORE_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX 0x00002014 /* RW-4R */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_A 1:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_A_LANE_0 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_A_LANE_1 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_A_LANE_2 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_A_LANE_3 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_B 5:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_B_LANE_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_B_LANE_1 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_B_LANE_2 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_ILA_LANE_SELECT_B_LANE_3 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_SAFE2HS_LD_MORE 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_SAFE2HS_LD_MORE_INIT 0x00000014 /* RWE-V */
|
|
#define NV_NVLDL_TX_SAFE_CTRL5_TX_SAFE2HS_LD_MORE_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN0_TX 0x00002018 /* RW-4R */
|
|
#define NV_NVLDL_TX_TRAIN0_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_INIT 0x00000260 /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL_INIT 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_LEN_0_SCL_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN0_TX_PRBS_INFINITE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX 0x0000201c /* RW-4R */
|
|
#define NV_NVLDL_TX_TRAIN1_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_INIT 0x00000631 /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_L2_EXIT 0x000006c1 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_L2_EXIT_ISSC 0x000006ea /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_SCL_INIT 0x00000013 /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_SCL_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_PRBS_LEN_1_SCL_L2_EXIT 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_RMT_CDR_LOCK_LEN 26:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_RMT_CDR_LOCK_LEN_INIT 0x0000021a /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_RMT_CDR_LOCK_LEN_SCL 31:27 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_RMT_CDR_LOCK_LEN_SCL_INIT 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN1_TX_RMT_CDR_LOCK_LEN_SCL_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN2_TX 0x00002034 /* RW-4R */
|
|
#define NV_NVLDL_TX_TRAIN2_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_LEN 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_LEN_INIT 0x000001fb /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_LEN_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_LEN_SCL_INIT 0x0000000e /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_LEN_SCL_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_INFINITE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_INFINITE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TRAIN2_TX_TRAIN_INFINITE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX 0x00002020 /* RW-4R */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_HS_SYMALIGN_CNT 7:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_HS_SYMALIGN_CNT_INIT 0x000000ff /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_HS_SYMALIGN_CNT_MINIMUM 0x00000030 /* RW--V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_DEAD_CNT 15:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_DEAD_CNT_INIT 0x0000002c /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_DEAD_CNT_MINIMUM 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_LINKDET_CNT 26:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_LINKDET_CNT_INIT 0x000005eb /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_LINKDET_CNT_SCL 31:27 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_LINKDET_CNT_SCL_INIT 0x00000005 /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL_TX_LINKDET_CNT_SCL_MINIMUM 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX 0x00002038 /* RW-4R */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX_NO_LINKDET 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX_NO_LINKDET_INIT 0x00000100 /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX_NO_LINKDET_SCALE 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX_NO_LINKDET_SCALE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX_ALIGN_DONE_COUNTDOWN 27:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL2_TX_ALIGN_DONE_COUNTDOWN_INIT 0x00000020 /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL3_TX 0x0000203c /* RW-4R */
|
|
#define NV_NVLDL_TX_SLSM_CTRL3_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SLSM_CTRL3_TX_OFF2SAFE_SAFEDET_CNT 9:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL3_TX_OFF2SAFE_SAFEDET_CNT_INIT 0x00000064 /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_CTRL3_TX_HS2SAFE_SAFEDET_CNT 19:10 /* RWEVF */
|
|
#define NV_NVLDL_TX_SLSM_CTRL3_TX_HS2SAFE_SAFEDET_CNT_INIT 0x00000064 /* RWE-V */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX 0x00002024 /* R--4R */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE 3:0 /* R-XVF */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_SUBSTATE_STABLE 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE 7:4 /* R-XVF */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_HS 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_EIGHTH 0x00000004 /* R---V */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
|
|
#define NV_NVLDL_TX_SLSM_STATUS_TX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL 0x00002028 /* RW-4R */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL__PRIV_LEVEL_MASK 0x00002704 /* */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* RWEVF */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_CONST_DET_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_CONST_DET_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* RWEVF */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_CLK_SWITCH_ERR 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_CLK_SWITCH_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TXSLSM_ERR_CNTL_CLK_SWITCH_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TXSLSM_TIMEOUT_0 0x0000202c /* RW-4R */
|
|
#define NV_NVLDL_TX_TXSLSM_TIMEOUT_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_TXSLSM_TIMEOUT_0_OFF2SAFE_LINK_DET_CNT 15:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TXSLSM_TIMEOUT_0_OFF2SAFE_LINK_DET_CNT_INIT 0x00001000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TXSLSM_TIMEOUT_0_CONST_DET_CNT 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_TXSLSM_TIMEOUT_0_CONST_DET_CNT_INIT 0x00001000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_TX 0x00002030 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRAM_TX__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SCRAM_TX_HS_SCRAM_CNT 29:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRAM_TX_HS_SCRAM_CNT_INIT 0x00000048 /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_TX_HS_SCRAM_CNT_MINIMUM 0x00000034 /* RW--V */
|
|
#define NV_NVLDL_TX_SCRAM_TX_HS_SCRAM_INFINITE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRAM_TX_HS_SCRAM_INFINITE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_TX_HS_SCRAM_INFINITE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0 0x00002080 /* RW-4R */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_SCRAM_CNT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_SCRAM_CNT_INIT 0x00000048 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_SCRAM_CNT_SCALE 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_SCRAM_CNT_SCALE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_ALIGN_CNT 26:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_ALIGN_CNT_INIT 0x00000033 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_ALIGN_CNT_SCALE 31:27 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_0_HS2E_ALIGN_CNT_SCALE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1 0x00002084 /* RW-4R */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_SCRAM_CNT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_SCRAM_CNT_INIT 0x00000218 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_SCRAM_CNT__PROD_ISSC 0x00000624 /* RW--V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_SCRAM_CNT_SCALE 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_SCRAM_CNT_SCALE_INIT 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_SCRAM_CNT_SCALE__PROD_ISSC 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_ALIGN_CNT 26:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_ALIGN_CNT_INIT 0x000000ff /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_ALIGN_CNT_SCALE 31:27 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_1_E2HS_ALIGN_CNT_SCALE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2 0x00002088 /* RW-4R */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2_E2S_LINKDET_CNT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2_E2S_LINKDET_CNT_INIT 0x000005eb /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2_E2S_LINKDET_CNT_SCALE 15:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2_E2S_LINKDET_CNT_SCALE_INIT 0x00000005 /* RWE-V */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2_PSAVE_STEP 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_EIGHTH_TX_2_PSAVE_STEP_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_0 0x00002040 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_0_INIT 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_0_INIT_INIT 0x003d0b37 /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_0_INIT_ZERO 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_1 0x00002044 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_1_INIT 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_1_INIT_INIT 0x004d1440 /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_1_INIT_ZERO 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_2 0x00002048 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_2__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_2_INIT 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_2_INIT_INIT 0x0037f649 /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_2_INIT_ZERO 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_3 0x0000204c /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_3__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_3_INIT 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_3_INIT_INIT 0x0012c5df /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRAM_LFSR_3_INIT_ZERO 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_0 0x00002060 /* RW-4R */
|
|
#define NV_NVLDL_TX_ERRINJ_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_0_RAND_TIME_SEED 30:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_0_RAND_TIME_SEED_INIT 0x63232b31 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_0_RAND_TIME_SEED_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_0_ENABLE_INJECTION 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_0_ENABLE_INJECTION_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_0_ENABLE_INJECTION_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_1 0x00002064 /* RW-4R */
|
|
#define NV_NVLDL_TX_ERRINJ_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_1_RAND_DATA_SEED 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_1_RAND_DATA_SEED_INIT 0x00230c47 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_1_RAND_DATA_SEED_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_2 0x00002068 /* RW-4R */
|
|
#define NV_NVLDL_TX_ERRINJ_2__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_2_INJECT_PERIOD 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_2_INJECT_PERIOD_INIT 0x00001000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_2_INJECT_PERIODIC 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_2_INJECT_PERIODIC_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3 0x0000206c /* RW-4R */
|
|
#define NV_NVLDL_TX_ERRINJ_3__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_3_BURST_OFFSET 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_3_BURST_OFFSET_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_BURST_LENGTH 13:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_3_BURST_LENGTH_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_BURST_OVERRIDE 15:15 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_3_BURST_OVERRIDE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_MAX_BURST_LENGTH 20:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_3_MAX_BURST_LENGTH_INIT 0x00000019 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_MAX_BURST_ENABLE 22:22 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_3_MAX_BURST_ENABLE_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_MAX_BURST_ENABLE_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_OVERRIDE 23:23 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_OVERRIDE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_OVERRIDE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_MASK 27:24 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_MASK_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_MASK_LANE_0 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_MASK_LANE_1 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_MASK_LANE_2 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_MASK_LANE_3 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_3_LANE_MASK_ALL 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_4 0x00002070 /* RW-4R */
|
|
#define NV_NVLDL_TX_ERRINJ_4__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_4_MIN_TIME_BETWEEN_ERRORS 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_4_MIN_TIME_BETWEEN_ERRORS_INIT 0x00000011 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_5 0x00002074 /* RW-4R */
|
|
#define NV_NVLDL_TX_ERRINJ_5__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_5_TIME_BIT_MASK 22:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_5_TIME_BIT_MASK_INIT 0x0000ffff /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_5_TIMESCALE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_5_TIMESCALE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_5_TIMESCALE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_6 0x00002078 /* RW-4R */
|
|
#define NV_NVLDL_TX_ERRINJ_6__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_6_MAX_INJECT 30:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_6_MAX_INJECT_INIT 0x7fffffff /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_6_MAX_INJECT_ENABLE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_ERRINJ_6_MAX_INJECT_ENABLE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERRINJ_6_MAX_INJECT_ENABLE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_ERRINJ_7 0x0000207c /* R--4R */
|
|
#define NV_NVLDL_TX_ERRINJ_7__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_ERRINJ_7_ERRORS_INJECTED 30:0 /* R-EVF */
|
|
#define NV_NVLDL_TX_ERRINJ_7_ERRORS_INJECTED_NONE 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS 0x00002090 /* RW-4R */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS__PRIV_LEVEL_MASK 0x00002704 /* */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS_REQ 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS_REQ_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS_REQ_ON 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS_REQ_ALL_ON 0x0000000f /* RWE-V */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS_RDY 31:31 /* R-EVF */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS_RDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TX_PSAVE_SW_CTRL_STS_RDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS 0x00002094 /* RW-4R */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS__PRIV_LEVEL_MASK 0x00002700 /* */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS_REQ 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS_REQ_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS_REQ_ON 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS_REQ_ALL_ON 0x0000000f /* RWE-V */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS_RDY 31:31 /* R-EVF */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS_RDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TX_PSAVE_UCODE_CTRL_STS_RDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS 0x00002098 /* R--4R */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_REQ 3:1 /* R-EVF */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_REQ_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_REQ_ON 0x00000007 /* R---V */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_FIRST_RECAL 30:30 /* R-EVF */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_FIRST_RECAL_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_FIRST_RECAL_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_RDY 31:31 /* R-EVF */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_RDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_TX_PSAVE_HW_CTRL_STS_RDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_TX_TL_CREDITS 0x00002100 /* RW-4R */
|
|
#define NV_NVLDL_TX_TL_CREDITS__PRIV_LEVEL_MASK 0x00002704 /* */
|
|
#define NV_NVLDL_TX_TL_CREDITS_MAX 8:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TL_CREDITS_MAX_DEFAULT 0x000001d6 /* RWE-V */
|
|
#define NV_NVLDL_TX_TL_CREDITS_MAX_MAXIMUM 0x000001df /* RW--V */
|
|
#define NV_NVLDL_TX_TL_CREDITS_INTF 24:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_TL_CREDITS_INTF_DEFAULT 0x0000002d /* RWE-V */
|
|
#define NV_NVLDL_TX_TL_CREDITS_INTF_MAXIMUM 0x000001df /* RW--V */
|
|
#define NV_NVLDL_TX_TL_INTF 0x00002104 /* RW-4R */
|
|
#define NV_NVLDL_TX_TL_INTF__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_TL_INTF_CYA_STOMP_ON_PARITY 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TL_INTF_CYA_STOMP_ON_PARITY_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT 0x00002108 /* RW-4R */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT__PRIV_LEVEL_MASK 0x00002704 /* */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT_HS 9:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT_HS_DEFAULT 0x000001fe /* RWE-V */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT_HS_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT_LS 29:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT_LS_DEFAULT 0x00000100 /* RWE-V */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT_LS_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_REPLAY_TIMEOUT_LS_TX_HS 0x00003000 /* RW--V */
|
|
#define NV_NVLDL_TX_REPLAY_THRESHOLD 0x0000210c /* RW-4R */
|
|
#define NV_NVLDL_TX_REPLAY_THRESHOLD__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_REPLAY_THRESHOLD_RECOVERY_TO_ACTIVE 15:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_REPLAY_THRESHOLD_RECOVERY_TO_ACTIVE_DEFAULT 0x00000005 /* RWE-V */
|
|
#define NV_NVLDL_TX_REPLAY_THRESHOLD_RECOVERY_TO_FAULT 23:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_REPLAY_THRESHOLD_RECOVERY_TO_FAULT_DEFAULT 0x00000007 /* RWE-V */
|
|
#define NV_NVLDL_TX_REPLAY_STATUS 0x00002110 /* R--4R */
|
|
#define NV_NVLDL_TX_REPLAY_STATUS__PRIV_LEVEL_MASK 0x00002718 /* */
|
|
#define NV_NVLDL_TX_REPLAY_STATUS_COUNT 7:0 /* R-XVF */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND 0x00002140 /* RW-4R */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_REQUEST 2:0 /* -WEUF */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_REQUEST_NOP 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_REQUEST_READ 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_REQUEST_WRITE 0x00000002 /* -W--V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_REQUEST_SWAP 0x00000003 /* -W--V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_READY 3:3 /* R-EVF */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_READY_NO 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_READY_YES 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_WADDR 14:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_WADDR_II 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_WADDR_SC 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_RADDR 22:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_RADDR_II 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_RADDR_SC 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_COMPLETE 24:24 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_COMPLETE_BUSY_NOP 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_COMMAND_COMPLETE_READY_CLEAR 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL 0x00002148 /* RW-4R */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_RETRY_TIMEOUT 5:0 /* RWEUF */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_RETRY_TIMEOUT_INIT 0x00000006 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_RETRY_TIMEOUT_NEVER 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_RETRY_TIMEBASE 7:6 /* RWEUF */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_RETRY_TIMEBASE_X1 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_RETRY_TIMEBASE_X64 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_RETRY_TIMEBASE_X4096 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_FORCE_COMMAND_TAG 10:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_FORCE_COMMAND_TAG_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_ABORT_COMMAND_TX 12:12 /* -WEVF */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_ABORT_COMMAND_TX_NOP 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_TX_R4TX_CONTROL_ABORT_COMMAND_TX_ABORT 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TX_R4TX_WDATA0 0x00002150 /* RW-4R */
|
|
#define NV_NVLDL_TX_R4TX_WDATA0__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_R4TX_WDATA0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_WDATA0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_WDATA1 0x00002154 /* RW-4R */
|
|
#define NV_NVLDL_TX_R4TX_WDATA1__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_R4TX_WDATA1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_WDATA1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_RDATA0 0x00002158 /* RW-4R */
|
|
#define NV_NVLDL_TX_R4TX_RDATA0__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_R4TX_RDATA0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_RDATA0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_R4TX_RDATA1 0x0000215c /* RW-4R */
|
|
#define NV_NVLDL_TX_R4TX_RDATA1__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_R4TX_RDATA1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_R4TX_RDATA1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_AN0_A 0x00002200 /* RW-4R */
|
|
#define NV_NVLDL_TX_AN0_A__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_AN0_A_REDUNDANCY_HS 2:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_AN0_A_REDUNDANCY_HS_DEFAULT 0x00000005 /* RWE-V */
|
|
#define NV_NVLDL_TX_AN0_A_REDUNDANCY_LS 6:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_AN0_A_REDUNDANCY_LS_DEFAULT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_AN0_A_START_MAXPKTLEN_PKTS 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_AN0_A_START_MAXPKTLEN_PKTS_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_AN0_A_START_MAXPKTLEN_PKTS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_AN0_B 0x00002204 /* RW-4R */
|
|
#define NV_NVLDL_TX_AN0_B__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_AN0_B_INJECT_DATA_102_71 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_AN0_B_INJECT_DATA_102_71_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_AN0_C 0x00002208 /* RW-4R */
|
|
#define NV_NVLDL_TX_AN0_C__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_AN0_C_INJECT_DATA_70_39 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_AN0_C_INJECT_DATA_70_39_INIT 0x0000cafe /* RWE-V */
|
|
#define NV_NVLDL_TX_AN0_D 0x0000220c /* RW-4R */
|
|
#define NV_NVLDL_TX_AN0_D__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_AN0_D_INJECT_DATA_38_20 18:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_AN0_D_INJECT_DATA_38_20_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_AN0_D_INJECT_DATA_38_20_AN0WRITE 0x00000014 /* RW--V */
|
|
#define NV_NVLDL_TX_AN0_D_INJECT_CTRL 29:28 /* -WEVF */
|
|
#define NV_NVLDL_TX_AN0_D_INJECT_CTRL_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_TX_AN0_D_INJECT_CTRL_INJECT_ONE 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TX_AN0_D_INJECT_CTRL_INJECT_REDUNDANT 0x00000002 /* -W--V */
|
|
#define NV_NVLDL_TX_TXLANECRC 0x0000221c /* RW-4R */
|
|
#define NV_NVLDL_TX_TXLANECRC__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_TXLANECRC_ENABLE 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TXLANECRC_ENABLE_DIS 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TXLANECRC_ENABLE_EN 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TXLANECRC_FREQUENCY 19:16 /* RWEUF */
|
|
#define NV_NVLDL_TX_TXLANECRC_FREQUENCY_256 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_TXLANECRC_FREQUENCY_2048 0x0000000b /* RWE-V */
|
|
#define NV_NVLDL_TX_TXLANECRC_FREQUENCY_4096 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_TXLANECRC_FREQUENCY_MAX 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_TX_TXLANECRC_FREQUENCY_MIN 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER 0x00002230 /* RW-4R */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_INJECT_CTRL 0:0 /* RWEUF */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_INJECT_CTRL_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_INJECT_CTRL_INJECT_ONE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_COLLISION_MODE 3:3 /* RWEVF */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_COLLISION_MODE_FIRST 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_COLLISION_MODE_OR 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_MAX_RATE_EXP 6:4 /* RWEUF */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_MAX_RATE_EXP_32 0x00000005 /* RWE-V */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_MANUAL_VALUE 27:24 /* -WEUF */
|
|
#define NV_NVLDL_TX_TX_ILA_RTRIGGER_MANUAL_VALUE_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_TX_TX_SLCG 0x00002234 /* RW-4R */
|
|
#define NV_NVLDL_TX_TX_SLCG__PRIV_LEVEL_MASK 0x00002704 /* */
|
|
#define NV_NVLDL_TX_TX_SLCG_TX_SLCG 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_TX_SLCG_TX_SLCG_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_TX_SLCG_TX_SLCG_DISABLED 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_ERROR_COUNT_CTRL 0x00002280 /* -W-4R */
|
|
#define NV_NVLDL_TX_ERROR_COUNT_CTRL__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY 8:8 /* -WXVF */
|
|
#define NV_NVLDL_TX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TX_ERROR_COUNT4 0x00002288 /* R--4R */
|
|
#define NV_NVLDL_TX_ERROR_COUNT4__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_ERROR_COUNT4_REPLAY_EVENTS 31:16 /* R-EUF */
|
|
#define NV_NVLDL_TX_ERROR_COUNT4_REPLAY_EVENTS_ZERO 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TX_DBG_A 0x00002300 /* R--4R */
|
|
#define NV_NVLDL_TX_DBG_A__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_DBG_A_TL_WATERMARK 8:0 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_A_CRED 20:12 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_A_PEND_RTN 31:23 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_B 0x00002304 /* R--4R */
|
|
#define NV_NVLDL_TX_DBG_B__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_DBG_B_TAIL 8:0 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_B_HEAD 20:12 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_B_REPLAY 30:22 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_C 0x00002308 /* R--4R */
|
|
#define NV_NVLDL_TX_DBG_C__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_DBG_C_TAIL 8:0 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_C_HEAD 20:12 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_C_UNSENT 30:22 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_D 0x0000230c /* R--4R */
|
|
#define NV_NVLDL_TX_DBG_D__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_DBG_D_TL_CREDITS 8:0 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_D_DL_CREDITS 20:12 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_D_R_CREDITS 30:22 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_E 0x00002310 /* R--4R */
|
|
#define NV_NVLDL_TX_DBG_E__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_DBG_E_R_CREDITS 8:0 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_E_DL_CREDITS 20:12 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_E_DL_WATERMARK 30:22 /* R-XVF */
|
|
#define NV_NVLDL_TX_DBG_F 0x00002314 /* -W-4R */
|
|
#define NV_NVLDL_TX_DBG_F__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_DBG_F_FORCE_TIMEOUT 0:0 /* -WXVF */
|
|
#define NV_NVLDL_TX_DBG_F_FORCE_TIMEOUT_NOP 0x00000000 /* -W--V */
|
|
#define NV_NVLDL_TX_DBG_F_FORCE_TIMEOUT_DOIT 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TX_CYA_A 0x00002380 /* RW-4R */
|
|
#define NV_NVLDL_TX_CYA_A__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_CYA_A_AN0REPLAY_BASE 6:0 /* RWEUF */
|
|
#define NV_NVLDL_TX_CYA_A_AN0REPLAY_BASE_INIT 0x0000001f /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAYCTR_CONDITION 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAYCTR_CONDITION_USE_UNACKED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAYCTR_CONDITION_USE_UNEMPTY 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_PREEMPTABLE_AN0 9:9 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_PREEMPTABLE_AN0_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAY_ON_HOLDTL_EXIT 10:10 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAY_ON_HOLDTL_EXIT_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAY_ON_HOLDTL_EXIT_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_ABORT_R4 11:11 /* -WEVF */
|
|
#define NV_NVLDL_TX_CYA_A_ABORT_R4_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_TX_CYA_A_ABORT_R4_DOIT 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_TX_CYA_A_R4_RETRY_INCR_REPLAY_CNT 12:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_R4_RETRY_INCR_REPLAY_CNT_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_R4_RETRY_INCR_REPLAY_CNT_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_R4_RETRY_ON_RCVY_EXIT 13:13 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_R4_RETRY_ON_RCVY_EXIT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_R4_RETRY_ON_RCVY_EXIT_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_ALLOW_RMT_TX_ALL_LANES_PD 14:14 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_ALLOW_RMT_TX_ALL_LANES_PD_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_ALLOW_RMT_TX_ALL_LANES_PD_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE 30:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE_ECOCHX_UNDO_BUG1597904 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE_ECOCHX_UNDO_BUG1755091 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE_ECOCHX_UNDO_BUG1791964 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE_ECOCHX_UNDO_BUG1847900 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE_ECOCHX_UNDO_BUG2464235_A 0x00000010 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_SPARE_ECOCHX_UNDO_BUG2464235_B 0x00000020 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAYCTR_CONDITION2 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAYCTR_CONDITION2_DONT_USE_R4 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_A_REPLAYCTR_CONDITION2_USE_R4 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_B 0x00002384 /* RW-4R */
|
|
#define NV_NVLDL_TX_CYA_B__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_CYA_B_MAX_CRED_RETURN 5:0 /* RWEUF */
|
|
#define NV_NVLDL_TX_CYA_B_MAX_CRED_RETURN_INIT 0x0000003f /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_B_CRED_RETURN_ON_TL_HOLD 8:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_B_CRED_RETURN_ON_TL_HOLD_ALLOW 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_B_CRED_RETURN_ON_TL_HOLD_BLOCK 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_B_SAFE2SAFE_DIS 9:9 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_B_SAFE2SAFE_DIS_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_B_SAFE2SAFE_DIS_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_B_DL_FLUSH_WAIT 10:10 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_B_DL_FLUSH_WAIT_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_B_DL_FLUSH_WAIT_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_B_INIT_TRAIN_HW_CLEAR 11:11 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_B_INIT_TRAIN_HW_CLEAR_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_B_INIT_TRAIN_HW_CLEAR_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_B_LOCK_IN_RST_RPLPTR 12:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_B_LOCK_IN_RST_RPLPTR_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_B_LOCK_IN_RST_RPLPTR_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_B_REPLAY_PENDING_ON_HOLDTL 13:13 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_B_REPLAY_PENDING_ON_HOLDTL_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_CYA_B_REPLAY_PENDING_ON_HOLDTL_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_CYA_B_SPARE 31:14 /* RWEVF */
|
|
#define NV_NVLDL_TX_CYA_B_SPARE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CFG 0x00002390 /* RW-4R */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CFG__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CFG_TWAIT 15:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CFG_TWAIT_INIT 0x00000052 /* RWE-V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL 0x00002394 /* RW-4R */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL__PRIV_LEVEL_MASK 0x00002700 /* */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL_MAX_ATTEMPTS 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL_MAX_ATTEMPTS_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL_MAX_ATTEMPTS_INFINITE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL_REQ 31:31 /* RWEVF */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL_REQ_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_CTRL_REQ_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS 0x00002398 /* R--4R */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS_ATTEMPT_COUNT 3:0 /* R-EVF */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS_ATTEMPT_COUNT_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS_STS 29:28 /* R-EVF */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS_STS_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS_STS_SEARCH 0x00000001 /* R---V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS_STS_FOUND 0x00000002 /* R---V */
|
|
#define NV_NVLDL_TX_LINK_RXDET_STATUS_STS_TIMEOUT 0x00000003 /* R---V */
|
|
#define NV_NVLDL_TX_SCRATCH_WARM 0x000027c0 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_WARM_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_COLD 0x000027c4 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_COLD_DATA 31:0 /* RWIVF */
|
|
#define NV_NVLDL_TX_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK0 0x000027d0 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00002700 /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK1 0x000027d4 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00002704 /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK2 0x000027d8 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00002708 /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK3 0x000027dc /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK4 0x000027e0 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00002710 /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK5 0x000027e4 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00002714 /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK6 0x000027e8 /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00002718 /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK7 0x000027ec /* RW-4R */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000271c /* */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL 0x00002400 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_EN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_EN_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_CONFIG_SETTINGS 11:1 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_RPT_EN 15:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2 0x00002404 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_0 0x00002408 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_0 0x0000240c /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_1 0x00002410 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_1_DATA 9:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_MATCH_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_1 0x00002414 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_1_DATA 9:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL 0x00002418 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX0_SLCT 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX0_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX1_SLCT 7:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX1_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX2_SLCT 11:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX2_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX3_SLCT 15:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_MUX3_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_FUNCTION 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE0_CTRL_FUNCTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_0 0x0000241c /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_0 0x00002420 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_1 0x00002424 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_1_DATA 6:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_MATCH_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_1 0x00002428 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_1_DATA 6:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL 0x0000242c /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX0_SLCT 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX0_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX1_SLCT 7:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX1_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX2_SLCT 11:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX2_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX3_SLCT 15:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_MUX3_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_FUNCTION 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE1_CTRL_FUNCTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_0 0x00002430 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_0 0x00002434 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_1 0x00002438 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_1_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_MATCH_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_1 0x0000243c /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_1__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_1_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL 0x00002440 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX0_SLCT 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX0_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX1_SLCT 7:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX1_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX2_SLCT 11:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX2_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX3_SLCT 15:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_MUX3_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_FUNCTION 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_DL_ILADET_STYLE2_CTRL_FUNCTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL 0x00002450 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_EN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_EN_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_CONFIG_SETTINGS 11:1 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_RPT_EN 15:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2 0x00002454 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_MATCH_0 0x00002458 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_MATCH_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_MATCH_0_DATA 17:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_DONTCARE_MASK_0 0x0000245c /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_DONTCARE_MASK_0_DATA 17:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_MATCH_0 0x00002460 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_MATCH_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_MATCH_0_DATA 14:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_DONTCARE_MASK_0 0x00002464 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_DONTCARE_MASK_0_DATA 14:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL 0x00002468 /* RW-4R */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL__PRIV_LEVEL_MASK 0x0000270c /* */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX0_SLCT 3:0 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX0_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX1_SLCT 7:4 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX1_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX2_SLCT 11:8 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX2_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX3_SLCT 15:12 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_MUX3_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_FUNCTION 31:16 /* RWEVF */
|
|
#define NV_NVLDL_TX_LA_TX_PL_ILADET_STYLE1_CTRL_FUNCTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1 0x00002ff0 /* RW-4R */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3 0x00002ff4 /* RW-4R */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK1 0x00002ff8 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK1_DATA 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK1_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK3 0x00002ffc /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK3_DATA 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SCRATCH_PRIVMASK3_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN 0x00002e00 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_COM_SYMBOL 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_COM_SYMBOL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1 0x00002e04 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_SKIP_SYMBOL 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_1_SKIP_SYMBOL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2 0x00002e08 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_MASK_COM_OUT 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_MASK_COM_OUT_INIT 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_MASK_SKIP_OUT 1:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_MASK_SKIP_OUT_INIT 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SEND_DATA_OUT 2:2 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_SEND_DATA_OUT_INIT 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_RESET_WORD_CNT_OUT 11:3 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SKIPCOMINSERTERGEN_2_RESET_WORD_CNT_OUT_INIT 0x00000100 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CAPTURESTART 0x00002e0c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_CAPTURESTART__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_CAPTURESTART_DPV_CAPTURESTART 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CAPTURESTART_DPV_CAPTURESTART_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG 0x00002e10 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_HOT_RESET 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_HOT_RESET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST 1:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_STARTTEST_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN 2:2 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_CFGCLKGATEEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD 3:3 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_PRBSSEEDLD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT 4:4 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_NRZ 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_PRBSALT_PAM4 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_CAPTUREEN 5:5 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_CAPTUREEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_DATAREQOVERRIDE 6:6 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPG_DATAREQOVERRIDE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_DATAVALIDOVERRIDE 7:7 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_DATAVALIDOVERRIDE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_MISRON 8:8 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIG_DPV_MISRON_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG 0x00002e14 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_DPG_TXDATAMUXSEL_IN 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_DPG_TXDATAMUXSEL_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_TRAINING_EN_IN 1:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_TRAINING_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN 2:2 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_TX_BIST_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN 3:3 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_LOOPBACK_IN_CORE_IN 4:4 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_LOOPBACK_IN_CORE_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SPARE_CONFIG_BITS_IN 6:5 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SPARE_CONFIG_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_ILA_DATA_CONFIG_BITS_IN 8:7 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_ILA_DATA_CONFIG_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_ILA_TRIGGER_CONFIG_BITS_IN 10:9 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_ILA_TRIGGER_CONFIG_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_ENCODER8B10B_EN_IN 11:11 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_ENCODER8B10B_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SCRAMBLER_EN_IN 12:12 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SCRAMBLER_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SKIP_EN_IN 13:13 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SKIP_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_XBAR_4_1_IN 14:14 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_XBAR_4_1_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_XBAR_2_1_IN 15:15 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_XBAR_2_1_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_DC_CHAR_IN 16:16 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_DC_CHAR_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN 17:17 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_IO_BIST_MODE_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_BYP_SYM_ALIGN_IN 18:18 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_BYP_SYM_ALIGN_IN_INIT 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SPARE_SEQUENCE_BITS_IN 20:19 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_CONFIGREG_SPARE_SEQUENCE_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG 0x00002e18 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG_DPV_STOPONERROR 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG_DPV_STOPONERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG_DPV_STOPERRORCOUNT 16:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG_DPV_STOPERRORCOUNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG_DPV_ERROROUTOFLOCKBITCNT 22:17 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCONFIG_DPV_ERROROUTOFLOCKBITCNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT 0x00002e1c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_ERRORCOUNTSTALL 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_ERRORCOUNTSTALL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_LOOPCNT 5:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_LOOPCNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_ERRORCHECKSTART 21:6 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_ERRORCHECKSTART_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_ERRORCHECKINTERVAL 26:22 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORCOUNT_DPV_ERRORCHECKINTERVAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_ERRORMASK 0x00002e20 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_ERRORMASK__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_ERRORMASK_DPV_ERRORBITMASK 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_ERRORMASK_DPV_ERRORBITMASK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG 0x00002e24 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1 0x00002e28 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_PRBS 0x00002e2c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_PRBS__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_PRBS_DPG_PRBSSEED_INIT 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG 0x00002e30 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1 0x00002e34 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_PRBS 0x00002e38 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_PRBS__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_PRBS_DPG_PRBSSEED_INIT 0x01111111 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG 0x00002e3c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1 0x00002e40 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_PRBS 0x00002e44 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_PRBS__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_PRBS_DPG_PRBSSEED_INIT 0x02222221 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG 0x00002e48 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1 0x00002e4c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_PRBS 0x00002e50 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_PRBS__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_PRBS_DPG_PRBSSEED_INIT 0x03333331 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_0 0x00002e54 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_0__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_0_PATTERNBUF1_0 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_0_PATTERNBUF1_0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_1 0x00002e58 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_1__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_1_PATTERNBUF1_1 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_1_PATTERNBUF1_1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_2 0x00002e5c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_2__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_2_PATTERNBUF1_2 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_2_PATTERNBUF1_2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_3 0x00002e60 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_3__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_3_PATTERNBUF1_3 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_3_PATTERNBUF1_3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_4 0x00002e64 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_4__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_4_PATTERNBUF1_4 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_4_PATTERNBUF1_4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_5 0x00002e68 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_5__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_5_PATTERNBUF1_5 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_5_PATTERNBUF1_5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_6 0x00002e6c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_6__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_6_PATTERNBUF1_6 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_6_PATTERNBUF1_6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_7 0x00002e70 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_7__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_7_PATTERNBUF1_7 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_7_PATTERNBUF1_7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_8 0x00002e74 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_8__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_8_PATTERNBUF1_8 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_8_PATTERNBUF1_8_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_9 0x00002e78 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_9__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_9_PATTERNBUF1_9 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_9_PATTERNBUF1_9_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_10 0x00002e7c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_10__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_10_PATTERNBUF1_10 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_10_PATTERNBUF1_10_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_11 0x00002e80 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_11__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_11_PATTERNBUF1_11 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_11_PATTERNBUF1_11_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_12 0x00002e84 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_12__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_12_PATTERNBUF1_12 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_12_PATTERNBUF1_12_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_13 0x00002e88 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_13__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_13_PATTERNBUF1_13 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_13_PATTERNBUF1_13_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_14 0x00002e8c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_14__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_14_PATTERNBUF1_14 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF1_14_PATTERNBUF1_14_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_0 0x00002e90 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_0__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_0_PATTERNBUF2_0 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_0_PATTERNBUF2_0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_1 0x00002e94 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_1__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_1_PATTERNBUF2_1 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_1_PATTERNBUF2_1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_2 0x00002e98 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_2__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_2_PATTERNBUF2_2 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_2_PATTERNBUF2_2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_3 0x00002e9c /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_3__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_3_PATTERNBUF2_3 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_3_PATTERNBUF2_3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_4 0x00002ea0 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_4__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_4_PATTERNBUF2_4 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_4_PATTERNBUF2_4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_5 0x00002ea4 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_5__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_5_PATTERNBUF2_5 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_5_PATTERNBUF2_5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_6 0x00002ea8 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_6__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_6_PATTERNBUF2_6 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_6_PATTERNBUF2_6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_7 0x00002eac /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_7__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_7_PATTERNBUF2_7 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_7_PATTERNBUF2_7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_8 0x00002eb0 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_8__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_8_PATTERNBUF2_8 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_8_PATTERNBUF2_8_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_9 0x00002eb4 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_9__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_9_PATTERNBUF2_9 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_9_PATTERNBUF2_9_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_10 0x00002eb8 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_10__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_10_PATTERNBUF2_10 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_10_PATTERNBUF2_10_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_11 0x00002ebc /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_11__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_11_PATTERNBUF2_11 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_11_PATTERNBUF2_11_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_12 0x00002ec0 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_12__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_12_PATTERNBUF2_12 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_12_PATTERNBUF2_12_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_13 0x00002ec4 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_13__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_13_PATTERNBUF2_13 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_13_PATTERNBUF2_13_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_14 0x00002ec8 /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_14__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_14_PATTERNBUF2_14 31:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_PBUF2_14_PATTERNBUF2_14_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_SELECTCONFIG 0x00002ecc /* RWI4R */
|
|
#define NV_NVLDL_TXIOBIST_SELECTCONFIG__PRIV_LEVEL_MASK 0x00002ff0 /* */
|
|
#define NV_NVLDL_TXIOBIST_SELECTCONFIG_DPV_SELECTLANE 1:0 /* RWIUF */
|
|
#define NV_NVLDL_TXIOBIST_SELECTCONFIG_DPV_SELECTLANE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_TXIOBIST_CBUF 0x00002ed0 /* R-I4R */
|
|
#define NV_NVLDL_TXIOBIST_CBUF__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_CBUF_DPV_CAPTUREBUF 31:0 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_CBUF_DPV_CAPTUREBUF_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS 0x00002ed4 /* R-I4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_00_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS 0x00002ed8 /* R-I4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_01_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS 0x00002edc /* R-I4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_02_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS 0x00002ee0 /* R-I4R */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LANE_03_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_LOOPCNT 0x00002ee4 /* R-I4R */
|
|
#define NV_NVLDL_TXIOBIST_LOOPCNT__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_LOOPCNT_DPV_LOOPCNTVAL 31:0 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_LOOPCNT_DPV_LOOPCNTVAL_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_STATUS 0x00002ee8 /* R-I4R */
|
|
#define NV_NVLDL_TXIOBIST_STATUS__PRIV_LEVEL_MASK 0x00002ff4 /* */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPG_RUNSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPG_RUNSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPV_RUNSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPV_RUNSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPV_VERIFYCOMPLETE 2:2 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPV_VERIFYCOMPLETE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPV_ERROROUTOFLOCKCNT 10:3 /* R-IUF */
|
|
#define NV_NVLDL_TXIOBIST_STATUS_DPV_ERROROUTOFLOCKCNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0 0x00003700 /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1 0x00003704 /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2 0x00003708 /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3 0x0000370c /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4 0x00003710 /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5 0x00003714 /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6 0x00003718 /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask6" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7 0x0000371c /* RW-4R */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
|
|
#define NV_NVLDL_RX_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX 0x00003000 /* RW-4R */
|
|
#define NV_NVLDL_RX_CONFIG_RX__PRIV_LEVEL_MASK 0x00003700 /* */
|
|
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT 3:0 /* R-EVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT_NONE 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_HW_POLARITY_INVERT_ALL 0x0000000f /* R---V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_FIFO_WR_REQ_DELAY 7:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_FIFO_WR_REQ_DELAY_INIT 0x0000000a /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE 8:8 /* R-EVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_HW_LANE_REVERSE_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT 19:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT_NONE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_INVERT_ALL 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE 23:22 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_ECC96 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_ECC_MODE_ECC88 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE 24:24 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_LANE_REVERSE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN 25:25 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_IOBIST_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST 26:26 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_PHY_NO_ADJUST_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE 27:27 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_PHY_ADJUST_OVERRIDE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE 28:28 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_POLARITY_OVERRIDE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE 29:29 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_REVERSAL_OVERRIDE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST 30:30 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_SKIP_TOGGLE_CONST_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CONFIG_RX_DEBUG_ENABLE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX 0x00003004 /* RW-4R */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX_FILTER 9:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX_FILTER_INIT 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX_FILTER_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX_CONSTCYC 25:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX_CONSTCYC_INIT 0x00000028 /* RWE-V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL0_RX_CONSTCYC_MINIMUM 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX 0x00003008 /* RW-4R */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_TOGGLE_LOCK 7:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_TOGGLE_LOCK_INIT 0x00000006 /* RWE-V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_TOGGLE_LOCK_MINIMUM 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_THRESH 14:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_THRESH_26 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_THRESH_28 0x00000006 /* RWE-V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_THRESH_30 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_THRESH_32 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_SYMALIGN 15:15 /* RWEVF */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_SYMALIGN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_SYMALIGN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_TOGGLE 31:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_SAFE_CTRL1_RX_TOGGLE_INIT 0x00000014 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX 0x00003010 /* RW-4R */
|
|
#define NV_NVLDL_RX_LOCK_RX__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_LOCK_CNT 9:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_LOCK_CNT_INIT 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_LOCK_CNT_MINIMUM 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_UNLOCK_CNT 21:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_UNLOCK_CNT_INIT 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_UNLOCK_DIS 23:23 /* RWEVF */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_UNLOCK_DIS_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SCRAM_UNLOCK_DIS_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SYMALIGN_LOCK_CNT 28:24 /* RWEVF */
|
|
#define NV_NVLDL_RX_LOCK_RX_HS_SYMALIGN_LOCK_CNT_MINIMUM 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX 0x00003014 /* R--4R */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE 3:0 /* R-EVF */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_SUBSTATE_STABLE 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE 7:4 /* R-XVF */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_HS 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_EIGHTH 0x00000004 /* R---V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_TRAIN 0x00000005 /* R---V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_SAFE 0x00000006 /* R---V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_OFF 0x00000007 /* R---V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_PRIMARY_STATE_UNKNOWN 0x0000000d /* R---V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_SURPRISE_LD_CNT 15:8 /* R-EVF */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_SURPRISE_LD_CNT_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS 31:31 /* R-EVF */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_SLSM_STATUS_RX_FENCE_STATUS_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0 0x00003018 /* RW-4R */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_ERR_CNT_MULTI 3:0 /* R-EVF */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_ERR_CNT_MULTI_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_COUNTER_CLR 30:30 /* -WEVF */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_COUNTER_CLR_OFF 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_COUNTER_CLR_ON 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_SATSTOP 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_SATSTOP_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_0_SATSTOP_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2 0x00003020 /* R--4R */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_0 7:0 /* R-EVF */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_0_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_0_SATURATED 0x000000ff /* R---V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_1 15:8 /* R-EVF */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_1_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_1_SATURATED 0x000000ff /* R---V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_2 23:16 /* R-EVF */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_2_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_2_SATURATED 0x000000ff /* R---V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_3 31:24 /* R-EVF */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_3_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_BF_ERRLOG_2_ERR_CNT_3_SATURATED 0x000000ff /* R---V */
|
|
#define NV_NVLDL_RX_CHECK_RX 0x00003024 /* RW-4R */
|
|
#define NV_NVLDL_RX_CHECK_RX__PRIV_LEVEL_MASK 0x00003718 /* */
|
|
#define NV_NVLDL_RX_CHECK_RX_CHECK_START_DELAY_CNT 11:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_CHECK_RX_CHECK_START_DELAY_CNT_INIT 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_RX_CHECK_RX_CHECK_START_DELAY_CNT_MINIMUM 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CHECK_RX_CHECK_END_DELAY_CNT 27:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_CHECK_RX_CHECK_END_DELAY_CNT_INIT 0x0000206d /* RWE-V */
|
|
#define NV_NVLDL_RX_CHECK_RX_CHECK_END_DELAY_CNT_MINIMUM 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_CHECK_RX_PRBS_CHK 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_CHECK_RX_PRBS_CHK_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CHECK_RX_PRBS_CHK_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL 0x00003028 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR 1:1 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_CONST_DET_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR 2:2 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_OFF2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE2NO_LINK_DET_ERR 3:3 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE2NO_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE2NO_LINK_DET_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR 4:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SCRAM_LOCK_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR 5:5 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_LOCK_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR 6:6 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SYM_ALIGN_END_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR 7:7 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FIFO_SKEW_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR 8:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_TRAIN2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR 9:9 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_HS2SAFE_LINK_DET_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR 10:10 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_FENCE_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_NO_LD_ERR 11:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_NO_LD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_NO_LD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2SAFE_LD_ERR 12:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2SAFE_LD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2SAFE_LD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_RXPWR_ERR 13:13 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_RXPWR_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_RXPWR_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_TXPWR_ERR 14:14 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_TXPWR_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_TXPWR_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR 15:15 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_RC_DEADLINE_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_NO_LD_STATUS 17:17 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_NO_LD_STATUS_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_SAFE_NO_LD_STATUS_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR 18:18 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_SD_NO_LD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR 19:19 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_SD_NO_LD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2S_SD_NO_LD_ERR 20:20 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2S_SD_NO_LD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2S_SD_NO_LD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR 21:21 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_O2S_STROBE_NO_SD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR 22:22 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_H2S_STROBE_NO_SD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2S_STROBE_NO_SD_ERR 23:23 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2S_STROBE_NO_SD_ERR_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_ERR_CNTL_E2S_STROBE_NO_SD_ERR_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0 0x0000302c /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_FIFO_SKEW_CNT 8:5 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_FIFO_SKEW_CNT_INIT 0x00000002 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_FIFO_SKEW_CNT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_FIFO_SKEW_CNT_UPPER 15:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_FIFO_SKEW_CNT_UPPER_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_FIFO_SKEW_CNT_UPPER_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_CONST_DET 31:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_CONST_DET_INIT 0x000061a8 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_CONST_DET_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1 0x00003030 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_SAFE2NO_LINK_DET 15:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_SAFE2NO_LINK_DET_INIT 0x00009000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_SAFE2NO_LINK_DET_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_OFF2SAFE_LINK_DET 26:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_OFF2SAFE_LINK_DET_INIT 0x000000e9 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_OFF2SAFE_LINK_DET__PROD_ISSC 0x000003ce /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_OFF2SAFE_LINK_DET_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_OFF2SAFE_LINK_DET_SCL 31:27 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_OFF2SAFE_LINK_DET_SCL_INIT 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_OFF2SAFE_LINK_DET_SCL_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2 0x00003034 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2_SYM_LOCK 15:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2_SYM_LOCK_INIT 0x00000fa0 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2_SYM_LOCK_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2_SCRAM_LOCK 31:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2_SCRAM_LOCK_INIT 0x00000600 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_2_SCRAM_LOCK_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3 0x00003038 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3_TRAIN2SAFE_LINK_DET 15:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3_TRAIN2SAFE_LINK_DET_INIT 0x0000bf00 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3_TRAIN2SAFE_LINK_DET__PROD_ISSC 0x0000f230 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3_TRAIN2SAFE_LINK_DET_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3_SYM_ALIGN_END 31:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3_SYM_ALIGN_END_INIT 0x000001f4 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_3_SYM_ALIGN_END_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4 0x0000303c /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_E2SAFE_LINK_DET 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_E2SAFE_LINK_DET_INIT 0x000000e9 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_E2SAFE_LINK_DET__PROD_ISSC 0x000003ce /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_E2SAFE_LINK_DET_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_E2SAFE_LINK_DET_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_E2SAFE_LINK_DET_SCL_INIT 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_E2SAFE_LINK_DET_SCL_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_HS2SAFE_LINK_DET 26:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_HS2SAFE_LINK_DET_INIT 0x000000c0 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_HS2SAFE_LINK_DET_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_HS2SAFE_LINK_DET_SCL 31:27 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_HS2SAFE_LINK_DET_SCL_INIT 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_4_HS2SAFE_LINK_DET_SCL_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5 0x00003074 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_RX 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_RX_MAXIMUM 0x000007ff /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_RX_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_RX_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_RX_SCL_INIT 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_RX_SCL_MAXIMUM 0x0000001f /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_TX 26:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_TX_INIT 0x00000484 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_TX_MAXIMUM 0x000007ff /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_TX_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_TX_SCL 31:27 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_TX_SCL_INIT 0x00000012 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_5_RC_PWR_TX_SCL_MAXIMUM 0x0000001f /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG 0x00003040 /* R--4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG_CONST_DET_LANE 11:8 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG_CONST_DET_LANE_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG_SCRAM_LOCK_LANE 19:16 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG_SCRAM_LOCK_LANE_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG_SYM_LOCK_LANE 27:24 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_0_LOG_SYM_LOCK_LANE_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_LOG 0x00003044 /* R--4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_LOG__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_LOG_FIFO_SKEW_LANE 19:16 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_LOG_FIFO_SKEW_LANE_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_LOG_SYM_ALIGN_END_LANE 27:24 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_1_LOG_SYM_ALIGN_END_LANE_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXBISTERR(i) (0x00003048+(i)*0x4) /* R--4A */
|
|
#define NV_NVLDL_RX_RXBISTERR__SIZE_1 4 /* */
|
|
#define NV_NVLDL_RX_RXBISTERR__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_RXBISTERR_LOCK_CNT 29:0 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXBISTERR_LOCK_CNT_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXBISTERR_ERR_STATUS 31:31 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXBISTERR_ERR_STATUS_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL2_RX 0x00003064 /* RW-4R */
|
|
#define NV_NVLDL_RX_SAFE_CTRL2_RX__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_SAFE_CTRL2_RX_INIT_TRAIN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SAFE_CTRL2_RX_INIT_TRAIN_NOT_DONE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_SAFE_CTRL2_RX_INIT_TRAIN_DONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0 0x00003068 /* R--4R */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_0 5:0 /* R-XVF */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_0_FULL 0x00000012 /* R---V */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_1 13:8 /* R-XVF */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_1_FULL 0x00000012 /* R---V */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_2 21:16 /* R-XVF */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_2_FULL 0x00000012 /* R---V */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_3 29:24 /* R-XVF */
|
|
#define NV_NVLDL_RX_FIFO_STATUS_RX_0_ENTRIES_USED_3_FULL 0x00000012 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0 0x00003080 /* RW-4R */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_CDR_LOCK 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_CDR_LOCK_INIT 0x00000212 /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_CDR_LOCK_SCALE 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_CDR_LOCK_SCALE_INIT 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_STEP 27:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_STEP_INIT 0x00000027 /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_FORCE 28:28 /* -WEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_FORCE_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_OVERLAP 29:29 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_OVERLAP_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_OVERLAP_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_PERIODIC_ENABLE 30:30 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_PERIODIC_ENABLE_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_0_RECAL_PERIODIC_ENABLE_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1 0x00003084 /* RW-4R */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_START 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_START_INIT 0x000007af /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_START_SCALE 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_START_SCALE_INIT 0x0000000d /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_DEADLINE 26:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_DEADLINE_INIT 0x00000486 /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_DEADLINE_SCALE 31:27 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_1_RECAL_DEADLINE_SCALE_INIT 0x00000012 /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_2 0x00003088 /* RW-4R */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_2_PSAVE_STEP 15:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_PHYCFG_RX_2_PSAVE_STEP_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS 0x0000308c /* R--4R */
|
|
#define NV_NVLDL_RX_PHYCFG_STS__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_PSAVE_STS 23:20 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_PSAVE_STS_ON 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_PSAVE_STS_OFF 0x0000000e /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_PSAVE_STS_ALL_OFF 0x0000000f /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_FSM_BUSY 25:25 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_FSM_BUSY_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_FSM_BUSY_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_EOM_ABORT 26:26 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_EOM_ABORT_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_EOM_ABORT_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_EOM_STS 27:27 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_EOM_STS_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_EOM_STS_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_PSAVE_STS_RDY 28:28 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_PSAVE_STS_RDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_PSAVE_STS_RDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_FORCE_BUSY 29:29 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_FORCE_BUSY_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_FORCE_BUSY_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_ABORT 30:30 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_ABORT_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_ABORT_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_BUSY 31:31 /* R-EVF */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_BUSY_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_PHYCFG_STS_RC_BUSY_ON 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS 0x00003090 /* RW-4R */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS_REQ 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS_REQ_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS_REQ_ON 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS_REQ_ALL_ON 0x0000000f /* RWE-V */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS_RDY 31:31 /* R-EVF */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS_RDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_PSAVE_SW_CTRL_STS_RDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS 0x00003094 /* RW-4R */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS__PRIV_LEVEL_MASK 0x00003700 /* */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS_REQ 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS_REQ_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS_REQ_ON 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS_REQ_ALL_ON 0x0000000f /* RWE-V */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS_RDY 31:31 /* R-EVF */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS_RDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_PSAVE_UCODE_CTRL_STS_RDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS 0x00003098 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RCREQ 3:1 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RCREQ_ON 0x00000007 /* R---V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RCREQ_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_SLREQ 11:9 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_SLREQ_ON 0x00000007 /* R---V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_SLREQ_OFF 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RCRDY 26:26 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RCRDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RCRDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_SLRDY 27:27 /* R-EVF */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_SLRDY_OFF 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_SLRDY_ON 0x00000001 /* R-E-V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RECAL_R4_ENABLE 30:30 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RECAL_R4_ENABLE_CLR 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_RECAL_R4_ENABLE_SET 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_AUTO_RECAL_EN 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_AUTO_RECAL_EN_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXPWR_HW_CTRL_STS_AUTO_RECAL_EN_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN0_RX 0x0000309c /* RW-4R */
|
|
#define NV_NVLDL_RX_TRAIN0_RX__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAIN_LEN 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAIN_LEN_INIT 0x000001fb /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAIN_LEN_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAIN_LEN_SCL_INIT 0x0000000e /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAIN_INFINITE 16:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAIN_INFINITE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAINING_PHASE 30:30 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAINING_PHASE_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_TRAINING_PHASE_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_FOM_SEL 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_FOM_SEL_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN0_RX_FOM_SEL_PRBS 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_TRAIN1_RX 0x000030a0 /* R--4R */
|
|
#define NV_NVLDL_RX_TRAIN1_RX__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_TRAIN1_RX_L0_LASTFOM 15:0 /* R-EUF */
|
|
#define NV_NVLDL_RX_TRAIN1_RX_L0_LASTFOM_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_TRAIN1_RX_L1_LASTFOM 31:16 /* R-EUF */
|
|
#define NV_NVLDL_RX_TRAIN1_RX_L1_LASTFOM_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_TRAIN2_RX 0x000030a4 /* R--4R */
|
|
#define NV_NVLDL_RX_TRAIN2_RX__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_TRAIN2_RX_L2_LASTFOM 15:0 /* R-EUF */
|
|
#define NV_NVLDL_RX_TRAIN2_RX_L2_LASTFOM_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_TRAIN2_RX_L3_LASTFOM 31:16 /* R-EUF */
|
|
#define NV_NVLDL_RX_TRAIN2_RX_L3_LASTFOM_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX 0x000030a8 /* RW-4R */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_LASTFOM_VLD 0:0 /* R-EVF */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_LASTFOM_VLD_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_LASTFOM_EQDONE 1:1 /* R-EVF */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_LASTFOM_EQDONE_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TRAIN_EQ_LEN 12:2 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TRAIN_EQ_LEN_INIT 0x00000328 /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TRAIN_EQ_LEN_L2_EXIT 0x000006b6 /* RW--V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TRAIN_EQ_LEN_SCL 17:13 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TRAIN_EQ_LEN_SCL_INIT 0x0000000d /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TRAIN_EQ_LEN_SCL_L2_EXIT 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_SAFE_DEAD_WAIT 27:18 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_SAFE_DEAD_WAIT_INIT 0x00000043 /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TXCLK_USED4_TRAINING 28:28 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN3_RX_TXCLK_USED4_TRAINING_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN4_RX 0x000030ac /* RW-4R */
|
|
#define NV_NVLDL_RX_TRAIN4_RX__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_TRAIN4_RX_FOM_WAIT_LEN 12:2 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN4_RX_FOM_WAIT_LEN_INIT 0x000000ca /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN4_RX_FOM_WAIT_LEN_SCL 17:13 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN4_RX_FOM_WAIT_LEN_SCL_INIT 0x0000000d /* RWE-V */
|
|
#define NV_NVLDL_RX_TRAIN4_RX_FOM_WAIT_DIS 18:18 /* RWEVF */
|
|
#define NV_NVLDL_RX_TRAIN4_RX_FOM_WAIT_DIS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND 0x00003140 /* RW-4R */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_REQUEST 2:0 /* -WEUF */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_REQUEST_NOP 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_REQUEST_READ 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_REQUEST_WRITE 0x00000002 /* -W--V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_REQUEST_SWAP 0x00000003 /* -W--V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_READY 3:3 /* R-EVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_READY_YES 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_READY_NO 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_WADDR 14:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_WADDR_II 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_WADDR_SC 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_RADDR 22:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_RADDR_II 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_RADDR_SC 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_COMPLETE 24:24 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_COMPLETE_BUSY_NOP 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_COMMAND_COMPLETE_READY_CLEAR 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA0 0x00003150 /* RW-4R */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA0__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA1 0x00003154 /* RW-4R */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA1__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_WDATA1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA0 0x00003158 /* RW-4R */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA0__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA1 0x0000315c /* RW-4R */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA1__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4LOCAL_RDATA1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND 0x00003160 /* RW-4R */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_REQUEST 2:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_REQUEST_INVALID 0x00000000 /* R---V */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_REQUEST_READ 0x00000001 /* R---V */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_REQUEST_WRITE 0x00000002 /* R---V */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_ADDR 15:8 /* R-XVF */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_TAG 19:16 /* R-XVF */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_COMPLETE 24:24 /* RWXVF */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_COMPLETE_IDLE_NOP 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_R4SWREQ_COMMAND_COMPLETE_BUSY_CLEAR 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA0 0x00003168 /* RW-4R */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA1 0x0000316c /* RW-4R */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_R4SWREQ_DATA1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_AN0_A 0x00003200 /* RW-4R */
|
|
#define NV_NVLDL_RX_AN0_A__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE 1:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE_20 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE_32 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE_LS 5:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE_LS_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE_LS_20 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_AN0_A_AN0_FILTER_SEQUENCE_LS_32 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_RXLANECRC 0x0000321c /* RW-4R */
|
|
#define NV_NVLDL_RX_RXLANECRC__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_RXLANECRC_ENABLE 0:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXLANECRC_ENABLE_EN 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXLANECRC_ENABLE_DIS 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXLANECRC_COUNTER_MODE 4:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXLANECRC_COUNTER_MODE_SIMPLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RXLANECRC_COUNTER_MODE_FREEZE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER 0x00003230 /* RW-4R */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_FILTER_VAL 3:0 /* RWEUF */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_FILTER_VAL_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_MODE 7:7 /* RWEVF */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_MODE_MATCH 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_MODE_MASK 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_WIDTH_EXP 10:8 /* RWEUF */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_WIDTH_EXP_1 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_A 17:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_A_LANE_0 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_A_LANE_1 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_A_LANE_2 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_A_LANE_3 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_B 20:19 /* RWEVF */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_B_LANE_0 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_B_LANE_1 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_B_LANE_2 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_RX_ILA_RTRIGGER_ILA_LANE_SELECT_B_LANE_3 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_RX_SCRATCH(i) (0x00003240+(i)*0x4) /* R--4A */
|
|
#define NV_NVLDL_RX_SCRATCH__SIZE_1 2 /* */
|
|
#define NV_NVLDL_RX_SCRATCH__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_SCRATCH_DATA 31:0 /* R-EVF */
|
|
#define NV_NVLDL_RX_SCRATCH_DATA_INIT 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL 0x00003280 /* RW-4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC 0:0 /* -WEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_FLIT_CRC_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC 1:1 /* -WEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_LANE_CRC_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES 2:2 /* -WEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_RATES_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY 3:3 /* -WEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_REPLAY_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS 4:4 /* -WEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_INIT 0x00000000 /* -WE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_CLEAR_ECC_COUNTS_CLEAR 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE 8:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_SHORT_RATE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE 9:9 /* RWEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_LONG_RATE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE 10:10 /* RWEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_FLIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_RATE_COUNT_MODE_SEQUENCE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE 11:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_FLIT 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT_CTRL_FLIT_COUNT_MODE_SEQUENCE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL 0x00003284 /* RW-4R */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN 2:0 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP 3:3 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN 6:4 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP 11:8 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_SHORT_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN 18:16 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_MAN_INIT 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP 19:19 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_THRESHOLD_EXP_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN 22:20 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_MAN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP 28:24 /* RWEUF */
|
|
#define NV_NVLDL_RX_ERROR_RATE_CTRL_LONG_TIMESCALE_EXP_INIT 0x00000006 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT1 0x00003288 /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT1__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT1_FLIT_CRC_ERRORS 15:0 /* R-EUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT1_FLIT_CRC_ERRORS_ZERO 0x00000000 /* R-E-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT2_LANECRC 0x0000328c /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT2_LANECRC__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT2_LANECRC_L0 7:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT2_LANECRC_L1 15:8 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT2_LANECRC_L2 23:16 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT2_LANECRC_L3 31:24 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT6 0x00003294 /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT6__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT6_RX_AN0_REPLAY 15:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT5 0x0000329c /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT5__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT5_SHORT_RATE_COUNTER 7:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT5_SHORT_DECREMENTED 15:15 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT5_LONG_RATE_COUNTER 23:16 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT5_LONG_DECREMENTED 31:31 /* R-XUF */
|
|
#define NV_NVLDL_RX_DBG_A 0x00003300 /* RW-4R */
|
|
#define NV_NVLDL_RX_DBG_A__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_DBG_A_RXDL_STATE 3:0 /* R-XVF */
|
|
#define NV_NVLDL_RX_DBG_A_LAST_OPCODE 11:8 /* R-XVF */
|
|
#define NV_NVLDL_RX_DBG_A_TRIGGER_ILA 31:31 /* -WXVF */
|
|
#define NV_NVLDL_RX_DBG_A_TRIGGER_ILA_DOIT 0x00000001 /* -W--V */
|
|
#define NV_NVLDL_RX_RX_SLCG 0x00003304 /* RW-4R */
|
|
#define NV_NVLDL_RX_RX_SLCG__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_RX_SLCG_RX_SLCG 0:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RX_SLCG_RX_SLCG_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_RX_SLCG_RX_SLCG_DISABLED 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_PM_RX 0x00003340 /* RW-4R */
|
|
#define NV_NVLDL_RX_PM_RX__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0 7:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP00 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP01 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP02 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP03 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP04 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP05 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP06 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP07 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP08 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP09 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP10 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP11 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP12 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP13 0x0000000d /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP14 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP15 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP16 0x00000010 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP17 0x00000011 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP18 0x00000012 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP19 0x00000013 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP20 0x00000014 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP21 0x00000015 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP22 0x00000016 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP23 0x00000017 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP24 0x00000018 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP25 0x00000019 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP26 0x0000001a /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP27 0x0000001b /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP28 0x0000001c /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP29 0x0000001d /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP30 0x0000001e /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP31 0x0000001f /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL0_GRP255 0x000000ff /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1 15:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP00 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP01 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP02 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP03 0x00000003 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP04 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP05 0x00000005 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP06 0x00000006 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP07 0x00000007 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP08 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP09 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP10 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP11 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP12 0x0000000c /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP13 0x0000000d /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP14 0x0000000e /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP15 0x0000000f /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP16 0x00000010 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP17 0x00000011 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP18 0x00000012 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP19 0x00000013 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP20 0x00000014 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP21 0x00000015 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP22 0x00000016 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP23 0x00000017 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP24 0x00000018 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP25 0x00000019 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP26 0x0000001a /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP27 0x0000001b /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP28 0x0000001c /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP29 0x0000001d /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP30 0x0000001e /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP31 0x0000001f /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_SEL1_GRP255 0x000000ff /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_ENABLE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_PM_RX_ENABLE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_PM_RX_ENABLE_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_A 0x00003380 /* RW-4R */
|
|
#define NV_NVLDL_RX_CYA_A__PRIV_LEVEL_MASK 0x00003700 /* */
|
|
#define NV_NVLDL_RX_CYA_A_CRCOK_ON_NXTSEQ_MATCH 0:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_A_CRCOK_ON_NXTSEQ_MATCH_ALLOWED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE 30:1 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1742107_R 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1748732 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG2271132 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_RESERVED_3 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_RESERVED_4 0x00000010 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1581985_R 0x00000020 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1756963 0x00000040 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1772538 0x00000080 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1789471 0x00000100 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1791964 0x00000200 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1791964_LD1 0x00000400 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_RESERVED_11 0x00000800 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1827568 0x00002000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1847900 0x00004000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1905859 0x00008000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG1905859_2 0x00010000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG2551034 0x00020000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_A_SPARE_ECOCHX_UNDO_BUG2689805 0x00040000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B 0x00003384 /* RW-4R */
|
|
#define NV_NVLDL_RX_CYA_B__PRIV_LEVEL_MASK 0x00003700 /* */
|
|
#define NV_NVLDL_RX_CYA_B_SPARE 12:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_SPARE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_CLR_CRC_EARLY_ON_RESET_SEQ 13:13 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_CLR_CRC_EARLY_ON_RESET_SEQ_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_CLR_CRC_EARLY_ON_RESET_SEQ_DISABLE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_ZERO_PKTLEN_ONLY_ON_DATVLD 14:14 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_ZERO_PKTLEN_ONLY_ON_DATVLD_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_ZERO_PKTLEN_ONLY_ON_DATVLD_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_INVALIDATE_CCRC_EARLY 15:15 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_INVALIDATE_CCRC_EARLY_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_INVALIDATE_CCRC_EARLY_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_INIT_TRAIN_HW_CLEAR 16:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_INIT_TRAIN_HW_CLEAR_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_INIT_TRAIN_HW_CLEAR_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_ALLOW_RMT_TX_ALL_LANES_PD 17:17 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_ALLOW_RMT_TX_ALL_LANES_PD_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_ALLOW_RMT_TX_ALL_LANES_PD_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_MASK_ERRORS_IN_SLEEP 19:19 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_MASK_ERRORS_IN_SLEEP_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_MASK_ERRORS_IN_SLEEP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_FAULT_NO_LD 21:21 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_FAULT_NO_LD_DIS 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_FAULT_NO_LD_ENABLE 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_LTSSM2RXDL_INVALIDATE 22:22 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_LTSSM2RXDL_INVALIDATE_USE 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_LTSSM2RXDL_INVALIDATE_DIS 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_RC_DEADLINE_MINION_REQ_EN 23:23 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_RC_DEADLINE_MINION_REQ_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_RC_DEADLINE_MINION_REQ_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_SAFE_CDR_EN 24:24 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_SAFE_CDR_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_SAFE_CDR_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_SURPRISE_LD_CDR_EN 25:25 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_SURPRISE_LD_CDR_EN_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_SURPRISE_LD_CDR_EN_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_ALLOW_ZERO_SCRAM_SEED 26:26 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_ALLOW_ZERO_SCRAM_SEED_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_ALLOW_ZERO_SCRAM_SEED_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_FENCE_ALLOWED_ALL 27:27 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_FENCE_ALLOWED_ALL_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_FENCE_ALLOWED_ALL_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_FENCE_ALLOWED_SCRAM_LOCK 28:28 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_FENCE_ALLOWED_SCRAM_LOCK_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_FENCE_ALLOWED_SCRAM_LOCK_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_ALWAYS_BREAK_CRC_ON_SWITCH 29:29 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_ALWAYS_BREAK_CRC_ON_SWITCH_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_RXDL2LTSSM_SQUELCH 30:30 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_RXDL2LTSSM_SQUELCH_ON 0x00000001 /* RWE-V */
|
|
#define NV_NVLDL_RX_CYA_B_RXDL2LTSSM_SQUELCH_OFF 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_SAFE2SAFE_DIS 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_CYA_B_SAFE2SAFE_DIS_ON 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_CYA_B_SAFE2SAFE_DIS_OFF 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX_1 0x00003388 /* RW-4R */
|
|
#define NV_NVLDL_RX_LOCK_RX_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LOCK_RX_1_HS_ALIGN_DONE_LOCK_CNT 4:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LOCK_RX_1_HS_ALIGN_DONE_LOCK_CNT_MINIMUM 0x00000004 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX_1_HS_ALIGN_DONE_UNLOCK_CNT 11:7 /* RWEVF */
|
|
#define NV_NVLDL_RX_LOCK_RX_1_HS_ALIGN_DONE_UNLOCK_CNT_INIT 0x00000006 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX_1_HS_SYMALIGN_UNLOCK_CNT 18:14 /* RWEVF */
|
|
#define NV_NVLDL_RX_LOCK_RX_1_HS_SYMALIGN_UNLOCK_CNT_INIT 0x00000006 /* RWE-V */
|
|
#define NV_NVLDL_RX_LOCK_RX_1_HS_SYMALIGN_UNLOCK_CNT_MINIMUM 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6 0x0000338c /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_HS_DEAD_WAIT_CNT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_HS_DEAD_WAIT_CNT_INIT 0x00000426 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_HS_DEAD_WAIT_CNT_MAXIMUM 0x0000003f /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_HS_DEAD_WAIT_CNT_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_HS_DEAD_WAIT_CNT_SCL_INIT 0x00000003 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_E2S_DEAD_WAIT_CNT 26:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_E2S_DEAD_WAIT_CNT_INIT 0x00000426 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_E2S_DEAD_WAIT_CNT_SCL 31:27 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_6_E2S_DEAD_WAIT_CNT_SCL_INIT 0x00000003 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_7 0x00003390 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_7__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_7_SAFE_RETRY_CNT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_7_SAFE_RETRY_CNT_INIT 0x00000020 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_7_SAFE_RETRY_CNT_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_7_SAFE_RETRY_CNT_SCL_INIT 0x00000008 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_8 0x00003394 /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_8__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_8_RC_ABORT_CNT 10:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_8_RC_ABORT_CNT_INIT 0x0000019c /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_8_RC_ABORT_CNT_SCL 15:11 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_8_RC_ABORT_CNT_SCL_INIT 0x00000002 /* RWE-V */
|
|
#define NV_NVLDL_RX_ERROR_COUNT7 0x00003398 /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT7__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT7_ECC_CORRECTED_L0 23:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT8 0x0000339c /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT8__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT8_ECC_CORRECTED_L1 23:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT9 0x000033a0 /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT9__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT9_ECC_CORRECTED_L2 23:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT10 0x000033a4 /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT10__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT10_ECC_CORRECTED_L3 23:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_ERROR_COUNT11 0x000033a8 /* R--4R */
|
|
#define NV_NVLDL_RX_ERROR_COUNT11__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_ERROR_COUNT11_ECC_DEC_FAILED 23:0 /* R-XUF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_9 0x000033ac /* RW-4R */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_9__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_9_RX_SAFE2HS_EQ_CNT 30:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_9_RX_SAFE2HS_EQ_CNT_INIT 0x3187db00 /* RWE-V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_9_RX_SAFE2HS_EQ_CNT_L2_EXIT 0x000d6c60 /* RW--V */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_9_RX_SAFE2HS_EQ_INFINITE 31:31 /* RWEVF */
|
|
#define NV_NVLDL_RX_RXSLSM_TIMEOUT_9_RX_SAFE2HS_EQ_INFINITE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_WARM 0x000037c0 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_WARM_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_COLD 0x000037c4 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_COLD_DATA 31:0 /* RWIVF */
|
|
#define NV_NVLDL_RX_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK0 0x000037d0 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00003700 /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK1 0x000037d4 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00003704 /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK2 0x000037d8 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00003708 /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK3 0x000037dc /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK4 0x000037e0 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00003710 /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK5 0x000037e4 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00003714 /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK6 0x000037e8 /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00003718 /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK7 0x000037ec /* RW-4R */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000371c /* */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL 0x00003400 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_EN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_EN_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_CONFIG_SETTINGS 11:1 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_RPT_EN 15:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2 0x00003404 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_0 0x00003408 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_0 0x0000340c /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_1 0x00003410 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_1 0x00003414 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_2 0x00003418 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_2_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_MATCH_2_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_2 0x0000341c /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_2_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL 0x00003420 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX0_SLCT 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX0_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX1_SLCT 7:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX1_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX2_SLCT 11:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX2_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX3_SLCT 15:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_MUX3_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_FUNCTION 31:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE0_CTRL_FUNCTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_0 0x00003424 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_0 0x00003428 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_1 0x0000342c /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_1 0x00003430 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_1_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_2 0x00003434 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_2_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_MATCH_2_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_2 0x00003438 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_2_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_DONTCARE_MASK_2_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL 0x0000343c /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX0_SLCT 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX0_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX1_SLCT 7:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX1_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX2_SLCT 11:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX2_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX3_SLCT 15:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_MUX3_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_FUNCTION 31:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_DL_ILADET_STYLE1_CTRL_FUNCTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL 0x00003450 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_EN 0:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_EN_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_CONFIG_SETTINGS 11:1 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_CONFIG_SETTINGS_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_RPT_EN 15:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_RPT_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN 19:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_EXIT_TRIG_EN_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY 22:20 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_0_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY 25:23 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_1_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY 28:26 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_2_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY 31:29 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_SMP_INT_3_EVENT_PRIORITY_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2 0x00003454 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE 1:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_0_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE 3:2 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_1_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE 5:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_2_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE 7:6 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_3_DET_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE 9:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_0_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE 11:10 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_1_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE 13:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_2_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE 15:14 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_3_TRIG_STYLE_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT 17:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_0_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT 19:18 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_1_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT 21:20 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_2_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT 23:22 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_CTRL_2_SMP_INT_3_REPORT_FORMAT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_0 0x00003458 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_0 0x0000345c /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_1 0x00003460 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_1_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_MATCH_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_1 0x00003464 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_1_DATA 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE0_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_0 0x00003468 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_0 0x0000346c /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_0__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_0_DATA 31:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_0_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_1 0x00003470 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_1_DATA 8:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_MATCH_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_1 0x00003474 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_1__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_1_DATA 8:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_DONTCARE_MASK_1_DATA_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL 0x00003478 /* RW-4R */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL__PRIV_LEVEL_MASK 0x0000370c /* */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX0_SLCT 3:0 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX0_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX1_SLCT 7:4 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX1_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX2_SLCT 11:8 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX2_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX3_SLCT 15:12 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_MUX3_SLCT_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_FUNCTION 31:16 /* RWEVF */
|
|
#define NV_NVLDL_RX_LA_RX_PL_ILADET_STYLE1_CTRL_FUNCTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1 0x00003ff0 /* RW-4R */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3 0x00003ff4 /* RW-4R */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000b /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK1 0x00003ff8 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK1_DATA 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK1_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK3 0x00003ffc /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK3_DATA 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_SCRATCH_PRIVMASK3_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN 0x00003e00 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_ALIGNER_BYPASS 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_ALIGNER_BYPASS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_REALIGN 1:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_REALIGN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_1 0x00003e04 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_1__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_1_SOF_BYTE 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ALIGNERGEN_1_SOF_BYTE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CAPTURESTART 0x00003e08 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_CAPTURESTART__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CAPTURESTART_DPV_CAPTURESTART 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CAPTURESTART_DPV_CAPTURESTART_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG 0x00003e0c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_HOT_RESET 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_HOT_RESET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_STARTTEST 1:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_STARTTEST_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_CFGCLKGATEEN 2:2 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_CFGCLKGATEEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPG_PRBSSEEDLD 3:3 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPG_PRBSSEEDLD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_PRBSALT 4:4 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_PRBSALT_NRZ 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_PRBSALT_PAM4 0x00000001 /* RW--V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_CAPTUREEN 5:5 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_CAPTUREEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_LOOPSYMBOLCNTEN 6:6 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_LOOPSYMBOLCNTEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_BITERRORCHECKEN 7:7 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_BITERRORCHECKEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_BITERRORCOUNTERTHRESHOLD 23:8 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_BITERRORCOUNTERTHRESHOLD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_SYMBOLERRORCHECKEN 24:24 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_SYMBOLERRORCHECKEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPG_DATAREQOVERRIDE 25:25 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPG_DATAREQOVERRIDE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_DATAVALIDOVERRIDE 26:26 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_DATAVALIDOVERRIDE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_MISRON 27:27 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIG_DPV_MISRON_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG 0x00003e10 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_DPG_TXDATAMUXSEL_IN 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_DPG_TXDATAMUXSEL_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_TRAINING_EN_IN 1:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_TRAINING_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_TX_BIST_EN_IN 2:2 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_TX_BIST_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN 3:3 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_DISABLE_WIRED_ENABLE_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_LOOPBACK_IN_CORE_IN 4:4 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_LOOPBACK_IN_CORE_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SPARE_CONFIG_BITS_IN 6:5 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SPARE_CONFIG_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ILA_DATA_CONFIG_BITS_IN 8:7 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ILA_DATA_CONFIG_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ILA_TRIGGER_CONFIG_BITS_IN 10:9 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ILA_TRIGGER_CONFIG_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ENCODER8B10B_EN_IN 11:11 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ENCODER8B10B_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SCRAMBLER_EN_IN 12:12 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SCRAMBLER_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SKIP_EN_IN 13:13 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SKIP_EN_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_XBAR_4_1_IN 14:14 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_XBAR_4_1_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_XBAR_2_1_IN 15:15 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_XBAR_2_1_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_DC_CHAR_IN 16:16 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_DC_CHAR_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_IO_BIST_MODE_IN 17:17 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_IO_BIST_MODE_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_BYP_SYM_ALIGN_IN 18:18 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_BYP_SYM_ALIGN_IN_INIT 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SPARE_SEQUENCE_BITS_IN 20:19 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_SPARE_SEQUENCE_BITS_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ILA_TRIGGER_IOBIST_SEQ_IN 21:21 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_CONFIGREG_ILA_TRIGGER_IOBIST_SEQ_IN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG 0x00003e14 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG_DPV_STOPONERROR 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG_DPV_STOPONERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG_DPV_STOPERRORCOUNT 16:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG_DPV_STOPERRORCOUNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG_DPV_ERROROUTOFLOCKBITCNT 22:17 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCONFIG_DPV_ERROROUTOFLOCKBITCNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT 0x00003e18 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_ERRORCOUNTSTALL 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_ERRORCOUNTSTALL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_LOOPCNT 5:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_LOOPCNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_ERRORCHECKSTART 21:6 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_ERRORCHECKSTART_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_ERRORCHECKINTERVAL 26:22 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORCOUNT_DPV_ERRORCHECKINTERVAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_ERRORMASK 0x00003e1c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_ERRORMASK__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_ERRORMASK_DPV_ERRORBITMASK 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_ERRORMASK_DPV_ERRORBITMASK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG 0x00003e20 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1 0x00003e24 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_PRBS 0x00003e28 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_PRBS__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_PRBS_DPG_PRBSSEED_INIT 0x00000001 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG 0x00003e2c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1 0x00003e30 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_PRBS 0x00003e34 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_PRBS__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_PRBS_DPG_PRBSSEED_INIT 0x01111111 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG 0x00003e38 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1 0x00003e3c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_PRBS 0x00003e40 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_PRBS__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_PRBS_DPG_PRBSSEED_INIT 0x02222221 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG 0x00003e44 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_XORPATTERNBUF 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_XORPATTERNBUF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1 0x00003e48 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_XORENABLE 0:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_XORENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPG_DATASEL 3:1 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPG_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_DATASEL 6:4 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_DATASEL_INIT 0x00000004 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPG_DATAINVERT 7:7 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPG_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_DATAINVERT 8:8 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_DATAINVERT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPG_LANEDISABLE 9:9 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPG_LANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_ERRORLANEDISABLE 10:10 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_ERRORLANEDISABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_ERRORSTATUSCLEAR 11:11 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_CONFIG_1_DPV_ERRORSTATUSCLEAR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_PRBS 0x00003e4c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_PRBS__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_PRBS_DPG_PRBSSEED 30:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_PRBS_DPG_PRBSSEED_INIT 0x03333331 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_0 0x00003e50 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_0__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_0_PATTERNBUF1_0 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_0_PATTERNBUF1_0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_1 0x00003e54 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_1__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_1_PATTERNBUF1_1 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_1_PATTERNBUF1_1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_2 0x00003e58 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_2__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_2_PATTERNBUF1_2 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_2_PATTERNBUF1_2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_3 0x00003e5c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_3__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_3_PATTERNBUF1_3 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_3_PATTERNBUF1_3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_4 0x00003e60 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_4__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_4_PATTERNBUF1_4 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_4_PATTERNBUF1_4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_5 0x00003e64 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_5__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_5_PATTERNBUF1_5 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_5_PATTERNBUF1_5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_6 0x00003e68 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_6__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_6_PATTERNBUF1_6 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_6_PATTERNBUF1_6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_7 0x00003e6c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_7__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_7_PATTERNBUF1_7 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_7_PATTERNBUF1_7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_8 0x00003e70 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_8__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_8_PATTERNBUF1_8 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_8_PATTERNBUF1_8_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_9 0x00003e74 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_9__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_9_PATTERNBUF1_9 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_9_PATTERNBUF1_9_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_10 0x00003e78 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_10__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_10_PATTERNBUF1_10 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_10_PATTERNBUF1_10_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_11 0x00003e7c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_11__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_11_PATTERNBUF1_11 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_11_PATTERNBUF1_11_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_12 0x00003e80 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_12__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_12_PATTERNBUF1_12 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_12_PATTERNBUF1_12_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_13 0x00003e84 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_13__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_13_PATTERNBUF1_13 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_13_PATTERNBUF1_13_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_14 0x00003e88 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_14__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_14_PATTERNBUF1_14 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF1_14_PATTERNBUF1_14_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_0 0x00003e8c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_0__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_0_PATTERNBUF2_0 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_0_PATTERNBUF2_0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_1 0x00003e90 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_1__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_1_PATTERNBUF2_1 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_1_PATTERNBUF2_1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_2 0x00003e94 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_2__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_2_PATTERNBUF2_2 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_2_PATTERNBUF2_2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_3 0x00003e98 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_3__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_3_PATTERNBUF2_3 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_3_PATTERNBUF2_3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_4 0x00003e9c /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_4__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_4_PATTERNBUF2_4 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_4_PATTERNBUF2_4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_5 0x00003ea0 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_5__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_5_PATTERNBUF2_5 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_5_PATTERNBUF2_5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_6 0x00003ea4 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_6__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_6_PATTERNBUF2_6 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_6_PATTERNBUF2_6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_7 0x00003ea8 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_7__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_7_PATTERNBUF2_7 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_7_PATTERNBUF2_7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_8 0x00003eac /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_8__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_8_PATTERNBUF2_8 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_8_PATTERNBUF2_8_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_9 0x00003eb0 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_9__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_9_PATTERNBUF2_9 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_9_PATTERNBUF2_9_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_10 0x00003eb4 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_10__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_10_PATTERNBUF2_10 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_10_PATTERNBUF2_10_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_11 0x00003eb8 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_11__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_11_PATTERNBUF2_11 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_11_PATTERNBUF2_11_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_12 0x00003ebc /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_12__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_12_PATTERNBUF2_12 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_12_PATTERNBUF2_12_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_13 0x00003ec0 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_13__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_13_PATTERNBUF2_13 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_13_PATTERNBUF2_13_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_14 0x00003ec4 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_14__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_14_PATTERNBUF2_14 31:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_PBUF2_14_PATTERNBUF2_14_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_SELECTCONFIG 0x00003ec8 /* RWI4R */
|
|
#define NV_NVLDL_RXIOBIST_SELECTCONFIG__PRIV_LEVEL_MASK 0x00003ff0 /* */
|
|
#define NV_NVLDL_RXIOBIST_SELECTCONFIG_DPV_SELECTLANE 1:0 /* RWIUF */
|
|
#define NV_NVLDL_RXIOBIST_SELECTCONFIG_DPV_SELECTLANE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_0 0x00003ecc /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_0__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_0_DPV_CAPTUREBUF 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_0_DPV_CAPTUREBUF_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_1 0x00003ed0 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_1__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_1_DPV_CAPTUREBUF_1 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_1_DPV_CAPTUREBUF_1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_2 0x00003ed4 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_2__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_2_DPV_CAPTUREBUF_2 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_2_DPV_CAPTUREBUF_2_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_3 0x00003ed8 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_3__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_3_DPV_CAPTUREBUF_3 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_3_DPV_CAPTUREBUF_3_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_4 0x00003edc /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_4__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_4_DPV_CAPTUREBUF_4 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_4_DPV_CAPTUREBUF_4_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_5 0x00003ee0 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_5__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_5_DPV_CAPTUREBUF_5 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_5_DPV_CAPTUREBUF_5_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_6 0x00003ee4 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_6__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_6_DPV_CAPTUREBUF_6 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_6_DPV_CAPTUREBUF_6_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_7 0x00003ee8 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_7__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_7_DPV_CAPTUREBUF_7 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_7_DPV_CAPTUREBUF_7_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_8 0x00003eec /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_8__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_8_DPV_CAPTUREBUF_8 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_8_DPV_CAPTUREBUF_8_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_9 0x00003ef0 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_9__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_9_DPV_CAPTUREBUF_9 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_9_DPV_CAPTUREBUF_9_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_10 0x00003ef4 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_10__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_10_DPV_CAPTUREBUF_10 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_10_DPV_CAPTUREBUF_10_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_11 0x00003ef8 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_11__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_11_DPV_CAPTUREBUF_11 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_11_DPV_CAPTUREBUF_11_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_12 0x00003efc /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_12__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_12_DPV_CAPTUREBUF_12 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_12_DPV_CAPTUREBUF_12_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_13 0x00003f00 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_13__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_13_DPV_CAPTUREBUF_13 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_13_DPV_CAPTUREBUF_13_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_14 0x00003f04 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_14__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_14_DPV_CAPTUREBUF_14 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_CBUF_14_DPV_CAPTUREBUF_14_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS 0x00003f08 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_BITERRORSTATUS 18:18 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_00_STATUS_DPV_BITERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS 0x00003f0c /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_BITERRORSTATUS 18:18 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_01_STATUS_DPV_BITERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS 0x00003f10 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_BITERRORSTATUS 18:18 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_02_STATUS_DPV_BITERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS 0x00003f14 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_ERRORSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_ERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_ERRORLOCKSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_ERRORLOCKSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_ERRORCOUNTER 17:2 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_ERRORCOUNTER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_BITERRORSTATUS 18:18 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LANE_03_STATUS_DPV_BITERRORSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_LOOPCNT 0x00003f18 /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_LOOPCNT__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_LOOPCNT_DPV_LOOPCNTVAL 31:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_LOOPCNT_DPV_LOOPCNTVAL_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_STATUS 0x00003f1c /* R-I4R */
|
|
#define NV_NVLDL_RXIOBIST_STATUS__PRIV_LEVEL_MASK 0x00003ff4 /* */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPG_RUNSTATUS 0:0 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPG_RUNSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPV_RUNSTATUS 1:1 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPV_RUNSTATUS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPV_VERIFYCOMPLETE 2:2 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPV_VERIFYCOMPLETE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPV_ERROROUTOFLOCKCNT 10:3 /* R-IUF */
|
|
#define NV_NVLDL_RXIOBIST_STATUS_DPV_ERROROUTOFLOCKCNT_INIT 0x00000000 /* R-I-V */
|
|
#endif // __ga102_dev_nvldl_ip_h__
|