636 lines
81 KiB
C
636 lines
81 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_nv_aza_pri_h__
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#define __ga102_dev_nv_aza_pri_h__
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/* This file is autogenerated. Do not edit */
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#define NV_AZA_PRI 0x001087ff:0x00108000 /* RW--D */
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#define NV_AZA_PRI_GCAP 0x00108000 /* C--4R */
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#define NV_AZA_PRI_GCAP_MAJ 31:24 /* C--VF */
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#define NV_AZA_PRI_GCAP_MAJ_R1 0x00000001 /* C---V */
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#define NV_AZA_PRI_GCAP_VMIN 23:16 /* C--VF */
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#define NV_AZA_PRI_GCAP_VMIN_R0 0x00000000 /* C---V */
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#define NV_AZA_PRI_GCAP_OSS 15:12 /* C--VF */
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#define NV_AZA_PRI_GCAP_OSS_FOUR 0x00000004 /* C---V */
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#define NV_AZA_PRI_GCAP_ISS 11:8 /* C--VF */
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#define NV_AZA_PRI_GCAP_ISS_FOUR 0x00000004 /* C---V */
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#define NV_AZA_PRI_GCAP_BSS 7:3 /* C--VF */
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#define NV_AZA_PRI_GCAP_BSS_ZERO 0x00000000 /* C---V */
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#define NV_AZA_PRI_GCAP_NSDO 2:1 /* C--VF */
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#define NV_AZA_PRI_GCAP_NSDO_FOUR 0x00000002 /* C---V */
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#define NV_AZA_PRI_GCAP_64BIT_OK 0:0 /* C--VF */
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#define NV_AZA_PRI_GCAP_64BIT_OK_YES 0x00000001 /* C---V */
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#define NV_AZA_PRI_OUTPAY 0x00108004 /* C--4R */
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#define NV_AZA_PRI_OUTPAY_INPAY 22:16 /* C--VF */
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#define NV_AZA_PRI_OUTPAY_INPAY_29WORDS 0x0000001d /* C---V */
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#define NV_AZA_PRI_OUTPAY_OUTPAY 6:0 /* C--VF */
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#define NV_AZA_PRI_OUTPAY_OUTPAY_60WORDS 0x0000003c /* C---V */
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#define NV_AZA_PRI_GCTL 0x00108008 /* RW-4R */
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#define NV_AZA_PRI_GCTL_UNSOL 8:8 /* RWIVF */
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#define NV_AZA_PRI_GCTL_UNSOL_NOT_ACCEPTED 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_GCTL_UNSOL_ACCEPTED 0x00000001 /* RW--V */
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#define NV_AZA_PRI_GCTL_FCNTRL 1:1 /* RWIVF */
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#define NV_AZA_PRI_GCTL_FCNTRL_DONT_INITIATE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_GCTL_FCNTRL_INITIATE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_GCTL_CRST 0:0 /* RWIVF */
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#define NV_AZA_PRI_GCTL_CRST_ASSERT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_GCTL_CRST_DEASSERT 0x00000001 /* RW--V */
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#define NV_AZA_PRI_WAKEEN 0x0010800c /* RW-4R */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE3 19:19 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE3_NOWAKE 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE3_WAKE 0x00000001 /* R---V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE3_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE2 18:18 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE2_NOWAKE 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE2_WAKE 0x00000001 /* R---V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE2_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE1 17:17 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE1_NOWAKE 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE1_WAKE 0x00000001 /* R---V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE1_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE0 16:16 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE0_NOWAKE 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE0_WAKE 0x00000001 /* R---V */
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#define NV_AZA_PRI_WAKEEN_SDIWAKE0_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_WAKEEN_SDIWEN3 3:3 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWEN3_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_WAKEEN_SDIWEN3_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_WAKEEN_SDIWEN2 2:2 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWEN2_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_WAKEEN_SDIWEN2_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_WAKEEN_SDIWEN1 1:1 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWEN1_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_WAKEEN_SDIWEN1_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_WAKEEN_SDIWEN0 0:0 /* RWIVF */
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#define NV_AZA_PRI_WAKEEN_SDIWEN0_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_WAKEEN_SDIWEN0_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_GSTS 0x00108010 /* RW-4R */
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#define NV_AZA_PRI_GSTS_FSTS 1:1 /* RWIVF */
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#define NV_AZA_PRI_GSTS_FSTS_NOFLUSH 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_GSTS_FSTS_FLUSH 0x00000001 /* R---V */
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#define NV_AZA_PRI_GSTS_FSTS_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_OUTSTRMPAY 0x00108018 /* C--4R */
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#define NV_AZA_PRI_OUTSTRMPAY_INSTRMPAY 31:16 /* C--VF */
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#define NV_AZA_PRI_OUTSTRMPAY_INSTRMPAY_NOLIMIT 0x00000000 /* C---V */
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#define NV_AZA_PRI_OUTSTRMPAY_OUTSTRMPAY 15:0 /* C--VF */
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#define NV_AZA_PRI_OUTSTRMPAY_OUTSTRMPAY_NOLIMIT 0x00000000 /* C---V */
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#define NV_AZA_PRI_INTCTL 0x00108020 /* RW-4R */
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#define NV_AZA_PRI_INTCTL_GIE 31:31 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_GIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_GIE_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_CIE 30:30 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_CIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_CIE_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE7 7:7 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE7_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE7_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE6 6:6 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE6_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE6_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE5 5:5 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE5_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE5_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE4 4:4 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE4_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE4_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE3 3:3 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE3_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE3_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE2 2:2 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE2_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE2_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE1 1:1 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE1_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE1_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTCTL_SIE0 0:0 /* RWIVF */
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#define NV_AZA_PRI_INTCTL_SIE0_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_INTCTL_SIE0_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_INTSTS 0x00108024 /* R--4R */
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#define NV_AZA_PRI_INTSTS_GIS 31:31 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_GIS_NO_INTR 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_GIS_INTR 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_CIS 30:30 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_CIS_NO_INTR 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_CIS_INTR 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS7 7:7 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS7_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS7_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS6 6:6 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS6_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS6_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS5 5:5 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS5_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS5_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS4 4:4 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS4_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS4_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS3 3:3 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS3_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS3_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS2 2:2 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS2_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS2_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS1 1:1 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS1_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS1_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_INTSTS_SIS0 0:0 /* R-IVF */
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#define NV_AZA_PRI_INTSTS_SIS0_NOINT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_INTSTS_SIS0_INT 0x00000001 /* R---V */
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#define NV_AZA_PRI_WALCLK 0x00108030 /* R--4R */
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#define NV_AZA_PRI_WALCLK_COUNTER 31:0 /* R-IVF */
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#define NV_AZA_PRI_WALCLK_COUNTER_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_SSYNC 0x00108038 /* RW-4R */
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#define NV_AZA_PRI_SSYNC_SSYNC7 7:7 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC7_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC7_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SSYNC_SSYNC6 6:6 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC6_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC6_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SSYNC_SSYNC5 5:5 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC5_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC5_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SSYNC_SSYNC4 4:4 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC4_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC4_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SSYNC_SSYNC3 3:3 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC3_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC3_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SSYNC_SSYNC2 2:2 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC2_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC2_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SSYNC_SSYNC1 1:1 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC1_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC1_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SSYNC_SSYNC0 0:0 /* RWIVF */
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#define NV_AZA_PRI_SSYNC_SSYNC0_NOBLOCK 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SSYNC_SSYNC0_BLOCK 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CORBLBASE 0x00108040 /* RW-4R */
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#define NV_AZA_PRI_CORBLBASE_CORBLBASE 31:7 /* RWIVF */
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#define NV_AZA_PRI_CORBLBASE_CORBLBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CORBUBASE 0x00108044 /* RW-4R */
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#define NV_AZA_PRI_CORBUBASE_CORBUBASE 31:0 /* RWIVF */
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#define NV_AZA_PRI_CORBUBASE_CORBUBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CORBWP 0x00108048 /* RW-4R */
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#define NV_AZA_PRI_CORBWP_RST 31:31 /* -WIVF */
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#define NV_AZA_PRI_CORBWP_RST_INIT 0x00000000 /* --I-V */
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#define NV_AZA_PRI_CORBWP_CORBRP 23:16 /* R-IVF */
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#define NV_AZA_PRI_CORBWP_CORBRP_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CORBWP_CORBWP 7:0 /* RWIVF */
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#define NV_AZA_PRI_CORBWP_CORBWP_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CORBCTL 0x0010804c /* RW-4R */
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#define NV_AZA_PRI_CORBCTL_CORBSZCAP 23:20 /* C--VF */
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#define NV_AZA_PRI_CORBCTL_CORBSZCAP_INIT 0x00000004 /* C---V */
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#define NV_AZA_PRI_CORBCTL_CORBSIZE 17:16 /* C--VF */
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#define NV_AZA_PRI_CORBCTL_CORBSIZE_256ENTRIES 0x00000002 /* C---V */
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#define NV_AZA_PRI_CORBCTL_CMEI 8:8 /* RWIVF */
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#define NV_AZA_PRI_CORBCTL_CMEI_NOERROR 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CORBCTL_CMEI_ERROR 0x00000001 /* R---V */
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#define NV_AZA_PRI_CORBCTL_CMEI_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_CORBCTL_CORBRUN 1:1 /* RWIVF */
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#define NV_AZA_PRI_CORBCTL_CORBRUN_STOP 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CORBCTL_CORBRUN_RUN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CORBCTL_CMEIE 0:0 /* RWIVF */
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#define NV_AZA_PRI_CORBCTL_CMEIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CORBCTL_CMEIE_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_RIRBLBASE 0x00108050 /* RW-4R */
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#define NV_AZA_PRI_RIRBLBASE_RIRBLBASE 31:7 /* RWIVF */
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#define NV_AZA_PRI_RIRBLBASE_RIRBLBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_RIRBUBASE 0x00108054 /* RW-4R */
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#define NV_AZA_PRI_RIRBUBASE_RIRBUBASE 31:0 /* RWIVF */
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#define NV_AZA_PRI_RIRBUBASE_RIRBUBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_RIRBWP 0x00108058 /* RW-4R */
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#define NV_AZA_PRI_RIRBWP_RINTCNT 23:16 /* RWIVF */
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#define NV_AZA_PRI_RIRBWP_RINTCNT_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_RIRBWP_RIRBWPRST 15:15 /* -WIVF */
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#define NV_AZA_PRI_RIRBWP_RIRBWPRST_INIT 0x00000000 /* C---V */
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#define NV_AZA_PRI_RIRBWP_RIRBWPRST_RESET_WP 0x00000001 /* -W--V */
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#define NV_AZA_PRI_RIRBWP_RIRBWP 7:0 /* R-IVF */
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#define NV_AZA_PRI_RIRBWP_RIRBWP_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_RIRBCTL 0x0010805c /* RW-4R */
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#define NV_AZA_PRI_RIRBCTL_RIRBSZCAP 23:20 /* C--VF */
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#define NV_AZA_PRI_RIRBCTL_RIRBSZCAP_INIT 0x00000004 /* C---V */
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#define NV_AZA_PRI_RIRBCTL_RIRBSIZE 17:16 /* C--VF */
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#define NV_AZA_PRI_RIRBCTL_RIRBSIZE_256ENTRIES 0x00000002 /* C---V */
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#define NV_AZA_PRI_RIRBCTL_RIRBOIS 10:10 /* RWIVF */
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#define NV_AZA_PRI_RIRBCTL_RIRBOIS_NOOVERRUN 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_RIRBCTL_RIRBOIS_OVERRUN 0x00000001 /* R---V */
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#define NV_AZA_PRI_RIRBCTL_RIRBOIS_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_RIRBCTL_RINTFL 8:8 /* RWIVF */
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#define NV_AZA_PRI_RIRBCTL_RINTFL_NORESPONSE 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_RIRBCTL_RINTFL_RESPONSE 0x00000001 /* R---V */
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#define NV_AZA_PRI_RIRBCTL_RINTFL_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_RIRBCTL_RIRBOIC 2:2 /* RWIVF */
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#define NV_AZA_PRI_RIRBCTL_RIRBOIC_NOINTR 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_RIRBCTL_RIRBOIC_INTR 0x00000001 /* RW--V */
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#define NV_AZA_PRI_RIRBCTL_RIRBDMAEN 1:1 /* RWIVF */
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#define NV_AZA_PRI_RIRBCTL_RIRBDMAEN_STOP 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_RIRBCTL_RIRBDMAEN_RUN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_RIRBCTL_RINTCTL 0:0 /* RWIVF */
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#define NV_AZA_PRI_RIRBCTL_RINTCTL_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_RIRBCTL_RINTCTL_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_ICOI 0x00108060 /* -W-4R */
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#define NV_AZA_PRI_ICOI_ICW 31:0 /* -WIVF */
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#define NV_AZA_PRI_ICOI_ICW_INIT 0x00000000 /* -WI-V */
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#define NV_AZA_PRI_IRII 0x00108064 /* R--4R */
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#define NV_AZA_PRI_IRII_IRR 31:0 /* R-IVF */
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#define NV_AZA_PRI_IRII_IRR_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_ICS 0x00108068 /* RW-4R */
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#define NV_AZA_PRI_ICS_IRRADD 7:4 /* R-IVF */
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#define NV_AZA_PRI_ICS_IRRADD_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_ICS_IRRUNSOL 3:3 /* R-IVF */
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#define NV_AZA_PRI_ICS_IRRUNSOL_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_ICS_ICVER 2:2 /* R-IVF */
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#define NV_AZA_PRI_ICS_ICVER_DEFAULT 0x00000001 /* R---V */
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#define NV_AZA_PRI_ICS_ICVER_REV_CYA_OFF 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_ICS_IRV 1:1 /* RWIVF */
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#define NV_AZA_PRI_ICS_IRV_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_ICS_IRV_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_ICS_ICB 0:0 /* R-IVF */
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#define NV_AZA_PRI_ICS_ICB_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_DPLBASE 0x00108070 /* RW-4R */
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#define NV_AZA_PRI_DPLBASE_DPLBASE 31:7 /* RWIVF */
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#define NV_AZA_PRI_DPLBASE_DPLBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_DPLBASE_ENABLE 0:0 /* RWIVF */
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#define NV_AZA_PRI_DPLBASE_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_DPUBASE 0x00108074 /* RW-4R */
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#define NV_AZA_PRI_DPUBASE_DPUBASE 31:0 /* RWIVF */
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#define NV_AZA_PRI_DPUBASE_DPUBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL(i) (0x00108080+(i)*32) /* RW-4A */
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#define NV_AZA_PRI_SDCTL__SIZE_1 8 /* */
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#define NV_AZA_PRI_SDCTL_FIFORDY 29:29 /* R-IVF */
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#define NV_AZA_PRI_SDCTL_FIFORDY_NOTREADY 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_SDCTL_FIFORDY_READY 0x00000001 /* R---V */
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#define NV_AZA_PRI_SDCTL_DESE 28:28 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_DESE_NOERROR 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_SDCTL_DESE_ERROR 0x00000001 /* R---V */
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#define NV_AZA_PRI_SDCTL_DESE_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_SDCTL_FIFOE 27:27 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_FIFOE_NOERROR 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_SDCTL_FIFOE_ERROR 0x00000001 /* R---V */
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#define NV_AZA_PRI_SDCTL_FIFOE_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_SDCTL_BCIS 26:26 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_BCIS_NOTCOMPLETE 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_SDCTL_BCIS_COMPLETE 0x00000001 /* R---V */
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#define NV_AZA_PRI_SDCTL_BCIS_W1C 0x00000001 /* -W--C */
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#define NV_AZA_PRI_SDCTL_STRM 23:20 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_STRM_UNUSED 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_DIR 19:19 /* C--VF */
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#define NV_AZA_PRI_SDCTL_DIR_UNIDIR 0x00000000 /* C---V */
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#define NV_AZA_PRI_SDCTL_TP 18:18 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_TP_LOW 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_TP_HIGH 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDCTL_STRIPE 17:16 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_STRIPE_1SDO 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_STRIPE_2SDO 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDCTL_STRIPE_4SDO 0x00000002 /* RW--V */
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#define NV_AZA_PRI_SDCTL_DEIE 4:4 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_DEIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_DEIE_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDCTL_FEIE 3:3 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_FEIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_FEIE_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDCTL_IOCE 2:2 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_IOCE_DISABLE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_IOCE_ENABLE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDCTL_RUN 1:1 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_RUN_STOP 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_RUN_RUN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDCTL_SRST 0:0 /* RWIVF */
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#define NV_AZA_PRI_SDCTL_SRST_NOTRESET 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDCTL_SRST_RESET 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDPICB(i) (0x00108084+(i)*32) /* R--4A */
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#define NV_AZA_PRI_SDPICB__SIZE_1 8 /* */
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#define NV_AZA_PRI_SDPICB_LPIB 31:0 /* R-IVF */
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#define NV_AZA_PRI_SDPICB_LPIB_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_SDCBL(i) (0x00108088+(i)*32) /* RW-4A */
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#define NV_AZA_PRI_SDCBL__SIZE_1 8 /* */
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#define NV_AZA_PRI_SDCBL_CBL 31:0 /* RWIVF */
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#define NV_AZA_PRI_SDCBL_CBL_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDLVI(i) (0x0010808c+(i)*32) /* RW-4A */
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#define NV_AZA_PRI_SDLVI__SIZE_1 8 /* */
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#define NV_AZA_PRI_SDLVI_LVI 7:0 /* RWIVF */
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#define NV_AZA_PRI_SDLVI_LVI_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDFMT(i) (0x00108090+(i)*32) /* RW-4A */
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#define NV_AZA_PRI_SDFMT__SIZE_1 8 /* */
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#define NV_AZA_PRI_SDFMT_BASE 30:30 /* RWIVF */
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#define NV_AZA_PRI_SDFMT_BASE_48KHZ 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDFMT_BASE_44KHZ 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDFMT_MULT 29:27 /* RWIVF */
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#define NV_AZA_PRI_SDFMT_MULT_X1 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDFMT_MULT_X2 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDFMT_MULT_X3 0x00000002 /* RW--V */
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#define NV_AZA_PRI_SDFMT_MULT_X4 0x00000003 /* RW--V */
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#define NV_AZA_PRI_SDFMT_DIV 26:24 /* RWIVF */
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#define NV_AZA_PRI_SDFMT_DIV_X1 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDFMT_DIV_X2 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDFMT_DIV_X3 0x00000002 /* RW--V */
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#define NV_AZA_PRI_SDFMT_DIV_X4 0x00000003 /* RW--V */
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#define NV_AZA_PRI_SDFMT_DIV_X5 0x00000004 /* RW--V */
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#define NV_AZA_PRI_SDFMT_DIV_X6 0x00000005 /* RW--V */
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#define NV_AZA_PRI_SDFMT_DIV_X7 0x00000006 /* RW--V */
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#define NV_AZA_PRI_SDFMT_DIV_X8 0x00000007 /* RW--V */
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#define NV_AZA_PRI_SDFMT_BITS 22:20 /* RWIVF */
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#define NV_AZA_PRI_SDFMT_BITS_8BITS 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDFMT_BITS_16BITS 0x00000001 /* RW--V */
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#define NV_AZA_PRI_SDFMT_BITS_20BITS 0x00000002 /* RW--V */
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#define NV_AZA_PRI_SDFMT_BITS_24BITS 0x00000003 /* RW--V */
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#define NV_AZA_PRI_SDFMT_BITS_32BITS 0x00000004 /* RW--V */
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#define NV_AZA_PRI_SDFMT_CHAN 19:16 /* RWIVF */
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#define NV_AZA_PRI_SDFMT_CHAN_1CHAN 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDFMT_FIFOS 15:0 /* R-IVF */
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#define NV_AZA_PRI_SDFMT_FIFOS_INIT 0x00000028 /* R-I-V */
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#define NV_AZA_PRI_SDBDPL(i) (0x00108098+(i)*32) /* RW-4A */
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#define NV_AZA_PRI_SDBDPL__SIZE_1 8 /* */
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#define NV_AZA_PRI_SDBDPL_BDLLBASE 31:7 /* RWIVF */
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#define NV_AZA_PRI_SDBDPL_BDLLBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_SDBDPU(i) (0x0010809c+(i)*32) /* RW-4A */
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#define NV_AZA_PRI_SDBDPU__SIZE_1 8 /* */
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#define NV_AZA_PRI_SDBDPU_BDLUBASE 31:0 /* RWIVF */
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#define NV_AZA_PRI_SDBDPU_BDLUBASE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT 0x00108700 /* RW-4R */
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#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_PW_REQ_THREAD 4:0 /* RWIVF */
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#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_PW_REQ_THREAD_INIT 0x0000000c /* RWI-V */
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#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_NP_REQ_THREAD 12:8 /* RWIVF */
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#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_NP_REQ_THREAD_INIT 0x0000000c /* RWI-V */
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#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_RSP_THREAD 20:16 /* RWIVF */
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#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_RSP_THREAD_INIT 0x0000000c /* RWI-V */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME 0x00108704 /* R--4R */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR0 7:0 /* R-IVF */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR0_INIT 0x00000001 /* R-I-V */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR1 15:8 /* R-IVF */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR1_INIT 0x00000001 /* R-I-V */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR2 23:16 /* R-IVF */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR2_INIT 0x00000001 /* R-I-V */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR3 31:24 /* R-IVF */
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#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR3_INIT 0x00000001 /* R-I-V */
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#define NV_AZA_PRI_CYA2_1_STR_WR_CNT 0x00108708 /* R--4R */
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#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR0 14:0 /* R-IVF */
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#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR0_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR1 30:16 /* R-IVF */
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#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR1_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA2_2_STR_WR_CNT 0x00108744 /* R--4R */
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#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR2 14:0 /* R-IVF */
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#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR2_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR3 30:16 /* R-IVF */
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#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR3_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN 0x0010870c /* RW-4R */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR0 0:0 /* RWIVF */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR0_DIS 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR0_EN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR1 8:8 /* RWIVF */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR1_DIS 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR1_EN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR2 16:16 /* RWIVF */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR2_DIS 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR2_EN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR3 24:24 /* RWIVF */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR3_DIS 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR3_EN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR 0x00108710 /* R--4R */
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#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR0 15:0 /* R-IVF */
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#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR0_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR1 31:16 /* R-IVF */
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#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR1_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR 0x00108740 /* R--4R */
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#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR2 15:0 /* R-IVF */
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#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR2_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR3 31:16 /* R-IVF */
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#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR3_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK 0x00108714 /* RW-4R */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0 2:0 /* RWIVF */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_100_PERCENT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_88_PERCENT 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_75_PERCENT 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_63_PERCENT 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_50_PERCENT 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_38_PERCENT 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_25_PERCENT 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_13_PERCENT 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1 10:8 /* RWIVF */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_100_PERCENT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_88_PERCENT 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_75_PERCENT 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_63_PERCENT 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_50_PERCENT 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_38_PERCENT 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_25_PERCENT 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_13_PERCENT 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2 18:16 /* RWIVF */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_100_PERCENT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_88_PERCENT 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_75_PERCENT 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_63_PERCENT 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_50_PERCENT 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_38_PERCENT 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_25_PERCENT 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_13_PERCENT 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3 26:24 /* RWIVF */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_100_PERCENT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_88_PERCENT 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_75_PERCENT 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_63_PERCENT 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_50_PERCENT 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_38_PERCENT 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_25_PERCENT 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_13_PERCENT 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE 0x00108718 /* RW-4R */
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#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE 1:0 /* RWIVF */
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#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_128BYTE 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_64BYTE 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_32BYTE 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_16BYTE 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY 0x0010871c /* RW-4R */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_THRESHOLD 11:0 /* RWIVF */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_THRESHOLD_INIT 0x000008c9 /* RWI-V */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC 16:16 /* RWIVF */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC_EN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC_DIS 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL 17:17 /* RWIVF */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL_EN 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL_DIS 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ 0x00108720 /* RW-4R */
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#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ_FREQ 0:0 /* RWIVF */
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#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ_FREQ_108MHZ 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ_FREQ_48MHZ 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT 0x00108724 /* RW-4R */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT 5:0 /* RWIVF */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_0 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_1 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_2 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_3 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_4 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_5 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_6 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_7 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_8 0x00000008 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_9 0x00000009 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_10 0x0000000a /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_11 0x0000000b /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_12 0x0000000c /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_13 0x0000000d /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_14 0x0000000e /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_15 0x0000000f /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_16 0x00000010 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_17 0x00000011 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_18 0x00000012 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_19 0x00000013 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_20 0x00000014 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_21 0x00000015 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_22 0x00000016 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_23 0x00000017 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_24 0x00000018 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_25 0x00000019 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_26 0x0000001a /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_27 0x0000001b /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_28 0x0000001c /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_29 0x0000001d /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_30 0x0000001e /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_31 0x0000001f /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_32 0x00000020 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_33 0x00000021 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_34 0x00000022 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_35 0x00000023 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_36 0x00000024 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_37 0x00000025 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_38 0x00000026 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_39 0x00000027 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_40 0x00000028 /* RW--V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_INT_CRST_NOCLR 7:7 /* RWIVF */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_INT_CRST_NOCLR_EN 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_INT_CRST_NOCLR_DIS 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAA_COH 0x00108728 /* RW-4R */
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#define NV_AZA_PRI_CYAA_COH_BDL 0:0 /* RWIVF */
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#define NV_AZA_PRI_CYAA_COH_BDL_NONCOHERENT 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAA_COH_BDL_COHERENT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_CYAA_COH_CORB 1:1 /* RWIVF */
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#define NV_AZA_PRI_CYAA_COH_CORB_NONCOHERENT 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAA_COH_CORB_COHERENT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_CYAA_COH_OSTRM 2:2 /* RWIVF */
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#define NV_AZA_PRI_CYAA_COH_OSTRM_NONCOHERENT 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAA_COH_OSTRM_COHERENT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_CYAA_COH_DPIB 3:3 /* RWIVF */
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#define NV_AZA_PRI_CYAA_COH_DPIB_NONCOHERENT 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAA_COH_DPIB_COHERENT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_CYAA_COH_ISTRM 4:4 /* RWIVF */
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#define NV_AZA_PRI_CYAA_COH_ISTRM_NONCOHERENT 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAA_COH_ISTRM_COHERENT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_CYAA_COH_RIRB 5:5 /* RWIVF */
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#define NV_AZA_PRI_CYAA_COH_RIRB_NONCOHERENT 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAA_COH_RIRB_COHERENT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_CYAB_IDLE_STRETCH 0x0010872c /* RW-4R */
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#define NV_AZA_PRI_CYAB_IDLE_STRETCH_VALUE 31:0 /* RWIVF */
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#define NV_AZA_PRI_CYAB_IDLE_STRETCH_VALUE_INIT 0x00000014 /* RWI-V */
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#define NV_AZA_PRI_CYAC_RINTFL_DELAY 0x00108730 /* RW-4R */
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#define NV_AZA_PRI_CYAC_RINTFL_DELAY_VALUE 15:0 /* RWIVF */
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#define NV_AZA_PRI_CYAC_RINTFL_DELAY_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK 0x00108748 /* RW-4R */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0 2:0 /* RWIVF */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_INIT 0x00000004 /* RWI-V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_1_FRAME 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_2_FRAMES 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_4_FRAMES 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_8_FRAMES 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_16_FRAMES 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_32_FRAMES 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_64_FRAMES 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_FULL 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1 10:8 /* RWIVF */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_INIT 0x00000004 /* RWI-V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_1_FRAME 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_2_FRAMES 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_4_FRAMES 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_8_FRAMES 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_16_FRAMES 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_32_FRAMES 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_64_FRAMES 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_FULL 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2 18:16 /* RWIVF */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_INIT 0x00000004 /* RWI-V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_1_FRAME 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_2_FRAMES 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_4_FRAMES 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_8_FRAMES 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_16_FRAMES 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_32_FRAMES 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_64_FRAMES 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_FULL 0x00000007 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3 26:24 /* RWIVF */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_INIT 0x00000004 /* RWI-V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_1_FRAME 0x00000000 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_2_FRAMES 0x00000001 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_4_FRAMES 0x00000002 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_8_FRAMES 0x00000003 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_16_FRAMES 0x00000004 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_32_FRAMES 0x00000005 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_64_FRAMES 0x00000006 /* RW--V */
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#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_FULL 0x00000007 /* RW--V */
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#define NV_AZA_PRI_SYNCH_BCLK_ADJ 0x00108734 /* RW-4R */
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#define NV_AZA_PRI_SYNCH_BCLK_ADJ_N_VAL 15:0 /* RWIVF */
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#define NV_AZA_PRI_SYNCH_BCLK_ADJ_N_VAL_INIT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_SYNCH_BCLK_ADJ_M_VAL 31:16 /* RWIVF */
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#define NV_AZA_PRI_SYNCH_BCLK_ADJ_M_VAL_INIT 0x00000001 /* RWI-V */
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#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS 0x00108738 /* R--4R */
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#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRAME_CNT 19:0 /* R-IVF */
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#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRAME_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRACT_CNT 31:20 /* R-IVF */
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#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRACT_CNT_INIT 0x00000002 /* R-I-V */
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#define NV_AZA_PRI_STR0_FIFO_ADDR 0x00108760 /* RW-4R */
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#define NV_AZA_PRI_STR0_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
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#define NV_AZA_PRI_STR0_FIFO_ADDR_START_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_AZA_PRI_STR0_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
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#define NV_AZA_PRI_STR0_FIFO_ADDR_END_ADDR_INIT 0x0000057f /* RWI-V */
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#define NV_AZA_PRI_STR1_FIFO_ADDR 0x00108764 /* RW-4R */
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#define NV_AZA_PRI_STR1_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
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#define NV_AZA_PRI_STR1_FIFO_ADDR_START_ADDR_INIT 0x00000580 /* RWI-V */
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#define NV_AZA_PRI_STR1_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
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#define NV_AZA_PRI_STR1_FIFO_ADDR_END_ADDR_INIT 0x00000aff /* RWI-V */
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#define NV_AZA_PRI_STR2_FIFO_ADDR 0x00108768 /* RW-4R */
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#define NV_AZA_PRI_STR2_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
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#define NV_AZA_PRI_STR2_FIFO_ADDR_START_ADDR_INIT 0x00000b00 /* RWI-V */
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#define NV_AZA_PRI_STR2_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
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#define NV_AZA_PRI_STR2_FIFO_ADDR_END_ADDR_INIT 0x0000107f /* RWI-V */
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#define NV_AZA_PRI_STR3_FIFO_ADDR 0x0010876c /* RW-4R */
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#define NV_AZA_PRI_STR3_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
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#define NV_AZA_PRI_STR3_FIFO_ADDR_START_ADDR_INIT 0x00001080 /* RWI-V */
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#define NV_AZA_PRI_STR3_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
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#define NV_AZA_PRI_STR3_FIFO_ADDR_END_ADDR_INIT 0x000015ff /* RWI-V */
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#define NV_AZA_PRI_DYNAMIC_STR_ADDR 0x00108770 /* RW-4R */
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#define NV_AZA_PRI_DYNAMIC_STR_ADDR_EN 0:0 /* RWIVF */
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#define NV_AZA_PRI_DYNAMIC_STR_ADDR_EN_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAE_IB_SDI0_FIFO 0x00108774 /* R--4R */
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#define NV_AZA_PRI_CYAE_IB_SDI0_FIFO_WR_CNT 3:0 /* R-IVF */
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#define NV_AZA_PRI_CYAE_IB_SDI0_FIFO_WR_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM 0x00108778 /* R--4R */
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#define NV_AZA_PRI_CYAF_AZA_SM_SA_STATE 31:29 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_SA_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR3_REQ_STATE 28:27 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR3_REQ_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR2_REQ_STATE 26:25 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR2_REQ_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR1_REQ_STATE 24:23 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR1_REQ_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR0_REQ_STATE 22:21 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_STR0_REQ_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_GRANT_STATE 20:16 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_GRANT_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_DMA_STATE 14:12 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_DMA_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB3_BDL_STATE 11:9 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB3_BDL_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB2_BDL_STATE 8:6 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB2_BDL_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB1_BDL_STATE 5:3 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB1_BDL_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB0_BDL_STATE 2:0 /* R-IVF */
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#define NV_AZA_PRI_CYAF_AZA_SM_OB0_BDL_STATE_INIT 0x00000000 /* R-I-V */
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#endif // __ga102_dev_nv_aza_pri_h__
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