1120 lines
116 KiB
C
1120 lines
116 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_chiplet_ism_h__
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#define __ga102_dev_chiplet_ism_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PCHIPLET_ISM 0x001ff1ff:0x001fd000 /* RW--D */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fd0fc /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR 0x001fd000 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fd0fc /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_WDATA 0x001fd004 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fd0fc /* */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_RDATA 0x001fd008 /* R--4R */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_STATUS 0x001fd00c /* R--4R */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_FBP0_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fd1fc /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR 0x001fd100 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fd1fc /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_WDATA 0x001fd104 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fd1fc /* */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_RDATA 0x001fd108 /* R--4R */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_STATUS 0x001fd10c /* R--4R */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_FBP1_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fd2fc /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR 0x001fd200 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fd2fc /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_WDATA 0x001fd204 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fd2fc /* */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_RDATA 0x001fd208 /* R--4R */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_STATUS 0x001fd20c /* R--4R */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_FBP2_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fd3fc /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR 0x001fd300 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fd3fc /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_WDATA 0x001fd304 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fd3fc /* */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_RDATA 0x001fd308 /* R--4R */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_STATUS 0x001fd30c /* R--4R */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_FBP3_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fd4fc /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR 0x001fd400 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fd4fc /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_WDATA 0x001fd404 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fd4fc /* */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_RDATA 0x001fd408 /* R--4R */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_STATUS 0x001fd40c /* R--4R */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_FBP4_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fd5fc /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR 0x001fd500 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fd5fc /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_WDATA 0x001fd504 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fd5fc /* */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_RDATA 0x001fd508 /* R--4R */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_STATUS 0x001fd50c /* R--4R */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_FBP5_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001ff0fc /* RW-4R */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR 0x001ff000 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001ff0fc /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_WDATA 0x001ff004 /* RW-4R */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001ff0fc /* */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_RDATA 0x001ff008 /* R--4R */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_STATUS 0x001ff00c /* R--4R */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_FBPS_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPC 0x001fe6ff:0x001fe000 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC0 0x001fe0ff:0x001fe000 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fe0fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR 0x001fe000 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fe0fc /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_WDATA 0x001fe004 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fe0fc /* */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_RDATA 0x001fe008 /* R--4R */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_STATUS 0x001fe00c /* R--4R */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPC0_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPC1 0x001fe1ff:0x001fe100 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fe1fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR 0x001fe100 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fe1fc /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_WDATA 0x001fe104 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fe1fc /* */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_RDATA 0x001fe108 /* R--4R */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_STATUS 0x001fe10c /* R--4R */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPC1_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPC2 0x001fe2ff:0x001fe200 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fe2fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR 0x001fe200 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fe2fc /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_WDATA 0x001fe204 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fe2fc /* */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_RDATA 0x001fe208 /* R--4R */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_STATUS 0x001fe20c /* R--4R */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPC2_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPC3 0x001fe3ff:0x001fe300 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fe3fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR 0x001fe300 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fe3fc /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_WDATA 0x001fe304 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fe3fc /* */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_RDATA 0x001fe308 /* R--4R */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_STATUS 0x001fe30c /* R--4R */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPC3_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPC4 0x001fe4ff:0x001fe400 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fe4fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR 0x001fe400 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fe4fc /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_WDATA 0x001fe404 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fe4fc /* */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_RDATA 0x001fe408 /* R--4R */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_STATUS 0x001fe40c /* R--4R */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPC4_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPC5 0x001fe5ff:0x001fe500 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fe5fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR 0x001fe500 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fe5fc /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_WDATA 0x001fe504 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fe5fc /* */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_RDATA 0x001fe508 /* R--4R */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_STATUS 0x001fe50c /* R--4R */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPC5_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPC6 0x001fe6ff:0x001fe600 /* RW--L */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001fe6fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR 0x001fe600 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001fe6fc /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_WDATA 0x001fe604 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001fe6fc /* */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_RDATA 0x001fe608 /* R--4R */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_STATUS 0x001fe60c /* R--4R */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPC6_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#define NV_PCHIPLET_ISM_GPCS 0x001ff1ff:0x001ff100 /* RW--L */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK 0x001ff1fc /* RW-4R */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ism" /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0xf /* RWE-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWE-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWE-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR 0x001ff100 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR__PRIV_LEVEL_MASK 0x001ff1fc /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_REG 3:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_REG_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_MACRO 6:4 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_MACRO_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PARTITION 10:7 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_PARTITION_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_BRANCH 12:11 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_BRANCH_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_HUB 16:13 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_ADDR_HUB_INIT 0x0 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_WDATA 0x001ff104 /* RW-4R */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_WDATA__PRIV_LEVEL_MASK 0x001ff1fc /* */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_WDATA_VALUE 15:0 /* RWIUF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_WDATA_VALUE_INIT 0x0000 /* RWI-V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_RDATA 0x001ff108 /* R--4R */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_RDATA_VALUE 15:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_RDATA_VALUE_INIT 0x0000 /* R---V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_STATUS 0x001ff10c /* R--4R */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_STATUS_VALUE 1:0 /* R--UF */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_STATUS_VALUE_INIT 0x0 /* R---V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_STATUS_VALUE_HUB_ADDR_ERR 0x1 /* R---V */
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#define NV_PCHIPLET_ISM_GPCS_PRIV_ACCESS_STATUS_VALUE_BRANCH_OR_PARTITION_ADDR_ERR 0x2 /* R---V */
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#endif // __ga102_dev_chiplet_ism_h__
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