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Ole Algoritme
2022-09-05 21:52:22 +02:00
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227
include/ampere/ga102/bootrom_api_parameters.h Normal file
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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
/* This file is autogenerated by ref2h.pl. Do not edit */
#ifndef BOOTROM_FUSEKEY_PARAS_H
#define BOOTROM_FUSEKEY_PARAS_H
#define AES_128_KEY_LEN_IN_BYTES 16u
#define AES_128_SIG_LEN_IN_BYTES AES_128_KEY_LEN_IN_BYTES
#define PROTECTINFO_LEN_IN_BYTES 4u
#define SECRET_FOR_FUSEKEY_SIGN_1 34u
#define SECRET_FOR_FUSEKEY_SIGN_2 35u
#define SECRET_FOR_FUSEKEY_DEC 38u
#define FUSE_NUM_OF_16B_KEY 3u
#define FUSE_NUM_OF_32B_KEY 1u
#define HEADER_RSVD_BYTES 13u
#define VERIFY_ECDSA_P256_PASS 0xDA55u
#define VERIFY_ECDSA_P256_FAIL 0xFA11u
#define PASS VERIFY_ECDSA_P256_PASS
#define FAIL VERIFY_ECDSA_P256_FAIL
#define ECC_P256_SIZE_DWORDS 8u
#define MAX_NUM_OF_FUSE_KEYS_IN_16B 11u
typedef unsigned char AES_128_KEY[AES_128_KEY_LEN_IN_BYTES]; // AES_128_KEY is an array of 16 bytes
typedef unsigned char ECC_256_KEY[AES_128_KEY_LEN_IN_BYTES * 2u]; // ECC_256_KEY is an array of 32 bytes
typedef unsigned char AES_128_SIG[AES_128_SIG_LEN_IN_BYTES]; // AES_128_SIG is an array of 16 bytes
typedef unsigned char ENC_FUSE_KEY_PROT_INFO[PROTECTINFO_LEN_IN_BYTES];
static const unsigned int CONST_USED_FOR_GENTK[4]={0x900du, 0u, 0u, 0u};
static const unsigned int CONST_USED_FOR_DECRYPT_MPK[4]={0x76543210u, 0xfedcba98u, 0x76543210u, 0xfedcba98u};
typedef enum
{
DRM_PLAYREADY, DRM_WIDEVINE
} DRM_SCHEME;
typedef struct
{
unsigned char version; //keyglob version
unsigned char numOf16BKey; //numbler of 16Bytes
unsigned char numOf32BKey; //numbler of 16Bytes
unsigned char rsvd[HEADER_RSVD_BYTES]; // reserved field for future, These need to be zeroed out in Turing
} ENC_FUSE_KEY_HEADER;
/*
* Paramter struct for FUNID==1: decryptFuseKeys
* "decryptFuseKeys" performed:
* 1. Verify the signature on the given keyglob, keyglob consist of header, keyArr and protInfoArr
* Hash = DMHash of keyglob with first value to be encrypted being E(secret[34], 1) instead of 0
* SigKey = AES_ENC(secret[35], 1)
* Sig = E(SigKey, Hash)
* 2. If sig checking pass, decrypt the fuse keys and install the decrypted keys and their protectInfo to the KMEM.
* eKey = AES_ENC(AES_ENC(scp_secrets[38], 0x1), PDI);
* keyblob = AES_DEC(eKey, keyglob); keyblob is plain text of keys
* 3. This API can be called by any ucode(NS/LS/HS)
* 4. How to call this function
* SW_PARAM_DECRYPT_FUSEKEYS* pointer_of_struct_for_dec_fuse_keys
* then fill each element of above pointer
* falc_strap(NV_CMSXXX_FALCON_BROM_FUNID_ID_DECFUSEKEY, pointer_of_struct_for_decrypt_fuse_keys);
*
* Arguments:
* see below struct comments
* Result:
* check the result by csb register BROM_RETCODE
* Alignment requirement
* 32B aligned
*/
typedef struct
{
ENC_FUSE_KEY_HEADER header; //(in) needs to be 16 bytes aligned address
AES_128_KEY keyArr[MAX_NUM_OF_FUSE_KEYS_IN_16B]; //(in) needs to be 16 bytes aligned address. Will increment in stride of 16
ENC_FUSE_KEY_PROT_INFO protInfoArr[MAX_NUM_OF_FUSE_KEYS_IN_16B]; //(in) needs to be 16 bytes aligned address, and the length must be multiple of 16 bytes, padding 0s if needed.
unsigned char rsvd[4]; // reserved for future, making pSignature to be 16B aligned
AES_128_SIG signature; //(in) needs to be 16 bytes aligned address
} SW_PARAM_DECRYPT_FUSEKEYS __attribute__((aligned(32)));
/*
* Paramter struct for FUNID==2: genTK
* "genTK" performed:
* This function returns a TK given an ID.
*
* TK is generated as follows
* tmpKey = Enc(dPDUK, CONST_USED_FOR_GENTK);
* TKEncKey= Enc(tmpKey, IS_HS | DRM_SCHEME_ID | UCODE_ID | FAMILYIDID);
* TK = Enc(TKEncKey, tkid)
* where
- IS_HS is 0 for LS and 1 for HS.
- UCODE_ID is 0xFFFFFFFF for LS
- ENG_ID is FALCON_ENGID_FAMILYID.
- ENG_ID (32 bits): 31:0
- UCODE_ID (32 bits): 63:32
- DRM_SCHEME_ID (32 bits): 95:64
- IS_HS (1 bit): 127:96
- tkid = required version of TK
- dPDUK is one of the fuse keys, after it is decrypted by BROM it is persisted in the KMEM
* If tkid > CTKID, return failure by reg BROM_RETCODE
* CTKID is from fuse, which starts at 0. It is field programmable fuses(aks FPF), and propagated to falcon FALCON_PR_CTKID register
* non-secure code is not allowed to call this API, LS/HS is allowed
*
* Arguments:
* See below comments
* How to call this function:
* falc_strap(NV_MSXXXFALCON_BROM_FUNID_ID_GENTK, pointer_of_struct_for_gen_tk);
* Alignment Reqirement
* 32 Bytes aligned
*
*/
typedef struct
{
AES_128_KEY tk; //(out) Tell Brom the dmem address where to store the TK. BR will check whether the mem_ptr is stay in DMEM
// If it is an invalid ptr, report ERR by BROM_RETCODE.
unsigned int tkid; //(in) The ID of the required TK
DRM_SCHEME drm_scheme_id; //(in) DRM scheme id, 0 for Playready, 1 for Widevine
} SW_PARAM_GENTK __attribute__((aligned(32)));
/*
* Paramter struct for FUNID==3: decryptMPK
* "decryptMPK" Synopsis:
* This function decrypts the given eMPK and installs the result to KMEM keyslot.
* It's protectInfo will be set as
* disposable = 1 and the corresponding ucodeIdMask =1
* protectInfo of dMPK = 0x400 | (1<<(FALCON_BROM_CURR_UCODE_ID+15))
* Operations Performed:
* tmpKey = Enc(PMUK, CONST_USED_FOR_DECRYPT_MPK)
* Dkey = Enc(tmpKey, fuseVersionForCurrUcode || ucodeId || family_id);
* dMPK = Dec(Dkey, eMPK);
* where:
* family_id(32 bits) : 31:0 from csb register FALCON_ENGID
* ucodeId(32 bits) : 63:32 from csb register FALCON_BROM_CURR_UCODE_ID
* fuseVersionForCurrUcode : 95:64 from csb register FALCON_UCODE_VERSION(ucodeID)
* Arguments:
* pMPK (in) Address of the encrypted MPK
*
* The output of plain text of MPK is installed by BROM to KMEM keyslot index NV_CMSDEC_FALCON_KMEM_MPK_LOW_IDX and NV_CMSDEC_FALCON_KMEM_MPK_HIGH_IDX
* This API can only be called by HS code.
* Check BROM_RETCODE to know the result of the function.
*
* Alignment requirement
* 32 bytes aligned
*/
typedef struct
{
ECC_256_KEY mpk; //(in) Address of the encrypted MPK
} SW_PARAM_DECRYPT_MPK __attribute__((aligned(32)));
/*
* Struct used for ECDSA sign or ECDSA verify
*/
typedef struct
{
unsigned int HASH[ECC_P256_SIZE_DWORDS]; // little-endian in a word
} ECC_P256_HASH;
typedef struct
{
unsigned int PRIVKEY[ECC_P256_SIZE_DWORDS]; // little-endian in a word
} ECC_P256_PRIVKEY;
typedef struct
{
unsigned int R[ECC_P256_SIZE_DWORDS]; // little-endian in a word
unsigned int S[ECC_P256_SIZE_DWORDS]; // little-endian in a word
} ECC_P256_SIGNATURE;
typedef struct
{
unsigned int Qx[ECC_P256_SIZE_DWORDS]; // little-endian in a word
unsigned int Qy[ECC_P256_SIZE_DWORDS]; // little-endian in a word
} ECC_P256_PUBKEY;
/*
* Paramter struct for FUNID==6: sign_ECDSA_P256
* Alignment requirement
* 4 bytes aligned
*/
typedef struct
{
ECC_P256_HASH hash;
ECC_P256_PRIVKEY privKey;
ECC_P256_SIGNATURE sig;
} SW_PARAM_SIGN_ECDSA_P256;
/*
* Paramter struct for FUNID==4: signWithMPK
* Alignment requirement
* 4 bytes aligned
*/
typedef struct
{
ECC_P256_HASH hash;
ECC_P256_SIGNATURE sig;
} SW_PARAM_SIGN_WITH_MPK;
/*
* Paramter struct for FUNID==7: verify_ECDSA_P256
* Alignment requirement
* 4 bytes aligned
*/
typedef struct
{
ECC_P256_HASH hash;
ECC_P256_SIGNATURE sig;
ECC_P256_PUBKEY pubKey;
unsigned int result; //0xDA55: pass; 0xFA11: fail
} SW_PARAM_VERIFY_ECDSA_P256;
#endif

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include/ampere/ga102/bootrom_pkc_parameters.h Normal file
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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
/* This file is autogenerated by ref2h.pl. Do not edit */
#ifndef BOOTROM_PKC_PARAMETERS_H
#define BOOTROM_PKC_PARAMETERS_H
#include "bootrom_pkc_parameters_macro.h"
struct ECC_sig
{
unsigned int R[1024 / 32];
unsigned int S[1024 / 32];
};
struct RSA_sig
{
unsigned int S[4096 / 32];
};
union pkc_sig
{
struct RSA_sig rsa3k_sig;
struct RSA_sig rsa4k_sig;
struct ECC_sig ecc256_sig;
struct ECC_sig ecc384_sig;
struct ECC_sig ecc521_sig;
};
struct RSA_pk
{
unsigned int n[4096 / 32]; // modulus
unsigned int e[4096 / 32]; // public key exponent
unsigned int np[4096 / 32]; // Montgomery pre-computered value for n
unsigned int ns_sqr[4096 / 32]; // Montgomery pre-computered value for n
};
// Curve C: y^2=x^3+ax+b (mod p)
struct ECC_pk
{
unsigned int p[1024 / 32]; // modulus of curve
unsigned int pp[1024 / 32]; // Montgomery pre-computered value for p, only useful for !ECC521
unsigned int ps_sqr[1024 / 32]; // Montgomery pre-computered value for p, only useful for !ECC521
unsigned int n[1024 / 32]; // order of curve
unsigned int np[1024 / 32]; // Montgomery pre-computered value for n, only useful for !ECC521
unsigned int ns_sqr[1024 / 32]; // Montgomery pre-computered value for n, only useful for !ECC521
unsigned int n640[1024 / 32];// 640 bit prime to help 521 bit modular multiplication, only useful for ECC521
unsigned int n640p[1024 / 32];// Montgomery pre-computered value for n640, only useful for ECC521
unsigned int n640s_sqr[1024 / 32];// Montgomery pre-computered value for n640, only useful for ECC521
unsigned int a[1024 / 32]; // coefficient of curve
unsigned int Gx[1024 / 32]; // base point
unsigned int Gy[1024 / 32]; // base point
unsigned int Qx[1024 / 32]; // public key
unsigned int Qy[1024 / 32]; // public key
};
union pkc_pk
{
struct RSA_pk rsa3k_pk;
struct RSA_pk rsa4k_pk;
struct ECC_pk ecc256_pk;
struct ECC_pk ecc384_pk;
struct ECC_pk ecc521_pk;
};
struct pkc_verification_parameters
{
union pkc_sig signature;
union pkc_pk* pk;
unsigned int hash_saving;
};
#endif

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include/ampere/ga102/bootrom_pkc_parameters_macro.h Normal file
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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
/* This file is autogenerated by ref2h.pl. Do not edit */
#ifndef BOOTROM_PKC_PARAMETERS_MACRO_H
#define BOOTROM_PKC_PARAMETERS_MACRO_H
#define BMEM_STACK_START 0xF00u
#define BMEM_GLOBAL_AREA_START BMEM_STACK_START
#define BOOTROM_GCOV_INIT 0x1
#define BOOTROM_GCOV_EXIT 0x2
#define ERROR_OK 0x00000000u
#define ERROR_BOOTROM_START 0x00000001
#define ERROR_INV_RANGE 0x00000002u
#define ERROR_ALGO_DIS 0x00000003u
#define ERROR_SIG_MISS 0x00000004u
#define ERROR_PK_MISS 0x00000005u
#define ERROR_SHA_BUSY 0x00000006u
#define ERROR_SHA_ERROR 0x00000007u
#define ERROR_PK_TAMPER 0x00000008u
#define ERROR_SIG_WRONG 0x00000009u
#define ERROR_ENG_NOPKC 0x0000000au
#define ERROR_EIDMSK_WRONG 0x0000000bu
#define ERROR_PARA_MISS 0x0000000cu
#define ERROR_INV_UCODID 0x0000000du
#define ERROR_INV_PKHASH 0x0000000eu
#define ERROR_PKA_ABNORMAL_STOP 0x0000000fu
#define ERROR_BOOTROM_RUNNING 0x00000010u
#define ERROR_INSTALL_SIG 0x00000011u
#define ERROR_BOOTROM_DOC_ERR 0x000000fdu
#define ERROR_BOOTROM_UNKNOW 0x000000feu
#define ERROR_BOOTROM_HANG 0x000000ffu
//LINE1 captures the position of directChannel.c where cause the hang
//LINE2 captures the position of bootrom_pkc.c where cause the hang
// or if the symtom is not hang, line2 captures the position where error happened
#define NV_CMSDEC_FALCON_DEBUGINFO_ERR 7:0
#define NV_CMSDEC_FALCON_DEBUGINFO_LINE1 15:8
#define NV_CMSDEC_FALCON_DEBUGINFO_LINE2 31:16
#endif

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_access_counter_h__
#define __ga102_dev_access_counter_h__
/* This file is autogenerated. Do not edit */
#define NV_ACCESS_COUNTER_NOTIFY_BUF /* ----G */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY 0x1F:0x00000000 /* RW--M */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_SIZE 32 /* */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_TYPE (0+0*32):(0*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_TYPE_CPU 0x00000000 /* RWX-V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_TYPE_GPU 0x00000001 /* RWX-V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_ADDR_TYPE (1+0*32):(0*32+1) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_ADDR_TYPE_GVA 0x00000000 /* RWX-V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_ADDR_TYPE_GPA 0x00000001 /* RWX-V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK (5+0*32):(0*32+2) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_0 0x00000000 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_1 0x00000001 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_2 0x00000002 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_3 0x00000003 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_4 0x00000004 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_5 0x00000005 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_6 0x00000006 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_7 0x00000007 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_8 0x00000008 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_9 0x00000009 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_10 0x0000000A /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_11 0x0000000B /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_12 0x0000000C /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_13 0x0000000D /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_14 0x0000000E /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_BANK_15 0x0000000F /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_APERTURE (9+0*32):(0*32+8) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_APERTURE_VID_MEM 0x00000000 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_APERTURE_PEER_MEM 0x00000001 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_INST_APERTURE (11+0*32):(0*32+10) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_INST_APERTURE_VID_MEM 0x00000000 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_INST_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_INST_LO (31+0*32):(0*32+12) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_INST_HI (31+1*32):(1*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_INST (31+1*32):(0*32+12) /* */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_ADDR_LO (31+2*32):(2*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_ADDR_HI (31+3*32):(3*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_ADDR (31+3*32):(2*32+0) /* */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_SUB_GRANULARITY (31+4*32):(4*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_NOTIFY_TAG (19+5*32):(5*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_COUNTER_VAL (15+6*32):(6*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_PEER_ID (2+7*32):(7*32+0) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_MMU_ENGINE_ID (28+7*32):(7*32+20) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_VALID (31+7*32):(7*32+31) /* RWXVF */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_VALID_FALSE 0x00000000 /* RWX-V */
#define NV_ACCESS_COUNTER_NOTIFY_BUF_ENTRY_VALID_TRUE 0x00000001 /* RWX-V */
#define NV_ACCESS_COUNTER_NOTIFIERS_ACCESS_COUNTER (0)
#endif // __ga102_dev_access_counter_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_chiplet_logic_h__
#define __ga102_dev_chiplet_logic_h__
/* This file is autogenerated. Do not edit */
#endif // __ga102_dev_chiplet_logic_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_esched_pbdma_h__
#define __ga102_dev_esched_pbdma_h__
/* This file is autogenerated. Do not edit */
#define NV_PBDMA 0x000007ff:0x00000000 /* RW--D */
#define NV_GPENTRY 0x00000007:0x00000000 /* ----M */
#define NV_GPENTRY_ENTRY_SIZE 8 /* */
#define NV_GPENTRY_OPERAND 31:0 /* RW-UF */
#define NV_GPENTRY_FETCH 0:0 /* RW-UF */
#define NV_GPENTRY_FETCH_UNCONDITIONAL 0x00000000 /* RW--V */
#define NV_GPENTRY_FETCH_CONDITIONAL 0x00000001 /* RW--V */
#define NV_GPENTRY_GET 31:2 /* RW-UF */
#define NV_GPENTRY_GET_HI 39:32 /* RW-UF */
#define NV_GPENTRY_LEVEL 41:41 /* RW-UF */
#define NV_GPENTRY_LEVEL_MAIN 0x00000000 /* RW--V */
#define NV_GPENTRY_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
#define NV_GPENTRY_LENGTH 62:42 /* RW-UF */
#define NV_GPENTRY_LENGTH_CONTROL 0x00000000 /* RW--V */
#define NV_GPENTRY_SYNC 63:63 /* RW-UF */
#define NV_GPENTRY_SYNC_PROCEED 0x00000000 /* RW--V */
#define NV_GPENTRY_SYNC_WAIT 0x00000001 /* RW--V */
#define NV_GPENTRY_OPCODE 39:32 /* RW-UF */
#define NV_GPENTRY_OPCODE_NOP 0x00000000 /* RW--V */
#define NV_GPENTRY_OPCODE_ILLEGAL 0x00000001 /* RW--V */
#define NV_GPENTRY_OPCODE_GP_CRC 0x00000002 /* RW--V */
#define NV_GPENTRY_OPCODE_PB_CRC 0x00000003 /* RW--V */
#define NV_PBDMA_GP_BASE 0x048 /* RW-4R */
#define NV_PBDMA_GP_BASE_OFFSET 31:3 /* RWXUF */
#define NV_PBDMA_GP_BASE_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_RSVD 2:0 /* RWXUF */
#define NV_PBDMA_GP_BASE_RSVD_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI 0x04c /* RW-4R */
#define NV_PBDMA_GP_BASE_HI_OFFSET 7:0 /* RWXUF */
#define NV_PBDMA_GP_BASE_HI_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI_LIMIT2 20:16 /* RWXUF */
#define NV_PBDMA_GP_BASE_HI_LIMIT2_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI_RSVDA 15:8 /* RWXUF */
#define NV_PBDMA_GP_BASE_HI_RSVDA_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_BASE_HI_RSVDB 31:21 /* RWXUF */
#define NV_PBDMA_GP_BASE_HI_RSVDB_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_FETCH 0x050 /* RW-4R */
#define NV_PBDMA_GP_FETCH_ENTRY 31:0 /* RWXUF */
#define NV_PBDMA_GP_FETCH_ENTRY_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_GET 0x014 /* RW-4R */
#define NV_PBDMA_GP_GET_ENTRY 31:0 /* RWXUF */
#define NV_PBDMA_GP_GET_ENTRY_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_PUT 0x000 /* RW-4R */
#define NV_PBDMA_GP_PUT_ENTRY 31:0 /* RWXUF */
#define NV_PBDMA_GP_PUT_ENTRY_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_FETCH 0x054 /* RW-4R */
#define NV_PBDMA_PB_FETCH_CONDITIONAL 0:0 /* RWXUF */
#define NV_PBDMA_PB_FETCH_CONDITIONAL_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_FETCH_CONDITIONAL_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_FETCH_ADDR 31:2 /* RWXUF */
#define NV_PBDMA_PB_FETCH_ADDR_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_FETCH_HI 0x058 /* RW-4R */
#define NV_PBDMA_PB_FETCH_HI_ADDR 7:0 /* RWXUF */
#define NV_PBDMA_PB_FETCH_HI_ADDR_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_FETCH_HI_LEVEL 9:9 /* RWXUF */
#define NV_PBDMA_PB_FETCH_HI_LEVEL_MAIN 0x00000000 /* RW--V */
#define NV_PBDMA_PB_FETCH_HI_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_FETCH_HI_SYNC 10:10 /* RWXUF */
#define NV_PBDMA_PB_FETCH_HI_SYNC_PROCEED 0x00000000 /* RW--V */
#define NV_PBDMA_PB_FETCH_HI_SYNC_WAIT 0x00000001 /* RW--V */
#define NV_PBDMA_PB_FETCH_HI_LENGTH 31:11 /* RWXUF */
#define NV_PBDMA_PB_FETCH_HI_LENGTH_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GET 0x018 /* RW-4R */
#define NV_PBDMA_GET_OFFSET 31:2 /* RWXUF */
#define NV_PBDMA_GET_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GET_HI 0x01c /* RW-4R */
#define NV_PBDMA_GET_HI_OFFSET 7:0 /* RWXUF */
#define NV_PBDMA_GET_HI_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PUT 0x05c /* RW-4R */
#define NV_PBDMA_PUT_OFFSET 31:2 /* RWXUF */
#define NV_PBDMA_PUT_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PUT_RSVD 1:0 /* R-IUF */
#define NV_PBDMA_PUT_RSVD_ZERO 0x00000000 /* R-I-V */
#define NV_PBDMA_PUT_HI 0x060 /* RW-4R */
#define NV_PBDMA_PUT_HI_OFFSET 7:0 /* RWXUF */
#define NV_PBDMA_PUT_HI_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_TOP_LEVEL_GET 0x020 /* RW-4R */
#define NV_PBDMA_TOP_LEVEL_GET_OFFSET 31:2 /* RWXUF */
#define NV_PBDMA_TOP_LEVEL_GET_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_TOP_LEVEL_GET_RSVD 1:0 /* R-IUF */
#define NV_PBDMA_TOP_LEVEL_GET_RSVD_ZERO 0x00000000 /* R-I-V */
#define NV_PBDMA_TOP_LEVEL_GET_HI 0x024 /* RW-4R */
#define NV_PBDMA_TOP_LEVEL_GET_HI_OFFSET 7:0 /* RWXUF */
#define NV_PBDMA_TOP_LEVEL_GET_HI_OFFSET_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_TOP_LEVEL_GET_HI_VALID 31:31 /* RWIUF */
#define NV_PBDMA_TOP_LEVEL_GET_HI_VALID_FALSE 0x00000000 /* RWI-V */
#define NV_PBDMA_TOP_LEVEL_GET_HI_VALID_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_GP_CRC 0x074 /* RW-4R */
#define NV_PBDMA_GP_CRC_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_GP_CRC_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_HEADER 0x084 /* RW-4R */
#define NV_PBDMA_PB_HEADER_METHOD_OR_SDMASK 15:2 /* RWXUF */
#define NV_PBDMA_PB_HEADER_METHOD 13:2 /* */
#define NV_PBDMA_PB_HEADER_METHOD_ZERO 0x00000000 /* */
#define NV_PBDMA_PB_HEADER_SDMASK 15:4 /* */
#define NV_PBDMA_PB_HEADER_SUBCHANNEL 18:16 /* RWXUF */
#define NV_PBDMA_PB_HEADER_SUBCHANNEL_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_HEADER_LEVEL 20:20 /* RWXVF */
#define NV_PBDMA_PB_HEADER_LEVEL_MAIN 0x00000000 /* RW--V */
#define NV_PBDMA_PB_HEADER_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_HEADER_FIRST 22:22 /* RWXVF */
#define NV_PBDMA_PB_HEADER_FIRST_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_HEADER_FIRST_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_HEADER_CONDITIONAL 23:23 /* RWXVF */
#define NV_PBDMA_PB_HEADER_CONDITIONAL_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_HEADER_CONDITIONAL_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_HEADER_FINAL 24:24 /* RWXVF */
#define NV_PBDMA_PB_HEADER_FINAL_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_HEADER_FINAL_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE 31:29 /* RWXUF */
#define NV_PBDMA_PB_HEADER_TYPE_SSDM 0x00000000 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE_INC 0x00000001 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE_STORE_SDM 0x00000002 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE_NON_INC 0x00000003 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE_IMMD 0x00000004 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE_INC_ONCE 0x00000005 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE_USE_SDM 0x00000006 /* RW--V */
#define NV_PBDMA_PB_HEADER_TYPE_END_SEG 0x00000007 /* RW--V */
#define NV_PBDMA_PB_COUNT 0x088 /* RW-4R */
#define NV_PBDMA_PB_COUNT_VALUE 12:0 /* RWXUF */
#define NV_PBDMA_PB_COUNT_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL0 16:16 /* RWXUF */
#define NV_PBDMA_PB_COUNT_DATAVAL0_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL0_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL0 17:17 /* RWXVF */
#define NV_PBDMA_PB_COUNT_LEVEL0_MAIN 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL0_SUBROUTINE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL0 18:18 /* RWXVF */
#define NV_PBDMA_PB_COUNT_CONDITIONAL0_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL0_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL0 19:19 /* RWXVF */
#define NV_PBDMA_PB_COUNT_FINAL0_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL0_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL1 20:20 /* RWXUF */
#define NV_PBDMA_PB_COUNT_DATAVAL1_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL1_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL1 21:21 /* RWXVF */
#define NV_PBDMA_PB_COUNT_LEVEL1_MAIN 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL1_SUBROUTINE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL1 22:22 /* RWXVF */
#define NV_PBDMA_PB_COUNT_CONDITIONAL1_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL1_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL1 23:23 /* RWXVF */
#define NV_PBDMA_PB_COUNT_FINAL1_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL1_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL2 24:24 /* RWXUF */
#define NV_PBDMA_PB_COUNT_DATAVAL2_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL2_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL2 25:25 /* RWXVF */
#define NV_PBDMA_PB_COUNT_LEVEL2_MAIN 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL2_SUBROUTINE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL2 26:26 /* RWXVF */
#define NV_PBDMA_PB_COUNT_CONDITIONAL2_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL2_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL2 27:27 /* RWXVF */
#define NV_PBDMA_PB_COUNT_FINAL2_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL2_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL3 28:28 /* RWXUF */
#define NV_PBDMA_PB_COUNT_DATAVAL3_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_DATAVAL3_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL3 29:29 /* RWXVF */
#define NV_PBDMA_PB_COUNT_LEVEL3_MAIN 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_LEVEL3_SUBROUTINE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL3 30:30 /* RWXVF */
#define NV_PBDMA_PB_COUNT_CONDITIONAL3_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_CONDITIONAL3_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL3 31:31 /* RWXVF */
#define NV_PBDMA_PB_COUNT_FINAL3_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_PB_COUNT_FINAL3_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_PB_DATA0 0x08c /* RW-4R */
#define NV_PBDMA_PB_DATA0_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_PB_DATA0_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_DATA1 0x090 /* RW-4R */
#define NV_PBDMA_PB_DATA1_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_PB_DATA1_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_DATA2 0x0f0 /* RW-4R */
#define NV_PBDMA_PB_DATA2_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_PB_DATA2_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_DATA3 0x068 /* RW-4R */
#define NV_PBDMA_PB_DATA3_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_PB_DATA3_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_PB_CRC 0x098 /* RW-4R */
#define NV_PBDMA_PB_CRC_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_PB_CRC_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SUBDEVICE 0x094 /* RW-4R */
#define NV_PBDMA_SUBDEVICE_ID 11:0 /* RWXUF */
#define NV_PBDMA_SUBDEVICE_ID_ENABLE 0x00000FFF /* RW--V */
#define NV_PBDMA_SUBDEVICE_STORED_MASK 27:16 /* RWXUF */
#define NV_PBDMA_SUBDEVICE_STORED_MASK_ENABLE 0x00000FFF /* RW--V */
#define NV_PBDMA_SUBDEVICE_STATUS 28:28 /* RWXUF */
#define NV_PBDMA_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* RW--V */
#define NV_PBDMA_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* RW--V */
#define NV_PBDMA_SUBDEVICE_CHANNEL_DMA 29:29 /* RWXUF */
#define NV_PBDMA_SUBDEVICE_CHANNEL_DMA_DISABLE 0x00000000 /* RW--V */
#define NV_PBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 0x00000001 /* RW--V */
#define NV_PBDMA_METHOD(i) (0x0c0+(i)*8) /* RW-4A */
#define NV_PBDMA_METHOD__SIZE_1 4 /* */
#define NV_PBDMA_METHOD_ADDR 13:2 /* RWXUF */
#define NV_PBDMA_METHOD_ADDR_NULL 0x00000000 /* RW--V */
#define NV_PBDMA_METHOD_SUBCH 18:16 /* RWXUF */
#define NV_PBDMA_METHOD_SUBCH_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_METHOD_FIRST 22:22 /* RWXUF */
#define NV_PBDMA_METHOD_FIRST_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_METHOD_FIRST_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_METHOD_VALID 31:31 /* RWXUF */
#define NV_PBDMA_METHOD_VALID_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_METHOD_VALID_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_DATA(i) (0x0c4+(i)*8) /* RW-4A */
#define NV_PBDMA_DATA__SIZE_1 4 /* */
#define NV_PBDMA_DATA_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_DATA_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_ALLOWED_SYNCPOINTS 0x0e8 /* R--4R */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_VALID 31:31 /* R-XVF */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_VALID_TRUE 1 /* R---V */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_VALID_FALSE 0 /* R---V */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_INDEX 30:16 /* R-XVF */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_VALID 15:15 /* R-XVF */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_VALID_TRUE 1 /* R---V */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_VALID_FALSE 0 /* R---V */
#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_INDEX 14:0 /* R-XVF */
#define NV_PBDMA_TARGET 0x0ac /* RW-4R */
#define NV_PBDMA_TARGET_ENGINE 1:0 /* RWXUF */
#define NV_PBDMA_TARGET_ENGINE_SW_LOCAL 3 /* RW--V */
#define NV_PBDMA_TARGET_ENG_CTX_VALID 16:16 /* RWXUF */
#define NV_PBDMA_TARGET_ENG_CTX_VALID_TRUE 1 /* RW--V */
#define NV_PBDMA_TARGET_ENG_CTX_VALID_FALSE 0 /* RW--V */
#define NV_PBDMA_TARGET_CE_CTX_VALID 17:17 /* RWXUF */
#define NV_PBDMA_TARGET_CE_CTX_VALID_TRUE 1 /* RW--V */
#define NV_PBDMA_TARGET_CE_CTX_VALID_FALSE 0 /* RW--V */
#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON 25:24 /* RWXUF */
#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_PBDMA_IDLE 0x0 /* RW--V */
#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_SEMAPHORE_ACQUIRE_FAILURE 0x1 /* RW--V */
#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_TSG_YIELD 0x2 /* RW--V */
#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_HOST_SUBCHANNEL_SWITCH 0x3 /* RW--V */
#define NV_PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT 29:29 /* RWXUF */
#define NV_PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT_TRUE 1 /* RW--V */
#define NV_PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT_FALSE 0 /* RW--V */
#define NV_PBDMA_TARGET_NEEDS_HOST_TSG_EVENT 31:31 /* RWXUF */
#define NV_PBDMA_TARGET_NEEDS_HOST_TSG_EVENT_TRUE 1 /* RW--V */
#define NV_PBDMA_TARGET_NEEDS_HOST_TSG_EVENT_FALSE 0 /* RW--V */
#define NV_PBDMA_TARGET_ENGINE_SW 31 /* */
#define NV_PBDMA_REF 0x028 /* RW-4R */
#define NV_PBDMA_REF_CNT 31:0 /* RWXUF */
#define NV_PBDMA_REF_CNT_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_RUNTIME 0x02c /* RW-4R */
#define NV_PBDMA_RUNTIME_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_RUNTIME_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_ADDR_LO 0x03c /* RW-4R */
#define NV_PBDMA_SEM_ADDR_LO_ADDR 31:2 /* RWXUF */
#define NV_PBDMA_SEM_ADDR_LO_ADDR_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_ADDR_HI 0x038 /* RW-4R */
#define NV_PBDMA_SEM_ADDR_HI_ADDR 7:0 /* RWXUF */
#define NV_PBDMA_SEM_ADDR_HI_ADDR_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_PAYLOAD_LO 0x040 /* RW-4R */
#define NV_PBDMA_SEM_PAYLOAD_LO_DATA 31:0 /* RWXVF */
#define NV_PBDMA_SEM_PAYLOAD_LO_DATA_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_PAYLOAD_HI 0x09c /* RW-4R */
#define NV_PBDMA_SEM_PAYLOAD_HI_DATA 31:0 /* RWXVF */
#define NV_PBDMA_SEM_PAYLOAD_HI_DATA_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE 0x044 /* RW-4R */
#define NV_PBDMA_SEM_EXECUTE_OPERATION 2:0 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_OPERATION_INVALID 0x00000007 /* -W--V */
#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_FAIL 19:19 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_FAIL_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_RELEASE_WFI 20:20 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_PAYLOAD_SIZE 24:24 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION 30:27 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IAND 0x00000003 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IOR 0x00000004 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IADD 0x00000005 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_INC 0x00000006 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_DEC 0x00000007 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_INVALID 0x0000000f /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_FORMAT 31:31 /* RWXVF */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 /* RW--V */
#define NV_PBDMA_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 /* RW--V */
#define NV_PBDMA_ACQUIRE_DEADLINE 0x034 /* RW-4R */
#define NV_PBDMA_ACQUIRE_DEADLINE_TIMESTAMP 31:0 /* RWXUF */
#define NV_PBDMA_ACQUIRE_DEADLINE_TIMESTAMP_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_ACQUIRE 0x030 /* RW-4R */
#define NV_PBDMA_ACQUIRE_RETRY_MAN 6:0 /* RWXUF */
#define NV_PBDMA_ACQUIRE_RETRY_MAN_2 0x00000002 /* RW--V */
#define NV_PBDMA_ACQUIRE_RETRY_EXP 10:7 /* RWXUF */
#define NV_PBDMA_ACQUIRE_RETRY_EXP_2 0x00000002 /* RW--V */
#define NV_PBDMA_ACQUIRE_TIMEOUT_EXP 14:11 /* RWXUF */
#define NV_PBDMA_ACQUIRE_TIMEOUT_EXP_MAX 0x0000000F /* RW--V */
#define NV_PBDMA_ACQUIRE_TIMEOUT_MAN 30:15 /* RWXUF */
#define NV_PBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0x0000FFFF /* RW--V */
#define NV_PBDMA_ACQUIRE_TIMEOUT_EN 31:31 /* RWXUF */
#define NV_PBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0x00000000 /* RW--V */
#define NV_PBDMA_ACQUIRE_TIMEOUT_EN_ENABLE 0x00000001 /* RW--V */
#define NV_PBDMA_CFG0 0x104 /* R--4R */
#define NV_PBDMA_CFG0_PBDMA_FAULT_ID 9:0 /* R-XUF */
#define NV_PBDMA_STATUS 0x100 /* R--4R */
#define NV_PBDMA_STATUS_GPF 3:0 /* R-IUF */
#define NV_PBDMA_STATUS_GPF_EMPTY 0x00000000 /* R-I-V */
#define NV_PBDMA_STATUS_GPF_SUSPENDED 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_GPF_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_GPF_BUSY 0x00000008 /* R---V */
#define NV_PBDMA_STATUS_GPP 7:4 /* R-IUF */
#define NV_PBDMA_STATUS_GPP_EMPTY 0x00000000 /* R-I-V */
#define NV_PBDMA_STATUS_GPP_SUSPENDED 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_GPP_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_GPP_BUSY 0x00000008 /* R---V */
#define NV_PBDMA_STATUS_PBP 11:8 /* R-IUF */
#define NV_PBDMA_STATUS_PBP_EMPTY 0x00000000 /* R-I-V */
#define NV_PBDMA_STATUS_PBP_SUSPENDED 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_PBP_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_PBP_BUSY 0x00000008 /* R---V */
#define NV_PBDMA_STATUS_MP 15:12 /* R-IUF */
#define NV_PBDMA_STATUS_MP_EMPTY 0x00000000 /* R-I-V */
#define NV_PBDMA_STATUS_MP_SUSPENDED 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_MP_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_MP_BUSY 0x00000008 /* R---V */
#define NV_PBDMA_STATUS_SEM 19:16 /* R-IUF */
#define NV_PBDMA_STATUS_SEM_EMPTY 0x00000000 /* R-I-V */
#define NV_PBDMA_STATUS_SEM_SUSPENDED 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_SEM_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_SEM_BUSY 0x00000008 /* R---V */
#define NV_PBDMA_STATUS_PBDMA 31:28 /* R-IUF */
#define NV_PBDMA_STATUS_PBDMA_EMPTY 0x00000000 /* R-I-V */
#define NV_PBDMA_STATUS_PBDMA_SUSPENDED 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_PBDMA_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_PBDMA_BUSY 0x00000008 /* R---V */
#define NV_PBDMA_STATUS_SCHED 0x15C /* R--4R */
#define NV_PBDMA_STATUS_SCHED_TSGID 11:0 /* */
#define NV_PBDMA_STATUS_SCHED_TSGID_HW 10:0 /* R-XUF */
#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS 15:13 /* R-EVF */
#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_INVALID 0x00000000 /* R-E-V */
#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_VALID 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_CHSW_SAVE 0x00000005 /* R---V */
#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_CHSW_LOAD 0x00000006 /* R---V */
#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_CHSW_SWITCH 0x00000007 /* R---V */
#define NV_PBDMA_STATUS_SCHED_NEXT_TSGID 27:16 /* */
#define NV_PBDMA_STATUS_SCHED_NEXT_TSGID_HW 26:16 /* R-XUF */
#define NV_PBDMA_STATUS_SCHED_CHAN 13:13 /* */
#define NV_PBDMA_STATUS_SCHED_CHAN_INVALID 0x00000000 /* */
#define NV_PBDMA_STATUS_SCHED_CHAN_VALID 0x00000001 /* */
#define NV_PBDMA_STATUS_SCHED_CHANLOAD 14:14 /* */
#define NV_PBDMA_STATUS_SCHED_CHANLOAD_NOT_IN_PROGRESS 0x00000000 /* */
#define NV_PBDMA_STATUS_SCHED_CHANLOAD_IN_PROGRESS 0x00000001 /* */
#define NV_PBDMA_STATUS_SCHED_CHSW 15:15 /* */
#define NV_PBDMA_STATUS_SCHED_CHSW_NOT_IN_PROGRESS 0x00000000 /* */
#define NV_PBDMA_STATUS_SCHED_CHSW_IN_PROGRESS 0x00000001 /* */
#define NV_PBDMA_STATUS_INST 0x160 /* R--4R */
#define NV_PBDMA_STATUS_INST_TARGET 1:0 /* R-XUF */
#define NV_PBDMA_STATUS_INST_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_PBDMA_STATUS_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_PBDMA_STATUS_INST_VALID 11:11 /* R-EVF */
#define NV_PBDMA_STATUS_INST_VALID_FALSE 0x00000000 /* R-E-V */
#define NV_PBDMA_STATUS_INST_VALID_TRUE 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_INST_PTR_LO 31:12 /* R-XUF */
#define NV_PBDMA_STATUS_INST_HI 0x164 /* R--4R */
#define NV_PBDMA_STATUS_INST_HI_PTR_HI 31:0 /* R-XUF */
#define NV_PBDMA_STATUS_NEXT_INST 0x138 /* R--4R */
#define NV_PBDMA_STATUS_NEXT_INST_TARGET 1:0 /* R-XUF */
#define NV_PBDMA_STATUS_NEXT_INST_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_PBDMA_STATUS_NEXT_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_NEXT_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_PBDMA_STATUS_NEXT_INST_VALID 11:11 /* R-EVF */
#define NV_PBDMA_STATUS_NEXT_INST_VALID_FALSE 0x00000000 /* R-E-V */
#define NV_PBDMA_STATUS_NEXT_INST_VALID_TRUE 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_NEXT_INST_PTR_LO 31:12 /* R-XUF */
#define NV_PBDMA_STATUS_NEXT_INST_HI 0x13C /* R--4R */
#define NV_PBDMA_STATUS_NEXT_INST_HI_PTR_HI 31:0 /* R-XUF */
#define NV_PBDMA_STATUS_USERD 0x168 /* R--4R */
#define NV_PBDMA_STATUS_USERD_TARGET 1:0 /* R--UF */
#define NV_PBDMA_STATUS_USERD_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_PBDMA_STATUS_USERD_TARGET_VID_MEM_NVLINK_COHERENT 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_USERD_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_USERD_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_PBDMA_STATUS_USERD_VALID 7:7 /* R-EVF */
#define NV_PBDMA_STATUS_USERD_VALID_FALSE 0x00000000 /* R-E-V */
#define NV_PBDMA_STATUS_USERD_VALID_TRUE 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_USERD_PTR_LO 31:8 /* R--UF */
#define NV_PBDMA_STATUS_USERD_HI 0x16C /* R--4R */
#define NV_PBDMA_STATUS_USERD_HI_PTR_HI 31:0 /* R--UF */
#define NV_PBDMA_STATUS_NEXT_USERD 0x140 /* R--4R */
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET 1:0 /* R--UF */
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_VID_MEM_NVLINK_COHERENT 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_PBDMA_STATUS_NEXT_USERD_VALID 7:7 /* R-EVF */
#define NV_PBDMA_STATUS_NEXT_USERD_VALID_FALSE 0x00000000 /* R-E-V */
#define NV_PBDMA_STATUS_NEXT_USERD_VALID_TRUE 0x00000001 /* R---V */
#define NV_PBDMA_STATUS_NEXT_USERD_PTR_LO 31:8 /* R--UF */
#define NV_PBDMA_STATUS_NEXT_USERD_HI 0x144 /* R--4R */
#define NV_PBDMA_STATUS_NEXT_USERD_HI_PTR_HI 31:0 /* R--UF */
#define NV_PBDMA_CHANNEL 0x120 /* R--4R */
#define NV_PBDMA_CHANNEL_CHID 11:0 /* */
#define NV_PBDMA_CHANNEL_CHID_HW 10:0 /* R-XUF */
#define NV_PBDMA_CHANNEL_VALID 13:13 /* R-IVF */
#define NV_PBDMA_CHANNEL_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_PBDMA_CHANNEL_VALID_TRUE 0x00000001 /* R---V */
#define NV_PBDMA_CHANNEL_GFID 21:16 /* R-XVF */
#define NV_PBDMA_NEXT_CHANNEL 0x124 /* R--4R */
#define NV_PBDMA_NEXT_CHANNEL_CHID 11:0 /* */
#define NV_PBDMA_NEXT_CHANNEL_CHID_HW 10:0 /* R-XUF */
#define NV_PBDMA_NEXT_CHANNEL_VALID 13:13 /* R-IVF */
#define NV_PBDMA_NEXT_CHANNEL_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_PBDMA_NEXT_CHANNEL_VALID_TRUE 0x00000001 /* R---V */
#define NV_PBDMA_NEXT_CHANNEL_GFID 21:16 /* R-XVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK 0x130 /* RW-4R */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_PBDMA_SECURE_CONFIG 0x134 /* RW-4R */
#define NV_PBDMA_SECURE_CONFIG__PRIV_LEVEL_MASK 0x130 /* */
#define NV_PBDMA_SECURE_CONFIG_FORCE_CE_SPLIT 0:0 /* RWIUF */
#define NV_PBDMA_SECURE_CONFIG_FORCE_CE_SPLIT_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_SECURE_CONFIG_FORCE_CE_SPLIT_TRUE 0x00000001 /* RWI-V */
#define NV_PBDMA_GP_SHADOW(i) (0x110+(i)*4) /* R--4A */
#define NV_PBDMA_GP_SHADOW__SIZE_1 2 /* */
#define NV_PBDMA_GP_SHADOW_VALUE 31:0 /* R-XUF */
#define NV_PBDMA_HDR_SHADOW 0x06c /* RW-4R */
#define NV_PBDMA_HDR_SHADOW_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_INTR_PRI_DEBUG 0x11c /* RW-4R */
#define NV_PBDMA_INTR_PRI_DEBUG_ADDRESS 31:0 /* RWXUF */
#define NV_PBDMA_MEM_OP_A 0x004 /* RW-4R */
#define NV_PBDMA_MEM_OP_A_DATA 31:0 /* RWXUF */
#define NV_PBDMA_MEM_OP_B 0x064 /* RW-4R */
#define NV_PBDMA_MEM_OP_B_DATA 31:0 /* RWXUF */
#define NV_PBDMA_MEM_OP_C 0x0a0 /* RW-4R */
#define NV_PBDMA_MEM_OP_C_DATA 31:0 /* RWXUF */
#define NV_PBDMA_SIGNATURE 0x010 /* RW-4R */
#define NV_PBDMA_SIGNATURE_HW 15:0 /* RWXUF */
#define NV_PBDMA_SIGNATURE_HW_VALID 0x0000face /* RW--V */
#define NV_PBDMA_SIGNATURE_HW_HOST_CLASS_ID 51055 /* RW--V */
#define NV_PBDMA_SIGNATURE_SW 31:16 /* RWXUF */
#define NV_PBDMA_SIGNATURE_SW_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_CONFIG 0x0f4 /* R--4R */
#define NV_PBDMA_CONFIG_L2_EVICT 0:0 /* R--VF */
#define NV_PBDMA_CONFIG_L2_EVICT_FIRST 0x00000000 /* R---V */
#define NV_PBDMA_CONFIG_L2_EVICT_NORMAL 0x00000001 /* R---V */
#define NV_PBDMA_CONFIG_CE_SPLIT 4:4 /* R--VF */
#define NV_PBDMA_CONFIG_CE_SPLIT_ENABLE 0x00000000 /* R---V */
#define NV_PBDMA_CONFIG_CE_SPLIT_DISABLE 0x00000001 /* R---V */
#define NV_PBDMA_CONFIG_CE_THROTTLE_MODE 5:5 /* R--VF */
#define NV_PBDMA_CONFIG_CE_THROTTLE_MODE_THROTTLE 0x00000000 /* R---V */
#define NV_PBDMA_CONFIG_CE_THROTTLE_MODE_NO_THROTTLE 0x00000001 /* R---V */
#define NV_PBDMA_CONFIG_AUTH_LEVEL 8:8 /* R--VF */
#define NV_PBDMA_CONFIG_AUTH_LEVEL_NON_PRIVILEGED 0x00000000 /* R---V */
#define NV_PBDMA_CONFIG_AUTH_LEVEL_PRIVILEGED 0x00000001 /* R---V */
#define NV_PBDMA_CONFIG_USERD_WRITEBACK 12:12 /* R--VF */
#define NV_PBDMA_CONFIG_USERD_WRITEBACK_DISABLE 0x00000000 /* R---V */
#define NV_PBDMA_CONFIG_USERD_WRITEBACK_ENABLE 0x00000001 /* R---V */
#define NV_PBDMA_CONFIG_PM_TRIGGER 31:31 /* R--VF */
#define NV_PBDMA_CONFIG_PM_TRIGGER_ASSERTED 0x00000001 /* R---V */
#define NV_PBDMA_CONFIG_PM_TRIGGER_DEASSERTED 0x00000000 /* R---V */
#define NV_PBDMA_INTR_NOTIFY 0x0f8 /* RW-4R */
#define NV_PBDMA_INTR_NOTIFY_VECTOR 11:0 /* RWXUF */
#define NV_PBDMA_INTR_NOTIFY_CTRL_GSP 30:30 /* RWXUF */
#define NV_PBDMA_INTR_NOTIFY_CTRL_GSP_DISABLE 0 /* R---V */
#define NV_PBDMA_INTR_NOTIFY_CTRL_GSP_ENABLE 1 /* R---V */
#define NV_PBDMA_INTR_NOTIFY_CTRL_CPU 31:31 /* RWXUF */
#define NV_PBDMA_INTR_NOTIFY_CTRL_CPU_DISABLE 0 /* R---V */
#define NV_PBDMA_INTR_NOTIFY_CTRL_CPU_ENABLE 1 /* R---V */
#define NV_PBDMA_SET_CHANNEL_INFO 0x0fc /* RW-4R */
#define NV_PBDMA_SET_CHANNEL_INFO_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_SET_CHANNEL_INFO_SCG_TYPE 0:0 /* */
#define NV_PBDMA_SET_CHANNEL_INFO_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 /* */
#define NV_PBDMA_SET_CHANNEL_INFO_SCG_TYPE_COMPUTE1 0x00000001 /* */
#define NV_PBDMA_SET_CHANNEL_INFO_VEID ((6-1)+8):8 /* */
#define NV_PBDMA_SET_CHANNEL_INFO_CHID 27:16 /* */
#define NV_PBDMA_SET_CHANNEL_INFO_RESERVED 31:27 /* */
#define NV_PBDMA_SET_CHANNEL_INFO_CHID_HW 26:16 /* */
#define NV_PBDMA_SPARE56 0x0e0 /* RW-4R */
#define NV_PBDMA_SPARE56_PB_GET_CONDITIONAL 0:0 /* RWXUF */
#define NV_PBDMA_SPARE56_PB_GET_CONDITIONAL_FALSE 0x00000000 /* RW--V */
#define NV_PBDMA_SPARE56_PB_GET_CONDITIONAL_TRUE 0x00000001 /* RW--V */
#define NV_PBDMA_SPARE56_PB_GET_LEVEL 3:3 /* RWXUF */
#define NV_PBDMA_SPARE56_PB_GET_LEVEL_MAIN 0x00000000 /* RW--V */
#define NV_PBDMA_SPARE56_PB_GET_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
#define NV_PBDMA_SPARE56_PB_GET_SYNC 4:4 /* RWXUF */
#define NV_PBDMA_SPARE56_PB_GET_SYNC_PROCEED 0x00000000 /* RW--V */
#define NV_PBDMA_SPARE56_PB_GET_SYNC_WAIT 0x00000001 /* RW--V */
#define NV_PBDMA_SPARE56_PB_GET_FIRST 7:7 /* */
#define NV_PBDMA_SPARE56_PB_GET_FIRST_FALSE 0x00000000 /* */
#define NV_PBDMA_SPARE56_PB_GET_FIRST_TRUE 0x00000001 /* */
#define NV_PBDMA_HCE_CTRL 0x0e4 /* RW-4R */
#define NV_PBDMA_HCE_CTRL_SP_AWAITS_HCEH 0:0 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_SP_AWAITS_HCEH_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_SP_AWAITS_HCEH_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_HCE_RENDER_DISABLED 2:2 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_HCE_RENDER_DISABLED_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_HCE_RENDER_DISABLED_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_HCE_SUBCHSW 4:4 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_HCE_SUBCHSW_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_HCE_SUBCHSW_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_HCE_PRIV_MODE_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_HCE_PRIV_MODE_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_LAUNCH_DMA_RCVD 16:16 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_LAUNCH_DMA_RCVD_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_LAUNCH_DMA_RCVD_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_NOP_RCVD 17:17 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_NOP_RCVD_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_NOP_RCVD_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_RCVD 18:18 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_RCVD_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_RCVD_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_END_RCVD 19:19 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_END_RCVD_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_END_RCVD_YES 0x00000001 /* RW--V */
#define NV_PBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD 20:20 /* RWXUF */
#define NV_PBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD_NO 0x00000000 /* RW--V */
#define NV_PBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD_YES 0x00000001 /* RW--V */
#define NV_PBDMA_SPLITTER_REM_LINES 0x078 /* RW-4R */
#define NV_PBDMA_SPLITTER_REM_LINES_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_SPLITTER_REM_LINES_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SPLITTER_OFFSET_IN_LOWER 0x07c /* RW-4R */
#define NV_PBDMA_SPLITTER_OFFSET_IN_LOWER_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_SPLITTER_OFFSET_IN_LOWER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SPLITTER_OFFSET_IN_UPPER 0x080 /* RW-4R */
#define NV_PBDMA_SPLITTER_OFFSET_IN_UPPER_VALUE 16:0 /* RWXUF */
#define NV_PBDMA_SPLITTER_OFFSET_IN_UPPER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SPLITTER_REM_PIXELS 0x0b4 /* RW-4R */
#define NV_PBDMA_SPLITTER_REM_PIXELS_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_SPLITTER_REM_PIXELS_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SPLITTER_OFFSET_OUT_LOWER 0x0b8 /* RW-4R */
#define NV_PBDMA_SPLITTER_OFFSET_OUT_LOWER_VALUE 31:0 /* RWXUF */
#define NV_PBDMA_SPLITTER_OFFSET_OUT_LOWER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_SPLITTER_OFFSET_OUT_UPPER 0x0bc /* RW-4R */
#define NV_PBDMA_SPLITTER_OFFSET_OUT_UPPER_VALUE 16:0 /* RWXUF */
#define NV_PBDMA_SPLITTER_OFFSET_OUT_UPPER_VALUE_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_GP_PEEK 0x0ec /* RW-4R */
#define NV_PBDMA_GP_PEEK_ENTRY 31:0 /* RWXUF */
#define NV_PBDMA_GP_PEEK_ENTRY_ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_CE_METHOD_STATE(i) (0x200+(i)*4) /* RW-4A */
#define NV_PBDMA_CE_METHOD_STATE__SIZE_1 42 /* */
#define NV_PBDMA_CE_METHOD_STATE_ENTRY 31:0 /* RWXUF */
#define NV_PBDMA_CE_METHOD_STATE_ENTRY__ZERO 0x00000000 /* RW--V */
#define NV_PBDMA_INTR_0 0x108 /* RW-4R */
#define NV_PBDMA_INTR_0_GPFIFO 13:13 /* RWIUF */
#define NV_PBDMA_INTR_0_GPFIFO_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_GPFIFO_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_GPFIFO_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_GPPTR 14:14 /* RWIUF */
#define NV_PBDMA_INTR_0_GPPTR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_GPPTR_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_GPPTR_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_GPENTRY 15:15 /* RWIUF */
#define NV_PBDMA_INTR_0_GPENTRY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_GPENTRY_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_GPENTRY_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_GPCRC 16:16 /* RWIUF */
#define NV_PBDMA_INTR_0_GPCRC_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_GPCRC_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_GPCRC_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_PBPTR 17:17 /* RWIUF */
#define NV_PBDMA_INTR_0_PBPTR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_PBPTR_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_PBPTR_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_PBENTRY 18:18 /* RWIUF */
#define NV_PBDMA_INTR_0_PBENTRY_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_PBENTRY_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_PBENTRY_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_PBCRC 19:19 /* RWIUF */
#define NV_PBDMA_INTR_0_PBCRC_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_PBCRC_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_PBCRC_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_METHOD 21:21 /* RWIUF */
#define NV_PBDMA_INTR_0_METHOD_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_METHOD_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_METHOD_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_DEVICE 23:23 /* RWIUF */
#define NV_PBDMA_INTR_0_DEVICE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_DEVICE_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_DEVICE_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_ENG_RESET 24:24 /* RWIUF */
#define NV_PBDMA_INTR_0_ENG_RESET_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_ENG_RESET_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_ENG_RESET_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_SEMAPHORE 25:25 /* RWIUF */
#define NV_PBDMA_INTR_0_SEMAPHORE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_SEMAPHORE_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_SEMAPHORE_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_ACQUIRE 26:26 /* RWIUF */
#define NV_PBDMA_INTR_0_ACQUIRE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_ACQUIRE_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_ACQUIRE_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_PRI 27:27 /* RWIUF */
#define NV_PBDMA_INTR_0_PRI_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_PRI_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_PRI_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_PBSEG 30:30 /* RWIUF */
#define NV_PBDMA_INTR_0_PBSEG_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_PBSEG_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_PBSEG_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_0_SIGNATURE 31:31 /* RWIUF */
#define NV_PBDMA_INTR_0_SIGNATURE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_0_SIGNATURE_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_0_SIGNATURE_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_1 0x148 /* RW-4R */
#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP 0:0 /* RWIUF */
#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB 1:1 /* RWIUF */
#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_1_HCE_PRIV 2:2 /* RWIUF */
#define NV_PBDMA_INTR_1_HCE_PRIV_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_1_HCE_PRIV_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_1_HCE_PRIV_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD 3:3 /* RWIUF */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS 4:4 /* RWIUF */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_INTR_1_CTXNOTVALID 31:31 /* RWIUF */
#define NV_PBDMA_INTR_1_CTXNOTVALID_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBDMA_INTR_1_CTXNOTVALID_PENDING 0x00000001 /* R---V */
#define NV_PBDMA_INTR_1_CTXNOTVALID_RESET 0x00000001 /* -W--C */
#define NV_PBDMA_HCE_DBG0 0x150 /* R--4R */
#define NV_PBDMA_HCE_DBG0_MTHD_ADDR 13:2 /* R-EUF */
#define NV_PBDMA_HCE_DBG0_MTHD_ADDR_VAL0 0x00000000 /* R-E-V */
#define NV_PBDMA_HCE_DBG1 0x154 /* R--4R */
#define NV_PBDMA_HCE_DBG1_MTHD_DATA 31:0 /* R-EUF */
#define NV_PBDMA_HCE_DBG1_MTHD_DATA_VAL0 0x00000000 /* R-E-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE(i) (0x170+(i)*4) /* RW-4A */
#define NV_PBDMA_INTR_0_EN_SET_TREE__SIZE_1 2 /* */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPFIFO 13:13 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPFIFO_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPPTR 14:14 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPPTR_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPPTR_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPENTRY 15:15 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPENTRY_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPENTRY_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPCRC 16:16 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPCRC_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_GPCRC_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBPTR 17:17 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBPTR_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBPTR_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBENTRY 18:18 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBENTRY_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBENTRY_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBCRC 19:19 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBCRC_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBCRC_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_METHOD 21:21 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_METHOD_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_METHOD_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_DEVICE 23:23 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_DEVICE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_DEVICE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_ENG_RESET 24:24 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_ENG_RESET_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_ENG_RESET_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_SEMAPHORE 25:25 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_SEMAPHORE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_SEMAPHORE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_ACQUIRE 26:26 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_ACQUIRE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_ACQUIRE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PRI 27:27 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PRI_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PRI_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBSEG 30:30 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBSEG_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_PBSEG_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_SIGNATURE 31:31 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_SET_TREE_SIGNATURE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_SET_TREE_SIGNATURE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_SET_TREE(i) (0x180+(i)*4) /* RW-4A */
#define NV_PBDMA_INTR_1_EN_SET_TREE__SIZE_1 2 /* */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ILLEGAL_OP 0:0 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ILLEGAL_OP_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ILLEGAL_OP_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ALIGNB 1:1 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ALIGNB_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ALIGNB_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_PRIV 2:2 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_PRIV_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_PRIV_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_MTHD 3:3 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_MTHD_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_MTHD_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_CLASS 4:4 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_CLASS_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_CLASS_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_CTXNOTVALID 31:31 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_SET_TREE_CTXNOTVALID_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_SET_TREE_CTXNOTVALID_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE(i) (0x190+(i)*4) /* RW-4A */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE__SIZE_1 2 /* */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPFIFO 13:13 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPFIFO_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPFIFO_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPPTR 14:14 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPPTR_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPPTR_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPENTRY 15:15 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPENTRY_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPENTRY_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPCRC 16:16 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPCRC_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPCRC_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBPTR 17:17 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBPTR_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBPTR_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBENTRY 18:18 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBENTRY_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBENTRY_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBCRC 19:19 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBCRC_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBCRC_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_METHOD 21:21 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_METHOD_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_METHOD_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_DEVICE 23:23 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_DEVICE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_DEVICE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ENG_RESET 24:24 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ENG_RESET_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ENG_RESET_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SEMAPHORE 25:25 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SEMAPHORE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SEMAPHORE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ACQUIRE 26:26 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ACQUIRE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ACQUIRE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PRI 27:27 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PRI_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PRI_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBSEG 30:30 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBSEG_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBSEG_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SIGNATURE 31:31 /* RWEUF */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SIGNATURE_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SIGNATURE_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE(i) (0x1a0+(i)*4) /* RW-4A */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE__SIZE_1 2 /* */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ILLEGAL_OP 0:0 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ILLEGAL_OP_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ILLEGAL_OP_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ALIGNB 1:1 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ALIGNB_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ALIGNB_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_PRIV 2:2 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_PRIV_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_PRIV_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_MTHD 3:3 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_MTHD_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_MTHD_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_CLASS 4:4 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_CLASS_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_CLASS_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_CTXNOTVALID 31:31 /* RWEUF */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_CTXNOTVALID_DISABLED 0x00000000 /* RWE-V */
#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_CTXNOTVALID_ENABLED 0x00000001 /* RW--V */
#define NV_PBDMA_LB_ENTRY_SIZE 128 /* */
#define NV_PBDMA_LB_GPBUF_CONTROL 0x1b0 /* R--4R */
#define NV_PBDMA_LB_GPBUF_CONTROL_SIZE 31:24 /* R-XUF */
#define NV_PBDMA_LB_GPBUF_CONTROL_SIZE_128B 0x00000001 /* R---V */
#define NV_PBDMA_LB_PBBUF_CONTROL 0x1c0 /* R--4R */
#define NV_PBDMA_LB_PBBUF_CONTROL_SIZE 31:23 /* R-XUF */
#define NV_PBDMA_LB_PBBUF_CONTROL_SIZE_128B 0x00000001 /* R---V */
#define NV_PBDMA_LB_GPBUF_STATUS 0x1d0 /* R--4R */
#define NV_PBDMA_LB_GPBUF_STATUS_STATE 3:0 /* R-EVF */
#define NV_PBDMA_LB_GPBUF_STATUS_STATE_EMPTY 0x00000000 /* R-E-V */
#define NV_PBDMA_LB_GPBUF_STATUS_STATE_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_LB_GPBUF_STATUS_STATE_BUSY 0x00000003 /* R---V */
#define NV_PBDMA_LB_GPBUF_STATUS_PBDMA_REQ_COUNT 14:4 /* R-EUF */
#define NV_PBDMA_LB_GPBUF_STATUS_PBDMA_REQ_COUNT_0 0x00000000 /* R-E-V */
#define NV_PBDMA_LB_GPBUF_STATUS_MEM_REQ_COUNT 25:15 /* R-EUF */
#define NV_PBDMA_LB_GPBUF_STATUS_MEM_REQ_COUNT_0 0x00000000 /* R-E-V */
#define NV_PBDMA_LB_PBBUF_STATUS 0x1e0 /* R--4R */
#define NV_PBDMA_LB_PBBUF_STATUS_STATE 3:0 /* R-EVF */
#define NV_PBDMA_LB_PBBUF_STATUS_STATE_EMPTY 0x00000000 /* R-E-V */
#define NV_PBDMA_LB_PBBUF_STATUS_STATE_BLOCKED 0x00000002 /* R---V */
#define NV_PBDMA_LB_PBBUF_STATUS_STATE_BUSY 0x00000003 /* R---V */
#define NV_PBDMA_LB_PBBUF_STATUS_PBDMA_REQ_COUNT 14:4 /* R-EUF */
#define NV_PBDMA_LB_PBBUF_STATUS_PBDMA_REQ_COUNT_0 0x00000000 /* R-E-V */
#define NV_PBDMA_LB_PBBUF_STATUS_MEM_REQ_COUNT 25:15 /* R-EUF */
#define NV_PBDMA_LB_PBBUF_STATUS_MEM_REQ_COUNT_0 0x00000000 /* R-E-V */
#define NV_PBDMA_LB_PBBUF_THROTTLE 0x1f0 /* RW-4R */
#define NV_PBDMA_LB_PBBUF_THROTTLE_ROWS 15:0 /* RWIUF */
#define NV_PBDMA_LB_PBBUF_THROTTLE_ROWS_131KB 0x00001000 /* RW--V */
#define NV_PBDMA_LB_PBBUF_THROTTLE_ROWS_INVALID 0x0000FFFF /* RWI-V */
#define NV_PBDMA_LB_GPBUF_THROTTLE 0x300 /* RW-4R */
#define NV_PBDMA_LB_GPBUF_THROTTLE_ROWS 15:0 /* RWIUF */
#define NV_PBDMA_LB_GPBUF_THROTTLE_ROWS_131KB 0x00001000 /* RW--V */
#define NV_PBDMA_LB_GPBUF_THROTTLE_ROWS_INVALID 0x0000FFFF /* RWI-V */
#define NV_PBDMA_GLOBAL_PRI_RANGE_0 0x44fff:0x40000 /* ----M */
#endif // __ga102_dev_esched_pbdma_h__

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include/ampere/ga102/dev_ext_devices.h Normal file
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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_ext_devices_h__
#define __ga102_dev_ext_devices_h__
/* This file is autogenerated. Do not edit */
#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */
#define NV_PROM 0x003FFFFF:0x00300000 /* R---D */
#define NV_PROM_2 0x00109FFF:0x00109000 /* R---D */
#define NV_PEXTDEV_BOOT_0 0x00101000 /* RW-4R */
#define NV_PEXTDEV_BOOT_0_STRAP_GV_WIDTH 0:0 /* R-IVF */
#define NV_PEXTDEV_BOOT_0_STRAP_GV_WIDTH_WIDE 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_0_STRAP_GV_WIDTH_NARROW 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_RAMCFG 5:1 /* R-IVF */
#define NV_PEXTDEV_BOOT_0_STRAP_RAMCFG_INIT 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-IVF */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_INIT 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_27000K 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318K 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_25000K 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 9:7 /* R-IVF */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC_M 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC_J 0x00000001 /* R-I-V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL_M 0x00000002 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL_N 0x00000003 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL_CN 0x00000004 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL_BDGHI 0x00000005 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_RESERVED0 0x00000006 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_RESERVED1 0x00000007 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_13_10 13:10 /* C--VF */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_13_10_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_17_14 17:14 /* C--VF */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_17_14_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_21_18 21:18 /* C--VF */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_21_18_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_0_STRAP_ROMTYPE 23:22 /* R-IVF */
#define NV_PEXTDEV_BOOT_0_STRAP_ROMTYPE_PARALLEL 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_ROMTYPE_SERIAL_AT25F 0x00000001 /* R-I-V */
#define NV_PEXTDEV_BOOT_0_STRAP_ROMTYPE_SERIAL_SST45VF 0x00000002 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_ROMTYPE_RESERVED 0x00000003 /* R---V */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_27_24 27:24 /* C--VF */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_27_24_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_30_28 30:28 /* C--VF */
#define NV_PEXTDEV_BOOT_0_STRAP_DUMMY_30_28_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 31:31 /* RWIVF */
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */
#define NV_PEXTDEV_BOOT_0_STRAP 30:0 /* R--VF */
#define NV_PEXTDEV_NEW_BOOT_0_STRAP 0x00101000 /* RW-4R */
#define NV_PEXTDEV_NEW_BOOT_0_STRAP_VALUE 30:0 /* RW-VF */
#define NV_PEXTDEV_NEW_BOOT_0_STRAP_OVERWRITE 31:31 /* RWIVF */
#define NV_PEXTDEV_NEW_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
#define NV_PEXTDEV_NEW_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */
#define NV_PEXTDEV_BOOT_3 0x0010100C /* RW-4R */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_0_4 4:0 /* C--VF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_0_4_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_5_7 7:5 /* C--VF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_5_7_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_SUBSYSTEM_USER 8:8 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_SUBSYSTEM_USER_DISABLED 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_SUBSYSTEM_USER_ENABLED 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BOARD 9:9 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BOARD_0 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BOARD_1 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_10_11 11:10 /* C--VF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_10_11_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_MIO_EN_33V_0 12:12 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_MIO_EN_33V_0_DISABLED 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_MIO_EN_33V_0_ENABLED 0x00000001 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_MIO_EN_33V_1 13:13 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_MIO_EN_33V_1_DISABLED 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_MIO_EN_33V_1_ENABLED 0x00000001 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_14_15 15:14 /* C--VF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DUMMY_14_15_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_PCI_IOBAR 16:16 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_PCI_IOBAR_DISABLE 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_PCI_IOBAR_ENABLE 0x00000001 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02 19:17 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_DISABLED 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_2x 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_4x 0x00000002 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_8x 0x00000003 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_16x 0x00000004 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_32x 0x00000005 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_64x 0x00000006 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR02_128x 0x00000007 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1 22:20 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_DISABLED 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_2x 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_4x 0x00000002 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_8x 0x00000003 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_16x 0x00000004 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_32x 0x00000005 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_64x 0x00000006 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BLOAT_BAR1_128x 0x00000007 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BAR2_SIZE 23:23 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BAR2_SIZE_32MB 0x00000000 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_BAR2_SIZE_16MB 0x00000001 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_DUMMY_24_24 24:24 /* C--VF */
#define NV_PEXTDEV_BOOT_3_STRAP_DUMMY_24_24_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DP_PLL_VDD_33V 25:25 /* R-IVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DP_PLL_VDD_33V_USE18V 0x00000000 /* R---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_DP_PLL_VDD_33V_USE33V 0x00000001 /* R-I-V */
#define NV_PEXTDEV_BOOT_3_STRAP_DUMMY_30_26 30:26 /* C--VF */
#define NV_PEXTDEV_BOOT_3_STRAP_DUMMY_30_26_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_OVERWRITE 31:31 /* RWIVF */
#define NV_PEXTDEV_BOOT_3_STRAP_1_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
#define NV_PEXTDEV_BOOT_3_STRAP_1_OVERWRITE_ENABLED 0x00000001 /* RW--V */
#define NV_PEXTDEV_BOOT_3_STRAP_1 30:0 /* R--VF */
#define NV_PEXTDEV_NEW_BOOT_3 0x0010100C /* RW-4R */
#define NV_PEXTDEV_NEW_BOOT_3_STRAP_1_VALUE 30:0 /* RWIVF */
#define NV_PEXTDEV_NEW_BOOT_3_STRAP_1_VALUE_ZERO 0x00000000 /* RWI-V */
#define NV_PEXTDEV_NEW_BOOT_3_STRAP_1_OVERWRITE 31:31 /* RWIVF */
#define NV_PEXTDEV_NEW_BOOT_3_STRAP_1_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
#define NV_PEXTDEV_NEW_BOOT_3_STRAP_1_OVERWRITE_ENABLED 0x00000001 /* RW--V */
#define NV_PEXTDEV_BOOT_6 0x00101034 /* RW-4R */
#define NV_PEXTDEV_BOOT_6_STRAP_2_DUMMY_0_30 30:0 /* C--VF */
#define NV_PEXTDEV_BOOT_6_STRAP_2_DUMMY_0_30_VAL 0x00000000 /* C---V */
#define NV_PEXTDEV_BOOT_6_STRAP_2_OVERWRITE 31:31 /* RWIVF */
#define NV_PEXTDEV_BOOT_6_STRAP_2_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
#define NV_PEXTDEV_BOOT_6_STRAP_2_OVERWRITE_ENABLED 0x00000001 /* RW--V */
#define NV_PEXTDEV_BOOT_6_STRAP_2 30:0 /* R--VF */
#define NV_PEXTDEV_NEW_BOOT_6 0x00101034 /* RW-4R */
#define NV_PEXTDEV_NEW_BOOT_6_STRAP_2_VALUE 30:0 /* RWIVF */
#define NV_PEXTDEV_NEW_BOOT_6_STRAP_2_VALUE_ZERO 0x00000000 /* RWI-V */
#define NV_PEXTDEV_NEW_BOOT_6_STRAP_2_OVERWRITE 31:31 /* RWIVF */
#define NV_PEXTDEV_NEW_BOOT_6_STRAP_2_OVERWRITE_DISABLED 0x00000000 /* RWI-V */
#define NV_PEXTDEV_NEW_BOOT_6_STRAP_2_OVERWRITE_ENABLED 0x00000001 /* RW--V */
#define NV_PROM_DATA(i) (0x00300000+(i)) /* R--1A */
#define NV_PROM_DATA__SIZE_1 1048576 /* */
#define NV_PROM_DATA_VALUE 7:0 /* R--VF */
#define NV_PROM_2_DATA(i) (0x00109000+(i)) /* R--1A */
#define NV_PROM_2_DATA__SIZE_1 4096 /* */
#define NV_PROM_2_DATA_VALUE 7:0 /* R--VF */
#endif // __ga102_dev_ext_devices_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_falcon_v1_h__
#define __ga102_dev_falcon_v1_h__
/* This file is autogenerated. Do not edit */
#define NV_FALCON_NVDEC_BASE 0x00848000
#define NV_FALCON_NVDEC0_BASE 0x00848000
#define NV_FALCON_NVDEC1_BASE 0x0084c000
#define NV_FALCON_NVDEC2_BASE 0x00850000
#define NV_FALCON_NVDEC3_BASE 0x00854000
#define NV_FALCON_NVDEC4_BASE 0x00858000
#define NV_FALCON_MSVLD_BASE 0x00830000
#define NV_FALCON_MSPDEC_BASE 0x00831000
#define NV_FALCON_MSPPP_BASE 0x00832000
#define NV_FALCON_SEC_BASE 0x00087000
#define NV_FALCON_PWR_BASE 0x0010a000
#define NV_FALCON_CE0_BASE 0x00104000
#define NV_FALCON_CE1_BASE 0x00105000
#define NV_PCE_CE2_BASE 0x00106000
#define NV_FALCON_MSENC_BASE 0x001c2000
#define NV_FALCON_NVENC_BASE 0x001c8000
#define NV_FALCON_HDA_BASE 0x001c3000
#endif // __ga102_dev_falcon_v1_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_fault_h__
#define __ga102_dev_fault_h__
/* This file is autogenerated. Do not edit */
#define NV_PFAULT /* ----G */
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 64 /* */
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 9 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 192 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 8 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 25 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 26 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 27 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 30 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 15 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 16 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 17 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 18 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 19 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 20 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 21 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 22 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 23 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 24 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 6 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 11 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 12 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 13 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 31 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST0 32 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST1 33 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST2 34 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST3 35 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST4 36 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST5 37 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST6 38 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST7 39 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST8 40 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST9 41 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST10 42 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST11 43 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST12 44 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST13 45 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST14 46 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST15 47 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST16 48 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST17 49 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST18 50 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST19 51 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST20 52 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST21 53 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST22 54 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST23 55 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST24 56 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST25 57 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST26 58 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST27 59 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST28 60 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST29 61 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST30 62 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST31 63 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 128 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 129 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 130 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 131 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 132 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 133 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 134 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 135 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 136 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 137 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 138 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 139 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 140 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 141 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 142 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 143 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 144 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 145 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 146 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 147 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 148 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 149 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 150 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 151 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 152 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 153 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 154 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 155 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 156 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 157 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 158 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 159 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 160 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 161 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 162 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 163 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 164 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 165 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 166 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 167 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 168 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 169 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 170 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 171 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 172 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 173 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 174 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 175 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 176 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 177 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 178 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 179 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 180 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 181 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 182 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 183 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 184 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 185 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 186 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 187 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 188 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 189 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 190 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 191 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 192 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 193 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 194 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 195 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 196 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 197 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 198 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 199 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 200 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 201 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 202 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 203 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 204 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 205 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 206 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 207 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 208 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 209 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 210 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 211 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 212 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 213 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 214 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 215 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 216 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 217 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 218 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 219 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 220 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 221 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 222 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 223 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 224 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 225 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 226 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 227 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 228 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 229 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 230 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 231 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 232 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 233 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 234 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 235 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 236 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 237 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 238 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 239 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 240 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 241 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 242 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 243 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 244 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 245 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 246 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 247 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 248 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 249 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 250 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 251 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 252 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 253 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 254 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 255 /* */
#define NV_PFAULT_FAULT_TYPE 4:0 /* */
#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */
#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */
#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */
#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */
#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */
#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */
#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */
#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */
#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE 0x0000000b /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */
#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */
#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */
#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */
#define NV_PFAULT_CLIENT 14:8 /* */
#define NV_PFAULT_CLIENT_GPC_T1_0 0x00000000 /* */
#define NV_PFAULT_CLIENT_GPC_T1_1 0x00000001 /* */
#define NV_PFAULT_CLIENT_GPC_T1_2 0x00000002 /* */
#define NV_PFAULT_CLIENT_GPC_T1_3 0x00000003 /* */
#define NV_PFAULT_CLIENT_GPC_T1_4 0x00000004 /* */
#define NV_PFAULT_CLIENT_GPC_T1_5 0x00000005 /* */
#define NV_PFAULT_CLIENT_GPC_T1_6 0x00000006 /* */
#define NV_PFAULT_CLIENT_GPC_T1_7 0x00000007 /* */
#define NV_PFAULT_CLIENT_GPC_PE_0 0x00000008 /* */
#define NV_PFAULT_CLIENT_GPC_PE_1 0x00000009 /* */
#define NV_PFAULT_CLIENT_GPC_PE_2 0x0000000A /* */
#define NV_PFAULT_CLIENT_GPC_PE_3 0x0000000B /* */
#define NV_PFAULT_CLIENT_GPC_PE_4 0x0000000C /* */
#define NV_PFAULT_CLIENT_GPC_PE_5 0x0000000D /* */
#define NV_PFAULT_CLIENT_GPC_PE_6 0x0000000E /* */
#define NV_PFAULT_CLIENT_GPC_PE_7 0x0000000F /* */
#define NV_PFAULT_CLIENT_GPC_RAST 0x00000010 /* */
#define NV_PFAULT_CLIENT_GPC_GCC 0x00000011 /* */
#define NV_PFAULT_CLIENT_GPC_GPCCS 0x00000012 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_0 0x00000013 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_1 0x00000014 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_2 0x00000015 /* */
#define NV_PFAULT_CLIENT_GPC_PROP_3 0x00000016 /* */
#define NV_PFAULT_CLIENT_GPC_T1_8 0x00000021 /* */
#define NV_PFAULT_CLIENT_GPC_T1_9 0x00000022 /* */
#define NV_PFAULT_CLIENT_GPC_T1_10 0x00000023 /* */
#define NV_PFAULT_CLIENT_GPC_T1_11 0x00000024 /* */
#define NV_PFAULT_CLIENT_GPC_T1_12 0x00000025 /* */
#define NV_PFAULT_CLIENT_GPC_T1_13 0x00000026 /* */
#define NV_PFAULT_CLIENT_GPC_T1_14 0x00000027 /* */
#define NV_PFAULT_CLIENT_GPC_T1_15 0x00000028 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_0 0x00000029 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_1 0x0000002A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_2 0x0000002B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_3 0x0000002C /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_4 0x0000002D /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_5 0x0000002E /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_6 0x0000002F /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_7 0x00000030 /* */
#define NV_PFAULT_CLIENT_GPC_PE_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_PE_9 0x00000032 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_8 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_9 0x00000034 /* */
#define NV_PFAULT_CLIENT_GPC_T1_16 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_T1_17 0x00000036 /* */
#define NV_PFAULT_CLIENT_GPC_T1_18 0x00000037 /* */
#define NV_PFAULT_CLIENT_GPC_T1_19 0x00000038 /* */
#define NV_PFAULT_CLIENT_GPC_PE_10 0x00000039 /* */
#define NV_PFAULT_CLIENT_GPC_PE_11 0x0000003A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_10 0x0000003B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_11 0x0000003C /* */
#define NV_PFAULT_CLIENT_GPC_T1_20 0x0000003D /* */
#define NV_PFAULT_CLIENT_GPC_T1_21 0x0000003E /* */
#define NV_PFAULT_CLIENT_GPC_T1_22 0x0000003F /* */
#define NV_PFAULT_CLIENT_GPC_T1_23 0x00000040 /* */
#define NV_PFAULT_CLIENT_GPC_PE_12 0x00000041 /* */
#define NV_PFAULT_CLIENT_GPC_PE_13 0x00000042 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_12 0x00000043 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_13 0x00000044 /* */
#define NV_PFAULT_CLIENT_GPC_T1_24 0x00000045 /* */
#define NV_PFAULT_CLIENT_GPC_T1_25 0x00000046 /* */
#define NV_PFAULT_CLIENT_GPC_T1_26 0x00000047 /* */
#define NV_PFAULT_CLIENT_GPC_T1_27 0x00000048 /* */
#define NV_PFAULT_CLIENT_GPC_PE_14 0x00000049 /* */
#define NV_PFAULT_CLIENT_GPC_PE_15 0x0000004A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_14 0x0000004B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_15 0x0000004C /* */
#define NV_PFAULT_CLIENT_GPC_T1_28 0x0000004D /* */
#define NV_PFAULT_CLIENT_GPC_T1_29 0x0000004E /* */
#define NV_PFAULT_CLIENT_GPC_T1_30 0x0000004F /* */
#define NV_PFAULT_CLIENT_GPC_T1_31 0x00000050 /* */
#define NV_PFAULT_CLIENT_GPC_PE_16 0x00000051 /* */
#define NV_PFAULT_CLIENT_GPC_PE_17 0x00000052 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_16 0x00000053 /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_17 0x00000054 /* */
#define NV_PFAULT_CLIENT_GPC_T1_32 0x00000055 /* */
#define NV_PFAULT_CLIENT_GPC_T1_33 0x00000056 /* */
#define NV_PFAULT_CLIENT_GPC_T1_34 0x00000057 /* */
#define NV_PFAULT_CLIENT_GPC_T1_35 0x00000058 /* */
#define NV_PFAULT_CLIENT_GPC_PE_18 0x00000059 /* */
#define NV_PFAULT_CLIENT_GPC_PE_19 0x0000005A /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_18 0x0000005B /* */
#define NV_PFAULT_CLIENT_GPC_TPCCS_19 0x0000005C /* */
#define NV_PFAULT_CLIENT_GPC_T1_36 0x0000005D /* */
#define NV_PFAULT_CLIENT_GPC_T1_37 0x0000005E /* */
#define NV_PFAULT_CLIENT_GPC_T1_38 0x0000005F /* */
#define NV_PFAULT_CLIENT_GPC_T1_39 0x00000060 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_2 0x00000072 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_3 0x00000073 /* */
#define NV_PFAULT_CLIENT_GPC_GPM 0x00000017 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_0 0x00000018 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_1 0x00000019 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_2 0x0000001A /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_3 0x0000001B /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_4 0x0000001C /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_5 0x0000001D /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_6 0x0000001E /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_7 0x0000001F /* */
#define NV_PFAULT_CLIENT_GPC_RGG_UTLB 0x00000020 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_8 0x00000031 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_9 0x00000032 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_10 0x00000033 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_11 0x00000034 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_12 0x00000035 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_13 0x00000036 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_14 0x00000037 /* */
#define NV_PFAULT_CLIENT_GPC_LTP_UTLB_15 0x00000038 /* */
#define NV_PFAULT_CLIENT_HUB_VIP 0x00000000 /* */
#define NV_PFAULT_CLIENT_HUB_CE0 0x00000001 /* */
#define NV_PFAULT_CLIENT_HUB_CE1 0x00000002 /* */
#define NV_PFAULT_CLIENT_HUB_DNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_DISPNISO 0x00000003 /* */
#define NV_PFAULT_CLIENT_HUB_FE0 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FE 0x00000004 /* */
#define NV_PFAULT_CLIENT_HUB_FECS0 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_FECS 0x00000005 /* */
#define NV_PFAULT_CLIENT_HUB_HOST 0x00000006 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU 0x00000007 /* */
#define NV_PFAULT_CLIENT_HUB_HOST_CPU_NB 0x00000008 /* */
#define NV_PFAULT_CLIENT_HUB_ISO 0x00000009 /* */
#define NV_PFAULT_CLIENT_HUB_MMU 0x0000000A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC0 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC 0x0000000B /* */
#define NV_PFAULT_CLIENT_HUB_CE3 0x0000000C /* */
#define NV_PFAULT_CLIENT_HUB_NVENC1 0x0000000D /* */
#define NV_PFAULT_CLIENT_HUB_NISO 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_ACTRS 0x0000000E /* */
#define NV_PFAULT_CLIENT_HUB_P2P 0x0000000F /* */
#define NV_PFAULT_CLIENT_HUB_PD 0x00000010 /* */
#define NV_PFAULT_CLIENT_HUB_PERF0 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PERF 0x00000011 /* */
#define NV_PFAULT_CLIENT_HUB_PMU 0x00000012 /* */
#define NV_PFAULT_CLIENT_HUB_RASTERTWOD 0x00000013 /* */
#define NV_PFAULT_CLIENT_HUB_SCC 0x00000014 /* */
#define NV_PFAULT_CLIENT_HUB_SCC_NB 0x00000015 /* */
#define NV_PFAULT_CLIENT_HUB_SEC 0x00000016 /* */
#define NV_PFAULT_CLIENT_HUB_SSYNC 0x00000017 /* */
#define NV_PFAULT_CLIENT_HUB_GRCOPY 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_CE2 0x00000018 /* */
#define NV_PFAULT_CLIENT_HUB_XV 0x00000019 /* */
#define NV_PFAULT_CLIENT_HUB_MMU_NB 0x0000001A /* */
#define NV_PFAULT_CLIENT_HUB_NVENC0 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_NVENC 0x0000001B /* */
#define NV_PFAULT_CLIENT_HUB_DFALCON 0x0000001C /* */
#define NV_PFAULT_CLIENT_HUB_SKED0 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_SKED 0x0000001D /* */
#define NV_PFAULT_CLIENT_HUB_AFALCON 0x0000001E /* */
#define NV_PFAULT_CLIENT_HUB_DONT_CARE 0x0000001F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE0 0x00000020 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE1 0x00000021 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE2 0x00000022 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE3 0x00000023 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE4 0x00000024 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE5 0x00000025 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE6 0x00000026 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE7 0x00000027 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE8 0x00000028 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE9 0x00000029 /* */
#define NV_PFAULT_CLIENT_HUB_HSHUB 0x0000002A /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X0 0x0000002B /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X1 0x0000002C /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X2 0x0000002D /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */
#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */
#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */
#define NV_PFAULT_CLIENT_HUB_DWBIF 0x00000036 /* */
#define NV_PFAULT_CLIENT_HUB_FBFALCON 0x00000037 /* */
#define NV_PFAULT_CLIENT_HUB_CE_SHIM 0x00000038 /* */
#define NV_PFAULT_CLIENT_HUB_GSP 0x00000039 /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC1 0x0000003A /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC2 0x0000003B /* */
#define NV_PFAULT_CLIENT_HUB_NVJPG0 0x0000003C /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC3 0x0000003D /* */
#define NV_PFAULT_CLIENT_HUB_NVDEC4 0x0000003E /* */
#define NV_PFAULT_CLIENT_HUB_OFA0 0x0000003F /* */
#define NV_PFAULT_CLIENT_HUB_HSCE10 0x00000040 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE11 0x00000041 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE12 0x00000042 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE13 0x00000043 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE14 0x00000044 /* */
#define NV_PFAULT_CLIENT_HUB_HSCE15 0x00000045 /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X8 0x00000046 /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X9 0x00000047 /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X10 0x00000048 /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X11 0x00000049 /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X12 0x0000004A /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X13 0x0000004B /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X14 0x0000004C /* */
#define NV_PFAULT_CLIENT_HUB_PTP_X15 0x0000004D /* */
#define NV_PFAULT_CLIENT_HUB_FE1 0x0000004E /* */
#define NV_PFAULT_CLIENT_HUB_FE2 0x0000004F /* */
#define NV_PFAULT_CLIENT_HUB_FE3 0x00000050 /* */
#define NV_PFAULT_CLIENT_HUB_FE4 0x00000051 /* */
#define NV_PFAULT_CLIENT_HUB_FE5 0x00000052 /* */
#define NV_PFAULT_CLIENT_HUB_FE6 0x00000053 /* */
#define NV_PFAULT_CLIENT_HUB_FE7 0x00000054 /* */
#define NV_PFAULT_CLIENT_HUB_FECS1 0x00000055 /* */
#define NV_PFAULT_CLIENT_HUB_FECS2 0x00000056 /* */
#define NV_PFAULT_CLIENT_HUB_FECS3 0x00000057 /* */
#define NV_PFAULT_CLIENT_HUB_FECS4 0x00000058 /* */
#define NV_PFAULT_CLIENT_HUB_FECS5 0x00000059 /* */
#define NV_PFAULT_CLIENT_HUB_FECS6 0x0000005A /* */
#define NV_PFAULT_CLIENT_HUB_FECS7 0x0000005B /* */
#define NV_PFAULT_CLIENT_HUB_SKED1 0x0000005C /* */
#define NV_PFAULT_CLIENT_HUB_SKED2 0x0000005D /* */
#define NV_PFAULT_CLIENT_HUB_SKED3 0x0000005E /* */
#define NV_PFAULT_CLIENT_HUB_SKED4 0x0000005F /* */
#define NV_PFAULT_CLIENT_HUB_SKED5 0x00000060 /* */
#define NV_PFAULT_CLIENT_HUB_SKED6 0x00000061 /* */
#define NV_PFAULT_CLIENT_HUB_SKED7 0x00000062 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#define NV_PFAULT_ACCESS_TYPE 19:16 /* */
#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */
#define NV_PFAULT_MMU_CLIENT_TYPE 20:20 /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */
#define NV_PFAULT_GPC_ID 28:24 /* */
#define NV_PFAULT_PROTECTED_MODE 29:29 /* */
#define NV_PFAULT_REPLAYABLE_FAULT_EN 30:30 /* */
#define NV_PFAULT_VALID 31:31 /* */
#endif // __ga102_dev_fault_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_fbhub_sec_bus_h__
#define __ga102_dev_fbhub_sec_bus_h__
/* This file is autogenerated. Do not edit */
#define NV_SFBHUB 0x0000FFFF:0x00000000 /* RW--D */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK 0x00000000 /* RW-4R */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK 0x00000004 /* RW-4R */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_SETUP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK 0x00000024 /* RW-4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG 0x00000008 /* RW-4R */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG__PRIV_LEVEL_MASK 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG1 1:1 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG1_ENCRYPT_EN 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG1_ENCRYPT_DIS 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG2 2:2 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG2_ENCRYPT_EN 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG2_ENCRYPT_DIS 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG3 3:3 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG3_ENCRYPT_EN 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG3_ENCRYPT_DIS 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG(i) (i):(i) /* */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG__SIZE_1 32 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG_ENCRYPT_EN 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_CFG_REG_ENCRYPT_DIS 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID 0x0000000C /* R--4R */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG1 1:1 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG1_FALSE 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG1_TRUE 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG2 2:2 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG2_FALSE 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG2_TRUE 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG3 3:3 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG3_FALSE 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG3_TRUE 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG(i) (i):(i) /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG__SIZE_1 32 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG_FALSE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_REG_TRUE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID 0x00000010 /* R--4R */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG1 1:1 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG1_FALSE 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG1_TRUE 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG2 2:2 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG2_FALSE 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG2_TRUE 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG3 3:3 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG3_FALSE 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG3_TRUE 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG(i) (i):(i) /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG__SIZE_1 32 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG_FALSE 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_REG_TRUE 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET 0x00000014 /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET__PRIV_LEVEL_MASK 0x00000004 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG1 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG1_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG1_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG2 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG2_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG2_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG3 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG3_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG3_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG(i) (i):(i) /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG__SIZE_1 32 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG_INIT 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_SET_REG_SET 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR 0x00000018 /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR__PRIV_LEVEL_MASK 0x00000004 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG1 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG1_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG1_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG2 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG2_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG2_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG3 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG3_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG3_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG(i) (i):(i) /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG__SIZE_1 32 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG_INIT 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_READ_VALID_CLR_REG_CLR 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET 0x0000001C /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET__PRIV_LEVEL_MASK 0x00000004 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG1 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG1_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG1_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG2 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG2_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG2_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG3 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG3_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG3_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG(i) (i):(i) /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG__SIZE_1 32 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG_INIT 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_SET_REG_SET 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR 0x00000020 /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR__PRIV_LEVEL_MASK 0x00000004 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG1 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG1_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG1_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG2 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG2_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG2_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG3 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG3_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG3_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG(i) (i):(i) /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG__SIZE_1 32 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG_INIT 0x00000000 /* */
#define NV_SFBHUB_ENCRYPTION_ACR_VIDMEM_WRITE_VALID_CLR_REG_CLR 0x00000001 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLIENT(i) (0x00000040+(i)*4) /* R--4A */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLIENT__SIZE_1 8 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLIENT_FIELD 31:0 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLIENT_FIELD_INIT 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE 0x00000060 /* R--4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_GC_OVERFLOW 0:0 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_GC_OVERFLOW_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_READ 1:1 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_READ_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_READ_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_WRITE 2:2 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_WRITE_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_WRITE_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_ENCRYPTION_DISABLED 3:3 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_KEY_IS_ZERO 4:4 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_KEY_IS_ZERO_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_NONCE_IS_ZERO 5:5 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_NONCE_IS_ZERO_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0 0x00000100 /* RW-4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0__PRIV_LEVEL_MASK 0x00000024 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_GC_OVERFLOW 0:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_GC_OVERFLOW_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_GC_OVERFLOW_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_READ 1:1 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_READ_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_READ_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_WRITE 2:2 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_WRITE_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_WRITE_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_ENCRYPTION_DISABLED 3:3 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_ENCRYPTION_DISABLED_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_ENCRYPTION_DISABLED_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_KEY_IS_ZERO 4:4 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_KEY_IS_ZERO_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_KEY_IS_ZERO_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_NONCE_IS_ZERO 5:5 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_NONCE_IS_ZERO_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_NONCE_IS_ZERO_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_VPR_PAGEIN_GC 6:6 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ0_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1 0x00000104 /* RW-4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1__PRIV_LEVEL_MASK 0x00000024 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_GC_OVERFLOW 0:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_GC_OVERFLOW_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_GC_OVERFLOW_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_READ 1:1 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_READ_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_READ_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_WRITE 2:2 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_WRITE_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_WRITE_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_ENCRYPTION_DISABLED 3:3 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_ENCRYPTION_DISABLED_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_ENCRYPTION_DISABLED_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_KEY_IS_ZERO 4:4 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_KEY_IS_ZERO_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_KEY_IS_ZERO_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_NONCE_IS_ZERO 5:5 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_NONCE_IS_ZERO_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_NONCE_IS_ZERO_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_VPR_PAGEIN_GC 6:6 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* RW--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CODE_MASK_IRQ1_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0 0x00000108 /* R--4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_GC_OVERFLOW 0:0 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_GC_OVERFLOW_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_READ 1:1 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_READ_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_READ_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_WRITE 2:2 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_WRITE_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_WRITE_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_ENCRYPTION_DISABLED 3:3 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_KEY_IS_ZERO 4:4 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_KEY_IS_ZERO_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_NONCE_IS_ZERO 5:5 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_NONCE_IS_ZERO_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ0_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1 0x0000010C /* R--4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_GC_OVERFLOW 0:0 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_GC_OVERFLOW_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_GC_OVERFLOW_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_READ 1:1 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_READ_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_READ_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_WRITE 2:2 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_WRITE_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_WRITE_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_ENCRYPTION_DISABLED 3:3 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_ENCRYPTION_DISABLED_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_ENCRYPTION_DISABLED_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_KEY_IS_ZERO 4:4 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_KEY_IS_ZERO_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_KEY_IS_ZERO_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_NONCE_IS_ZERO 5:5 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_NONCE_IS_ZERO_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_NONCE_IS_ZERO_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_VPR_PAGEIN_GC 6:6 /* R-IVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* R---V */
#define NV_SFBHUB_ENCRYPTION_ERROR_STATUS_IRQ1_INVALID_VPR_PAGEIN_GC_CLR 0x00000000 /* R-I-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0 0x00000110 /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0__PRIV_LEVEL_MASK 0x00000024 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_GC_OVERFLOW 0:0 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_GC_OVERFLOW_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_GC_OVERFLOW_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_READ 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_READ_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_READ_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_WRITE 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_WRITE_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_WRITE_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_ENCRYPTION_DISABLED 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_ENCRYPTION_DISABLED_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_ENCRYPTION_DISABLED_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_KEY_IS_ZERO 4:4 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_KEY_IS_ZERO_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_KEY_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_NONCE_IS_ZERO 5:5 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_NONCE_IS_ZERO_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_NONCE_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_VPR_PAGEIN_GC 6:6 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ0_INVALID_VPR_PAGEIN_GC_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1 0x00000114 /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1__PRIV_LEVEL_MASK 0x00000024 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_GC_OVERFLOW 0:0 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_GC_OVERFLOW_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_GC_OVERFLOW_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_READ 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_READ_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_READ_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_WRITE 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_WRITE_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_WRITE_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_ENCRYPTION_DISABLED 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_ENCRYPTION_DISABLED_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_ENCRYPTION_DISABLED_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_KEY_IS_ZERO 4:4 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_KEY_IS_ZERO_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_KEY_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_NONCE_IS_ZERO 5:5 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_NONCE_IS_ZERO_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_NONCE_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_VPR_PAGEIN_GC 6:6 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_VPR_PAGEIN_GC_SET 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_SET_IRQ1_INVALID_VPR_PAGEIN_GC_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0 0x00000118 /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0__PRIV_LEVEL_MASK 0x00000024 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_GC_OVERFLOW 0:0 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_GC_OVERFLOW_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_GC_OVERFLOW_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_READ 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_READ_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_READ_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_WRITE 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_WRITE_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_WRITE_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_ENCRYPTION_DISABLED 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_ENCRYPTION_DISABLED_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_ENCRYPTION_DISABLED_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_KEY_IS_ZERO 4:4 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_KEY_IS_ZERO_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_KEY_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_NONCE_IS_ZERO 5:5 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_NONCE_IS_ZERO_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_NONCE_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_VPR_PAGEIN_GC 6:6 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_VPR_PAGEIN_GC_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ0_INVALID_VPR_PAGEIN_GC_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1 0x0000011C /* -W-4R */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1__PRIV_LEVEL_MASK 0x00000024 /* */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_GC_OVERFLOW 0:0 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_GC_OVERFLOW_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_GC_OVERFLOW_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_READ 1:1 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_READ_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_READ_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_WRITE 2:2 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_WRITE_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_WRITE_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_ENCRYPTION_DISABLED 3:3 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_ENCRYPTION_DISABLED_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_ENCRYPTION_DISABLED_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_KEY_IS_ZERO 4:4 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_KEY_IS_ZERO_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_KEY_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_NONCE_IS_ZERO 5:5 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_NONCE_IS_ZERO_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_NONCE_IS_ZERO_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_VPR_PAGEIN_GC 6:6 /* -WIVF */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_VPR_PAGEIN_GC_CLR 0x00000001 /* -W--V */
#define NV_SFBHUB_ENCRYPTION_ERROR_CLR_IRQ1_INVALID_VPR_PAGEIN_GC_INIT 0x00000000 /* -WI-V */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBKEY(i) (0x00001000+(i)*4) /* RW-4A */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBKEY__SIZE_1 16 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBKEY__REGION_SIZE 4 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBKEY__PRIV_LEVEL_MASK 0x00000004 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBKEY_FIELD 31:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBKEY_FIELD_INIT 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBNONCE(i) (0x00002000+(i)*4) /* RW-4A */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBNONCE__SIZE_1 16 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBNONCE__REGION_SIZE 4 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBNONCE__PRIV_LEVEL_MASK 0x00000004 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBNONCE_FIELD 31:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBNONCE_FIELD_INIT 0x00000000 /* RWI-V */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBCOUNTER(i) (0x00003000+(i)*4) /* RW-4A */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBCOUNTER__SIZE_1 8 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBCOUNTER__REGION_SIZE 2 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBCOUNTER__PRIV_LEVEL_MASK 0x00000004 /* */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBCOUNTER_FIELD 31:0 /* RWIVF */
#define NV_SFBHUB_ENCRYPTION_REGION_SUBCOUNTER_FIELD_INIT 0x00000000 /* RWI-V */
#endif // __ga102_dev_fbhub_sec_bus_h__

228
include/ampere/ga102/dev_fbif_v4.h Normal file
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@@ -0,0 +1,228 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_fbif_v4_h__
#define __ga102_dev_fbif_v4_h__
/* This file is autogenerated. Do not edit */
#define NV_FALCON_NVDEC_BASE 0x00848000
#define NV_FALCON_NVDEC0_BASE 0x00848000
#define NV_FALCON_NVDEC1_BASE 0x0084c000
#define NV_FALCON_MSVLD_BASE 0x00084000
#define NV_FALCON_MSPDEC_BASE 0x00085000
#define NV_FALCON_MSPPP_BASE 0x00086000
#define NV_FALCON_PWR_BASE 0x0010a000
#define NV_FALCON_CE0_BASE 0x00104000
#define NV_FALCON_CE1_BASE 0x00105000
#define NV_FALCON_NVENC_BASE 0x001c8000
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK 0x00000070 /* RWI4R */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
#define NV_PFALCON_FBIF_TRANSCFG__PRIV_LEVEL_MASK 0x00000070 /* */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_INIT 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x00000002 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_INIT 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x00000002 /* R---V */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK0_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK0_ENABLE 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK0_DISABLE 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK1_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK1_ENABLE 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_WACHK1_DISABLE 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK0_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK0_ENABLE 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK0_DISABLE 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK1_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK1_ENABLE 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_RACHK1_DISABLE 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG 16:16 /* RWIVF */
#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG_OWN 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_INSTBLK 0x00000020 /* R--4R */
#define NV_PFALCON_FBIF_INSTBLK_PTR 27:0 /* R--VF */
#define NV_PFALCON_FBIF_INSTBLK_TARGET 29:28 /* R--VF */
#define NV_PFALCON_FBIF_INSTBLK_TARGET_LOCAL_FB 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
#define NV_PFALCON_FBIF_BIND_STATUS 0x00000028 /* R--4R */
#define NV_PFALCON_FBIF_BIND_STATUS_STATUS 1:0 /* R-IVF */
#define NV_PFALCON_FBIF_BIND_STATUS_STATUS_NOT_BIND 0x00000000 /* R-I-V */
#define NV_PFALCON_FBIF_BIND_STATUS_STATUS_BOUND 0x00000002 /* R---V */
#define NV_PFALCON_FBIF_BIND_STATUS_GFID 9:4 /* R--VF */
#define NV_PFALCON_FBIF_BIND_STATUS_GFID_INIT 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_BIND_STATUS_ENGINE_ID 23:16 /* R--VF */
#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
#define NV_PFALCON_FBIF_CTL_FLUSH 0:0 /* RW-VF */
#define NV_PFALCON_FBIF_CTL_FLUSH_SET 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_FLUSH_CLEAR 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */
#define NV_PFALCON_FBIF_CTL_INVAL_CONTEXT_SET 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */
#define NV_PFALCON_FBIF_CTL_CLR_BWCOUNT_SET 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_ENABLE 4:4 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ENABLE_INIT 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_CTL_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_ENABLE_FALSE 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */
#define NV_PFALCON_FBIF_CTL_CLR_IDLEWDERR_SET 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_RESET 6:6 /* RW-VF */
#define NV_PFALCON_FBIF_CTL_RESET_SET 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_RESET_CLEAR 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_IDLE 8:8 /* R--VF */
#define NV_PFALCON_FBIF_CTL_IDLE_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_CTL_IDLE_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */
#define NV_PFALCON_FBIF_CTL_IDLEWDERR_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_CTL_IDLEWDERR_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_CTL_SRTOUT 10:10 /* R--VF */
#define NV_PFALCON_FBIF_CTL_SRTOUT_TRUE 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_CTL_SRTOUT_FALSE 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */
#define NV_PFALCON_FBIF_CTL_CLR_SRTOUT_SET 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_CTL_CLR_SRTOUT_CLEAR 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */
#define NV_PFALCON_FBIF_CTL_SRTOVAL_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_THROTTLE 0x0000002c /* RW-4R */
#define NV_PFALCON_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
#define NV_PFALCON_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */
#define NV_PFALCON_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
#define NV_PFALCON_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */
#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */
#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */
#define NV_PFALCON_FBIF_REGIONCFG 0x0000006c /* RW-4R */
#define NV_PFALCON_FBIF_REGIONCFG__PRIV_LEVEL_MASK 0x00000070 /* */
#define NV_PFALCON_FBIF_REGIONCFG_T0 3:0 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T0_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_T1 7:4 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T1_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_T2 11:8 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T2_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_T3 15:12 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T3_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_T4 19:16 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T4_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_T5 23:20 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T5_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_T6 27:24 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T6_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_REGIONCFG_T7 31:28 /* RWIVF */
#define NV_PFALCON_FBIF_REGIONCFG_T7_INIT 0x00000000 /* RWI-V */
#define NV_PFALCON_FBIF_CG1 0x00000074 /* RW-4R */
#define NV_PFALCON_FBIF_CG1_SLCG 3:0 /* */
#define NV_PFALCON_FBIF_CG1_SLCG_ENABLED 0 /* */
#define NV_PFALCON_FBIF_CG1_SLCG_DISABLED 0xF /* */
#define NV_PFALCON_FBIF_CG1_SLCG__PROD 0x0 /* */
#define NV_PFALCON_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */
#define NV_PFALCON_FBIF_CG1_SLCG_MSD0_ENABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CG1_SLCG_MSD0_DISABLED 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */
#define NV_PFALCON_FBIF_CG1_SLCG_MSD1_ENABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CG1_SLCG_MSD1_DISABLED 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */
#define NV_PFALCON_FBIF_CG1_SLCG_FB0_ENABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CG1_SLCG_FB0_DISABLED 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */
#define NV_PFALCON_FBIF_CG1_SLCG_FB1_ENABLED 0x00000000 /* RW--V */
#define NV_PFALCON_FBIF_CG1_SLCG_FB1_DISABLED 0x00000001 /* RWI-V */
#define NV_PFALCON_FBIF_ACHK_BLK(i) (0x00000030+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_BLK__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */
#define NV_PFALCON_FBIF_ACHK_CTL(i) (0x00000034+(i)*8) /* RW-4A */
#define NV_PFALCON_FBIF_ACHK_CTL__SIZE_1 2 /* */
#define NV_PFALCON_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */
#define NV_PFALCON_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */
#define NV_PFALCON_FBIF_ACHK_CTL_TYPE_INSIDE 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */
#define NV_PFALCON_FBIF_ACHK_CTL_STATE_DISABLE 0x00000000 /* R---V */
#define NV_PFALCON_FBIF_ACHK_CTL_STATE_ENABLE 0x00000001 /* R---V */
#define NV_PFALCON_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */
#define NV_PFALCON_FBIF_BW_ALLOC 0x0000004c /* RW-4R */
#define NV_PFALCON_FBIF_BW_ALLOC_VAL 31:0 /* */
#define NV_PFALCON_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */
#define NV_PFALCON_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */
#define NV_PFALCON_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */
#define NV_PFALCON_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */
#endif // __ga102_dev_fbif_v4_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_fifo_h__
#define __ga102_dev_fifo_h__
/* This file is autogenerated. Do not edit */
#define NV_HOST_PFIFO_NUM_RUNLISTS 16
#define NV_HOST_MAX_NUM_LBS 12
#endif // __ga102_dev_fifo_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_flush_h__
#define __ga102_dev_flush_h__
/* This file is autogenerated. Do not edit */
#define NV_UFLUSH 0x00070fff:0x00070000 /* RW--D */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE 0x00070004 /* RW-4R */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_PENDING_ISSUE 0x00000000 /* -W--V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_SYSMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE 0x00070008 /* RW-4R */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_PENDING_ISSUE 0x00000000 /* -W--V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_PEERMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS 0x0007000c /* RW-4R */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_PENDING_ISSUE 0x00000000 /* -W--V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_CLEAN_COMPTAGS_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_FLUSH_DIRTY 0x00070010 /* RW-4R */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_PENDING_ISSUE 0x00000000 /* -W--V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_FLUSH_DIRTY_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS 0x00070014 /* RW-4R */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS_PENDING_ISSUE 0x00000000 /* -W--V */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_L2_WAIT_FOR_SYS_PENDING_READS_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_UFLUSH_FB_FLUSH 0x00070000 /* RW-4R */
#define NV_UFLUSH_FB_FLUSH_PENDING 0:0 /* RWIUF */
#define NV_UFLUSH_FB_FLUSH_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_UFLUSH_FB_FLUSH_PENDING_BUSY 0x00000001 /* R---V */
#define NV_UFLUSH_FB_FLUSH_PENDING_ISSUE 0x00000000 /* -W--V */
#define NV_UFLUSH_FB_FLUSH_OUTSTANDING 1:1 /* R-IUF */
#define NV_UFLUSH_FB_FLUSH_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_UFLUSH_FB_FLUSH_OUTSTANDING_TRUE 0x00000001 /* R---V */
#endif // __ga102_dev_flush_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
/* This file is autogenerated by ref2h.pl. Do not edit */
#define NV_JTAG_SEC_CFG_CLUSTER_ID_ga103 0
#define NV_JTAG_SEC_CFG_ID_ga103 8
#define NV_JTAG_SEC_CFG_CHAINLENGTH_ga103 50
#define NV_JTAG_SEC_CFG_d0_0_i1500_cluster_bypass_ga103 31:31
#define NV_JTAG_SEC_CFG_f0_0_i1500_cluster_bypass_ga103 23:23
#define NV_JTAG_SEC_CFG_f0_1_i1500_cluster_bypass_ga103 22:22
#define NV_JTAG_SEC_CFG_f0_2_i1500_cluster_bypass_ga103 3:3
#define NV_JTAG_SEC_CFG_f0_3_i1500_cluster_bypass_ga103 2:2
#define NV_JTAG_SEC_CFG_f0_4_i1500_cluster_bypass_ga103 1:1
#define NV_JTAG_SEC_CFG_g0_0_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 21:21
#define NV_JTAG_SEC_CFG_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 20:20
#define NV_JTAG_SEC_CFG_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 19:19
#define NV_JTAG_SEC_CFG_g0_1_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 18:18
#define NV_JTAG_SEC_CFG_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 17:17
#define NV_JTAG_SEC_CFG_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 16:16
#define NV_JTAG_SEC_CFG_g0_2_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 15:15
#define NV_JTAG_SEC_CFG_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 14:14
#define NV_JTAG_SEC_CFG_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 13:13
#define NV_JTAG_SEC_CFG_g0_3_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 12:12
#define NV_JTAG_SEC_CFG_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 11:11
#define NV_JTAG_SEC_CFG_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 10:10
#define NV_JTAG_SEC_CFG_g0_4_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 6:6
#define NV_JTAG_SEC_CFG_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 5:5
#define NV_JTAG_SEC_CFG_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 4:4
#define NV_JTAG_SEC_CFG_g0_5_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 9:9
#define NV_JTAG_SEC_CFG_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 8:8
#define NV_JTAG_SEC_CFG_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 7:7
#define NV_JTAG_SEC_CFG_m0_0_i1500_cluster_bypass_ga103 26:26
#define NV_JTAG_SEC_CFG_m1_0_i1500_cluster_bypass_ga103 24:24
#define NV_JTAG_SEC_CFG_n0_0_i1500_cluster_bypass_ga103 25:25
#define NV_JTAG_SEC_CFG_s0_0_i1500_cluster_bypass_ga103 32:32
#define NV_JTAG_SEC_CFG_t0_0_GAC_T0_OTHER0_i1500_cluster_bypass_ga103 30:30
#define NV_JTAG_SEC_CFG_t0_0_GAC_T0_OTHER1_i1500_cluster_bypass_ga103 29:29
#define NV_JTAG_SEC_CFG_t0_0_GAC_T0_OTHER2_i1500_cluster_bypass_ga103 28:28
#define NV_JTAG_SEC_CFG_t0_0_GAC_T0_OTHER3_i1500_cluster_bypass_ga103 27:27
#define NV_JTAG_SEC_CFG_testmaster_en_atpg_scan_ga103 35:35
#define NV_JTAG_SEC_CFG_testmaster_en_boundary_scan_ga103 39:39
#define NV_JTAG_SEC_CFG_testmaster_en_fuse_secure_ga103 44:44
#define NV_JTAG_SEC_CFG_testmaster_en_hbm_ga103 37:37
#define NV_JTAG_SEC_CFG_testmaster_en_iobist_ga103 38:38
#define NV_JTAG_SEC_CFG_testmaster_en_ist_debug_ga103 47:47
#define NV_JTAG_SEC_CFG_testmaster_en_jtag2host_ga103 41:41
#define NV_JTAG_SEC_CFG_testmaster_en_non_critical_regs_ga103 46:46
#define NV_JTAG_SEC_CFG_testmaster_en_obs_secure_ga103 43:43
#define NV_JTAG_SEC_CFG_testmaster_en_ram_dump_ga103 36:36
#define NV_JTAG_SEC_CFG_testmaster_en_scan_dump_ga103 34:34
#define NV_JTAG_SEC_CFG_testmaster_en_sec_mode_ga103 45:45
#define NV_JTAG_SEC_CFG_testmaster_en_top_fs_ga103 42:42
#define NV_JTAG_SEC_CFG_testmaster_en_wbr_ga103 40:40
#define NV_JTAG_SEC_CFG_testmaster_global_enable_ga103 49:49
#define NV_JTAG_SEC_CFG_testmaster_reserved_ga103 48:48
#define NV_JTAG_SEC_CFG_testmaster_tdo_pipeline_ga103 33:33
#define NV_JTAG_SEC_CFG_x0_0_i1500_cluster_bypass_ga103 0:0
#define NV_JTAG_SEC_CFG_features_ga103 49:34
#define NV_JTAG_SEC_CHK_CLUSTER_ID_ga103 0
#define NV_JTAG_SEC_CHK_ID_ga103 7
#define NV_JTAG_SEC_CHK_CHAINLENGTH_ga103 290
#define NV_JTAG_SEC_CHK_d0_0_i1500_cluster_bypass_ga103 31:31
#define NV_JTAG_SEC_CHK_f0_0_i1500_cluster_bypass_ga103 23:23
#define NV_JTAG_SEC_CHK_f0_1_i1500_cluster_bypass_ga103 22:22
#define NV_JTAG_SEC_CHK_f0_2_i1500_cluster_bypass_ga103 3:3
#define NV_JTAG_SEC_CHK_f0_3_i1500_cluster_bypass_ga103 2:2
#define NV_JTAG_SEC_CHK_f0_4_i1500_cluster_bypass_ga103 1:1
#define NV_JTAG_SEC_CHK_g0_0_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 21:21
#define NV_JTAG_SEC_CHK_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 20:20
#define NV_JTAG_SEC_CHK_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 19:19
#define NV_JTAG_SEC_CHK_g0_1_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 18:18
#define NV_JTAG_SEC_CHK_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 17:17
#define NV_JTAG_SEC_CHK_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 16:16
#define NV_JTAG_SEC_CHK_g0_2_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 15:15
#define NV_JTAG_SEC_CHK_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 14:14
#define NV_JTAG_SEC_CHK_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 13:13
#define NV_JTAG_SEC_CHK_g0_3_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 12:12
#define NV_JTAG_SEC_CHK_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 11:11
#define NV_JTAG_SEC_CHK_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 10:10
#define NV_JTAG_SEC_CHK_g0_4_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 6:6
#define NV_JTAG_SEC_CHK_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 5:5
#define NV_JTAG_SEC_CHK_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 4:4
#define NV_JTAG_SEC_CHK_g0_5_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 9:9
#define NV_JTAG_SEC_CHK_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 8:8
#define NV_JTAG_SEC_CHK_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 7:7
#define NV_JTAG_SEC_CHK_m0_0_i1500_cluster_bypass_ga103 26:26
#define NV_JTAG_SEC_CHK_m1_0_i1500_cluster_bypass_ga103 24:24
#define NV_JTAG_SEC_CHK_n0_0_i1500_cluster_bypass_ga103 25:25
#define NV_JTAG_SEC_CHK_s0_0_i1500_cluster_bypass_ga103 32:32
#define NV_JTAG_SEC_CHK_t0_0_GAC_T0_OTHER0_i1500_cluster_bypass_ga103 30:30
#define NV_JTAG_SEC_CHK_t0_0_GAC_T0_OTHER1_i1500_cluster_bypass_ga103 29:29
#define NV_JTAG_SEC_CHK_t0_0_GAC_T0_OTHER2_i1500_cluster_bypass_ga103 28:28
#define NV_JTAG_SEC_CHK_t0_0_GAC_T0_OTHER3_i1500_cluster_bypass_ga103 27:27
#define NV_JTAG_SEC_CHK_testmaster_secureid_ga103 289:34
#define NV_JTAG_SEC_CHK_testmaster_tdo_pipeline_ga103 33:33
#define NV_JTAG_SEC_CHK_x0_0_i1500_cluster_bypass_ga103 0:0
#define NV_JTAG_SEC_CMD_CLUSTER_ID_ga103 0
#define NV_JTAG_SEC_CMD_ID_ga103 9
#define NV_JTAG_SEC_CMD_CHAINLENGTH_ga103 42
#define NV_JTAG_SEC_CMD_d0_0_i1500_cluster_bypass_ga103 31:31
#define NV_JTAG_SEC_CMD_f0_0_i1500_cluster_bypass_ga103 23:23
#define NV_JTAG_SEC_CMD_f0_1_i1500_cluster_bypass_ga103 22:22
#define NV_JTAG_SEC_CMD_f0_2_i1500_cluster_bypass_ga103 3:3
#define NV_JTAG_SEC_CMD_f0_3_i1500_cluster_bypass_ga103 2:2
#define NV_JTAG_SEC_CMD_f0_4_i1500_cluster_bypass_ga103 1:1
#define NV_JTAG_SEC_CMD_g0_0_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 21:21
#define NV_JTAG_SEC_CMD_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 20:20
#define NV_JTAG_SEC_CMD_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 19:19
#define NV_JTAG_SEC_CMD_g0_1_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 18:18
#define NV_JTAG_SEC_CMD_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 17:17
#define NV_JTAG_SEC_CMD_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 16:16
#define NV_JTAG_SEC_CMD_g0_2_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 15:15
#define NV_JTAG_SEC_CMD_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 14:14
#define NV_JTAG_SEC_CMD_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 13:13
#define NV_JTAG_SEC_CMD_g0_3_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 12:12
#define NV_JTAG_SEC_CMD_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 11:11
#define NV_JTAG_SEC_CMD_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 10:10
#define NV_JTAG_SEC_CMD_g0_4_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 6:6
#define NV_JTAG_SEC_CMD_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 5:5
#define NV_JTAG_SEC_CMD_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 4:4
#define NV_JTAG_SEC_CMD_g0_5_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 9:9
#define NV_JTAG_SEC_CMD_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 8:8
#define NV_JTAG_SEC_CMD_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 7:7
#define NV_JTAG_SEC_CMD_m0_0_i1500_cluster_bypass_ga103 26:26
#define NV_JTAG_SEC_CMD_m1_0_i1500_cluster_bypass_ga103 24:24
#define NV_JTAG_SEC_CMD_n0_0_i1500_cluster_bypass_ga103 25:25
#define NV_JTAG_SEC_CMD_s0_0_i1500_cluster_bypass_ga103 32:32
#define NV_JTAG_SEC_CMD_t0_0_GAC_T0_OTHER0_i1500_cluster_bypass_ga103 30:30
#define NV_JTAG_SEC_CMD_t0_0_GAC_T0_OTHER1_i1500_cluster_bypass_ga103 29:29
#define NV_JTAG_SEC_CMD_t0_0_GAC_T0_OTHER2_i1500_cluster_bypass_ga103 28:28
#define NV_JTAG_SEC_CMD_t0_0_GAC_T0_OTHER3_i1500_cluster_bypass_ga103 27:27
#define NV_JTAG_SEC_CMD_testmaster_failed_unlock_ga103 37:37
#define NV_JTAG_SEC_CMD_testmaster_reserved_ga103 41:38
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_ready_status_ga103 35:35
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_start_ga103 34:34
#define NV_JTAG_SEC_CMD_testmaster_tdo_pipeline_ga103 33:33
#define NV_JTAG_SEC_CMD_testmaster_trng_enable_ga103 36:36
#define NV_JTAG_SEC_CMD_x0_0_i1500_cluster_bypass_ga103 0:0
#define NV_JTAG_SEC_RDAT_CLUSTER_ID_ga103 0
#define NV_JTAG_SEC_RDAT_ID_ga103 136
#define NV_JTAG_SEC_RDAT_CHAINLENGTH_ga103 184
#define NV_JTAG_SEC_RDAT_d0_0_i1500_cluster_bypass_ga103 31:31
#define NV_JTAG_SEC_RDAT_f0_0_i1500_cluster_bypass_ga103 23:23
#define NV_JTAG_SEC_RDAT_f0_1_i1500_cluster_bypass_ga103 22:22
#define NV_JTAG_SEC_RDAT_f0_2_i1500_cluster_bypass_ga103 3:3
#define NV_JTAG_SEC_RDAT_f0_3_i1500_cluster_bypass_ga103 2:2
#define NV_JTAG_SEC_RDAT_f0_4_i1500_cluster_bypass_ga103 1:1
#define NV_JTAG_SEC_RDAT_g0_0_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 21:21
#define NV_JTAG_SEC_RDAT_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 20:20
#define NV_JTAG_SEC_RDAT_g0_0_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 19:19
#define NV_JTAG_SEC_RDAT_g0_1_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 18:18
#define NV_JTAG_SEC_RDAT_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 17:17
#define NV_JTAG_SEC_RDAT_g0_1_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 16:16
#define NV_JTAG_SEC_RDAT_g0_2_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 15:15
#define NV_JTAG_SEC_RDAT_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 14:14
#define NV_JTAG_SEC_RDAT_g0_2_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 13:13
#define NV_JTAG_SEC_RDAT_g0_3_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 12:12
#define NV_JTAG_SEC_RDAT_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 11:11
#define NV_JTAG_SEC_RDAT_g0_3_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 10:10
#define NV_JTAG_SEC_RDAT_g0_4_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 6:6
#define NV_JTAG_SEC_RDAT_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 5:5
#define NV_JTAG_SEC_RDAT_g0_4_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 4:4
#define NV_JTAG_SEC_RDAT_g0_5_GAC_G0_OTHER0_i1500_cluster_bypass_ga103 9:9
#define NV_JTAG_SEC_RDAT_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER3_i1500_cluster_bypass_ga103 8:8
#define NV_JTAG_SEC_RDAT_g0_5_GAC_G0_OTHER2_GAC_G0_OTHER6_i1500_cluster_bypass_ga103 7:7
#define NV_JTAG_SEC_RDAT_m0_0_i1500_cluster_bypass_ga103 26:26
#define NV_JTAG_SEC_RDAT_m1_0_i1500_cluster_bypass_ga103 24:24
#define NV_JTAG_SEC_RDAT_n0_0_i1500_cluster_bypass_ga103 25:25
#define NV_JTAG_SEC_RDAT_s0_0_i1500_cluster_bypass_ga103 32:32
#define NV_JTAG_SEC_RDAT_t0_0_GAC_T0_OTHER0_i1500_cluster_bypass_ga103 30:30
#define NV_JTAG_SEC_RDAT_t0_0_GAC_T0_OTHER1_i1500_cluster_bypass_ga103 29:29
#define NV_JTAG_SEC_RDAT_t0_0_GAC_T0_OTHER2_i1500_cluster_bypass_ga103 28:28
#define NV_JTAG_SEC_RDAT_t0_0_GAC_T0_OTHER3_i1500_cluster_bypass_ga103 27:27
#define NV_JTAG_SEC_RDAT_testmaster_c_data_ga103 183:44
#define NV_JTAG_SEC_RDAT_testmaster_c_valid_value_ga103 43:34
#define NV_JTAG_SEC_RDAT_testmaster_tdo_pipeline_ga103 33:33
#define NV_JTAG_SEC_RDAT_x0_0_i1500_cluster_bypass_ga103 0:0
#define NV_JTAG_SEC_UNLOCK_STATUS_ID_ga103 249
#define NV_JTAG_SEC_UNLOCK_STATUS_CHAINLENGTH_ga103 578
#define NV_JTAG_SEC_UNLOCK_STATUS_features_ga103 577:562
#define NV_JTAG_NUM_CLUSTERS_ga103 34
#define NV_JTAG_SEC_CFG_CLUSTER_ID_ga104 0
#define NV_JTAG_SEC_CFG_ID_ga104 8
#define NV_JTAG_SEC_CFG_CHAINLENGTH_ga104 48
#define NV_JTAG_SEC_CFG_d0_0_i1500_cluster_bypass_ga104 29:29
#define NV_JTAG_SEC_CFG_f0_0_i1500_cluster_bypass_ga104 22:22
#define NV_JTAG_SEC_CFG_f0_1_i1500_cluster_bypass_ga104 21:21
#define NV_JTAG_SEC_CFG_f0_2_i1500_cluster_bypass_ga104 2:2
#define NV_JTAG_SEC_CFG_f0_3_i1500_cluster_bypass_ga104 1:1
#define NV_JTAG_SEC_CFG_g0_0_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 20:20
#define NV_JTAG_SEC_CFG_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 19:19
#define NV_JTAG_SEC_CFG_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 18:18
#define NV_JTAG_SEC_CFG_g0_1_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 17:17
#define NV_JTAG_SEC_CFG_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 16:16
#define NV_JTAG_SEC_CFG_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 15:15
#define NV_JTAG_SEC_CFG_g0_2_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 14:14
#define NV_JTAG_SEC_CFG_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 13:13
#define NV_JTAG_SEC_CFG_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 12:12
#define NV_JTAG_SEC_CFG_g0_3_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 11:11
#define NV_JTAG_SEC_CFG_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 10:10
#define NV_JTAG_SEC_CFG_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 9:9
#define NV_JTAG_SEC_CFG_g0_4_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 5:5
#define NV_JTAG_SEC_CFG_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 4:4
#define NV_JTAG_SEC_CFG_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 3:3
#define NV_JTAG_SEC_CFG_g0_5_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 8:8
#define NV_JTAG_SEC_CFG_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 7:7
#define NV_JTAG_SEC_CFG_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 6:6
#define NV_JTAG_SEC_CFG_m0_0_i1500_cluster_bypass_ga104 24:24
#define NV_JTAG_SEC_CFG_n0_0_i1500_cluster_bypass_ga104 23:23
#define NV_JTAG_SEC_CFG_s0_0_i1500_cluster_bypass_ga104 30:30
#define NV_JTAG_SEC_CFG_t0_0_GAD_T0_OTHER0_i1500_cluster_bypass_ga104 28:28
#define NV_JTAG_SEC_CFG_t0_0_GAD_T0_OTHER1_i1500_cluster_bypass_ga104 27:27
#define NV_JTAG_SEC_CFG_t0_0_GAD_T0_OTHER2_i1500_cluster_bypass_ga104 26:26
#define NV_JTAG_SEC_CFG_t0_0_GAD_T0_OTHER3_i1500_cluster_bypass_ga104 25:25
#define NV_JTAG_SEC_CFG_testmaster_en_atpg_scan_ga104 33:33
#define NV_JTAG_SEC_CFG_testmaster_en_boundary_scan_ga104 37:37
#define NV_JTAG_SEC_CFG_testmaster_en_fuse_secure_ga104 42:42
#define NV_JTAG_SEC_CFG_testmaster_en_hbm_ga104 35:35
#define NV_JTAG_SEC_CFG_testmaster_en_iobist_ga104 36:36
#define NV_JTAG_SEC_CFG_testmaster_en_ist_debug_ga104 45:45
#define NV_JTAG_SEC_CFG_testmaster_en_jtag2host_ga104 39:39
#define NV_JTAG_SEC_CFG_testmaster_en_non_critical_regs_ga104 44:44
#define NV_JTAG_SEC_CFG_testmaster_en_obs_secure_ga104 41:41
#define NV_JTAG_SEC_CFG_testmaster_en_ram_dump_ga104 34:34
#define NV_JTAG_SEC_CFG_testmaster_en_scan_dump_ga104 32:32
#define NV_JTAG_SEC_CFG_testmaster_en_sec_mode_ga104 43:43
#define NV_JTAG_SEC_CFG_testmaster_en_top_fs_ga104 40:40
#define NV_JTAG_SEC_CFG_testmaster_en_wbr_ga104 38:38
#define NV_JTAG_SEC_CFG_testmaster_global_enable_ga104 47:47
#define NV_JTAG_SEC_CFG_testmaster_reserved_ga104 46:46
#define NV_JTAG_SEC_CFG_testmaster_tdo_pipeline_ga104 31:31
#define NV_JTAG_SEC_CFG_x0_0_i1500_cluster_bypass_ga104 0:0
#define NV_JTAG_SEC_CFG_features_ga104 47:32
#define NV_JTAG_SEC_CHK_CLUSTER_ID_ga104 0
#define NV_JTAG_SEC_CHK_ID_ga104 7
#define NV_JTAG_SEC_CHK_CHAINLENGTH_ga104 288
#define NV_JTAG_SEC_CHK_d0_0_i1500_cluster_bypass_ga104 29:29
#define NV_JTAG_SEC_CHK_f0_0_i1500_cluster_bypass_ga104 22:22
#define NV_JTAG_SEC_CHK_f0_1_i1500_cluster_bypass_ga104 21:21
#define NV_JTAG_SEC_CHK_f0_2_i1500_cluster_bypass_ga104 2:2
#define NV_JTAG_SEC_CHK_f0_3_i1500_cluster_bypass_ga104 1:1
#define NV_JTAG_SEC_CHK_g0_0_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 20:20
#define NV_JTAG_SEC_CHK_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 19:19
#define NV_JTAG_SEC_CHK_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 18:18
#define NV_JTAG_SEC_CHK_g0_1_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 17:17
#define NV_JTAG_SEC_CHK_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 16:16
#define NV_JTAG_SEC_CHK_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 15:15
#define NV_JTAG_SEC_CHK_g0_2_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 14:14
#define NV_JTAG_SEC_CHK_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 13:13
#define NV_JTAG_SEC_CHK_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 12:12
#define NV_JTAG_SEC_CHK_g0_3_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 11:11
#define NV_JTAG_SEC_CHK_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 10:10
#define NV_JTAG_SEC_CHK_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 9:9
#define NV_JTAG_SEC_CHK_g0_4_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 5:5
#define NV_JTAG_SEC_CHK_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 4:4
#define NV_JTAG_SEC_CHK_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 3:3
#define NV_JTAG_SEC_CHK_g0_5_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 8:8
#define NV_JTAG_SEC_CHK_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 7:7
#define NV_JTAG_SEC_CHK_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 6:6
#define NV_JTAG_SEC_CHK_m0_0_i1500_cluster_bypass_ga104 24:24
#define NV_JTAG_SEC_CHK_n0_0_i1500_cluster_bypass_ga104 23:23
#define NV_JTAG_SEC_CHK_s0_0_i1500_cluster_bypass_ga104 30:30
#define NV_JTAG_SEC_CHK_t0_0_GAD_T0_OTHER0_i1500_cluster_bypass_ga104 28:28
#define NV_JTAG_SEC_CHK_t0_0_GAD_T0_OTHER1_i1500_cluster_bypass_ga104 27:27
#define NV_JTAG_SEC_CHK_t0_0_GAD_T0_OTHER2_i1500_cluster_bypass_ga104 26:26
#define NV_JTAG_SEC_CHK_t0_0_GAD_T0_OTHER3_i1500_cluster_bypass_ga104 25:25
#define NV_JTAG_SEC_CHK_testmaster_secureid_ga104 287:32
#define NV_JTAG_SEC_CHK_testmaster_tdo_pipeline_ga104 31:31
#define NV_JTAG_SEC_CHK_x0_0_i1500_cluster_bypass_ga104 0:0
#define NV_JTAG_SEC_CMD_CLUSTER_ID_ga104 0
#define NV_JTAG_SEC_CMD_ID_ga104 9
#define NV_JTAG_SEC_CMD_CHAINLENGTH_ga104 40
#define NV_JTAG_SEC_CMD_d0_0_i1500_cluster_bypass_ga104 29:29
#define NV_JTAG_SEC_CMD_f0_0_i1500_cluster_bypass_ga104 22:22
#define NV_JTAG_SEC_CMD_f0_1_i1500_cluster_bypass_ga104 21:21
#define NV_JTAG_SEC_CMD_f0_2_i1500_cluster_bypass_ga104 2:2
#define NV_JTAG_SEC_CMD_f0_3_i1500_cluster_bypass_ga104 1:1
#define NV_JTAG_SEC_CMD_g0_0_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 20:20
#define NV_JTAG_SEC_CMD_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 19:19
#define NV_JTAG_SEC_CMD_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 18:18
#define NV_JTAG_SEC_CMD_g0_1_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 17:17
#define NV_JTAG_SEC_CMD_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 16:16
#define NV_JTAG_SEC_CMD_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 15:15
#define NV_JTAG_SEC_CMD_g0_2_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 14:14
#define NV_JTAG_SEC_CMD_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 13:13
#define NV_JTAG_SEC_CMD_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 12:12
#define NV_JTAG_SEC_CMD_g0_3_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 11:11
#define NV_JTAG_SEC_CMD_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 10:10
#define NV_JTAG_SEC_CMD_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 9:9
#define NV_JTAG_SEC_CMD_g0_4_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 5:5
#define NV_JTAG_SEC_CMD_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 4:4
#define NV_JTAG_SEC_CMD_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 3:3
#define NV_JTAG_SEC_CMD_g0_5_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 8:8
#define NV_JTAG_SEC_CMD_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 7:7
#define NV_JTAG_SEC_CMD_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 6:6
#define NV_JTAG_SEC_CMD_m0_0_i1500_cluster_bypass_ga104 24:24
#define NV_JTAG_SEC_CMD_n0_0_i1500_cluster_bypass_ga104 23:23
#define NV_JTAG_SEC_CMD_s0_0_i1500_cluster_bypass_ga104 30:30
#define NV_JTAG_SEC_CMD_t0_0_GAD_T0_OTHER0_i1500_cluster_bypass_ga104 28:28
#define NV_JTAG_SEC_CMD_t0_0_GAD_T0_OTHER1_i1500_cluster_bypass_ga104 27:27
#define NV_JTAG_SEC_CMD_t0_0_GAD_T0_OTHER2_i1500_cluster_bypass_ga104 26:26
#define NV_JTAG_SEC_CMD_t0_0_GAD_T0_OTHER3_i1500_cluster_bypass_ga104 25:25
#define NV_JTAG_SEC_CMD_testmaster_failed_unlock_ga104 35:35
#define NV_JTAG_SEC_CMD_testmaster_reserved_ga104 39:36
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_ready_status_ga104 33:33
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_start_ga104 32:32
#define NV_JTAG_SEC_CMD_testmaster_tdo_pipeline_ga104 31:31
#define NV_JTAG_SEC_CMD_testmaster_trng_enable_ga104 34:34
#define NV_JTAG_SEC_CMD_x0_0_i1500_cluster_bypass_ga104 0:0
#define NV_JTAG_SEC_RDAT_CLUSTER_ID_ga104 0
#define NV_JTAG_SEC_RDAT_ID_ga104 136
#define NV_JTAG_SEC_RDAT_CHAINLENGTH_ga104 182
#define NV_JTAG_SEC_RDAT_d0_0_i1500_cluster_bypass_ga104 29:29
#define NV_JTAG_SEC_RDAT_f0_0_i1500_cluster_bypass_ga104 22:22
#define NV_JTAG_SEC_RDAT_f0_1_i1500_cluster_bypass_ga104 21:21
#define NV_JTAG_SEC_RDAT_f0_2_i1500_cluster_bypass_ga104 2:2
#define NV_JTAG_SEC_RDAT_f0_3_i1500_cluster_bypass_ga104 1:1
#define NV_JTAG_SEC_RDAT_g0_0_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 20:20
#define NV_JTAG_SEC_RDAT_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 19:19
#define NV_JTAG_SEC_RDAT_g0_0_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 18:18
#define NV_JTAG_SEC_RDAT_g0_1_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 17:17
#define NV_JTAG_SEC_RDAT_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 16:16
#define NV_JTAG_SEC_RDAT_g0_1_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 15:15
#define NV_JTAG_SEC_RDAT_g0_2_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 14:14
#define NV_JTAG_SEC_RDAT_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 13:13
#define NV_JTAG_SEC_RDAT_g0_2_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 12:12
#define NV_JTAG_SEC_RDAT_g0_3_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 11:11
#define NV_JTAG_SEC_RDAT_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 10:10
#define NV_JTAG_SEC_RDAT_g0_3_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 9:9
#define NV_JTAG_SEC_RDAT_g0_4_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 5:5
#define NV_JTAG_SEC_RDAT_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 4:4
#define NV_JTAG_SEC_RDAT_g0_4_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 3:3
#define NV_JTAG_SEC_RDAT_g0_5_GAD_G0_OTHER0_i1500_cluster_bypass_ga104 8:8
#define NV_JTAG_SEC_RDAT_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER3_i1500_cluster_bypass_ga104 7:7
#define NV_JTAG_SEC_RDAT_g0_5_GAD_G0_OTHER2_GAD_G0_OTHER6_i1500_cluster_bypass_ga104 6:6
#define NV_JTAG_SEC_RDAT_m0_0_i1500_cluster_bypass_ga104 24:24
#define NV_JTAG_SEC_RDAT_n0_0_i1500_cluster_bypass_ga104 23:23
#define NV_JTAG_SEC_RDAT_s0_0_i1500_cluster_bypass_ga104 30:30
#define NV_JTAG_SEC_RDAT_t0_0_GAD_T0_OTHER0_i1500_cluster_bypass_ga104 28:28
#define NV_JTAG_SEC_RDAT_t0_0_GAD_T0_OTHER1_i1500_cluster_bypass_ga104 27:27
#define NV_JTAG_SEC_RDAT_t0_0_GAD_T0_OTHER2_i1500_cluster_bypass_ga104 26:26
#define NV_JTAG_SEC_RDAT_t0_0_GAD_T0_OTHER3_i1500_cluster_bypass_ga104 25:25
#define NV_JTAG_SEC_RDAT_testmaster_c_data_ga104 181:42
#define NV_JTAG_SEC_RDAT_testmaster_c_valid_value_ga104 41:32
#define NV_JTAG_SEC_RDAT_testmaster_tdo_pipeline_ga104 31:31
#define NV_JTAG_SEC_RDAT_x0_0_i1500_cluster_bypass_ga104 0:0
#define NV_JTAG_SEC_UNLOCK_STATUS_ID_ga104 249
#define NV_JTAG_SEC_UNLOCK_STATUS_CHAINLENGTH_ga104 544
#define NV_JTAG_SEC_UNLOCK_STATUS_features_ga104 543:528
#define NV_JTAG_NUM_CLUSTERS_ga104 32
#define NV_JTAG_SEC_CFG_CLUSTER_ID_ga107 0
#define NV_JTAG_SEC_CFG_ID_ga107 8
#define NV_JTAG_SEC_CFG_CHAINLENGTH_ga107 31
#define NV_JTAG_SEC_CFG_d0_0_i1500_cluster_bypass_ga107 12:12
#define NV_JTAG_SEC_CFG_f0_0_i1500_cluster_bypass_ga107 5:5
#define NV_JTAG_SEC_CFG_f0_1_i1500_cluster_bypass_ga107 0:0
#define NV_JTAG_SEC_CFG_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 4:4
#define NV_JTAG_SEC_CFG_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 3:3
#define NV_JTAG_SEC_CFG_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 2:2
#define NV_JTAG_SEC_CFG_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 1:1
#define NV_JTAG_SEC_CFG_m0_0_i1500_cluster_bypass_ga107 7:7
#define NV_JTAG_SEC_CFG_n0_0_i1500_cluster_bypass_ga107 6:6
#define NV_JTAG_SEC_CFG_sx0_0_i1500_cluster_bypass_ga107 13:13
#define NV_JTAG_SEC_CFG_t0_0_GAF_T0_OTHER0_i1500_cluster_bypass_ga107 11:11
#define NV_JTAG_SEC_CFG_t0_0_GAF_T0_OTHER1_i1500_cluster_bypass_ga107 10:10
#define NV_JTAG_SEC_CFG_t0_0_GAF_T0_OTHER2_i1500_cluster_bypass_ga107 9:9
#define NV_JTAG_SEC_CFG_t0_0_GAF_T0_OTHER3_i1500_cluster_bypass_ga107 8:8
#define NV_JTAG_SEC_CFG_testmaster_en_atpg_scan_ga107 16:16
#define NV_JTAG_SEC_CFG_testmaster_en_boundary_scan_ga107 20:20
#define NV_JTAG_SEC_CFG_testmaster_en_fuse_secure_ga107 25:25
#define NV_JTAG_SEC_CFG_testmaster_en_hbm_ga107 18:18
#define NV_JTAG_SEC_CFG_testmaster_en_iobist_ga107 19:19
#define NV_JTAG_SEC_CFG_testmaster_en_ist_debug_ga107 28:28
#define NV_JTAG_SEC_CFG_testmaster_en_jtag2host_ga107 22:22
#define NV_JTAG_SEC_CFG_testmaster_en_non_critical_regs_ga107 27:27
#define NV_JTAG_SEC_CFG_testmaster_en_obs_secure_ga107 24:24
#define NV_JTAG_SEC_CFG_testmaster_en_ram_dump_ga107 17:17
#define NV_JTAG_SEC_CFG_testmaster_en_scan_dump_ga107 15:15
#define NV_JTAG_SEC_CFG_testmaster_en_sec_mode_ga107 26:26
#define NV_JTAG_SEC_CFG_testmaster_en_top_fs_ga107 23:23
#define NV_JTAG_SEC_CFG_testmaster_en_wbr_ga107 21:21
#define NV_JTAG_SEC_CFG_testmaster_global_enable_ga107 30:30
#define NV_JTAG_SEC_CFG_testmaster_reserved_ga107 29:29
#define NV_JTAG_SEC_CFG_testmaster_tdo_pipeline_ga107 14:14
#define NV_JTAG_SEC_CFG_features_ga107 30:15
#define NV_JTAG_SEC_CHK_CLUSTER_ID_ga107 0
#define NV_JTAG_SEC_CHK_ID_ga107 7
#define NV_JTAG_SEC_CHK_CHAINLENGTH_ga107 271
#define NV_JTAG_SEC_CHK_d0_0_i1500_cluster_bypass_ga107 12:12
#define NV_JTAG_SEC_CHK_f0_0_i1500_cluster_bypass_ga107 5:5
#define NV_JTAG_SEC_CHK_f0_1_i1500_cluster_bypass_ga107 0:0
#define NV_JTAG_SEC_CHK_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 4:4
#define NV_JTAG_SEC_CHK_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 3:3
#define NV_JTAG_SEC_CHK_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 2:2
#define NV_JTAG_SEC_CHK_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 1:1
#define NV_JTAG_SEC_CHK_m0_0_i1500_cluster_bypass_ga107 7:7
#define NV_JTAG_SEC_CHK_n0_0_i1500_cluster_bypass_ga107 6:6
#define NV_JTAG_SEC_CHK_sx0_0_i1500_cluster_bypass_ga107 13:13
#define NV_JTAG_SEC_CHK_t0_0_GAF_T0_OTHER0_i1500_cluster_bypass_ga107 11:11
#define NV_JTAG_SEC_CHK_t0_0_GAF_T0_OTHER1_i1500_cluster_bypass_ga107 10:10
#define NV_JTAG_SEC_CHK_t0_0_GAF_T0_OTHER2_i1500_cluster_bypass_ga107 9:9
#define NV_JTAG_SEC_CHK_t0_0_GAF_T0_OTHER3_i1500_cluster_bypass_ga107 8:8
#define NV_JTAG_SEC_CHK_testmaster_secureid_ga107 270:15
#define NV_JTAG_SEC_CHK_testmaster_tdo_pipeline_ga107 14:14
#define NV_JTAG_SEC_CMD_CLUSTER_ID_ga107 0
#define NV_JTAG_SEC_CMD_ID_ga107 9
#define NV_JTAG_SEC_CMD_CHAINLENGTH_ga107 23
#define NV_JTAG_SEC_CMD_d0_0_i1500_cluster_bypass_ga107 12:12
#define NV_JTAG_SEC_CMD_f0_0_i1500_cluster_bypass_ga107 5:5
#define NV_JTAG_SEC_CMD_f0_1_i1500_cluster_bypass_ga107 0:0
#define NV_JTAG_SEC_CMD_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 4:4
#define NV_JTAG_SEC_CMD_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 3:3
#define NV_JTAG_SEC_CMD_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 2:2
#define NV_JTAG_SEC_CMD_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 1:1
#define NV_JTAG_SEC_CMD_m0_0_i1500_cluster_bypass_ga107 7:7
#define NV_JTAG_SEC_CMD_n0_0_i1500_cluster_bypass_ga107 6:6
#define NV_JTAG_SEC_CMD_sx0_0_i1500_cluster_bypass_ga107 13:13
#define NV_JTAG_SEC_CMD_t0_0_GAF_T0_OTHER0_i1500_cluster_bypass_ga107 11:11
#define NV_JTAG_SEC_CMD_t0_0_GAF_T0_OTHER1_i1500_cluster_bypass_ga107 10:10
#define NV_JTAG_SEC_CMD_t0_0_GAF_T0_OTHER2_i1500_cluster_bypass_ga107 9:9
#define NV_JTAG_SEC_CMD_t0_0_GAF_T0_OTHER3_i1500_cluster_bypass_ga107 8:8
#define NV_JTAG_SEC_CMD_testmaster_failed_unlock_ga107 18:18
#define NV_JTAG_SEC_CMD_testmaster_reserved_ga107 22:19
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_ready_status_ga107 16:16
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_start_ga107 15:15
#define NV_JTAG_SEC_CMD_testmaster_tdo_pipeline_ga107 14:14
#define NV_JTAG_SEC_CMD_testmaster_trng_enable_ga107 17:17
#define NV_JTAG_SEC_RDAT_CLUSTER_ID_ga107 0
#define NV_JTAG_SEC_RDAT_ID_ga107 136
#define NV_JTAG_SEC_RDAT_CHAINLENGTH_ga107 165
#define NV_JTAG_SEC_RDAT_d0_0_i1500_cluster_bypass_ga107 12:12
#define NV_JTAG_SEC_RDAT_f0_0_i1500_cluster_bypass_ga107 5:5
#define NV_JTAG_SEC_RDAT_f0_1_i1500_cluster_bypass_ga107 0:0
#define NV_JTAG_SEC_RDAT_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 4:4
#define NV_JTAG_SEC_RDAT_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 3:3
#define NV_JTAG_SEC_RDAT_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga107 2:2
#define NV_JTAG_SEC_RDAT_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga107 1:1
#define NV_JTAG_SEC_RDAT_m0_0_i1500_cluster_bypass_ga107 7:7
#define NV_JTAG_SEC_RDAT_n0_0_i1500_cluster_bypass_ga107 6:6
#define NV_JTAG_SEC_RDAT_sx0_0_i1500_cluster_bypass_ga107 13:13
#define NV_JTAG_SEC_RDAT_t0_0_GAF_T0_OTHER0_i1500_cluster_bypass_ga107 11:11
#define NV_JTAG_SEC_RDAT_t0_0_GAF_T0_OTHER1_i1500_cluster_bypass_ga107 10:10
#define NV_JTAG_SEC_RDAT_t0_0_GAF_T0_OTHER2_i1500_cluster_bypass_ga107 9:9
#define NV_JTAG_SEC_RDAT_t0_0_GAF_T0_OTHER3_i1500_cluster_bypass_ga107 8:8
#define NV_JTAG_SEC_RDAT_testmaster_c_data_ga107 164:25
#define NV_JTAG_SEC_RDAT_testmaster_c_valid_value_ga107 24:15
#define NV_JTAG_SEC_RDAT_testmaster_tdo_pipeline_ga107 14:14
#define NV_JTAG_SEC_UNLOCK_STATUS_ID_ga107 249
#define NV_JTAG_SEC_UNLOCK_STATUS_CHAINLENGTH_ga107 255
#define NV_JTAG_SEC_UNLOCK_STATUS_features_ga107 254:239
#define NV_JTAG_NUM_CLUSTERS_ga107 15
#define NV_JTAG_SEC_CFG_CLUSTER_ID_ga102 0
#define NV_JTAG_SEC_CFG_ID_ga102 8
#define NV_JTAG_SEC_CFG_CHAINLENGTH_ga102 57
#define NV_JTAG_SEC_CFG_d0_0_i1500_cluster_bypass_ga102 38:38
#define NV_JTAG_SEC_CFG_f0_0_i1500_cluster_bypass_ga102 29:29
#define NV_JTAG_SEC_CFG_f0_1_i1500_cluster_bypass_ga102 28:28
#define NV_JTAG_SEC_CFG_f0_2_i1500_cluster_bypass_ga102 27:27
#define NV_JTAG_SEC_CFG_f0_3_i1500_cluster_bypass_ga102 5:5
#define NV_JTAG_SEC_CFG_f0_4_i1500_cluster_bypass_ga102 4:4
#define NV_JTAG_SEC_CFG_f0_5_i1500_cluster_bypass_ga102 3:3
#define NV_JTAG_SEC_CFG_g0_0_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 26:26
#define NV_JTAG_SEC_CFG_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 25:25
#define NV_JTAG_SEC_CFG_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 24:24
#define NV_JTAG_SEC_CFG_g0_1_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 23:23
#define NV_JTAG_SEC_CFG_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 22:22
#define NV_JTAG_SEC_CFG_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 21:21
#define NV_JTAG_SEC_CFG_g0_2_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 20:20
#define NV_JTAG_SEC_CFG_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 19:19
#define NV_JTAG_SEC_CFG_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 18:18
#define NV_JTAG_SEC_CFG_g0_3_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 17:17
#define NV_JTAG_SEC_CFG_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 16:16
#define NV_JTAG_SEC_CFG_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 15:15
#define NV_JTAG_SEC_CFG_g0_4_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 14:14
#define NV_JTAG_SEC_CFG_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 13:13
#define NV_JTAG_SEC_CFG_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 12:12
#define NV_JTAG_SEC_CFG_g0_5_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 8:8
#define NV_JTAG_SEC_CFG_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 7:7
#define NV_JTAG_SEC_CFG_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 6:6
#define NV_JTAG_SEC_CFG_g0_6_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 11:11
#define NV_JTAG_SEC_CFG_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 10:10
#define NV_JTAG_SEC_CFG_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 9:9
#define NV_JTAG_SEC_CFG_l0_0_i1500_cluster_bypass_ga102 2:2
#define NV_JTAG_SEC_CFG_m0_0_i1500_cluster_bypass_ga102 31:31
#define NV_JTAG_SEC_CFG_m1_0_i1500_cluster_bypass_ga102 30:30
#define NV_JTAG_SEC_CFG_nx0_0_GAB_NX0_OTHER0_i1500_cluster_bypass_ga102 1:1
#define NV_JTAG_SEC_CFG_nx0_0_GAB_NX0_OTHER1_i1500_cluster_bypass_ga102 0:0
#define NV_JTAG_SEC_CFG_s0_0_i1500_cluster_bypass_ga102 39:39
#define NV_JTAG_SEC_CFG_t0_0_GAB_T0_OTHER0_i1500_cluster_bypass_ga102 37:37
#define NV_JTAG_SEC_CFG_t0_0_GAB_T0_OTHER1_i1500_cluster_bypass_ga102 36:36
#define NV_JTAG_SEC_CFG_t0_0_GAB_T0_OTHER2_i1500_cluster_bypass_ga102 35:35
#define NV_JTAG_SEC_CFG_t0_0_GAB_T0_OTHER3_i1500_cluster_bypass_ga102 34:34
#define NV_JTAG_SEC_CFG_t0_0_GAB_T0_OTHER4_i1500_cluster_bypass_ga102 33:33
#define NV_JTAG_SEC_CFG_t0_0_GAB_T0_OTHER5_i1500_cluster_bypass_ga102 32:32
#define NV_JTAG_SEC_CFG_testmaster_en_atpg_scan_ga102 42:42
#define NV_JTAG_SEC_CFG_testmaster_en_boundary_scan_ga102 46:46
#define NV_JTAG_SEC_CFG_testmaster_en_fuse_secure_ga102 51:51
#define NV_JTAG_SEC_CFG_testmaster_en_hbm_ga102 44:44
#define NV_JTAG_SEC_CFG_testmaster_en_iobist_ga102 45:45
#define NV_JTAG_SEC_CFG_testmaster_en_ist_debug_ga102 54:54
#define NV_JTAG_SEC_CFG_testmaster_en_jtag2host_ga102 48:48
#define NV_JTAG_SEC_CFG_testmaster_en_non_critical_regs_ga102 53:53
#define NV_JTAG_SEC_CFG_testmaster_en_obs_secure_ga102 50:50
#define NV_JTAG_SEC_CFG_testmaster_en_ram_dump_ga102 43:43
#define NV_JTAG_SEC_CFG_testmaster_en_scan_dump_ga102 41:41
#define NV_JTAG_SEC_CFG_testmaster_en_sec_mode_ga102 52:52
#define NV_JTAG_SEC_CFG_testmaster_en_top_fs_ga102 49:49
#define NV_JTAG_SEC_CFG_testmaster_en_wbr_ga102 47:47
#define NV_JTAG_SEC_CFG_testmaster_global_enable_ga102 56:56
#define NV_JTAG_SEC_CFG_testmaster_reserved_ga102 55:55
#define NV_JTAG_SEC_CFG_testmaster_tdo_pipeline_ga102 40:40
#define NV_JTAG_SEC_CFG_features_ga102 56:41
#define NV_JTAG_SEC_CHK_CLUSTER_ID_ga102 0
#define NV_JTAG_SEC_CHK_ID_ga102 7
#define NV_JTAG_SEC_CHK_CHAINLENGTH_ga102 297
#define NV_JTAG_SEC_CHK_d0_0_i1500_cluster_bypass_ga102 38:38
#define NV_JTAG_SEC_CHK_f0_0_i1500_cluster_bypass_ga102 29:29
#define NV_JTAG_SEC_CHK_f0_1_i1500_cluster_bypass_ga102 28:28
#define NV_JTAG_SEC_CHK_f0_2_i1500_cluster_bypass_ga102 27:27
#define NV_JTAG_SEC_CHK_f0_3_i1500_cluster_bypass_ga102 5:5
#define NV_JTAG_SEC_CHK_f0_4_i1500_cluster_bypass_ga102 4:4
#define NV_JTAG_SEC_CHK_f0_5_i1500_cluster_bypass_ga102 3:3
#define NV_JTAG_SEC_CHK_g0_0_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 26:26
#define NV_JTAG_SEC_CHK_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 25:25
#define NV_JTAG_SEC_CHK_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 24:24
#define NV_JTAG_SEC_CHK_g0_1_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 23:23
#define NV_JTAG_SEC_CHK_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 22:22
#define NV_JTAG_SEC_CHK_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 21:21
#define NV_JTAG_SEC_CHK_g0_2_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 20:20
#define NV_JTAG_SEC_CHK_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 19:19
#define NV_JTAG_SEC_CHK_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 18:18
#define NV_JTAG_SEC_CHK_g0_3_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 17:17
#define NV_JTAG_SEC_CHK_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 16:16
#define NV_JTAG_SEC_CHK_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 15:15
#define NV_JTAG_SEC_CHK_g0_4_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 14:14
#define NV_JTAG_SEC_CHK_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 13:13
#define NV_JTAG_SEC_CHK_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 12:12
#define NV_JTAG_SEC_CHK_g0_5_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 8:8
#define NV_JTAG_SEC_CHK_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 7:7
#define NV_JTAG_SEC_CHK_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 6:6
#define NV_JTAG_SEC_CHK_g0_6_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 11:11
#define NV_JTAG_SEC_CHK_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 10:10
#define NV_JTAG_SEC_CHK_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 9:9
#define NV_JTAG_SEC_CHK_l0_0_i1500_cluster_bypass_ga102 2:2
#define NV_JTAG_SEC_CHK_m0_0_i1500_cluster_bypass_ga102 31:31
#define NV_JTAG_SEC_CHK_m1_0_i1500_cluster_bypass_ga102 30:30
#define NV_JTAG_SEC_CHK_nx0_0_GAB_NX0_OTHER0_i1500_cluster_bypass_ga102 1:1
#define NV_JTAG_SEC_CHK_nx0_0_GAB_NX0_OTHER1_i1500_cluster_bypass_ga102 0:0
#define NV_JTAG_SEC_CHK_s0_0_i1500_cluster_bypass_ga102 39:39
#define NV_JTAG_SEC_CHK_t0_0_GAB_T0_OTHER0_i1500_cluster_bypass_ga102 37:37
#define NV_JTAG_SEC_CHK_t0_0_GAB_T0_OTHER1_i1500_cluster_bypass_ga102 36:36
#define NV_JTAG_SEC_CHK_t0_0_GAB_T0_OTHER2_i1500_cluster_bypass_ga102 35:35
#define NV_JTAG_SEC_CHK_t0_0_GAB_T0_OTHER3_i1500_cluster_bypass_ga102 34:34
#define NV_JTAG_SEC_CHK_t0_0_GAB_T0_OTHER4_i1500_cluster_bypass_ga102 33:33
#define NV_JTAG_SEC_CHK_t0_0_GAB_T0_OTHER5_i1500_cluster_bypass_ga102 32:32
#define NV_JTAG_SEC_CHK_testmaster_secureid_ga102 296:41
#define NV_JTAG_SEC_CHK_testmaster_tdo_pipeline_ga102 40:40
#define NV_JTAG_SEC_CMD_CLUSTER_ID_ga102 0
#define NV_JTAG_SEC_CMD_ID_ga102 9
#define NV_JTAG_SEC_CMD_CHAINLENGTH_ga102 49
#define NV_JTAG_SEC_CMD_d0_0_i1500_cluster_bypass_ga102 38:38
#define NV_JTAG_SEC_CMD_f0_0_i1500_cluster_bypass_ga102 29:29
#define NV_JTAG_SEC_CMD_f0_1_i1500_cluster_bypass_ga102 28:28
#define NV_JTAG_SEC_CMD_f0_2_i1500_cluster_bypass_ga102 27:27
#define NV_JTAG_SEC_CMD_f0_3_i1500_cluster_bypass_ga102 5:5
#define NV_JTAG_SEC_CMD_f0_4_i1500_cluster_bypass_ga102 4:4
#define NV_JTAG_SEC_CMD_f0_5_i1500_cluster_bypass_ga102 3:3
#define NV_JTAG_SEC_CMD_g0_0_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 26:26
#define NV_JTAG_SEC_CMD_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 25:25
#define NV_JTAG_SEC_CMD_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 24:24
#define NV_JTAG_SEC_CMD_g0_1_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 23:23
#define NV_JTAG_SEC_CMD_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 22:22
#define NV_JTAG_SEC_CMD_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 21:21
#define NV_JTAG_SEC_CMD_g0_2_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 20:20
#define NV_JTAG_SEC_CMD_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 19:19
#define NV_JTAG_SEC_CMD_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 18:18
#define NV_JTAG_SEC_CMD_g0_3_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 17:17
#define NV_JTAG_SEC_CMD_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 16:16
#define NV_JTAG_SEC_CMD_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 15:15
#define NV_JTAG_SEC_CMD_g0_4_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 14:14
#define NV_JTAG_SEC_CMD_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 13:13
#define NV_JTAG_SEC_CMD_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 12:12
#define NV_JTAG_SEC_CMD_g0_5_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 8:8
#define NV_JTAG_SEC_CMD_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 7:7
#define NV_JTAG_SEC_CMD_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 6:6
#define NV_JTAG_SEC_CMD_g0_6_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 11:11
#define NV_JTAG_SEC_CMD_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 10:10
#define NV_JTAG_SEC_CMD_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 9:9
#define NV_JTAG_SEC_CMD_l0_0_i1500_cluster_bypass_ga102 2:2
#define NV_JTAG_SEC_CMD_m0_0_i1500_cluster_bypass_ga102 31:31
#define NV_JTAG_SEC_CMD_m1_0_i1500_cluster_bypass_ga102 30:30
#define NV_JTAG_SEC_CMD_nx0_0_GAB_NX0_OTHER0_i1500_cluster_bypass_ga102 1:1
#define NV_JTAG_SEC_CMD_nx0_0_GAB_NX0_OTHER1_i1500_cluster_bypass_ga102 0:0
#define NV_JTAG_SEC_CMD_s0_0_i1500_cluster_bypass_ga102 39:39
#define NV_JTAG_SEC_CMD_t0_0_GAB_T0_OTHER0_i1500_cluster_bypass_ga102 37:37
#define NV_JTAG_SEC_CMD_t0_0_GAB_T0_OTHER1_i1500_cluster_bypass_ga102 36:36
#define NV_JTAG_SEC_CMD_t0_0_GAB_T0_OTHER2_i1500_cluster_bypass_ga102 35:35
#define NV_JTAG_SEC_CMD_t0_0_GAB_T0_OTHER3_i1500_cluster_bypass_ga102 34:34
#define NV_JTAG_SEC_CMD_t0_0_GAB_T0_OTHER4_i1500_cluster_bypass_ga102 33:33
#define NV_JTAG_SEC_CMD_t0_0_GAB_T0_OTHER5_i1500_cluster_bypass_ga102 32:32
#define NV_JTAG_SEC_CMD_testmaster_failed_unlock_ga102 44:44
#define NV_JTAG_SEC_CMD_testmaster_reserved_ga102 48:45
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_ready_status_ga102 42:42
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_start_ga102 41:41
#define NV_JTAG_SEC_CMD_testmaster_tdo_pipeline_ga102 40:40
#define NV_JTAG_SEC_CMD_testmaster_trng_enable_ga102 43:43
#define NV_JTAG_SEC_RDAT_CLUSTER_ID_ga102 0
#define NV_JTAG_SEC_RDAT_ID_ga102 136
#define NV_JTAG_SEC_RDAT_CHAINLENGTH_ga102 191
#define NV_JTAG_SEC_RDAT_d0_0_i1500_cluster_bypass_ga102 38:38
#define NV_JTAG_SEC_RDAT_f0_0_i1500_cluster_bypass_ga102 29:29
#define NV_JTAG_SEC_RDAT_f0_1_i1500_cluster_bypass_ga102 28:28
#define NV_JTAG_SEC_RDAT_f0_2_i1500_cluster_bypass_ga102 27:27
#define NV_JTAG_SEC_RDAT_f0_3_i1500_cluster_bypass_ga102 5:5
#define NV_JTAG_SEC_RDAT_f0_4_i1500_cluster_bypass_ga102 4:4
#define NV_JTAG_SEC_RDAT_f0_5_i1500_cluster_bypass_ga102 3:3
#define NV_JTAG_SEC_RDAT_g0_0_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 26:26
#define NV_JTAG_SEC_RDAT_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 25:25
#define NV_JTAG_SEC_RDAT_g0_0_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 24:24
#define NV_JTAG_SEC_RDAT_g0_1_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 23:23
#define NV_JTAG_SEC_RDAT_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 22:22
#define NV_JTAG_SEC_RDAT_g0_1_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 21:21
#define NV_JTAG_SEC_RDAT_g0_2_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 20:20
#define NV_JTAG_SEC_RDAT_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 19:19
#define NV_JTAG_SEC_RDAT_g0_2_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 18:18
#define NV_JTAG_SEC_RDAT_g0_3_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 17:17
#define NV_JTAG_SEC_RDAT_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 16:16
#define NV_JTAG_SEC_RDAT_g0_3_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 15:15
#define NV_JTAG_SEC_RDAT_g0_4_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 14:14
#define NV_JTAG_SEC_RDAT_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 13:13
#define NV_JTAG_SEC_RDAT_g0_4_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 12:12
#define NV_JTAG_SEC_RDAT_g0_5_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 8:8
#define NV_JTAG_SEC_RDAT_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 7:7
#define NV_JTAG_SEC_RDAT_g0_5_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 6:6
#define NV_JTAG_SEC_RDAT_g0_6_GAB_G0_OTHER0_i1500_cluster_bypass_ga102 11:11
#define NV_JTAG_SEC_RDAT_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER3_i1500_cluster_bypass_ga102 10:10
#define NV_JTAG_SEC_RDAT_g0_6_GAB_G0_OTHER2_GAB_G0_OTHER7_i1500_cluster_bypass_ga102 9:9
#define NV_JTAG_SEC_RDAT_l0_0_i1500_cluster_bypass_ga102 2:2
#define NV_JTAG_SEC_RDAT_m0_0_i1500_cluster_bypass_ga102 31:31
#define NV_JTAG_SEC_RDAT_m1_0_i1500_cluster_bypass_ga102 30:30
#define NV_JTAG_SEC_RDAT_nx0_0_GAB_NX0_OTHER0_i1500_cluster_bypass_ga102 1:1
#define NV_JTAG_SEC_RDAT_nx0_0_GAB_NX0_OTHER1_i1500_cluster_bypass_ga102 0:0
#define NV_JTAG_SEC_RDAT_s0_0_i1500_cluster_bypass_ga102 39:39
#define NV_JTAG_SEC_RDAT_t0_0_GAB_T0_OTHER0_i1500_cluster_bypass_ga102 37:37
#define NV_JTAG_SEC_RDAT_t0_0_GAB_T0_OTHER1_i1500_cluster_bypass_ga102 36:36
#define NV_JTAG_SEC_RDAT_t0_0_GAB_T0_OTHER2_i1500_cluster_bypass_ga102 35:35
#define NV_JTAG_SEC_RDAT_t0_0_GAB_T0_OTHER3_i1500_cluster_bypass_ga102 34:34
#define NV_JTAG_SEC_RDAT_t0_0_GAB_T0_OTHER4_i1500_cluster_bypass_ga102 33:33
#define NV_JTAG_SEC_RDAT_t0_0_GAB_T0_OTHER5_i1500_cluster_bypass_ga102 32:32
#define NV_JTAG_SEC_RDAT_testmaster_c_data_ga102 190:51
#define NV_JTAG_SEC_RDAT_testmaster_c_valid_value_ga102 50:41
#define NV_JTAG_SEC_RDAT_testmaster_tdo_pipeline_ga102 40:40
#define NV_JTAG_SEC_UNLOCK_STATUS_ID_ga102 249
#define NV_JTAG_SEC_UNLOCK_STATUS_CHAINLENGTH_ga102 697
#define NV_JTAG_SEC_UNLOCK_STATUS_features_ga102 696:681
#define NV_JTAG_NUM_CLUSTERS_ga102 41
#define NV_JTAG_SEC_CFG_CLUSTER_ID_ga106 0
#define NV_JTAG_SEC_CFG_ID_ga106 8
#define NV_JTAG_SEC_CFG_CHAINLENGTH_ga106 34
#define NV_JTAG_SEC_CFG_d0_0_i1500_cluster_bypass_ga106 15:15
#define NV_JTAG_SEC_CFG_f0_0_i1500_cluster_bypass_ga106 9:9
#define NV_JTAG_SEC_CFG_f0_1_i1500_cluster_bypass_ga106 8:8
#define NV_JTAG_SEC_CFG_f0_2_i1500_cluster_bypass_ga106 1:1
#define NV_JTAG_SEC_CFG_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 7:7
#define NV_JTAG_SEC_CFG_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 6:6
#define NV_JTAG_SEC_CFG_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 5:5
#define NV_JTAG_SEC_CFG_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 4:4
#define NV_JTAG_SEC_CFG_g0_2_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 3:3
#define NV_JTAG_SEC_CFG_g0_2_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 2:2
#define NV_JTAG_SEC_CFG_m0_0_i1500_cluster_bypass_ga106 11:11
#define NV_JTAG_SEC_CFG_n0_0_i1500_cluster_bypass_ga106 10:10
#define NV_JTAG_SEC_CFG_s0_0_i1500_cluster_bypass_ga106 16:16
#define NV_JTAG_SEC_CFG_t0_0_GAE_T0_OTHER0_i1500_cluster_bypass_ga106 14:14
#define NV_JTAG_SEC_CFG_t0_0_GAE_T0_OTHER1_i1500_cluster_bypass_ga106 13:13
#define NV_JTAG_SEC_CFG_t0_0_GAE_T0_OTHER2_i1500_cluster_bypass_ga106 12:12
#define NV_JTAG_SEC_CFG_testmaster_en_atpg_scan_ga106 19:19
#define NV_JTAG_SEC_CFG_testmaster_en_boundary_scan_ga106 23:23
#define NV_JTAG_SEC_CFG_testmaster_en_fuse_secure_ga106 28:28
#define NV_JTAG_SEC_CFG_testmaster_en_hbm_ga106 21:21
#define NV_JTAG_SEC_CFG_testmaster_en_iobist_ga106 22:22
#define NV_JTAG_SEC_CFG_testmaster_en_ist_debug_ga106 31:31
#define NV_JTAG_SEC_CFG_testmaster_en_jtag2host_ga106 25:25
#define NV_JTAG_SEC_CFG_testmaster_en_non_critical_regs_ga106 30:30
#define NV_JTAG_SEC_CFG_testmaster_en_obs_secure_ga106 27:27
#define NV_JTAG_SEC_CFG_testmaster_en_ram_dump_ga106 20:20
#define NV_JTAG_SEC_CFG_testmaster_en_scan_dump_ga106 18:18
#define NV_JTAG_SEC_CFG_testmaster_en_sec_mode_ga106 29:29
#define NV_JTAG_SEC_CFG_testmaster_en_top_fs_ga106 26:26
#define NV_JTAG_SEC_CFG_testmaster_en_wbr_ga106 24:24
#define NV_JTAG_SEC_CFG_testmaster_global_enable_ga106 33:33
#define NV_JTAG_SEC_CFG_testmaster_reserved_ga106 32:32
#define NV_JTAG_SEC_CFG_testmaster_tdo_pipeline_ga106 17:17
#define NV_JTAG_SEC_CFG_x0_0_i1500_cluster_bypass_ga106 0:0
#define NV_JTAG_SEC_CFG_features_ga106 33:18
#define NV_JTAG_SEC_CHK_CLUSTER_ID_ga106 0
#define NV_JTAG_SEC_CHK_ID_ga106 7
#define NV_JTAG_SEC_CHK_CHAINLENGTH_ga106 274
#define NV_JTAG_SEC_CHK_d0_0_i1500_cluster_bypass_ga106 15:15
#define NV_JTAG_SEC_CHK_f0_0_i1500_cluster_bypass_ga106 9:9
#define NV_JTAG_SEC_CHK_f0_1_i1500_cluster_bypass_ga106 8:8
#define NV_JTAG_SEC_CHK_f0_2_i1500_cluster_bypass_ga106 1:1
#define NV_JTAG_SEC_CHK_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 7:7
#define NV_JTAG_SEC_CHK_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 6:6
#define NV_JTAG_SEC_CHK_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 5:5
#define NV_JTAG_SEC_CHK_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 4:4
#define NV_JTAG_SEC_CHK_g0_2_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 3:3
#define NV_JTAG_SEC_CHK_g0_2_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 2:2
#define NV_JTAG_SEC_CHK_m0_0_i1500_cluster_bypass_ga106 11:11
#define NV_JTAG_SEC_CHK_n0_0_i1500_cluster_bypass_ga106 10:10
#define NV_JTAG_SEC_CHK_s0_0_i1500_cluster_bypass_ga106 16:16
#define NV_JTAG_SEC_CHK_t0_0_GAE_T0_OTHER0_i1500_cluster_bypass_ga106 14:14
#define NV_JTAG_SEC_CHK_t0_0_GAE_T0_OTHER1_i1500_cluster_bypass_ga106 13:13
#define NV_JTAG_SEC_CHK_t0_0_GAE_T0_OTHER2_i1500_cluster_bypass_ga106 12:12
#define NV_JTAG_SEC_CHK_testmaster_secureid_ga106 273:18
#define NV_JTAG_SEC_CHK_testmaster_tdo_pipeline_ga106 17:17
#define NV_JTAG_SEC_CHK_x0_0_i1500_cluster_bypass_ga106 0:0
#define NV_JTAG_SEC_CMD_CLUSTER_ID_ga106 0
#define NV_JTAG_SEC_CMD_ID_ga106 9
#define NV_JTAG_SEC_CMD_CHAINLENGTH_ga106 26
#define NV_JTAG_SEC_CMD_d0_0_i1500_cluster_bypass_ga106 15:15
#define NV_JTAG_SEC_CMD_f0_0_i1500_cluster_bypass_ga106 9:9
#define NV_JTAG_SEC_CMD_f0_1_i1500_cluster_bypass_ga106 8:8
#define NV_JTAG_SEC_CMD_f0_2_i1500_cluster_bypass_ga106 1:1
#define NV_JTAG_SEC_CMD_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 7:7
#define NV_JTAG_SEC_CMD_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 6:6
#define NV_JTAG_SEC_CMD_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 5:5
#define NV_JTAG_SEC_CMD_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 4:4
#define NV_JTAG_SEC_CMD_g0_2_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 3:3
#define NV_JTAG_SEC_CMD_g0_2_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 2:2
#define NV_JTAG_SEC_CMD_m0_0_i1500_cluster_bypass_ga106 11:11
#define NV_JTAG_SEC_CMD_n0_0_i1500_cluster_bypass_ga106 10:10
#define NV_JTAG_SEC_CMD_s0_0_i1500_cluster_bypass_ga106 16:16
#define NV_JTAG_SEC_CMD_t0_0_GAE_T0_OTHER0_i1500_cluster_bypass_ga106 14:14
#define NV_JTAG_SEC_CMD_t0_0_GAE_T0_OTHER1_i1500_cluster_bypass_ga106 13:13
#define NV_JTAG_SEC_CMD_t0_0_GAE_T0_OTHER2_i1500_cluster_bypass_ga106 12:12
#define NV_JTAG_SEC_CMD_testmaster_failed_unlock_ga106 21:21
#define NV_JTAG_SEC_CMD_testmaster_reserved_ga106 25:22
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_ready_status_ga106 19:19
#define NV_JTAG_SEC_CMD_testmaster_sha_cal_start_ga106 18:18
#define NV_JTAG_SEC_CMD_testmaster_tdo_pipeline_ga106 17:17
#define NV_JTAG_SEC_CMD_testmaster_trng_enable_ga106 20:20
#define NV_JTAG_SEC_CMD_x0_0_i1500_cluster_bypass_ga106 0:0
#define NV_JTAG_SEC_RDAT_CLUSTER_ID_ga106 0
#define NV_JTAG_SEC_RDAT_ID_ga106 136
#define NV_JTAG_SEC_RDAT_CHAINLENGTH_ga106 168
#define NV_JTAG_SEC_RDAT_d0_0_i1500_cluster_bypass_ga106 15:15
#define NV_JTAG_SEC_RDAT_f0_0_i1500_cluster_bypass_ga106 9:9
#define NV_JTAG_SEC_RDAT_f0_1_i1500_cluster_bypass_ga106 8:8
#define NV_JTAG_SEC_RDAT_f0_2_i1500_cluster_bypass_ga106 1:1
#define NV_JTAG_SEC_RDAT_g0_0_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 7:7
#define NV_JTAG_SEC_RDAT_g0_0_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 6:6
#define NV_JTAG_SEC_RDAT_g0_1_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 5:5
#define NV_JTAG_SEC_RDAT_g0_1_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 4:4
#define NV_JTAG_SEC_RDAT_g0_2_GAE_G0_OTHER0_i1500_cluster_bypass_ga106 3:3
#define NV_JTAG_SEC_RDAT_g0_2_GAE_G0_OTHER2_i1500_cluster_bypass_ga106 2:2
#define NV_JTAG_SEC_RDAT_m0_0_i1500_cluster_bypass_ga106 11:11
#define NV_JTAG_SEC_RDAT_n0_0_i1500_cluster_bypass_ga106 10:10
#define NV_JTAG_SEC_RDAT_s0_0_i1500_cluster_bypass_ga106 16:16
#define NV_JTAG_SEC_RDAT_t0_0_GAE_T0_OTHER0_i1500_cluster_bypass_ga106 14:14
#define NV_JTAG_SEC_RDAT_t0_0_GAE_T0_OTHER1_i1500_cluster_bypass_ga106 13:13
#define NV_JTAG_SEC_RDAT_t0_0_GAE_T0_OTHER2_i1500_cluster_bypass_ga106 12:12
#define NV_JTAG_SEC_RDAT_testmaster_c_data_ga106 167:28
#define NV_JTAG_SEC_RDAT_testmaster_c_valid_value_ga106 27:18
#define NV_JTAG_SEC_RDAT_testmaster_tdo_pipeline_ga106 17:17
#define NV_JTAG_SEC_RDAT_x0_0_i1500_cluster_bypass_ga106 0:0
#define NV_JTAG_SEC_UNLOCK_STATUS_ID_ga106 249
#define NV_JTAG_SEC_UNLOCK_STATUS_CHAINLENGTH_ga106 306
#define NV_JTAG_SEC_UNLOCK_STATUS_features_ga106 305:290
#define NV_JTAG_NUM_CLUSTERS_ga106 18

959
include/ampere/ga102/dev_hdacodec.h Normal file
View File

@@ -0,0 +1,959 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_hdacodec_h__
#define __ga102_dev_hdacodec_h__
/* This file is autogenerated. Do not edit */
#define NV_HDACODEC 0x0010efff:0x0010ec00 /* RW--D */
#define NV_HDACODEC_NUM_CW 4 /* */
#define NV_HDACODEC_NUM_PW 4 /* */
#define NV_HDACODEC_NUM_DE 4 /* */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW0_DE(i) (0x0010ec00+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW0_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW0_DE_INDEX 15:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW0_DE_INDEX_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW0_DE_DATABYTE 7:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW0_DE_DATABYTE_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW1_DE(i) (0x0010ec30+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW1_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW1_DE_INDEX 15:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW1_DE_INDEX_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW1_DE_DATABYTE 7:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW1_DE_DATABYTE_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW2_DE(i) (0x0010ec60+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW2_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW2_DE_INDEX 15:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW2_DE_INDEX_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW2_DE_DATABYTE 7:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW2_DE_DATABYTE_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW3_DE(i) (0x0010ec90+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW3_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW3_DE_INDEX 15:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW3_DE_INDEX_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW3_DE_DATABYTE 7:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW3_DE_DATABYTE_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW_DE(i,j) (0x0010ec00+((i)*48)+((j)*4)) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW_DE__SIZE_2 4 /* */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW_DE_INDEX 15:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW_DE_INDEX_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW_DE_DATABYTE 7:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_ELD_BUFWR_PW_DE_DATABYTE_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE(i) (0x0010ec10+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_ELDV 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_ELDV_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_ELDV_VALID 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_ELDV_INVALID 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_PD 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_PD_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_PD_PRESENT 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_PD_NOT_PRESENT 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_IA 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_IA_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_IA_ASRTD 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_IA_DEASRTD 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_CP_READY 27:27 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_CP_READY_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_CP_READY_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_CP_READY_READY 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_VALID 30:30 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_VALID_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_VALID_VLD 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_VALID_INVLD 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE 29:28 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_DONT_CARE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_RESERVED 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_PROTECTION_OFF 0x00000002 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RQSTD_CP_STATE_PROTECTION_ON 0x00000003 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RESEND 31:31 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RESEND_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RESEND_TRIGGER 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RESEND_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW0_DE_RESEND_DONE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE(i) (0x0010ec40+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_ELDV 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_ELDV_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_ELDV_VALID 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_ELDV_INVALID 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_PD 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_PD_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_PD_PRESENT 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_PD_NOT_PRESENT 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_IA 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_IA_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_IA_ASRTD 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_IA_DEASRTD 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_CP_READY 27:27 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_CP_READY_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_CP_READY_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_CP_READY_READY 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_VALID 30:30 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_VALID_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_VALID_VLD 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_VALID_INVLD 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE 29:28 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_DONT_CARE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_RESERVED 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_PROTECTION_OFF 0x00000002 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RQSTD_CP_STATE_PROTECTION_ON 0x00000003 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RESEND 31:31 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RESEND_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RESEND_TRIGGER 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RESEND_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW1_DE_RESEND_DONE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE(i) (0x0010ec70+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_ELDV 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_ELDV_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_ELDV_VALID 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_ELDV_INVALID 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_PD 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_PD_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_PD_PRESENT 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_PD_NOT_PRESENT 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_IA 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_IA_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_IA_ASRTD 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_IA_DEASRTD 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_CP_READY 27:27 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_CP_READY_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_CP_READY_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_CP_READY_READY 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_VALID 30:30 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_VALID_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_VALID_VLD 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_VALID_INVLD 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE 29:28 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_DONT_CARE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_RESERVED 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_PROTECTION_OFF 0x00000002 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RQSTD_CP_STATE_PROTECTION_ON 0x00000003 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RESEND 31:31 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RESEND_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RESEND_TRIGGER 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RESEND_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW2_DE_RESEND_DONE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE(i) (0x0010eca0+(i)*4) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_ELDV 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_ELDV_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_ELDV_VALID 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_ELDV_INVALID 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_PD 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_PD_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_PD_PRESENT 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_PD_NOT_PRESENT 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_IA 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_IA_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_IA_ASRTD 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_IA_DEASRTD 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_CP_READY 27:27 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_CP_READY_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_CP_READY_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_CP_READY_READY 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_VALID 30:30 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_VALID_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_VALID_VLD 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_VALID_INVLD 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE 29:28 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_DONT_CARE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_RESERVED 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_PROTECTION_OFF 0x00000002 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RQSTD_CP_STATE_PROTECTION_ON 0x00000003 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RESEND 31:31 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RESEND_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RESEND_TRIGGER 0x00000001 /* -W--T */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RESEND_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW3_DE_RESEND_DONE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE(i,j) (0x0010ec10+((i)*48)+((j)*4)) /* RWI4A */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE__SIZE_2 4 /* */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_ELDV 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_ELDV_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_ELDV_VALID 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_ELDV_INVALID 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_PD 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_PD_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_PD_PRESENT 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_PD_NOT_PRESENT 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_IA 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_IA_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_IA_ASRTD 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_IA_DEASRTD 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_CP_READY 27:27 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_CP_READY_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_CP_READY_READY 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_CP_READY_NOT_READY 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_VALID 30:30 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_VALID_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_VALID_VLD 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_VALID_INVLD 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE 29:28 /* R-IVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_DONT_CARE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_RESERVED 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_PROTECTION_OFF 0x00000002 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RQSTD_CP_STATE_PROTECTION_ON 0x00000003 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RESEND 31:31 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RESEND_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RESEND_TRIGGER 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RESEND_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_HDA_PRESENCE_PW_DE_RESEND_DONE 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN 0x0010ecc0 /* RWI4R */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW0 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW0_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW0_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW0_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW1 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW1_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW1_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW1_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW2 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW2_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW2_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW2_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW3 3:3 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW3_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW3_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW3_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW(i) (0+(i)):(0+(i)) /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW_INIT 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW_ENABLE 0x00000001 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_CW_DISABLE 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE0 8:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE0_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE0_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE0_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE1 9:9 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE1_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE1_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE1_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE2 10:10 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE2_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE2_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE2_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE3 11:11 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE3_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE3_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW0_DE3_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE0 12:12 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE0_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE0_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE0_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE1 13:13 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE1_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE1_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE1_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE2 14:14 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE2_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE2_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE2_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE3 15:15 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE3_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE3_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW1_DE3_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE0 16:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE0_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE0_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE0_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE1 17:17 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE1_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE1_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE1_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE2 18:18 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE2_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE2_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE2_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE3 19:19 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE3_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE3_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW2_DE3_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE0 20:20 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE0_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE0_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE0_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE1 21:21 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE1_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE1_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE1_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE2 22:22 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE2_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE2_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE2_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE3 23:23 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE3_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE3_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW3_DE3_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW_DE(i,j) (8+(i)*4+(j)):(8+(i)*4+(j)) /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW_DE__SIZE_2 4 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW_DE_INIT 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW_DE_ENABLE 0x00000001 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_EN_PW_DE_DISABLE 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS 0x0010ecc4 /* RWI4R */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW0 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW0_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW0_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW0_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW1 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW1_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW1_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW1_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW2 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW2_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW2_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW2_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW3 3:3 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW3_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW3_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW3_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW(i) (0+(i)):(0+(i)) /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW_INIT 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW_PENDING 0x00000001 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW_NOT_PENDING 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_CW_RESET 0x00000001 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE0 8:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE0_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE0_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE0_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE1 9:9 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE1_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE1_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE1_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE2 10:10 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE2_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE2_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE2_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE3 11:11 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE3_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE3_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW0_DE3_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE0 12:12 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE0_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE0_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE0_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE1 13:13 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE1_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE1_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE1_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE2 14:14 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE2_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE2_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE2_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE3 15:15 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE3_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE3_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW1_DE3_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE0 16:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE0_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE0_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE0_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE1 17:17 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE1_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE1_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE1_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE2 18:18 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE2_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE2_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE2_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE3 19:19 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE3_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE3_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW2_DE3_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE0 20:20 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE0_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE0_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE0_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE1 21:21 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE1_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE1_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE1_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE2 22:22 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE2_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE2_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE2_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE3 23:23 /* RWIVF */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE3_PENDING 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE3_NOT_PENDING 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW3_DE3_RESET 0x00000001 /* -W--V */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW_DE(i,j) (8+(i)*4+(j)):(8+(i)*4+(j)) /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW_DE__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW_DE__SIZE_2 4 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW_DE_INIT 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW_DE_PENDING 0x00000001 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW_DE_NOT_PENDING 0x00000000 /* */
#define NV_HDACODEC_AUDIO_INTERRUPT_STS_PW_DE_RESET 0x00000001 /* */
#define NV_HDACODEC_DISP_TO_AUDIO_HDA_SCRATCH_CW(i) (0x0010ecd0+(i)*8) /* RW-4A */
#define NV_HDACODEC_DISP_TO_AUDIO_HDA_SCRATCH_CW__SIZE_1 4 /* */
#define NV_HDACODEC_DISP_TO_AUDIO_HDA_SCRATCH_CW_RESERVED 31:0 /* RWIVF */
#define NV_HDACODEC_DISP_TO_AUDIO_HDA_SCRATCH_CW_RESERVED_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_TO_DISP_HDA_CODEC_SCRATCH_CW(i) (0x0010ecd4+(i)*8) /* R-I4A */
#define NV_HDACODEC_AUDIO_TO_DISP_HDA_CODEC_SCRATCH_CW__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_TO_DISP_HDA_CODEC_SCRATCH_CW_DATA 31:0 /* R-IVF */
#define NV_HDACODEC_AUDIO_TO_DISP_HDA_CODEC_SCRATCH_CW_DATA_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_DP_MN_PW(i) (0x0010ecf0+(i)*4) /* RW-4A */
#define NV_HDACODEC_DP_MN_PW__SIZE_1 4 /* */
#define NV_HDACODEC_DP_MN_PW_N_VAL 23:0 /* RWIVF */
#define NV_HDACODEC_DP_MN_PW_N_VAL_INIT 0x00008000 /* RWI-V */
#define NV_HDACODEC_DP_MN_PW_M_DELTA 27:24 /* RWIVF */
#define NV_HDACODEC_DP_MN_PW_M_DELTA_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_DP_MN_PW_M_MOD 31:30 /* RWIVF */
#define NV_HDACODEC_DP_MN_PW_M_MOD_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_DP_MN_PW_M_MOD_NONE 0x00000000 /* RW--V */
#define NV_HDACODEC_DP_MN_PW_M_MOD_INC 0x00000001 /* RW--V */
#define NV_HDACODEC_DP_MN_PW_M_MOD_DEC 0x00000002 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0320 0x0010ed00 /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_0320_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_0320_VALUE_INIT 0x0000D2F0 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_0320_VALUE_54M 0x0000D2F0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0320_VALUE_24M 0x00005DC0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0320_VALUE_27M 0x00006978 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0441 0x0010ed04 /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_0441_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_0441_VALUE_INIT 0x0000EA60 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_0441_VALUE_54M 0x0000EA60 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0441_VALUE_27M 0x00007530 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0882 0x0010ed08 /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_0882_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_0882_VALUE_INIT 0x0000EA60 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_0882_VALUE_54M 0x0000EA60 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0882_VALUE_27M 0x00007530 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_1764 0x0010ed0c /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_1764_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_1764_VALUE_INIT 0x0000EA60 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_1764_VALUE_54M 0x0000EA60 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_1764_VALUE_27M 0x00007530 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0480 0x0010ed10 /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_0480_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_0480_VALUE_INIT 0x0000D2F0 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_0480_VALUE_54M 0x0000D2F0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0480_VALUE_24M 0x00005DC0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0480_VALUE_27M 0x00006978 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0960 0x0010ed14 /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_0960_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_0960_VALUE_INIT 0x0000D2F0 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_0960_VALUE_54M 0x0000D2F0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0960_VALUE_24M 0x00005DC0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_0960_VALUE_27M 0x00006978 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_1920 0x0010ed18 /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_1920_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_1920_VALUE_INIT 0x0000D2F0 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_1920_VALUE_54M 0x0000D2F0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_1920_VALUE_24M 0x00005DC0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_1920_VALUE_27M 0x00006978 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_DEFAULT 0x0010ed1c /* RWI4R */
#define NV_HDACODEC_AUDIO_AVAL_DEFAULT_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_AVAL_DEFAULT_VALUE_INIT 0x0000D2F0 /* RWI-V */
#define NV_HDACODEC_AUDIO_AVAL_DEFAULT_VALUE_54M 0x0000D2F0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_DEFAULT_VALUE_24M 0x00005DC0 /* RW--V */
#define NV_HDACODEC_AUDIO_AVAL_DEFAULT_VALUE_27M 0x00006978 /* RW--V */
#define NV_HDACODEC_AUDIO_NVAL_0320 0x0010ed20 /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_0320_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_0320_VALUE_INIT 0x00001000 /* RWI-V */
#define NV_HDACODEC_AUDIO_NVAL_0441 0x0010ed24 /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_0441_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_0441_VALUE_INIT 0x00001880 /* RWI-V */
#define NV_HDACODEC_AUDIO_NVAL_0882 0x0010ed28 /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_0882_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_0882_VALUE_INIT 0x00003100 /* RWI-V */
#define NV_HDACODEC_AUDIO_NVAL_1764 0x0010ed2c /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_1764_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_1764_VALUE_INIT 0x00006200 /* RWI-V */
#define NV_HDACODEC_AUDIO_NVAL_0480 0x0010ed30 /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_0480_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_0480_VALUE_INIT 0x00001800 /* RWI-V */
#define NV_HDACODEC_AUDIO_NVAL_0960 0x0010ed34 /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_0960_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_0960_VALUE_INIT 0x00003000 /* RWI-V */
#define NV_HDACODEC_AUDIO_NVAL_1920 0x0010ed38 /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_1920_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_1920_VALUE_INIT 0x00006000 /* RWI-V */
#define NV_HDACODEC_AUDIO_NVAL_DEFAULT 0x0010ed3c /* RWI4R */
#define NV_HDACODEC_AUDIO_NVAL_DEFAULT_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_NVAL_DEFAULT_VALUE_INIT 0x00001800 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT 0x0010ef1c /* RWI4R */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE0 1:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE0_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE0_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE0_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE0_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE1 3:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE1_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE1_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE1_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE1_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE2 5:4 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE2_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE2_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE2_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE2_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE3 7:6 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE3_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE3_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE3_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW0_DE3_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE0 9:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE0_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE0_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE0_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE0_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE1 11:10 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE1_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE1_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE1_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE1_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE2 13:12 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE2_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE2_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE2_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE2_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE3 15:14 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE3_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE3_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE3_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW1_DE3_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE0 17:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE0_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE0_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE0_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE0_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE1 19:18 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE1_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE1_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE1_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE1_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE2 21:20 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE2_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE2_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE2_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE2_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE3 23:22 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE3_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE3_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE3_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW2_DE3_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE0 25:24 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE0_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE0_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE0_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE0_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE1 27:26 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE1_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE1_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE1_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE1_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE2 29:28 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE2_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE2_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE2_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE2_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE3 31:30 /* RWIVF */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE3_INIT 0 /* RWI-V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE3_ALL 0 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE3_HDMI 1 /* RW--V */
#define NV_HDACODEC_AUDIO_HDMI_OR_DP_MODE_SELECT_PW3_DE3_DP 2 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0320 0x0010ef20 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0320_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0320_VALUE_INIT 0x00008CA0 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0320_VALUE_54M 0x00008CA0 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0320_VALUE_24M 0x00003E80 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0320_VALUE_27M 0x00004650 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0441 0x0010ef24 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0441_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0441_VALUE_INIT 0x00009C40 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0441_VALUE_54M 0x00009C40 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0441_VALUE_27M 0x00004E20 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0882 0x0010ef28 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0882_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0882_VALUE_INIT 0x00009C40 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0882_VALUE_54M 0x00009C40 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0882_VALUE_27M 0x00004E20 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1764 0x0010ef2c /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1764_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1764_VALUE_INIT 0x00009C40 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1764_VALUE_54M 0x00009C40 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1764_VALUE_27M 0x00004E20 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0480 0x0010ef30 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0480_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0480_VALUE_INIT 0x00008CA0 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0480_VALUE_54M 0x00008CA0 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0480_VALUE_24M 0x00003E80 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0480_VALUE_27M 0x00004650 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0960 0x0010ef34 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0960_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0960_VALUE_INIT 0x00008CA0 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0960_VALUE_54M 0x00008CA0 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0960_VALUE_24M 0x00003E80 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_0960_VALUE_27M 0x00004650 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1920 0x0010ef38 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1920_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1920_VALUE_INIT 0x00008CA0 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1920_VALUE_54M 0x00008CA0 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1920_VALUE_24M 0x00003E80 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_1920_VALUE_27M 0x00004650 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_DEFAULT 0x0010ef3c /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_AVAL_DEFAULT_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_AVAL_DEFAULT_VALUE_INIT 0x00008CA0 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_DEFAULT_VALUE_54M 0x00008CA0 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_DEFAULT_VALUE_24M 0x00003E80 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_AVAL_DEFAULT_VALUE_27M 0x00004650 /* RW--V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0320 0x0010ef40 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0320_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0320_VALUE_INIT 0x00001000 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0441 0x0010ef44 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0441_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0441_VALUE_INIT 0x00001880 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0882 0x0010ef48 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0882_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0882_VALUE_INIT 0x00003100 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_1764 0x0010ef4c /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_1764_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_1764_VALUE_INIT 0x00006200 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0480 0x0010ef50 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0480_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0480_VALUE_INIT 0x00001800 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0960 0x0010ef54 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0960_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_0960_VALUE_INIT 0x00003000 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_1920 0x0010ef58 /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_1920_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_1920_VALUE_INIT 0x00006000 /* RWI-V */
#define NV_HDACODEC_AUDIO_FRL_NVAL_DEFAULT 0x0010ef5c /* RWI4R */
#define NV_HDACODEC_AUDIO_FRL_NVAL_DEFAULT_VALUE 19:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FRL_NVAL_DEFAULT_VALUE_INIT 0x00001800 /* RWI-V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0480 0x0010ef60 /* RWI4R */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0480_VALUE 12:0 /* RWIVF */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0480_VALUE_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0960 0x0010ef64 /* RWI4R */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0960_VALUE 12:0 /* RWIVF */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0960_VALUE_INIT 0x00000232 /* RWI-V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0960_VALUE_54M 0x00000232 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0960_VALUE_24M 0x000000FA /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0960_VALUE_27M 0x00000119 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1920 0x0010ef68 /* RWI4R */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1920_VALUE 12:0 /* RWIVF */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1920_VALUE_INIT 0x00000119 /* RWI-V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1920_VALUE_54M 0x00000119 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1920_VALUE_24M 0x0000007D /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1920_VALUE_27M 0x0000008D /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0882 0x0010ef6c /* RWI4R */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0882_VALUE 12:0 /* RWIVF */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0882_VALUE_INIT 0x00000264 /* RWI-V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0882_VALUE_54M 0x00000264 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0882_VALUE_24M 0x00000110 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_0882_VALUE_27M 0x00000132 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1764 0x0010ef70 /* RWI4R */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1764_VALUE 12:0 /* RWIVF */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1764_VALUE_INIT 0x00000132 /* RWI-V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1764_VALUE_54M 0x00000132 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1764_VALUE_24M 0x00000088 /* RW--V */
#define NV_HDACODEC_COUNTER_VALUE_FOR_CTS_1764_VALUE_27M 0x00000099 /* RW--V */
#define NV_HDACODEC_DIP_DATA_RESEND_PKT_NUMBER 0x0010ef74 /* RWI4R */
#define NV_HDACODEC_DIP_DATA_RESEND_PKT_NUMBER_VALUE 2:0 /* RWIVF */
#define NV_HDACODEC_DIP_DATA_RESEND_PKT_NUMBER_VALUE_INIT 0x00000004 /* RWI-V */
#define NV_HDACODEC_DIP_DATA_RESEND_PKT_NUMBER_VALUE_HDMI 0x00000004 /* RW--V */
#define NV_HDACODEC_DIP_DATA_RESEND_PKT_NUMBER_VALUE_DP 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_FORMAT_BITS_CHNG_DETECT_CYA 0x0010ef78 /* RWI4R */
#define NV_HDACODEC_AUDIO_FORMAT_BITS_CHNG_DETECT_CYA_DISABLE 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_FORMAT_BITS_CHNG_DETECT_CYA_DISABLE_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320 0x0010ed40 /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_D_N_INIT 0x00003DEB /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_D_N_270M 0x00003DEB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_D_N_216M 0x00000C2F /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_D_N_432M 0x00000CAF /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_D_N_120M 0x00000653 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_D_N_108M 0x00000B2F /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_N_INIT 0x00000400 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_N_270M 0x00000400 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_N_216M 0x00000100 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_N_432M 0x00000080 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_N_120M 0x00000100 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0320_N_108M 0x00000200 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441 0x0010ed44 /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_D_N_INIT 0x00009703 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_D_N_270M 0x00009703 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_D_N_216M 0x0000068F /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_D_N_432M 0x000006F1 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_D_N_120M 0x000009E9 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_D_N_108M 0x000005CB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_N_INIT 0x00000DC8 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_N_270M 0x00000DC8 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_N_216M 0x000000C4 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_N_432M 0x00000062 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_N_120M 0x0000024C /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0441_N_108M 0x00000188 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882 0x0010ed48 /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_D_N_INIT 0x0000893B /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_D_N_270M 0x0000893B /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_D_N_216M 0x000005CB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_D_N_432M 0x0000068F /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_D_N_120M 0x0000079D /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_D_N_108M 0x00000443 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_N_INIT 0x00001B90 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_N_270M 0x00001B90 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_N_216M 0x00000188 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_N_432M 0x000000C4 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_N_120M 0x00000498 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0882_N_108M 0x00000310 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764 0x0010ed4c /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_D_N_INIT 0x00006DAB /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_D_N_270M 0x00006DAB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_D_N_216M 0x00000443 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_D_N_432M 0x000005CB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_D_N_120M 0x00000305 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_D_N_108M 0x00000133 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_N_INIT 0x00003720 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_N_270M 0x00003720 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_N_216M 0x00000310 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_N_432M 0x00000188 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_N_120M 0x00000930 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1764_N_108M 0x00000620 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480 0x0010ed50 /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_D_N_INIT 0x00003BEB /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_D_N_270M 0x00003BEB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_D_N_216M 0x000003E5 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_D_N_432M 0x00000425 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_D_N_120M 0x000001F1 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_D_N_108M 0x00000365 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_N_INIT 0x00000600 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_N_270M 0x00000600 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_N_216M 0x00000080 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_N_432M 0x00000040 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_N_120M 0x00000080 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0480_N_108M 0x00000100 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960 0x0010ed54 /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_D_N_INIT 0x000035EB /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_D_N_270M 0x000035EB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_D_N_216M 0x00000365 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_D_N_432M 0x000003E5 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_D_N_120M 0x00000171 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_D_N_108M 0x00000265 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_N_INIT 0x00000C00 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_N_270M 0x00000C00 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_N_216M 0x00000100 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_N_432M 0x00000080 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_N_120M 0x00000100 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_0960_N_108M 0x00000200 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920 0x0010ed58 /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_D_N_INIT 0x000029EB /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_D_N_270M 0x000029EB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_D_N_216M 0x00000265 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_D_N_432M 0x00000365 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_D_N_120M 0x00000071 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_D_N_108M 0x00000065 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_N_INIT 0x00001800 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_N_270M 0x00001800 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_N_216M 0x00000200 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_N_432M 0x00000100 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_N_120M 0x00000200 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_1920_N_108M 0x00000400 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840 0x0010ed5c /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_D_N_INIT 0x000011EB /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_D_N_270M 0x000011EB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_D_N_216M 0x00000065 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_D_N_432M 0x00000265 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_N_INIT 0x00003000 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_N_270M 0x00003000 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_N_216M 0x00000400 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_3840_N_432M 0x00000200 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680 0x0010ed60 /* RWI4R */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_D_N 15:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_D_N_INIT 0x000011EB /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_D_N_270M 0x000011EB /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_D_N_216M 0x00000065 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_D_N_432M 0x00000065 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_N 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_N_INIT 0x00003000 /* RWI-V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_N_270M 0x00003000 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_N_216M 0x00000400 /* RW--V */
#define NV_HDACODEC_AUDIO_TIMESTAMP_7680_N_432M 0x00000400 /* RW--V */
#define NV_HDACODEC_AUDIO_GEN_CTL 0x0010ed6c /* RWI4R */
#define NV_HDACODEC_AUDIO_GEN_CTL_CTS_RESET_VAL 2:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_CTS_RESET_VAL_INIT 0x00000001 /* RWI-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_CHSTS_FS_3840 7:4 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_CHSTS_FS_3840_INIT 0x00000005 /* RWI-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_COPY_POLARITY 8:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_COPY_POLARITY_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_COPY_POLARITY_OLD 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_GEN_CTL_COPY_POLARITY_NEW 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW0 16:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW0_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW0_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW1 17:17 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW1_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW1_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW2 18:18 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW2_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW2_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW3 19:19 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW3_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW3_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW(i) (16+(i)):(16+(i)) /* */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW_INIT 0x00000000 /* */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW_ERROR 0x00000001 /* */
#define NV_HDACODEC_AUDIO_GEN_CTL_ASMPL_FIFO_OVFLOW_CW_RESET 0x00000001 /* */
#define NV_HDACODEC_AUDIO_GEN_CTL_KEEP_ALIVE 30:30 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_KEEP_ALIVE_ENABLE 0x00000001 /* RWI-V */
#define NV_HDACODEC_AUDIO_GEN_CTL_KEEP_ALIVE_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_GEN_CTL_INJECT_NULLSMPL 31:31 /* RWIVF */
#define NV_HDACODEC_AUDIO_GEN_CTL_INJECT_NULLSMPL_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_GEN_CTL_INJECT_NULLSMPL_DISABLE 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_CTRL 0x0010ed78 /* RWI4R */
#define NV_HDACODEC_AUDIO_CTRL_DEV_ID 31:16 /* RWIVF */
#define NV_HDACODEC_AUDIO_CTRL_DEV_ID_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_CTRL_REV_ID 7:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_CTRL_REV_ID_INIT 0x00000001 /* RWI-V */
#define NV_HDACODEC_IP_VER 0x0010ed7c /* RW-4R */
#define NV_HDACODEC_IP_VER_DEV 7:0 /* R-IVF */
#define NV_HDACODEC_IP_VER_DEV_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_IP_VER_ECO 15:8 /* RWIVF */
#define NV_HDACODEC_IP_VER_ECO_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_IP_VER_MINOR 23:16 /* R-IVF */
#define NV_HDACODEC_IP_VER_MINOR_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_IP_VER_MAJOR 31:24 /* R-IVF */
#define NV_HDACODEC_IP_VER_MAJOR_INIT 0x00000003 /* R-I-V */
#define NV_HDACODEC_AUDIO_SPARE 0x0010ed70 /* RWI4R */
#define NV_HDACODEC_AUDIO_SPARE_RESERVED 31:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_SPARE_RESERVED_INIT 0x00000000 /* RWI-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM 0x0010ed74 /* RWI4R */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW0 0:0 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW0_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW0_NO_ERROR 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW0_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW1 1:1 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW1_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW1_NO_ERROR 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW1_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW2 2:2 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW2_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW2_NO_ERROR 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW2_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW3 3:3 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW3_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW3_NO_ERROR 0x00000000 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW3_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW(i) (0+(i)):(0+(i)) /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW_INIT 0x00000000 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW_ERROR 0x00000001 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW_NO_ERROR 0x00000000 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_PWFIFO_UNDERFLOW_CW_RESET 0x00000001 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW0 8:8 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW0_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW0_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW0_NO_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW0_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW1 9:9 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW1_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW1_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW1_NO_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW1_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW2 10:10 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW2_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW2_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW2_NO_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW2_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW3 11:11 /* RWIVF */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW3_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW3_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW3_NO_ERROR 0x00000001 /* R---V */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW3_RESET 0x00000001 /* -W--C */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW(i) (8+(i)):(8+(i)) /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW__SIZE_1 4 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW_INIT 0x00000000 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW_ERROR 0x00000001 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW_NO_ERROR 0x00000001 /* */
#define NV_HDACODEC_AUDIO_SECURE_STREAM_SECFIFO_OVERFLOW_CW_RESET 0x00000001 /* */
#define NV_HDACODEC_AUDIO_DEBUG_REG1 0x0010ed80 /* RWI4R */
#define NV_HDACODEC_AUDIO_DEBUG_REG1_COUNT 27:0 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG1_COUNT_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG1_DBG_MODE 28:28 /* RWIVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG1_DBG_MODE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG1_DBG_MODE_ENABLE 0x00000001 /* RW--V */
#define NV_HDACODEC_AUDIO_DEBUG_REG1_DBG_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_HDACODEC_AUDIO_DEBUG_REG2 0x0010ed84 /* R-I4R */
#define NV_HDACODEC_AUDIO_DEBUG_REG2_TSTAMP_PKT 31:0 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG2_TSTAMP_PKT_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG3 0x0010ef88 /* R-I4R */
#define NV_HDACODEC_AUDIO_DEBUG_REG3_LINK_FIFO_WR_CNT 3:0 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG3_LINK_FIFO_WR_CNT_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG4 0x0010ef8c /* R-I4R */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW3_MAP_STATE 21:19 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW3_MAP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW2_MAP_STATE 18:16 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW2_MAP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW1_MAP_STATE 13:11 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW1_MAP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW0_MAP_STATE 10:8 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CW0_MAP_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_SDI_STATE 5:3 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_SDI_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CAD_STATE 2:0 /* R-IVF */
#define NV_HDACODEC_AUDIO_DEBUG_REG4_CAD_STATE_INIT 0x00000000 /* R-I-V */
#define NV_HDACODEC_BITCLK_GATED_FORCE 0x0010ef80 /* RWI4R */
#define NV_HDACODEC_BITCLK_GATED_FORCE_ON 0:0 /* RWIVF */
#define NV_HDACODEC_BITCLK_GATED_FORCE_ON_INIT 0x00000001 /* RWI-V */
#define NV_HDACODEC_STR_FRAME_BOUNDARY 0x0010ef84 /* RWI4R */
#define NV_HDACODEC_STR_FRAME_BOUNDARY_THRESHOLD 11:0 /* RWIVF */
#define NV_HDACODEC_STR_FRAME_BOUNDARY_THRESHOLD_INIT 0x000008C9 /* RWI-V */
#endif // __ga102_dev_hdacodec_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_host_h__
#define __ga102_dev_host_h__
/* This file is autogenerated. Do not edit */
#define NV_PJTAG 0x0000CBFF:0x0000C800 /* RW--D */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK 0x0000C840 /* RWI4R */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIUF */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIUF */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pjtag_access" /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F/* RWI-V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008/* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIUF */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIUF */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIUF */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIUF */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIUF */
#define NV_PJTAG_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK 0x0000C848 /* RWI4R */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_PJTAG_ACCESS_CTRL 0x0000C800 /* RW-4R */
#define NV_PJTAG_ACCESS_CTRL_INSTR_ID 7:0 /* RW-UF */
#define NV_PJTAG_ACCESS_CTRL_REG_LENGTH 18:8 /* RW-UF */
#define NV_PJTAG_ACCESS_CTRL_DWORD_EN 24:19 /* RW-UF */
#define NV_PJTAG_ACCESS_CTRL_CLUSTER_SEL 29:25 /* RW-UF */
#define NV_PJTAG_ACCESS_CTRL_CTRL_STATUS 30:30 /* RW-UF */
#define NV_PJTAG_ACCESS_CTRL_REQ_CTRL 31:31 /* RW-UF */
#define NV_PJTAG_ACCESS_DATA 0x0000C804 /* RW-4R */
#define NV_PJTAG_ACCESS_DATA_VALUE 31:0 /* RW-UF */
#define NV_PJTAG_ACCESS_MASK 0x0000C80C /* RW-4R */
#define NV_PJTAG_ACCESS_MASK_VALUE 31:0 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG 0x0000C808 /* RW-4R */
#define NV_PJTAG_ACCESS_CONFIG_REG_LENGTH 7:0 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_DWORD_EN 15:8 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_BURST 16:16 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_READ_WRITE 17:17 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_LAST_CLUSTER_INV 18:18 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_SPARE 19:19 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_UPDT_DIS 20:20 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_CAPT_DIS 21:21 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_CLUSTER_SEL 24:22 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_SHFT_DIS 25:25 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_AUTO_DWORD_INCR 26:26 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_BURST_WRITE 27:27 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG_SPARE_BITS 31:28 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG2 0x0000C810 /* RW-4R */
#define NV_PJTAG_ACCESS_CONFIG2_PIPELINE_SHFT_DIS 0:0 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG2_FLIP_BITS 1:1 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG2_PAUSE_CYCLES 4:2 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG2_SPARE_BITS 28:5 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG2_HOST_CONTROL_ERROR 29:29 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG2_BURST_READ_WARNING 30:30 /* RW-UF */
#define NV_PJTAG_ACCESS_CONFIG2_BURST_READ_ERROR 31:31 /* RW-UF */
#define NV_PJTAG_ACCESS_CTRL__PRIV_LEVEL_MASK 0x0000C840 /* */
#define NV_PJTAG_ACCESS_DATA__PRIV_LEVEL_MASK 0x0000C840 /* */
#define NV_PJTAG_ACCESS_MASK__PRIV_LEVEL_MASK 0x0000C840 /* */
#define NV_PJTAG_ACCESS_CONFIG__PRIV_LEVEL_MASK 0x0000C840 /* */
#define NV_PJTAG_ACCESS_CONFIG2__PRIV_LEVEL_MASK 0x0000C840 /* */
#define NV_PJTAG_ACCESS_SEC 0x0000C844 /* RWI4R */
#define NV_PJTAG_ACCESS_SEC__PRIV_LEVEL_MASK 0x0000C848 /* */
#define NV_PJTAG_ACCESS_SEC_SHA2_EN 0:0 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_SHA2_EN_DISABLED 0x0 /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_SHA2_EN_ENABLED 0x1 /* RW--V */
#define NV_PJTAG_ACCESS_SEC_MODE 4:4 /* R-IUF */
#define NV_PJTAG_ACCESS_SEC_MODE_ISM_ONLY 0x1 /* R-I-V */
#define NV_PJTAG_ACCESS_SEC_MODE_STANDARD 0x0 /* R---V */
#define NV_PJTAG_ACCESS_SEC_SWITCH_TO_ISM_ONLY 5:5 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_SWITCH_TO_ISM_ONLY_REQ 0x1 /* -W--T */
#define NV_PJTAG_ACCESS_SEC_SWITCH_TO_ISM_ONLY_IDLE 0x0 /* RWI-V */
#define NV_PJTAG_ACCESS_SEC_SWITCH_TO_STANDARD 6:6 /* RWIUF */
#define NV_PJTAG_ACCESS_SEC_SWITCH_TO_STANDARD_REQ 0x1 /* -W--T */
#define NV_PJTAG_ACCESS_SEC_SWITCH_TO_STANDARD_IDLE 0x0 /* RWI-V */
#endif // __ga102_dev_host_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_i2cs_h__
#define __ga102_dev_i2cs_h__
/* This file is autogenerated. Do not edit */
#define NV_NVI2CS_SENSOR_00 0x00000000 /* R-I1R */
#define NV_NVI2CS_SENSOR_00_RLTS 7:0 /* R-IUF */
#define NV_NVI2CS_SENSOR_00_RLTS_MIN 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_00_RLTS_MAX 0x000000ff /* R---V */
#define NV_NVI2CS_SENSOR_01 0x00000001 /* R-I1R */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_0 0:0 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_0_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_0_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_1 1:1 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_1_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_1_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_2 2:2 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_2_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_2_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_3 3:3 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_3_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_3_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_4 4:4 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_4_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_4_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_5 5:5 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_5_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_5_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_6 6:6 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_6_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_6_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_7 7:7 /* R-IVF */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_7_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_01_RSL_THERMAL_7_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_02 0x00000002 /* R-I1R */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_8 0:0 /* R-IVF */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_8_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_8_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_9 1:1 /* R-IVF */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_9_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_9_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_10 2:2 /* R-IVF */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_10_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_10_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_11 3:3 /* R-IVF */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_11_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_02_RSL_THERMAL_11_PENDING 0x00000001 /* R---V */
#define NV_NVI2CS_SENSOR_03 0x00000003 /* RWI1R */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_0_EN 0:0 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_0_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_0_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_1_EN 1:1 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_1_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_1_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_2_EN 2:2 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_2_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_2_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_3_EN 3:3 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_3_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_3_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_4_EN 4:4 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_4_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_4_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_5_EN 5:5 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_5_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_5_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_6_EN 6:6 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_6_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_6_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_7_EN 7:7 /* RWIVF */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_7_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_03_RCL_THERMAL_7_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_04 0x00000004 /* RWI1R */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_8_EN 0:0 /* RWIVF */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_8_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_8_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_9_EN 1:1 /* RWIVF */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_9_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_9_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_10_EN 2:2 /* RWIVF */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_10_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_10_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_11_EN 3:3 /* RWIVF */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_11_EN_NO 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_04_RCL_THERMAL_11_EN_YES 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_05 0x00000005 /* RWI1R */
#define NV_NVI2CS_SENSOR_05_THERMAL_0 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_05_THERMAL_0_INIT 0x0000006e /* RWI-V */
#define NV_NVI2CS_SENSOR_06 0x00000006 /* RWI1R */
#define NV_NVI2CS_SENSOR_06_THERMAL_1 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_06_THERMAL_1_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_07 0x00000007 /* RWI1R */
#define NV_NVI2CS_SENSOR_07_THERMAL_2 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_07_THERMAL_2_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_08 0x00000008 /* RWI1R */
#define NV_NVI2CS_SENSOR_08_THERMAL_3 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_08_THERMAL_3_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_09 0x00000009 /* RWI1R */
#define NV_NVI2CS_SENSOR_09_THERMAL_4 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_09_THERMAL_4_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_0A 0x0000000A /* RWI1R */
#define NV_NVI2CS_SENSOR_0A_THERMAL_5 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_0A_THERMAL_5_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_0B 0x0000000B /* RWI1R */
#define NV_NVI2CS_SENSOR_0B_THERMAL_6 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_0B_THERMAL_6_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_0C 0x0000000C /* RWI1R */
#define NV_NVI2CS_SENSOR_0C_THERMAL_7 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_0C_THERMAL_7_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_0D 0x0000000D /* RWI1R */
#define NV_NVI2CS_SENSOR_0D_THERMAL_8 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_0D_THERMAL_8_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_0E 0x0000000E /* RWI1R */
#define NV_NVI2CS_SENSOR_0E_THERMAL_9 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_0E_THERMAL_9_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_0F 0x0000000F /* RWI1R */
#define NV_NVI2CS_SENSOR_0F_THERMAL_10 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_0F_THERMAL_10_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_10 0x00000010 /* RWI1R */
#define NV_NVI2CS_SENSOR_10_THERMAL_11 7:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_10_THERMAL_11_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_11 0x00000011 /* R-I1R */
#define NV_NVI2CS_SENSOR_11_RIET 7:7 /* R-IUF */
#define NV_NVI2CS_SENSOR_11_RIET_INIT 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_13 0x00000013 /* R-I1R */
#define NV_NVI2CS_SENSOR_13_UNCLAMPED_TEMP 7:0 /* R-IUF */
#define NV_NVI2CS_SENSOR_13_UNCLAMPED_TEMP_INIT 0x00000000 /* R-I-V */
#define NV_NVI2CS_SENSOR_14 0x00000014 /* C--1R */
#define NV_NVI2CS_SENSOR_14_NEG_TEMP_OFFSET 7:0 /* C--UF */
#define NV_NVI2CS_SENSOR_14_NEG_TEMP_OFFSET_INIT 0x00000040 /* C---V */
#define NV_NVI2CS_SENSOR_22 0x00000022 /* RWI1R */
#define NV_NVI2CS_SENSOR_22_SLEEP_CTRL 0:0 /* RWIUF */
#define NV_NVI2CS_SENSOR_22_SLEEP_CTRL_ALLOW_SLEEP 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_22_SLEEP_CTRL_FORCE_WAKE 0x00000001 /* RW--V */
#define NV_NVI2CS_SENSOR_32 0x00000032 /* RWI1R */
#define NV_NVI2CS_SENSOR_32_TSCFG0 7:0 /* RWIVF */
#define NV_NVI2CS_SENSOR_32_TSCFG0_INIT 0x0000009D /* RWI-V */
#define NV_NVI2CS_SENSOR_33 0x00000033 /* RWI1R */
#define NV_NVI2CS_SENSOR_33_TSCFG1 7:0 /* RWIVF */
#define NV_NVI2CS_SENSOR_33_TSCFG1_INIT 0x0000005D /* RWI-V */
#define NV_NVI2CS_SENSOR_34 0x00000034 /* RWI1R */
#define NV_NVI2CS_SENSOR_34_TSCFG2 7:0 /* RWIVF */
#define NV_NVI2CS_SENSOR_34_TSCFG2_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SENSOR_35 0x00000035 /* RWI1R */
#define NV_NVI2CS_SENSOR_35_TSCFG3 7:0 /* RWIVF */
#define NV_NVI2CS_SENSOR_35_TSCFG3_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_GPUID_INT_REV 0x00000060 /* R--1R */
#define NV_NVI2CS_GPUID_INT_REV_MINOR_REV 3:0 /* R-XVF */
#define NV_NVI2CS_GPUID_INT_REV_MAJOR_REV 7:4 /* R-XVF */
#define NV_NVI2CS_GPUID_EXT_REV 0x00000061 /* R--1R */
#define NV_NVI2CS_GPUID_EXT_REV_FIB_REV 3:0 /* R-XVF */
#define NV_NVI2CS_GPUID_EXT_REV_MASK_REV 7:4 /* R-XVF */
#define NV_NVI2CS_GPUID_VENDOR_ID_L 0x00000062 /* R-I1R */
#define NV_NVI2CS_GPUID_VENDOR_ID_L_VENDOR_ID 7:0 /* R-IVF */
#define NV_NVI2CS_GPUID_VENDOR_ID_L_VENDOR_ID_INIT 0x000000DE /* R-I-V */
#define NV_NVI2CS_GPUID_VENDOR_ID_H 0x00000063 /* R-I1R */
#define NV_NVI2CS_GPUID_VENDOR_ID_H_VENDOR_ID 7:0 /* R-IVF */
#define NV_NVI2CS_GPUID_VENDOR_ID_H_VENDOR_ID_INIT 0x00000010 /* R-I-V */
#define NV_NVI2CS_GPUID_DEVICE_ID(i) (0x00000064+(i)*1) /* R--1A */
#define NV_NVI2CS_GPUID_DEVICE_ID__SIZE_1 2 /* */
#define NV_NVI2CS_GPUID_DEVICE_ID_DATA_BYTE0 7:0 /* R-XVF */
#define NV_NVI2CS_GPUID_DEVICE_ID_DATA_BYTE1 7:0 /* R-XVF */
#define NV_NVI2CS_GPUID_SUB_VENDOR_ID(i) (0x00000066+(i)*1) /* R--1A */
#define NV_NVI2CS_GPUID_SUB_VENDOR_ID__SIZE_1 2 /* */
#define NV_NVI2CS_GPUID_SUB_VENDOR_ID_DATA_BYTE0 7:0 /* R-XVF */
#define NV_NVI2CS_GPUID_SUB_VENDOR_ID_DATA_BYTE1 7:0 /* R-XVF */
#define NV_NVI2CS_GPUID_SUB_DEVICE_ID(i) (0x00000068+(i)*1) /* R--1A */
#define NV_NVI2CS_GPUID_SUB_DEVICE_ID__SIZE_1 2 /* */
#define NV_NVI2CS_GPUID_SUB_DEVICE_ID_DATA_BYTE0 7:0 /* R-XVF */
#define NV_NVI2CS_GPUID_SUB_DEVICE_ID_DATA_BYTE1 7:0 /* R-XVF */
#define NV_NVI2CS_GPUID_FOUNDRY_ID 0x0000006A /* R-I1R */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID 2:0 /* C-IVF */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_INIT 5/* C-I-V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_TSMC 0x00000000 /* C---V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_UMC 0x00000001 /* C---V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_IBM 0x00000002 /* C---V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_SMIC 0x00000003 /* C---V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_CHARTERED 0x00000004 /* C---V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_SAMSUNG 0x00000005 /* C---V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_SONY 0x00000006 /* C---V */
#define NV_NVI2CS_GPUID_FOUNDRY_ID_FOUNDRY_ID_TOSHIBA 0x00000007 /* C---V */
#define NV_NVI2CS_GPUID_FAB_ID 0x0000006B /* R--1R */
#define NV_NVI2CS_GPUID_FAB_ID_FAB_ID 1:0 /* R-XVF */
#define NV_NVI2CS_GPUID_MINOR_EXT_REV_ID 0x0000006C /* R--1R */
#define NV_NVI2CS_GPUID_MINOR_EXT_REV_ID_MINOR_EXT_REV_ID 3:0 /* R-XVF */
#define NV_NVI2CS_SENSOR_FD 0x000000FD /* R-I1R */
#define NV_NVI2CS_SENSOR_FD_VENDOR_ID 7:0 /* R-IVF */
#define NV_NVI2CS_SENSOR_FD_VENDOR_ID_INIT 0x00000010 /* R-I-V */
#define NV_NVI2CS_SENSOR_FE 0x000000FE /* R-I1R */
#define NV_NVI2CS_SENSOR_FE_VENDOR_ID 7:0 /* R-IVF */
#define NV_NVI2CS_SENSOR_FE_VENDOR_ID_INIT 0x000000DE /* R-I-V */
#define NV_NVI2CS_SENSOR_FF 0x000000FF /* R-I1R */
#define NV_NVI2CS_SENSOR_FF_REV_ID 7:0 /* R-IVF */
#define NV_NVI2CS_SENSOR_FF_REV_ID_INIT 0x00000001 /* R-I-V */
#define NV_NVI2CS_BAR0_ADDR_BYTE(i) (0x00000040+(i)*1) /* RWI1A */
#define NV_NVI2CS_BAR0_ADDR_BYTE__SIZE_1 4 /* */
#define NV_NVI2CS_BAR0_ADDR_BYTE_ADDR 7:0 /* RWIUF */
#define NV_NVI2CS_BAR0_ADDR_BYTE_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_BAR0_ADDR_WORD 0x00000050 /* RWI4R */
#define NV_NVI2CS_BAR0_ADDR_WORD_ADDR 31:0 /* RWIUF */
#define NV_NVI2CS_BAR0_ADDR_WORD_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_BAR0_WDAT_BYTE(i) (0x00000044+(i)*1) /* -WI1A */
#define NV_NVI2CS_BAR0_WDAT_BYTE__SIZE_1 4 /* */
#define NV_NVI2CS_BAR0_WDAT_BYTE_WDATA 7:0 /* -WIUF */
#define NV_NVI2CS_BAR0_WDAT_BYTE_WDATA_INIT 0x00000000 /* -WI-V */
#define NV_NVI2CS_BAR0_WDAT_WORD 0x00000054 /* -WI4R */
#define NV_NVI2CS_BAR0_WDAT_WORD_WDATA 31:0 /* -WIUF */
#define NV_NVI2CS_BAR0_WDAT_WORD_WDATA_INIT 0x00000000 /* -WI-V */
#define NV_NVI2CS_BAR0_RDAT_BYTE(i) (0x00000044+(i)*1) /* R-I1A */
#define NV_NVI2CS_BAR0_RDAT_BYTE__SIZE_1 4 /* */
#define NV_NVI2CS_BAR0_RDAT_BYTE_RDATA 7:0 /* R-IUF */
#define NV_NVI2CS_BAR0_RDAT_BYTE_RDATA_INIT 0x00000000 /* R-I-V */
#define NV_NVI2CS_BAR0_RDAT_WORD 0x00000054 /* R-I4R */
#define NV_NVI2CS_BAR0_RDAT_WORD_RDATA 31:0 /* R-IUF */
#define NV_NVI2CS_BAR0_RDAT_WORD_RDATA_INIT 0x00000000 /* R-I-V */
#define NV_NVI2CS_BAR0_CSR 0x00000048 /* RWI1R */
#define NV_NVI2CS_BAR0_CSR_WRBE 3:0 /* RWIVF */
#define NV_NVI2CS_BAR0_CSR_WRBE_NO_BYTES 0x00000000 /* RWI-V */
#define NV_NVI2CS_BAR0_CSR_WRBE_ALL_BYTES 0x0000000f /* RW--V */
#define NV_NVI2CS_BAR0_CSR_TYPE 4:4 /* RWIVF */
#define NV_NVI2CS_BAR0_CSR_TYPE_WRITE 0x00000000 /* RWI-V */
#define NV_NVI2CS_BAR0_CSR_TYPE_READ 0x00000001 /* RW--V */
#define NV_NVI2CS_BAR0_CSR_REQ 7:7 /* R-IVF */
#define NV_NVI2CS_BAR0_CSR_REQ_IN_PROG 0x00000000 /* R---V */
#define NV_NVI2CS_BAR0_CSR_REQ_DONE 0x00000001 /* R-I-V */
#define NV_NVI2CS_BAR0_PASSWORD(i) (0x0000004c+(i)*1) /* -W-1A */
#define NV_NVI2CS_BAR0_PASSWORD__SIZE_1 4 /* */
#define NV_NVI2CS_BAR0_PASSWORD_ENABLE 7:0 /* -W-VF */
#define NV_NVI2CS_BAR0_PASSWORD_ENABLE_LOCK 0x00000000 /* -W--V */
#define NV_NVI2CS_BAR0_PASSWORD_ENABLE_UNLOCK_BYTE0 0x00000068 /* -W--V */
#define NV_NVI2CS_BAR0_PASSWORD_ENABLE_UNLOCK_BYTE1 0x00000074 /* -W--V */
#define NV_NVI2CS_BAR0_PASSWORD_ENABLE_UNLOCK_BYTE2 0x00000076 /* -W--V */
#define NV_NVI2CS_BAR0_PASSWORD_ENABLE_UNLOCK_BYTE3 0x0000006e /* -W--V */
#define NV_NVI2CS_SCRATCH_BYTE(i) (0x000000F8+(i)*1) /* RWI1A */
#define NV_NVI2CS_SCRATCH_BYTE__SIZE_1 4 /* */
#define NV_NVI2CS_SCRATCH_BYTE_DATA 7:0 /* RWIVF */
#define NV_NVI2CS_SCRATCH_BYTE_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_SCRATCH_WORD 0x0000005B /* RWI4R */
#define NV_NVI2CS_SCRATCH_WORD_DATA 31:0 /* RWIVF */
#define NV_NVI2CS_SCRATCH_WORD_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_COMMAND_BYTE(i) (0x00000070+(i)*1) /* RWI1A */
#define NV_NVI2CS_MSGBOX_COMMAND_BYTE__SIZE_1 4 /* */
#define NV_NVI2CS_MSGBOX_COMMAND_BYTE_DATA 7:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_COMMAND_BYTE_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_COMMAND_BYTE_INTR 7:7 /* RWIVF */
#define NV_NVI2CS_MSGBOX_COMMAND_BYTE_INTR_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_COMMAND_BYTE_INTR_PENDING 0x00000001 /* RW--V */
#define NV_NVI2CS_MSGBOX_COMMAND_WORD 0x0000005C /* RWI4R */
#define NV_NVI2CS_MSGBOX_COMMAND_WORD_DATA 30:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_COMMAND_WORD_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_COMMAND_WORD_INTR 31:31 /* RWIVF */
#define NV_NVI2CS_MSGBOX_COMMAND_WORD_INTR_NOT_PENDING 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_COMMAND_WORD_INTR_PENDING 0x00000001 /* RW--V */
#define NV_NVI2CS_MSGBOX_DATA_IN_BYTE(i) (0x00000074+(i)*1) /* RWI1A */
#define NV_NVI2CS_MSGBOX_DATA_IN_BYTE__SIZE_1 4 /* */
#define NV_NVI2CS_MSGBOX_DATA_IN_BYTE_DATA 7:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_DATA_IN_BYTE_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_DATA_IN_WORD 0x0000005D /* RWI4R */
#define NV_NVI2CS_MSGBOX_DATA_IN_WORD_DATA 31:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_DATA_IN_WORD_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_DATA_OUT_BYTE(i) (0x00000078+(i)*1) /* RWI1A */
#define NV_NVI2CS_MSGBOX_DATA_OUT_BYTE__SIZE_1 4 /* */
#define NV_NVI2CS_MSGBOX_DATA_OUT_BYTE_DATA 7:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_DATA_OUT_BYTE_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_DATA_OUT_WORD 0x0000005E /* RWI4R */
#define NV_NVI2CS_MSGBOX_DATA_OUT_WORD_DATA 31:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_DATA_OUT_WORD_DATA_INIT 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_MUTEX_BYTE 0x0000007C /* RWI1R */
#define NV_NVI2CS_MSGBOX_MUTEX_BYTE_CLIENT 7:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_MUTEX_BYTE_CLIENT_NONE 0x00000000 /* RWI-V */
#define NV_NVI2CS_MSGBOX_MUTEX_WORD 0x0000005F /* RWI4R */
#define NV_NVI2CS_MSGBOX_MUTEX_WORD_CLIENT 7:0 /* RWIVF */
#define NV_NVI2CS_MSGBOX_MUTEX_WORD_CLIENT_NONE 0x00000000 /* RWI-V */
#endif // __ga102_dev_i2cs_h__

65
include/ampere/ga102/dev_imp.h Normal file
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@@ -0,0 +1,65 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_imp_h__
#define __ga102_dev_imp_h__
/* This file is autogenerated. Do not edit */
#define NV_MCLK_MHZ_CUTOFF0 1000
#define NV_MCLK_MHZ_HBM_CUTOFF0 1050
#define NV_MCLK_MHZ_CUTOFF__SIZE1 2
#define NV_PFB_HBM_RT_LAT_DRAMCLK_COMPONENT_R0 118
#define NV_PFB_HBM_RT_LAT_NANOSEC_COMPONENT_R0 68
#define NV_PFB_RT_LAT_LTCCLK_COMPONENT_R0 131
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R0 131
#define NV_PFB_GDDR5X_RT_LAT_LTCCLK_COMPONENT_R0 131
#define NV_PFB_GDDR5_RT_LAT_LTCCLK_COMPONENT_R0 131
#define NV_PFB_HBM_RT_LAT_DRAMCLK_COMPONENT_R1 125
#define NV_PFB_HBM_RT_LAT_NANOSEC_COMPONENT_R1 68
#define NV_PFB_RT_LAT_LTCCLK_COMPONENT_R1 1458
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R1 1458
#define NV_PFB_GDDR5X_RT_LAT_LTCCLK_COMPONENT_R1 1158
#define NV_PFB_GDDR5_RT_LAT_LTCCLK_COMPONENT_R1 866
#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_R0 486
#define NV_PFB_GDDR5_RT_LAT_NANOSEC_COMPONENT_R0 564
#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_R0 682
#define NV_PFB_GDDR5X_RT_LAT_NANOSEC_COMPONENT_R0 540
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R0 1434
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R0 62
#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_R1 652
#define NV_PFB_GDDR5_RT_LAT_NANOSEC_COMPONENT_R1 690
#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_R1 944
#define NV_PFB_GDDR5X_RT_LAT_NANOSEC_COMPONENT_R1 708
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R1 1152
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R1 62
#define NV_PFB_SDDR3_RT_LAT_DRAMCLK_COMPONENT_R0 488
#define NV_PFB_SDDR3_RT_LAT_NANOSEC_COMPONENT_R0 634
#define NV_PFB_SDDR3_RT_LAT_DRAMCLK_COMPONENT_R1 488
#define NV_PFB_SDDR3_RT_LAT_NANOSEC_COMPONENT_R1 634
#define NV_PFB_HUBCLKS 104
#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE 250 // 250 cycles per CRC replay
#define NV_PFB_GDDR5_MAX_CRC_REPLAYS 2 // 2 CRC replays
#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE 250 // 250 cycles per CRC replay
#define NV_PFB_GDDR5X_MAX_CRC_REPLAYS 2 // 2 CRC replays
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE 250 // 250 cycles per CRC replay
#define NV_PFB_GDDR6_MAX_CRC_REPLAYS 2 // 2 CRC replays
#define NV_PFB_RT_LAT_XBARCLK_COMPONENT 159
#define NV_PFB_RT_LAT_SYSCLK_COMPONENT 64
#define NV_MCLK_MHZ_CUTOFF0_B 600
#define NV_MCLK_MHZ_CUTOFF1_B 1000
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R0_B 123
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R0_B 2139
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R0_B 62
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R1_B 123
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R1_B 2995
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R1_B 62
#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R2_B 123
#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R2_B 6828
#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R2_B 60
#endif // __ga102_dev_imp_h__

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include/ampere/ga102/dev_ist_seq_slv.h Normal file
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@@ -0,0 +1,308 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_ist_seq_slv_h__
#define __ga102_dev_ist_seq_slv_h__
/* This file is autogenerated. Do not edit */
#define NV_IST_SEQ_SLV 0x1C53FF:0x1C5000 /* RW--D */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK 0x1C5000 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ist_disable_debug_features" /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x00000008 /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCK 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWER 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCK 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWER 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK 0x1C5064 /* RW-4R */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCK 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWER 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCK 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWER 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWD-V */
#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK 0x1C5100 /* RW-4R */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCK 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWER 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCK 0x00000001 /* RWD-V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWER 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWD-V */
#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0 0x1C5004 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0_PRE_IST_MODE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0_PRE_IST_MODE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0 0x1C5008 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0_MASK_0 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0_MASK_0_INIT 0x00000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0 0x1C500C /* RW-4R */
#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0_VAL 5:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0_VAL_INIT 0x00000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0 0x1C5010 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0_MASK_2 15:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0_MASK_2_INIT 0x00000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0 0x1C5014 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0 0x1C5018 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0 0x1C502c /* RW-4R */
#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0_IST_LINK_CTRL_SEL 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0_IST_LINK_CTRL_SEL_INIT 0x00000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0 0x1C5030 /* R--4R */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_IST_MODE 0:0 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_IST_MODE_INIT 0x0 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_EXP_PATT_RD_SUCCESS 1:1 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_EXP_PATT_RD_SUCCESS_INIT 0x0 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_WR_READ_SUCCESS 2:2 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_WR_READ_SUCCESS_INIT 0x0 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0 0x1C5034 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0_COUNTER_VAL_INIT 0x6146580 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0 0x1C5038 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0 0x1C503c /* RW-4R */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0__PRIV_LEVEL_MASK 0x1C5064 /* */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0_START_DWORD_NO 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0_START_DWORD_NO_INIT 0x00000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0 0x1C5040 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0__PRIV_LEVEL_MASK 0x1C5064 /* */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_WRITE_ENABLE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_WRITE_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_READ_ENABLE 1:1 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_READ_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0 0x1C5044 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0__PRIV_LEVEL_MASK 0x1C5064 /* */
#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0_WRITE_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0_WRITE_VAL_INIT 0x00000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0 0x1C5048 /* R--4R */
#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0__PRIV_LEVEL_MASK 0x1C5064 /* */
#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0_READ_VAL 31:0 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0_READ_VAL_INIT 0x00000000 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0 0x1C504c /* R--4R */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0__PRIV_LEVEL_MASK 0x1C5064 /* */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_DONE 0:0 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_DONE_INIT 0x0 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_READ_DONE 1:1 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_READ_DONE_INIT 0x0 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_READ_OVERFLOW 2:2 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_READ_OVERFLOW_INIT 0x0 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0 0x1C5050 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0__PRIV_LEVEL_MASK 0x1C5064 /* */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0_NO_OF_DWORDS 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0_NO_OF_DWORDS_INIT 0x0000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0 0x1C5054 /* R--4R */
#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0__PRIV_LEVEL_MASK 0x1C5064 /* */
#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0_DWORD_NO 31:0 /* R-DUF */
#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0_DWORD_NO_INIT 0x0000000 /* R-D-V */
#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0 0x1C5058 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0_ENABLE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0 0x1C5060 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0_ENABLE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0 0x1C5068 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0 0x1C506c /* RW-4R */
#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0_FORCE_PRGM 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0_FORCE_PRGM_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0 0x1C5070 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0__PRIV_LEVEL_MASK 0x1C5100 /* */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0_START_ADDRESS 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0_START_ADDRESS_INIT 0x0000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0 0x1C5074 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0_COUNTER_VAL_INIT 0x608F3D00 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0 0x1C5078 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL 15:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL_INIT 0x1770 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0 0x1C507c /* RW-4R */
#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL 15:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL_INIT 0x1770 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_DGPU_IST_0 0x1C5080 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_DGPU_IST_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_DGPU_IST_0_DGPU_IST_ENABLED 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_DGPU_IST_0_DGPU_IST_ENABLED_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0 0x1C5084 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0_RAND_LFSR_ENABLE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0_RAND_LFSR_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0 0x1C5088 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0_SEED_VAL 15:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0_SEED_VAL_INIT 0x6f41 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0 0x1C508c /* RW-4R */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_ENABLE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_TRIGGER 1:1 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_TRIGGER_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0 0x1C5090 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0__PRIV_LEVEL_MASK 0x1C5100 /* */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0_START_ADDRESS 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0_START_ADDRESS_INIT 0x0000000 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0 0x1C5094 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_ENABLE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_SPARE 1:1 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_SPARE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0 0x1C5098 /* RW-4R */
#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0_COUNTER_VAL 31:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0_COUNTER_VAL_INIT 0x00000032 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0 0x1C509c /* RW-4R */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0__PRIV_LEVEL_MASK 0x1C5000 /* */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_ENABLE 0:0 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_MATHS_MODE_GATING_ENABLE 1:1 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_MATHS_MODE_GATING_ENABLE_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_0 2:2 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_0_INIT 0x0 /* RWD-V */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_1 3:3 /* RWDUF */
#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_1_INIT 0x0 /* RWD-V */
#endif // __ga102_dev_ist_seq_slv_h__

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@@ -0,0 +1,510 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_master_h__
#define __ga102_dev_master_h__
/* This file is autogenerated. Do not edit */
#define NV_PMC 0x00000fff:0x00000000 /* RW--D */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_BOOT_0_ID 31:0 /* */
#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */
#define NV_PMC_BOOT_0_MINOR_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_10 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_11 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_12 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_13 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_14 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_15 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_INIT 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */
#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_INIT 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_RESERVED_0 11:8 /* */
#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */
#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_INIT 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV10 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV20 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV30 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV40 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV50 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV60 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV70 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV80 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_G80 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV90 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_G90 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_NV100 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_G100 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GF100 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GF110 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GK100 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GK110 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GK200 0x00000010 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GM000 0x00000011 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GM100 0x00000011 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GM200 0x00000012 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GP100 0x00000013 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GV100 0x00000014 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 0x00000015 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU100 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU110 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_LR10 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 0x00000017 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_G000 0x0000001E /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_AMODEL 0x0000001F /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_INIT 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY 31:29 /* R--VF */
#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_UMC 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_IBM 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_SMIC 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_CHARTERED 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_SEC 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_SONY 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_TOSHIBA 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_FOUNDRY_INIT 5 /* R---V */
#define NV_PMC_BOOT_1 0x00000004 /* C--4R */
#define NV_PMC_BOOT_1_VGPU8 8:8 /* C--VF */
#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* C---V */
#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* ----V */
#define NV_PMC_BOOT_1_VGPU16 16:16 /* */
#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* */
#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* */
#define NV_PMC_BOOT_1_VGPU 17:16 /* C--VF */
#define NV_PMC_BOOT_1_VGPU_REAL 0x00000000 /* C---V */
#define NV_PMC_BOOT_1_VGPU_PV 0x00000001 /* ----V */
#define NV_PMC_BOOT_1_VGPU_VF 0x00000002 /* ----V */
#define NV_PMC_BOOT_2 0x00000008 /* R--4R */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION 3:0 /* R-XVF */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_2_FAB_ID 7:4 /* R-XVF */
#define NV_PMC_BOOT_2_FAB_ID_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_2_FAB_ID_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_2_FAB_ID_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_2_FAB_ID_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_2_EMULATION 31:31 /* R-XVF */
#define NV_PMC_BOOT_2_EMULATION_NO 0x00000000 /* R---V */
#define NV_PMC_BOOT_2_EMULATION_YES 0x00000001 /* R---V */
#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
#define NV_PMC_BOOT_42_MINOR_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_10 0x0000000A /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_11 0x0000000B /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_12 0x0000000C /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_13 0x0000000D /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_14 0x0000000E /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_15 0x0000000F /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
#define NV_PMC_BOOT_42_MAJOR_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_0 0x00000000 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_1 0x00000001 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_2 0x00000002 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_3 0x00000003 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_4 0x00000004 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_5 0x00000005 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_6 0x00000006 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_7 0x00000007 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_8 0x00000008 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_9 0x00000009 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_A 0x0000000A /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_B 0x0000000B /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_C 0x0000000C /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_D 0x0000000D /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_E 0x0000000E /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_F 0x0000000F /* */
#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV10 0x00000001 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV20 0x00000002 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV30 0x00000003 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV40 0x00000004 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV50 0x00000005 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV60 0x00000006 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV70 0x00000007 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV80 0x00000008 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_G80 0x00000008 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV90 0x00000009 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_G90 0x00000009 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_NV100 0x0000000A /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_G100 0x0000000A /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GF100 0x0000000C /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GF110 0x0000000D /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GK100 0x0000000E /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GK110 0x0000000F /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GK200 0x00000010 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GM000 0x00000011 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GM100 0x00000011 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GM200 0x00000012 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GP100 0x00000013 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV100 0x00000014 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV110 0x00000015 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_TU100 0x00000016 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_LR10 0x00000016 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_G000 0x0000001E /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_AMODEL 0x0000001F /* */
#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
#define NV_PMC_BOOT_42_CHIP_ID_G94 0x00000094 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_G98 0x00000098 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GT200 0x000000A0 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GT206 0x000000A6 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_IGT206 0x000000A7 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GT212 0x000000A2 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_IGT209 0x000000A9 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GT214 0x000000A4 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GT215 0x000000A3 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GT216 0x000000A5 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GT218 0x000000A8 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF100 0x000000C0 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF104 0x000000C4 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF105 0x000000C5 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF106 0x000000C3 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF108 0x000000C1 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF110 0x000000D0 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF110D 0x000000C6 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF110F 0x000000C7 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF112 0x000000D2 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF114 0x000000D4 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF116 0x000000D6 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF117 0x000000D7 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF118 0x000000D8 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF119 0x000000D9 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GF11A 0x000000CA /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK100 0x000000E0 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK104 0x000000E4 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK106 0x000000E6 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK107 0x000000E7 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK110 0x000000F0 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK20A 0x000000EA /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK207 0x00000107 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK208 0x00000108 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GK209 0x00000109 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM000 0x00000110 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM107 0x00000117 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM108 0x00000118 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM109 0x00000119 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM20C 0x0000011C /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM20B 0x0000012B /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM20D 0x0000012D /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM104 0x00000114 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM204 0x00000124 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM206 0x00000126 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GM200 0x00000120 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP000 0x00000131 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP100 0x00000130 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP102 0x00000132 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP104 0x00000134 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP104V 0x00000139 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP106 0x00000136 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP107F 0x00000133 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP107 0x00000137 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP108 0x00000138 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP108V 0x0000013A /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP10B 0x0000013B /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP10D 0x0000013D /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GV100 0x00000140 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GV000 0x00000141 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GV100F 0x0000014F /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GV10B 0x0000014B /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GV11B 0x0000015B /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU100 0x00000160 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU101 0x00000160 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_LR10 0x00000160 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU000 0x00000161 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU102 0x00000162 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU104 0x00000164 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU105 0x00000165 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU106 0x00000166 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU107 0x00000167 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU117 0x00000167 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU116 0x00000168 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA000 0x00000171 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA101 0x00000171 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA102 0x00000172 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA102F 0x0000017F /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA103 0x00000173 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA104 0x00000174 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA106 0x00000176 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA107 0x00000177 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA114 0x00000179 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_G000 0x000001E0 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_G000_SOC 0x000001E1 /* R---V */
#define NV_PMC_BOOT_42_RSVD 31:29 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK 0x00000080 /* RW-4R */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmc_host_grp0" /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLE_FUSE0 15 /* RWI-V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE_FUSE1 8 /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK 0x00000084 /* RW-4R */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_PMC_VIRTUAL_BOOT_1 0x00000090 /* C--4R */
#define NV_PMC_VIRTUAL_BOOT_1_VGPU 17:16 /* C--VF */
#define NV_PMC_VIRTUAL_BOOT_1_VGPU_REAL 0x00000000 /* ----V */
#define NV_PMC_VIRTUAL_BOOT_1_VGPU_PV 0x00000001 /* ----V */
#define NV_PMC_VIRTUAL_BOOT_1_VGPU_VF 0x00000002 /* C---V */
#define NV_PMC_INTR_LTC 0x000001C0 /* R--4R */
#define NV_PMC_INTR_LTC_PART_MASK 31:0 /* R--VF */
#define NV_PMC_INTR_LTC_PART_MASK_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_LTC_PART_MASK_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_LTC_PART(i) (i):(i) /* */
#define NV_PMC_INTR_LTC_PART__SIZE_1 32 /* */
#define NV_PMC_INTR_LTC_PART_NOT_PENDING 0x00000000 /* */
#define NV_PMC_INTR_LTC_PART_PENDING 0x00000001 /* */
#define NV_PMC_INTR_FBPA 0x000001D0 /* R--4R */
#define NV_PMC_INTR_FBPA_PART_MASK 29:0 /* R--VF */
#define NV_PMC_INTR_FBPA_PART_MASK_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_FBPA_PART_MASK_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL 30:30 /* R--VF */
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL 31:31 /* R--VF */
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_NOT_PENDING 0x00000000 /* R---V */
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_PENDING 0x00000001 /* R---V */
#define NV_PMC_INTR_FBPA_PART(i) (i):(i) /* */
#define NV_PMC_INTR_FBPA_PART__SIZE_1 30 /* */
#define NV_PMC_INTR_FBPA_PART_NOT_PENDING 0x00000000 /* */
#define NV_PMC_INTR_FBPA_PART_PENDING 0x00000001 /* */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PWR 13:13 /* */
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVLINK 25:25 /* RWIVF */
#define NV_PMC_ENABLE_NVLINK_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_NVLINK_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_ZPW 26:26 /* RWIVF */
#define NV_PMC_ENABLE_ZPW_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_ZPW_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_ENABLE_SEC 1:1 /* */
#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_NVDEC 15:15 /* */
#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
#define NV_PMC_ELPG_ENABLE 0x0000020C /* RW-4R */
#define NV_PMC_ELPG_ENABLE__PRIV_LEVEL_MASK 0x00000080 /* */
#define NV_PMC_ELPG_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ELPG_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ELPG_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ELPG_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ELPG_ENABLE_XBAR 2:2 /* RWIVF */
#define NV_PMC_ELPG_ENABLE_XBAR_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ELPG_ENABLE_XBAR_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ELPG_ENABLE_L2 3:3 /* RWIVF */
#define NV_PMC_ELPG_ENABLE_L2_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ELPG_ENABLE_L2_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ELPG_ENABLE_HUB 29:29 /* RWIVF */
#define NV_PMC_ELPG_ENABLE_HUB_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ELPG_ENABLE_HUB_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS 31:0 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_STATUS_DISABLE_ALL 0x00000000 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT(i) (i):(i) /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT__SIZE_1 26 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
#define NV_PMC_DEVICE_ELPG_ENABLE(i) (0x000000700+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ELPG_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ELPG_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS 31:0 /* RWIVF */
#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_ENABLE_ALL 0xFFFFFFFF /* RWI-V */
#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT(i) (i):(i) /* */
#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT__SIZE_1 26 /* */
#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
#define NV_PMC_PRI_PMC_CG1 0x00000800 /* RW-4R */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PMC_PRI_PMC_CG1_SLCG 1:1 /* RWIVF */
#define NV_PMC_PRI_PMC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PMC_PRI_PMC_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_PMC_PRI_PMC_CG1_SLCG__PROD 0x00000001 /* RW--V */
#endif // __ga102_dev_master_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_mmu_h__
#define __ga102_dev_mmu_h__
/* This file is autogenerated. Do not edit */
#define NV_MMU_PDE /* ----G */
#define NV_MMU_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */
#define NV_MMU_PDE_SIZE_FULL 0x00000000 /* RW--V */
#define NV_MMU_PDE_SIZE_HALF 0x00000001 /* RW--V */
#define NV_MMU_PDE_SIZE_QUARTER 0x00000002 /* RW--V */
#define NV_MMU_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */
#define NV_MMU_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */
#define NV_MMU_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */
#define NV_MMU_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */
#define NV_MMU_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PDE__SIZE 8
#define NV_MMU_PTE /* ----G */
#define NV_MMU_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */
#define NV_MMU_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */
#define NV_MMU_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */
#define NV_MMU_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */
#define NV_MMU_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */
#define NV_MMU_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
#define NV_MMU_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_PTE_LOCK (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PTE_LOCK_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_LOCK_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE (1*32+30):(1*32+30) /* RWXVF */
#define NV_MMU_PTE_READ_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_READ_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE (1*32+31):(1*32+31) /* RWXVF */
#define NV_MMU_PTE_WRITE_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_PTE_WRITE_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_PTE__SIZE 8
#define NV_MMU_PTE_COMPTAGS_NONE 0x0 /* */
#define NV_MMU_PTE_COMPTAGS_1 0x1 /* */
#define NV_MMU_PTE_COMPTAGS_2 0x2 /* */
#define NV_MMU_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */
#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x06 /* R---V */
#define NV_MMU_PTE_KIND_Z16 0x01 /* R---V */
#define NV_MMU_PTE_KIND_S8 0x02 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24 0x03 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8 0x04 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8 0x05 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x08 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x09 /* R---V */
#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0x0A /* R---V */
#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0x0B /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0x0C /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0x0D /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0x0E /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0x0F /* R---V */
#define NV_MMU_PTE_KIND_Z16_2C 0x2a /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS2_2C 0x11 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS4_2C 0xC3 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS8_2C 0x46 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS16_2C 0x6c /* R---V */
#define NV_MMU_PTE_KIND_Z16_2Z 0x6b /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS2_2Z 0x10 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS4_2Z 0x60 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS8_2Z 0x61 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS16_2Z 0x62 /* R---V */
#define NV_MMU_PTE_KIND_Z16_2CZ 0x36 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS2_2CZ 0x37 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS4_2CZ 0x38 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS8_2CZ 0x39 /* R---V */
#define NV_MMU_PTE_KIND_Z16_MS16_2CZ 0x5f /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_1Z 0x12 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS2_1Z 0x13 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS4_1Z 0x14 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS8_1Z 0x15 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS16_1Z 0x16 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_2CZ 0x17 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS2_2CZ 0x18 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS4_2CZ 0x19 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS8_2CZ 0x1a /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS16_2CZ 0x1b /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_2CS 0x1c /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS2_2CS 0x1d /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS4_2CS 0x1e /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS8_2CS 0x1f /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS16_2CS 0x20 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_4CSZV 0x21 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS2_4CSZV 0x22 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS4_4CSZV 0x23 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS8_4CSZV 0x24 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_MS16_4CSZV 0x25 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12 0x26 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4 0x27 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8 0x28 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24 0x29 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_1ZV 0x2e /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_1ZV 0x2f /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_1ZV 0x30 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_1ZV 0x31 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CS 0x32 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CS 0x33 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CS 0x34 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CS 0x35 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2CZV 0x3a /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2CZV 0x3b /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2CZV 0x3c /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2CZV 0x3d /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_2ZV 0x3e /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_2ZV 0x3f /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_2ZV 0x40 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_2ZV 0x41 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC12_4CSZV 0x42 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS4_VC4_4CSZV 0x43 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC8_4CSZV 0x44 /* R---V */
#define NV_MMU_PTE_KIND_V8Z24_MS8_VC24_4CSZV 0x45 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_1Z 0x47 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS2_1Z 0x48 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS4_1Z 0x49 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS8_1Z 0x4a /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS16_1Z 0x4b /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_2CS 0x4c /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS2_2CS 0x4d /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS4_2CS 0x4e /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS8_2CS 0x4f /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS16_2CS 0x50 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_2CZ 0x51 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS2_2CZ 0x52 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS4_2CZ 0x53 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS8_2CZ 0x54 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS16_2CZ 0x55 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_4CSZV 0x56 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS2_4CSZV 0x57 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS4_4CSZV 0x58 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS8_4CSZV 0x59 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_MS16_4CSZV 0x5a /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12 0x5b /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4 0x5c /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8 0x5d /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24 0x5e /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_1ZV 0x63 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_1ZV 0x64 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_1ZV 0x65 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_1ZV 0x66 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CS 0x67 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CS 0x68 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CS 0x69 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CS 0x6a /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2CZV 0x6f /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2CZV 0x70 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2CZV 0x71 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2CZV 0x72 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_2ZV 0x73 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_2ZV 0x74 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_2ZV 0x75 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_2ZV 0x76 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC12_4CSZV 0x77 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS4_VC4_4CSZV 0x78 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC8_4CSZV 0x79 /* R---V */
#define NV_MMU_PTE_KIND_Z24V8_MS8_VC24_4CSZV 0x7a /* R---V */
#define NV_MMU_PTE_KIND_ZF32 0x7b /* R---V */
#define NV_MMU_PTE_KIND_ZF32_1Z 0x7c /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS2_1Z 0x7d /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS4_1Z 0x7e /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS8_1Z 0x7f /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS16_1Z 0x80 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_2CS 0x81 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS2_2CS 0x82 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS4_2CS 0x83 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS8_2CS 0x84 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS16_2CS 0x85 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_2CZ 0x86 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS2_2CZ 0x87 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS4_2CZ 0x88 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS8_2CZ 0x89 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_MS16_2CZ 0x8a /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12 0x8b /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4 0x8c /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8 0x8d /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24 0x8e /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CS 0x8f /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CS 0x90 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CS 0x91 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CS 0x92 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1ZV 0x97 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1ZV 0x98 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1ZV 0x99 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1ZV 0x9a /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_1CZV 0x9b /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_1CZV 0x9c /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_1CZV 0x9d /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_1CZV 0x9e /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CS 0x9f /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CS 0xa0 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CS 0xa1 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CS 0xa2 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC12_2CSZV 0xa3 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS4_VC4_2CSZV 0xa4 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC8_2CSZV 0xa5 /* R---V */
#define NV_MMU_PTE_KIND_X8Z24_X16V8S8_MS8_VC24_2CSZV 0xa6 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12 0xa7 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4 0xa8 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8 0xa9 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24 0xaa /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CS 0xab /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CS 0xac /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CS 0xad /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CS 0xae /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1ZV 0xb3 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1ZV 0xb4 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1ZV 0xb5 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1ZV 0xb6 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_1CZV 0xb7 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_1CZV 0xb8 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_1CZV 0xb9 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_1CZV 0xba /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CS 0xbb /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CS 0xbc /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CS 0xbd /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CS 0xbe /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC12_2CSZV 0xbf /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS4_VC4_2CSZV 0xc0 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC8_2CSZV 0xc1 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X16V8S8_MS8_VC24_2CSZV 0xc2 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_1CS 0xc4 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_1CS 0xc5 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_1CS 0xc6 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_1CS 0xc7 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_1CS 0xc8 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_2CSZV 0xce /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CSZV 0xcf /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CSZV 0xd0 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CSZV 0xd1 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CSZV 0xd2 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_2CS 0xd3 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS2_2CS 0xd4 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS4_2CS 0xd5 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS8_2CS 0xd6 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_MS16_2CS 0xd7 /* R---V */
#define NV_MMU_PTE_KIND_S8_2S 0x2b /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_16BX2 0xfe /* R---V */
#define NV_MMU_PTE_KIND_C32_2C 0xd8 /* R---V */
#define NV_MMU_PTE_KIND_C32_2CBR 0xd9 /* R---V */
#define NV_MMU_PTE_KIND_C32_2CBA 0xda /* R---V */
#define NV_MMU_PTE_KIND_C32_2CRA 0xdb /* R---V */
#define NV_MMU_PTE_KIND_C32_2BRA 0xdc /* R---V */
#define NV_MMU_PTE_KIND_C32_MS2_2C 0xdd /* R---V */
#define NV_MMU_PTE_KIND_C32_MS2_2CBR 0xde /* R---V */
#define NV_MMU_PTE_KIND_C32_MS2_4CBRA 0xcc /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2C 0xdf /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2CBR 0xe0 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2CBA 0xe1 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2CRA 0xe2 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_2BRA 0xe3 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS4_4CBRA 0x2c /* R---V */
#define NV_MMU_PTE_KIND_C32_MS8_MS16_2C 0xe4 /* R---V */
#define NV_MMU_PTE_KIND_C32_MS8_MS16_2CRA 0xe5 /* R---V */
#define NV_MMU_PTE_KIND_C64_2C 0xe6 /* R---V */
#define NV_MMU_PTE_KIND_C64_2CBR 0xe7 /* R---V */
#define NV_MMU_PTE_KIND_C64_2CBA 0xe8 /* R---V */
#define NV_MMU_PTE_KIND_C64_2CRA 0xe9 /* R---V */
#define NV_MMU_PTE_KIND_C64_2BRA 0xea /* R---V */
#define NV_MMU_PTE_KIND_C64_MS2_2C 0xeb /* R---V */
#define NV_MMU_PTE_KIND_C64_MS2_2CBR 0xec /* R---V */
#define NV_MMU_PTE_KIND_C64_MS2_4CBRA 0xcd /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2C 0xed /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2CBR 0xee /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2CBA 0xef /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2CRA 0xf0 /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_2BRA 0xf1 /* R---V */
#define NV_MMU_PTE_KIND_C64_MS4_4CBRA 0x2d /* R---V */
#define NV_MMU_PTE_KIND_C64_MS8_MS16_2C 0xf2 /* R---V */
#define NV_MMU_PTE_KIND_C64_MS8_MS16_2CRA 0xf3 /* R---V */
#define NV_MMU_PTE_KIND_C128_2C 0xf4 /* R---V */
#define NV_MMU_PTE_KIND_C128_2CR 0xf5 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS2_2C 0xf6 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS2_2CR 0xf7 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS4_2C 0xf8 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS4_2CR 0xf9 /* R---V */
#define NV_MMU_PTE_KIND_C128_MS8_MS16_2C 0xfa /* R---V */
#define NV_MMU_PTE_KIND_C128_MS8_MS16_2CR 0xfb /* R---V */
#define NV_MMU_PTE_KIND_X8C24 0xfc /* R---V */
#define NV_MMU_PTE_KIND_PITCH_NO_SWIZZLE 0xfd /* R---V */
#define NV_MMU_PTE_KIND_SMHOST_MESSAGE 0xcb /* R---V */
#define NV_MMU_VER1_PDE /* ----G */
#define NV_MMU_VER1_PDE_APERTURE_BIG (0*32+1):(0*32+0) /* RWXVF */
#define NV_MMU_VER1_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER1_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER1_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER1_PDE_SIZE (0*32+3):(0*32+2) /* RWXVF */
#define NV_MMU_VER1_PDE_SIZE_FULL 0x00000000 /* RW--V */
#define NV_MMU_VER1_PDE_SIZE_HALF 0x00000001 /* RW--V */
#define NV_MMU_VER1_PDE_SIZE_QUARTER 0x00000002 /* RW--V */
#define NV_MMU_VER1_PDE_SIZE_EIGHTH 0x00000003 /* RW--V */
#define NV_MMU_VER1_PDE_ADDRESS_BIG_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_VER1_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_VER1_PDE_APERTURE_SMALL (1*32+1):(1*32+0) /* RWXVF */
#define NV_MMU_VER1_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER1_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER1_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER1_PDE_VOL_SMALL (1*32+2):(1*32+2) /* RWXVF */
#define NV_MMU_VER1_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_VER1_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_VER1_PDE_VOL_BIG (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_VER1_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_VER1_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_VER1_PDE_ADDRESS_SMALL_SYS (1*32+31):(1*32+4) /* RWXVF */
#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID (1*32+31-3):(1*32+4) /* RWXVF */
#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER (1*32+31):(1*32+32-3) /* RWXVF */
#define NV_MMU_VER1_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_VER1_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER1_PDE__SIZE 8
#define NV_MMU_VER1_PTE /* ----G */
#define NV_MMU_VER1_PTE_VALID (0*32+0):(0*32+0) /* RWXVF */
#define NV_MMU_VER1_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER1_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER1_PTE_PRIVILEGE (0*32+1):(0*32+1) /* RWXVF */
#define NV_MMU_VER1_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER1_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER1_PTE_READ_ONLY (0*32+2):(0*32+2) /* RWXVF */
#define NV_MMU_VER1_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_VER1_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_VER1_PTE_ENCRYPTED (0*32+3):(0*32+3) /* RWXVF */
#define NV_MMU_VER1_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_VER1_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_VER1_PTE_ADDRESS_SYS (0*32+31):(0*32+4) /* RWXVF */
#define NV_MMU_VER1_PTE_ADDRESS_VID (0*32+31-3):(0*32+4) /* RWXVF */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER (0*32+31):(0*32+32-3) /* RWXVF */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_VER1_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_VER1_PTE_VOL (1*32+0):(1*32+0) /* RWXVF */
#define NV_MMU_VER1_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_VER1_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_VER1_PTE_APERTURE (1*32+2):(1*32+1) /* RWXVF */
#define NV_MMU_VER1_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_VER1_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER1_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER1_PTE_ATOMIC_DISABLE (1*32+3):(1*32+3) /* RWXVF */
#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER1_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER1_PTE_COMPTAGLINE (1*32+20+11):(1*32+12) /* RWXVF */
#define NV_MMU_VER1_PTE_KIND (1*32+11):(1*32+4) /* RWXVF */
#define NV_MMU_VER1_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER1_PTE__SIZE 8
#define NV_MMU_VER1_PTE_COMPTAGS_NONE 0x0 /* */
#define NV_MMU_VER1_PTE_COMPTAGS_1 0x1 /* */
#define NV_MMU_VER1_PTE_COMPTAGS_2 0x2 /* */
#define NV_MMU_NEW_PDE /* ----G */
#define NV_MMU_NEW_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_NEW_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_PDE_IS_PDE 0:0 /* RWXVF */
#define NV_MMU_NEW_PDE_IS_PDE_TRUE 0x0 /* RW--V */
#define NV_MMU_NEW_PDE_IS_PDE_FALSE 0x1 /* RW--V */
#define NV_MMU_NEW_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_NEW_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_PDE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_NEW_PDE_APERTURE_INVALID 0x00000000 /* RW--V */
#define NV_MMU_NEW_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_NEW_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_NEW_PDE_VOL 3:3 /* RWXVF */
#define NV_MMU_NEW_PDE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_NEW_PDE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_NEW_PDE_NO_ATS 5:5 /* RWXVF */
#define NV_MMU_NEW_PDE_NO_ATS_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_PDE_NO_ATS_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_PDE_ADDRESS_SYS 53:8 /* RWXVF */
#define NV_MMU_NEW_PDE_ADDRESS_VID (35-3):8 /* RWXVF */
#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */
#define NV_MMU_NEW_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_NEW_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_NEW_PDE__SIZE 8
#define NV_MMU_NEW_DUAL_PDE /* ----G */
#define NV_MMU_NEW_DUAL_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_IS_PDE 0:0 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_NO_ATS 5:5 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_NEW_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */
#define NV_MMU_NEW_DUAL_PDE__SIZE 16
#define NV_MMU_NEW_PTE /* ----G */
#define NV_MMU_NEW_PTE_VALID 0:0 /* RWXVF */
#define NV_MMU_NEW_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_PTE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_NEW_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_NEW_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_NEW_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_NEW_PTE_VOL 3:3 /* RWXVF */
#define NV_MMU_NEW_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_NEW_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_NEW_PTE_ENCRYPTED 4:4 /* RWXVF */
#define NV_MMU_NEW_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_NEW_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_NEW_PTE_PRIVILEGE 5:5 /* RWXVF */
#define NV_MMU_NEW_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_PTE_READ_ONLY 6:6 /* RWXVF */
#define NV_MMU_NEW_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */
#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_NEW_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_SYS 53:8 /* RWXVF */
#define NV_MMU_NEW_PTE_ADDRESS_VID (35-3):8 /* RWXVF */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_NEW_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_NEW_PTE_COMPTAGLINE (20+35):36 /* RWXVF */
#define NV_MMU_NEW_PTE_KIND 63:56 /* RWXVF */
#define NV_MMU_NEW_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_NEW_PTE__SIZE 8
#define NV_MMU_VER2_PDE /* ----G */
#define NV_MMU_VER2_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_VER2_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_PDE_IS_PDE 0:0 /* RWXVF */
#define NV_MMU_VER2_PDE_IS_PDE_TRUE 0x0 /* RW--V */
#define NV_MMU_VER2_PDE_IS_PDE_FALSE 0x1 /* RW--V */
#define NV_MMU_VER2_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER2_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_PDE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_VER2_PDE_APERTURE_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER2_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER2_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER2_PDE_VOL 3:3 /* RWXVF */
#define NV_MMU_VER2_PDE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_VER2_PDE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_VER2_PDE_NO_ATS 5:5 /* RWXVF */
#define NV_MMU_VER2_PDE_NO_ATS_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_PDE_NO_ATS_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_PDE_ADDRESS_SYS 53:8 /* RWXVF */
#define NV_MMU_VER2_PDE_ADDRESS_VID (35-3):8 /* RWXVF */
#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */
#define NV_MMU_VER2_PDE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_VER2_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER2_PDE__SIZE 8
#define NV_MMU_VER2_DUAL_PDE /* ----G */
#define NV_MMU_VER2_DUAL_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_IS_PDE 0:0 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_VOL_BIG 3:3 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_TRUE 0x00000001 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_VOL_BIG_FALSE 0x00000000 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_NO_ATS 5:5 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_NO_ATS_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_NO_ATS_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SYS 53:(8-4) /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID (35-3):(8-4) /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER 35:(36-3) /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL 67:67 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_VOL_SMALL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_SYS 117:72 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID (99-3):72 /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER 99:(100-3) /* RWXVF */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SMALL_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER2_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */
#define NV_MMU_VER2_DUAL_PDE__SIZE 16
#define NV_MMU_VER2_PTE /* ----G */
#define NV_MMU_VER2_PTE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER2_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_PTE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_VER2_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_VER2_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER2_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER2_PTE_VOL 3:3 /* RWXVF */
#define NV_MMU_VER2_PTE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_MMU_VER2_PTE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_MMU_VER2_PTE_ENCRYPTED 4:4 /* RWXVF */
#define NV_MMU_VER2_PTE_ENCRYPTED_TRUE 0x00000001 /* R---V */
#define NV_MMU_VER2_PTE_ENCRYPTED_FALSE 0x00000000 /* R---V */
#define NV_MMU_VER2_PTE_PRIVILEGE 5:5 /* RWXVF */
#define NV_MMU_VER2_PTE_PRIVILEGE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_PTE_PRIVILEGE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_PTE_READ_ONLY 6:6 /* RWXVF */
#define NV_MMU_VER2_PTE_READ_ONLY_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_PTE_READ_ONLY_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_PTE_ATOMIC_DISABLE 7:7 /* RWXVF */
#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER2_PTE_ATOMIC_DISABLE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_SYS 53:8 /* RWXVF */
#define NV_MMU_VER2_PTE_ADDRESS_VID (35-3):8 /* RWXVF */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER 35:(36-3) /* RWXVF */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_0 0x00000000 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_1 0x00000001 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_2 0x00000002 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_3 0x00000003 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_4 0x00000004 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_5 0x00000005 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_6 0x00000006 /* RW--V */
#define NV_MMU_VER2_PTE_ADDRESS_VID_PEER_7 0x00000007 /* RW--V */
#define NV_MMU_VER2_PTE_COMPTAGLINE (20+35):36 /* RWXVF */
#define NV_MMU_VER2_PTE_KIND 63:56 /* RWXVF */
#define NV_MMU_VER2_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER2_PTE__SIZE 8
#define NV_MMU_VER3_PDE /* ----G */
#define NV_MMU_VER3_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_VER3_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_PDE_IS_PDE 0:0 /* RWXVF */
#define NV_MMU_VER3_PDE_IS_PDE_TRUE 0x0 /* RW--V */
#define NV_MMU_VER3_PDE_IS_PDE_FALSE 0x1 /* RW--V */
#define NV_MMU_VER3_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER3_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_VER3_PDE_APERTURE_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_PCF 5:3 /* RWXVF */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_PCF_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_PDE_ADDRESS 51:12 /* RWXVF */
#define NV_MMU_VER3_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER3_PDE__SIZE 8
#define NV_MMU_VER3_DUAL_PDE /* ----G */
#define NV_MMU_VER3_DUAL_PDE_IS_PTE 0:0 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_IS_PTE_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_IS_PTE_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_IS_PDE 0:0 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_IS_PDE_TRUE 0x0 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_IS_PDE_FALSE 0x1 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG 2:1 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_BIG_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG 5:3 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_BIG_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG 51:8 /* RWXVF */ //(NV_MMU_VER3_DUAL_PDE_ADDR_BIG_SHIFT) /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL 66:65 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_VIDEO_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_APERTURE_SMALL_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL 69:67 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED__OR__INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_ALLOWED 0x00000000 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED__OR__SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_ALLOWED 0x00000001 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED__OR__INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_CACHED_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_INVALID_ATS_NOT_ALLOWED 0x00000002 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED__OR__SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_VALID_UNCACHED_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_PCF_SMALL_SPARSE_ATS_NOT_ALLOWED 0x00000003 /* RW--V */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SMALL 115:76 /* RWXVF */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER3_DUAL_PDE_ADDRESS_BIG_SHIFT 8 /* */
#define NV_MMU_VER3_DUAL_PDE__SIZE 16
#define NV_MMU_VER3_PTE /* ----G */
#define NV_MMU_VER3_PTE_VALID 0:0 /* RWXVF */
#define NV_MMU_VER3_PTE_VALID_TRUE 0x1 /* RW--V */
#define NV_MMU_VER3_PTE_VALID_FALSE 0x0 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE 2:1 /* RWXVF */
#define NV_MMU_VER3_PTE_APERTURE_VIDEO_MEMORY 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE_PEER_MEMORY 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_COHERENT_MEMORY 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_APERTURE_SYSTEM_NON_COHERENT_MEMORY 0x00000003 /* RW--V */
#define NV_MMU_VER3_PTE_PCF 7:3 /* RWXVF */
#define NV_MMU_VER3_PTE_PCF_INVALID 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_SPARSE 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_MAPPING_NOWHERE 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_NO_VALID_4KB_PAGE 0x00000003 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACE 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACE 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACE 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACE 0x00000008 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACE 0x00000009 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACE 0x0000000C /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACE 0x0000000D /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_CACHED_ACD 0x00000010 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_ATOMIC_UNCACHED_ACD 0x00000011 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_PRIVILEGE_RW_ATOMIC_CACHED_ACD 0x00000012 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_CACHED_ACD 0x00000018 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RW_NO_ATOMIC_UNCACHED_ACD 0x00000019 /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_CACHED_ACD 0x0000001C /* RW--V */
#define NV_MMU_VER3_PTE_PCF_REGULAR_RO_NO_ATOMIC_UNCACHED_ACD 0x0000001D /* RW--V */
#define NV_MMU_VER3_PTE_KIND 11:8 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_SYS 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_PEER 51:12 /* RWXVF */
#define NV_MMU_VER3_PTE_ADDRESS_VID 39:12 /* RWXVF */ //TODO: Do we really need this?
#define NV_MMU_VER3_PTE_PEER_ID 63:(64-3) /* RWXVF */
#define NV_MMU_VER3_PTE_PEER_ID_0 0x00000000 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_1 0x00000001 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_2 0x00000002 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_3 0x00000003 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_4 0x00000004 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_5 0x00000005 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_6 0x00000006 /* RW--V */
#define NV_MMU_VER3_PTE_PEER_ID_7 0x00000007 /* RW--V */
#define NV_MMU_VER3_PTE_ADDRESS_SHIFT 0x0000000c /* */
#define NV_MMU_VER3_PTE__SIZE 8
#define NV_MMU_CLIENT /* ----G */
#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */
#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */
#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */
#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */
#endif // __ga102_dev_mmu_h__

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include/ampere/ga102/dev_mmu_hshub_SW.h Normal file
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include/ampere/ga102/dev_nv_aza_pri.h Normal file
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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nv_aza_pri_h__
#define __ga102_dev_nv_aza_pri_h__
/* This file is autogenerated. Do not edit */
#define NV_AZA_PRI 0x001087ff:0x00108000 /* RW--D */
#define NV_AZA_PRI_GCAP 0x00108000 /* C--4R */
#define NV_AZA_PRI_GCAP_MAJ 31:24 /* C--VF */
#define NV_AZA_PRI_GCAP_MAJ_R1 0x00000001 /* C---V */
#define NV_AZA_PRI_GCAP_VMIN 23:16 /* C--VF */
#define NV_AZA_PRI_GCAP_VMIN_R0 0x00000000 /* C---V */
#define NV_AZA_PRI_GCAP_OSS 15:12 /* C--VF */
#define NV_AZA_PRI_GCAP_OSS_FOUR 0x00000004 /* C---V */
#define NV_AZA_PRI_GCAP_ISS 11:8 /* C--VF */
#define NV_AZA_PRI_GCAP_ISS_FOUR 0x00000004 /* C---V */
#define NV_AZA_PRI_GCAP_BSS 7:3 /* C--VF */
#define NV_AZA_PRI_GCAP_BSS_ZERO 0x00000000 /* C---V */
#define NV_AZA_PRI_GCAP_NSDO 2:1 /* C--VF */
#define NV_AZA_PRI_GCAP_NSDO_FOUR 0x00000002 /* C---V */
#define NV_AZA_PRI_GCAP_64BIT_OK 0:0 /* C--VF */
#define NV_AZA_PRI_GCAP_64BIT_OK_YES 0x00000001 /* C---V */
#define NV_AZA_PRI_OUTPAY 0x00108004 /* C--4R */
#define NV_AZA_PRI_OUTPAY_INPAY 22:16 /* C--VF */
#define NV_AZA_PRI_OUTPAY_INPAY_29WORDS 0x0000001d /* C---V */
#define NV_AZA_PRI_OUTPAY_OUTPAY 6:0 /* C--VF */
#define NV_AZA_PRI_OUTPAY_OUTPAY_60WORDS 0x0000003c /* C---V */
#define NV_AZA_PRI_GCTL 0x00108008 /* RW-4R */
#define NV_AZA_PRI_GCTL_UNSOL 8:8 /* RWIVF */
#define NV_AZA_PRI_GCTL_UNSOL_NOT_ACCEPTED 0x00000000 /* RWI-V */
#define NV_AZA_PRI_GCTL_UNSOL_ACCEPTED 0x00000001 /* RW--V */
#define NV_AZA_PRI_GCTL_FCNTRL 1:1 /* RWIVF */
#define NV_AZA_PRI_GCTL_FCNTRL_DONT_INITIATE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_GCTL_FCNTRL_INITIATE 0x00000001 /* RW--V */
#define NV_AZA_PRI_GCTL_CRST 0:0 /* RWIVF */
#define NV_AZA_PRI_GCTL_CRST_ASSERT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_GCTL_CRST_DEASSERT 0x00000001 /* RW--V */
#define NV_AZA_PRI_WAKEEN 0x0010800c /* RW-4R */
#define NV_AZA_PRI_WAKEEN_SDIWAKE3 19:19 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWAKE3_NOWAKE 0x00000000 /* R-I-V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE3_WAKE 0x00000001 /* R---V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE3_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_WAKEEN_SDIWAKE2 18:18 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWAKE2_NOWAKE 0x00000000 /* R-I-V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE2_WAKE 0x00000001 /* R---V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE2_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_WAKEEN_SDIWAKE1 17:17 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWAKE1_NOWAKE 0x00000000 /* R-I-V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE1_WAKE 0x00000001 /* R---V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE1_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_WAKEEN_SDIWAKE0 16:16 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWAKE0_NOWAKE 0x00000000 /* R-I-V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE0_WAKE 0x00000001 /* R---V */
#define NV_AZA_PRI_WAKEEN_SDIWAKE0_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_WAKEEN_SDIWEN3 3:3 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWEN3_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_WAKEEN_SDIWEN3_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_WAKEEN_SDIWEN2 2:2 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWEN2_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_WAKEEN_SDIWEN2_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_WAKEEN_SDIWEN1 1:1 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWEN1_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_WAKEEN_SDIWEN1_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_WAKEEN_SDIWEN0 0:0 /* RWIVF */
#define NV_AZA_PRI_WAKEEN_SDIWEN0_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_WAKEEN_SDIWEN0_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_GSTS 0x00108010 /* RW-4R */
#define NV_AZA_PRI_GSTS_FSTS 1:1 /* RWIVF */
#define NV_AZA_PRI_GSTS_FSTS_NOFLUSH 0x00000000 /* R-I-V */
#define NV_AZA_PRI_GSTS_FSTS_FLUSH 0x00000001 /* R---V */
#define NV_AZA_PRI_GSTS_FSTS_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_OUTSTRMPAY 0x00108018 /* C--4R */
#define NV_AZA_PRI_OUTSTRMPAY_INSTRMPAY 31:16 /* C--VF */
#define NV_AZA_PRI_OUTSTRMPAY_INSTRMPAY_NOLIMIT 0x00000000 /* C---V */
#define NV_AZA_PRI_OUTSTRMPAY_OUTSTRMPAY 15:0 /* C--VF */
#define NV_AZA_PRI_OUTSTRMPAY_OUTSTRMPAY_NOLIMIT 0x00000000 /* C---V */
#define NV_AZA_PRI_INTCTL 0x00108020 /* RW-4R */
#define NV_AZA_PRI_INTCTL_GIE 31:31 /* RWIVF */
#define NV_AZA_PRI_INTCTL_GIE_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_GIE_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_CIE 30:30 /* RWIVF */
#define NV_AZA_PRI_INTCTL_CIE_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_CIE_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE7 7:7 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE7_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE7_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE6 6:6 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE6_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE6_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE5 5:5 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE5_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE5_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE4 4:4 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE4_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE4_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE3 3:3 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE3_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE3_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE2 2:2 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE2_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE2_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE1 1:1 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE1_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE1_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTCTL_SIE0 0:0 /* RWIVF */
#define NV_AZA_PRI_INTCTL_SIE0_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_INTCTL_SIE0_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_INTSTS 0x00108024 /* R--4R */
#define NV_AZA_PRI_INTSTS_GIS 31:31 /* R-IVF */
#define NV_AZA_PRI_INTSTS_GIS_NO_INTR 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_GIS_INTR 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_CIS 30:30 /* R-IVF */
#define NV_AZA_PRI_INTSTS_CIS_NO_INTR 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_CIS_INTR 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS7 7:7 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS7_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS7_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS6 6:6 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS6_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS6_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS5 5:5 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS5_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS5_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS4 4:4 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS4_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS4_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS3 3:3 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS3_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS3_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS2 2:2 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS2_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS2_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS1 1:1 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS1_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS1_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_INTSTS_SIS0 0:0 /* R-IVF */
#define NV_AZA_PRI_INTSTS_SIS0_NOINT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_INTSTS_SIS0_INT 0x00000001 /* R---V */
#define NV_AZA_PRI_WALCLK 0x00108030 /* R--4R */
#define NV_AZA_PRI_WALCLK_COUNTER 31:0 /* R-IVF */
#define NV_AZA_PRI_WALCLK_COUNTER_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_SSYNC 0x00108038 /* RW-4R */
#define NV_AZA_PRI_SSYNC_SSYNC7 7:7 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC7_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC7_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_SSYNC_SSYNC6 6:6 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC6_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC6_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_SSYNC_SSYNC5 5:5 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC5_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC5_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_SSYNC_SSYNC4 4:4 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC4_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC4_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_SSYNC_SSYNC3 3:3 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC3_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC3_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_SSYNC_SSYNC2 2:2 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC2_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC2_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_SSYNC_SSYNC1 1:1 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC1_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC1_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_SSYNC_SSYNC0 0:0 /* RWIVF */
#define NV_AZA_PRI_SSYNC_SSYNC0_NOBLOCK 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SSYNC_SSYNC0_BLOCK 0x00000001 /* RW--V */
#define NV_AZA_PRI_CORBLBASE 0x00108040 /* RW-4R */
#define NV_AZA_PRI_CORBLBASE_CORBLBASE 31:7 /* RWIVF */
#define NV_AZA_PRI_CORBLBASE_CORBLBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CORBUBASE 0x00108044 /* RW-4R */
#define NV_AZA_PRI_CORBUBASE_CORBUBASE 31:0 /* RWIVF */
#define NV_AZA_PRI_CORBUBASE_CORBUBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CORBWP 0x00108048 /* RW-4R */
#define NV_AZA_PRI_CORBWP_RST 31:31 /* -WIVF */
#define NV_AZA_PRI_CORBWP_RST_INIT 0x00000000 /* --I-V */
#define NV_AZA_PRI_CORBWP_CORBRP 23:16 /* R-IVF */
#define NV_AZA_PRI_CORBWP_CORBRP_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CORBWP_CORBWP 7:0 /* RWIVF */
#define NV_AZA_PRI_CORBWP_CORBWP_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CORBCTL 0x0010804c /* RW-4R */
#define NV_AZA_PRI_CORBCTL_CORBSZCAP 23:20 /* C--VF */
#define NV_AZA_PRI_CORBCTL_CORBSZCAP_INIT 0x00000004 /* C---V */
#define NV_AZA_PRI_CORBCTL_CORBSIZE 17:16 /* C--VF */
#define NV_AZA_PRI_CORBCTL_CORBSIZE_256ENTRIES 0x00000002 /* C---V */
#define NV_AZA_PRI_CORBCTL_CMEI 8:8 /* RWIVF */
#define NV_AZA_PRI_CORBCTL_CMEI_NOERROR 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CORBCTL_CMEI_ERROR 0x00000001 /* R---V */
#define NV_AZA_PRI_CORBCTL_CMEI_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_CORBCTL_CORBRUN 1:1 /* RWIVF */
#define NV_AZA_PRI_CORBCTL_CORBRUN_STOP 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CORBCTL_CORBRUN_RUN 0x00000001 /* RW--V */
#define NV_AZA_PRI_CORBCTL_CMEIE 0:0 /* RWIVF */
#define NV_AZA_PRI_CORBCTL_CMEIE_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CORBCTL_CMEIE_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_RIRBLBASE 0x00108050 /* RW-4R */
#define NV_AZA_PRI_RIRBLBASE_RIRBLBASE 31:7 /* RWIVF */
#define NV_AZA_PRI_RIRBLBASE_RIRBLBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_RIRBUBASE 0x00108054 /* RW-4R */
#define NV_AZA_PRI_RIRBUBASE_RIRBUBASE 31:0 /* RWIVF */
#define NV_AZA_PRI_RIRBUBASE_RIRBUBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_RIRBWP 0x00108058 /* RW-4R */
#define NV_AZA_PRI_RIRBWP_RINTCNT 23:16 /* RWIVF */
#define NV_AZA_PRI_RIRBWP_RINTCNT_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_RIRBWP_RIRBWPRST 15:15 /* -WIVF */
#define NV_AZA_PRI_RIRBWP_RIRBWPRST_INIT 0x00000000 /* C---V */
#define NV_AZA_PRI_RIRBWP_RIRBWPRST_RESET_WP 0x00000001 /* -W--V */
#define NV_AZA_PRI_RIRBWP_RIRBWP 7:0 /* R-IVF */
#define NV_AZA_PRI_RIRBWP_RIRBWP_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_RIRBCTL 0x0010805c /* RW-4R */
#define NV_AZA_PRI_RIRBCTL_RIRBSZCAP 23:20 /* C--VF */
#define NV_AZA_PRI_RIRBCTL_RIRBSZCAP_INIT 0x00000004 /* C---V */
#define NV_AZA_PRI_RIRBCTL_RIRBSIZE 17:16 /* C--VF */
#define NV_AZA_PRI_RIRBCTL_RIRBSIZE_256ENTRIES 0x00000002 /* C---V */
#define NV_AZA_PRI_RIRBCTL_RIRBOIS 10:10 /* RWIVF */
#define NV_AZA_PRI_RIRBCTL_RIRBOIS_NOOVERRUN 0x00000000 /* R-I-V */
#define NV_AZA_PRI_RIRBCTL_RIRBOIS_OVERRUN 0x00000001 /* R---V */
#define NV_AZA_PRI_RIRBCTL_RIRBOIS_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_RIRBCTL_RINTFL 8:8 /* RWIVF */
#define NV_AZA_PRI_RIRBCTL_RINTFL_NORESPONSE 0x00000000 /* R-I-V */
#define NV_AZA_PRI_RIRBCTL_RINTFL_RESPONSE 0x00000001 /* R---V */
#define NV_AZA_PRI_RIRBCTL_RINTFL_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_RIRBCTL_RIRBOIC 2:2 /* RWIVF */
#define NV_AZA_PRI_RIRBCTL_RIRBOIC_NOINTR 0x00000000 /* RWI-V */
#define NV_AZA_PRI_RIRBCTL_RIRBOIC_INTR 0x00000001 /* RW--V */
#define NV_AZA_PRI_RIRBCTL_RIRBDMAEN 1:1 /* RWIVF */
#define NV_AZA_PRI_RIRBCTL_RIRBDMAEN_STOP 0x00000000 /* RWI-V */
#define NV_AZA_PRI_RIRBCTL_RIRBDMAEN_RUN 0x00000001 /* RW--V */
#define NV_AZA_PRI_RIRBCTL_RINTCTL 0:0 /* RWIVF */
#define NV_AZA_PRI_RIRBCTL_RINTCTL_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_RIRBCTL_RINTCTL_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_ICOI 0x00108060 /* -W-4R */
#define NV_AZA_PRI_ICOI_ICW 31:0 /* -WIVF */
#define NV_AZA_PRI_ICOI_ICW_INIT 0x00000000 /* -WI-V */
#define NV_AZA_PRI_IRII 0x00108064 /* R--4R */
#define NV_AZA_PRI_IRII_IRR 31:0 /* R-IVF */
#define NV_AZA_PRI_IRII_IRR_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_ICS 0x00108068 /* RW-4R */
#define NV_AZA_PRI_ICS_IRRADD 7:4 /* R-IVF */
#define NV_AZA_PRI_ICS_IRRADD_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_ICS_IRRUNSOL 3:3 /* R-IVF */
#define NV_AZA_PRI_ICS_IRRUNSOL_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_ICS_ICVER 2:2 /* R-IVF */
#define NV_AZA_PRI_ICS_ICVER_DEFAULT 0x00000001 /* R---V */
#define NV_AZA_PRI_ICS_ICVER_REV_CYA_OFF 0x00000000 /* R-I-V */
#define NV_AZA_PRI_ICS_IRV 1:1 /* RWIVF */
#define NV_AZA_PRI_ICS_IRV_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_ICS_IRV_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_ICS_ICB 0:0 /* R-IVF */
#define NV_AZA_PRI_ICS_ICB_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_DPLBASE 0x00108070 /* RW-4R */
#define NV_AZA_PRI_DPLBASE_DPLBASE 31:7 /* RWIVF */
#define NV_AZA_PRI_DPLBASE_DPLBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_DPLBASE_ENABLE 0:0 /* RWIVF */
#define NV_AZA_PRI_DPLBASE_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_DPUBASE 0x00108074 /* RW-4R */
#define NV_AZA_PRI_DPUBASE_DPUBASE 31:0 /* RWIVF */
#define NV_AZA_PRI_DPUBASE_DPUBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL(i) (0x00108080+(i)*32) /* RW-4A */
#define NV_AZA_PRI_SDCTL__SIZE_1 8 /* */
#define NV_AZA_PRI_SDCTL_FIFORDY 29:29 /* R-IVF */
#define NV_AZA_PRI_SDCTL_FIFORDY_NOTREADY 0x00000000 /* R-I-V */
#define NV_AZA_PRI_SDCTL_FIFORDY_READY 0x00000001 /* R---V */
#define NV_AZA_PRI_SDCTL_DESE 28:28 /* RWIVF */
#define NV_AZA_PRI_SDCTL_DESE_NOERROR 0x00000000 /* R-I-V */
#define NV_AZA_PRI_SDCTL_DESE_ERROR 0x00000001 /* R---V */
#define NV_AZA_PRI_SDCTL_DESE_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_SDCTL_FIFOE 27:27 /* RWIVF */
#define NV_AZA_PRI_SDCTL_FIFOE_NOERROR 0x00000000 /* R-I-V */
#define NV_AZA_PRI_SDCTL_FIFOE_ERROR 0x00000001 /* R---V */
#define NV_AZA_PRI_SDCTL_FIFOE_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_SDCTL_BCIS 26:26 /* RWIVF */
#define NV_AZA_PRI_SDCTL_BCIS_NOTCOMPLETE 0x00000000 /* R-I-V */
#define NV_AZA_PRI_SDCTL_BCIS_COMPLETE 0x00000001 /* R---V */
#define NV_AZA_PRI_SDCTL_BCIS_W1C 0x00000001 /* -W--C */
#define NV_AZA_PRI_SDCTL_STRM 23:20 /* RWIVF */
#define NV_AZA_PRI_SDCTL_STRM_UNUSED 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_DIR 19:19 /* C--VF */
#define NV_AZA_PRI_SDCTL_DIR_UNIDIR 0x00000000 /* C---V */
#define NV_AZA_PRI_SDCTL_TP 18:18 /* RWIVF */
#define NV_AZA_PRI_SDCTL_TP_LOW 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_TP_HIGH 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDCTL_STRIPE 17:16 /* RWIVF */
#define NV_AZA_PRI_SDCTL_STRIPE_1SDO 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_STRIPE_2SDO 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDCTL_STRIPE_4SDO 0x00000002 /* RW--V */
#define NV_AZA_PRI_SDCTL_DEIE 4:4 /* RWIVF */
#define NV_AZA_PRI_SDCTL_DEIE_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_DEIE_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDCTL_FEIE 3:3 /* RWIVF */
#define NV_AZA_PRI_SDCTL_FEIE_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_FEIE_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDCTL_IOCE 2:2 /* RWIVF */
#define NV_AZA_PRI_SDCTL_IOCE_DISABLE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_IOCE_ENABLE 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDCTL_RUN 1:1 /* RWIVF */
#define NV_AZA_PRI_SDCTL_RUN_STOP 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_RUN_RUN 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDCTL_SRST 0:0 /* RWIVF */
#define NV_AZA_PRI_SDCTL_SRST_NOTRESET 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDCTL_SRST_RESET 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDPICB(i) (0x00108084+(i)*32) /* R--4A */
#define NV_AZA_PRI_SDPICB__SIZE_1 8 /* */
#define NV_AZA_PRI_SDPICB_LPIB 31:0 /* R-IVF */
#define NV_AZA_PRI_SDPICB_LPIB_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_SDCBL(i) (0x00108088+(i)*32) /* RW-4A */
#define NV_AZA_PRI_SDCBL__SIZE_1 8 /* */
#define NV_AZA_PRI_SDCBL_CBL 31:0 /* RWIVF */
#define NV_AZA_PRI_SDCBL_CBL_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDLVI(i) (0x0010808c+(i)*32) /* RW-4A */
#define NV_AZA_PRI_SDLVI__SIZE_1 8 /* */
#define NV_AZA_PRI_SDLVI_LVI 7:0 /* RWIVF */
#define NV_AZA_PRI_SDLVI_LVI_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDFMT(i) (0x00108090+(i)*32) /* RW-4A */
#define NV_AZA_PRI_SDFMT__SIZE_1 8 /* */
#define NV_AZA_PRI_SDFMT_BASE 30:30 /* RWIVF */
#define NV_AZA_PRI_SDFMT_BASE_48KHZ 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDFMT_BASE_44KHZ 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDFMT_MULT 29:27 /* RWIVF */
#define NV_AZA_PRI_SDFMT_MULT_X1 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDFMT_MULT_X2 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDFMT_MULT_X3 0x00000002 /* RW--V */
#define NV_AZA_PRI_SDFMT_MULT_X4 0x00000003 /* RW--V */
#define NV_AZA_PRI_SDFMT_DIV 26:24 /* RWIVF */
#define NV_AZA_PRI_SDFMT_DIV_X1 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDFMT_DIV_X2 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDFMT_DIV_X3 0x00000002 /* RW--V */
#define NV_AZA_PRI_SDFMT_DIV_X4 0x00000003 /* RW--V */
#define NV_AZA_PRI_SDFMT_DIV_X5 0x00000004 /* RW--V */
#define NV_AZA_PRI_SDFMT_DIV_X6 0x00000005 /* RW--V */
#define NV_AZA_PRI_SDFMT_DIV_X7 0x00000006 /* RW--V */
#define NV_AZA_PRI_SDFMT_DIV_X8 0x00000007 /* RW--V */
#define NV_AZA_PRI_SDFMT_BITS 22:20 /* RWIVF */
#define NV_AZA_PRI_SDFMT_BITS_8BITS 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDFMT_BITS_16BITS 0x00000001 /* RW--V */
#define NV_AZA_PRI_SDFMT_BITS_20BITS 0x00000002 /* RW--V */
#define NV_AZA_PRI_SDFMT_BITS_24BITS 0x00000003 /* RW--V */
#define NV_AZA_PRI_SDFMT_BITS_32BITS 0x00000004 /* RW--V */
#define NV_AZA_PRI_SDFMT_CHAN 19:16 /* RWIVF */
#define NV_AZA_PRI_SDFMT_CHAN_1CHAN 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDFMT_FIFOS 15:0 /* R-IVF */
#define NV_AZA_PRI_SDFMT_FIFOS_INIT 0x00000028 /* R-I-V */
#define NV_AZA_PRI_SDBDPL(i) (0x00108098+(i)*32) /* RW-4A */
#define NV_AZA_PRI_SDBDPL__SIZE_1 8 /* */
#define NV_AZA_PRI_SDBDPL_BDLLBASE 31:7 /* RWIVF */
#define NV_AZA_PRI_SDBDPL_BDLLBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_SDBDPU(i) (0x0010809c+(i)*32) /* RW-4A */
#define NV_AZA_PRI_SDBDPU__SIZE_1 8 /* */
#define NV_AZA_PRI_SDBDPU_BDLUBASE 31:0 /* RWIVF */
#define NV_AZA_PRI_SDBDPU_BDLUBASE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT 0x00108700 /* RW-4R */
#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_PW_REQ_THREAD 4:0 /* RWIVF */
#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_PW_REQ_THREAD_INIT 0x0000000c /* RWI-V */
#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_NP_REQ_THREAD 12:8 /* RWIVF */
#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_NP_REQ_THREAD_INIT 0x0000000c /* RWI-V */
#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_RSP_THREAD 20:16 /* RWIVF */
#define NV_AZA_PRI_CYA0_XV2AZA_WR_LIMIT_RSP_THREAD_INIT 0x0000000c /* RWI-V */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME 0x00108704 /* R--4R */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR0 7:0 /* R-IVF */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR0_INIT 0x00000001 /* R-I-V */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR1 15:8 /* R-IVF */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR1_INIT 0x00000001 /* R-I-V */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR2 23:16 /* R-IVF */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR2_INIT 0x00000001 /* R-I-V */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR3 31:24 /* R-IVF */
#define NV_AZA_PRI_CYA1_STR_BYTES_PER_FRAME_STR3_INIT 0x00000001 /* R-I-V */
#define NV_AZA_PRI_CYA2_1_STR_WR_CNT 0x00108708 /* R--4R */
#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR0 14:0 /* R-IVF */
#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR0_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR1 30:16 /* R-IVF */
#define NV_AZA_PRI_CYA2_1_STR_WR_CNT_STR1_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA2_2_STR_WR_CNT 0x00108744 /* R--4R */
#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR2 14:0 /* R-IVF */
#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR2_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR3 30:16 /* R-IVF */
#define NV_AZA_PRI_CYA2_2_STR_WR_CNT_STR3_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN 0x0010870c /* RW-4R */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR0 0:0 /* RWIVF */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR0_DIS 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR0_EN 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR1 8:8 /* RWIVF */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR1_DIS 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR1_EN 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR2 16:16 /* RWIVF */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR2_DIS 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR2_EN 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR3 24:24 /* RWIVF */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR3_DIS 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA3_STR_FIFO_MONITOR_EN_STR3_EN 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR 0x00108710 /* R--4R */
#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR0 15:0 /* R-IVF */
#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR0_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR1 31:16 /* R-IVF */
#define NV_AZA_PRI_CYA4_1_STR_FIFO_MONITOR_STR1_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR 0x00108740 /* R--4R */
#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR2 15:0 /* R-IVF */
#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR2_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR3 31:16 /* R-IVF */
#define NV_AZA_PRI_CYA4_2_STR_FIFO_MONITOR_STR3_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK 0x00108714 /* RW-4R */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0 2:0 /* RWIVF */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_100_PERCENT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_88_PERCENT 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_75_PERCENT 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_63_PERCENT 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_50_PERCENT 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_38_PERCENT 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_25_PERCENT 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR0_13_PERCENT 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1 10:8 /* RWIVF */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_100_PERCENT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_88_PERCENT 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_75_PERCENT 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_63_PERCENT 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_50_PERCENT 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_38_PERCENT 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_25_PERCENT 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR1_13_PERCENT 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2 18:16 /* RWIVF */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_100_PERCENT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_88_PERCENT 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_75_PERCENT 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_63_PERCENT 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_50_PERCENT 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_38_PERCENT 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_25_PERCENT 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR2_13_PERCENT 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3 26:24 /* RWIVF */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_100_PERCENT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_88_PERCENT 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_75_PERCENT 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_63_PERCENT 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_50_PERCENT 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_38_PERCENT 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_25_PERCENT 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYA5_STR_FIFO_SHRINK_STR3_13_PERCENT 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE 0x00108718 /* RW-4R */
#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE 1:0 /* RWIVF */
#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_128BYTE 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_64BYTE 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_32BYTE 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYA6_MAX_UPSTRM_REQ_SIZE_REQ_SIZE_16BYTE 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY 0x0010871c /* RW-4R */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_THRESHOLD 11:0 /* RWIVF */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_THRESHOLD_INIT 0x000008c9 /* RWI-V */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC 16:16 /* RWIVF */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC_EN 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_AZA_SYNC_DIS 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL 17:17 /* RWIVF */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL_EN 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA7_STR_FRAME_BOUNDARY_32BIT_MN_VAL_DIS 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ 0x00108720 /* RW-4R */
#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ_FREQ 0:0 /* RWIVF */
#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ_FREQ_108MHZ 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA8_WALCLK_INPUT_FREQ_FREQ_48MHZ 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT 0x00108724 /* RW-4R */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT 5:0 /* RWIVF */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_0 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_1 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_2 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_3 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_4 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_5 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_6 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_7 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_8 0x00000008 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_9 0x00000009 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_10 0x0000000a /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_11 0x0000000b /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_12 0x0000000c /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_13 0x0000000d /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_14 0x0000000e /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_15 0x0000000f /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_16 0x00000010 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_17 0x00000011 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_18 0x00000012 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_19 0x00000013 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_20 0x00000014 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_21 0x00000015 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_22 0x00000016 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_23 0x00000017 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_24 0x00000018 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_25 0x00000019 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_26 0x0000001a /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_27 0x0000001b /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_28 0x0000001c /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_29 0x0000001d /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_30 0x0000001e /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_31 0x0000001f /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_32 0x00000020 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_33 0x00000021 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_34 0x00000022 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_35 0x00000023 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_36 0x00000024 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_37 0x00000025 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_38 0x00000026 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_39 0x00000027 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_SELECT_40 0x00000028 /* RW--V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_INT_CRST_NOCLR 7:7 /* RWIVF */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_INT_CRST_NOCLR_EN 0x00000001 /* RWI-V */
#define NV_AZA_PRI_CYA9_DEBUG_SIGNAL_SELECT_INT_CRST_NOCLR_DIS 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAA_COH 0x00108728 /* RW-4R */
#define NV_AZA_PRI_CYAA_COH_BDL 0:0 /* RWIVF */
#define NV_AZA_PRI_CYAA_COH_BDL_NONCOHERENT 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAA_COH_BDL_COHERENT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_CYAA_COH_CORB 1:1 /* RWIVF */
#define NV_AZA_PRI_CYAA_COH_CORB_NONCOHERENT 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAA_COH_CORB_COHERENT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_CYAA_COH_OSTRM 2:2 /* RWIVF */
#define NV_AZA_PRI_CYAA_COH_OSTRM_NONCOHERENT 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAA_COH_OSTRM_COHERENT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_CYAA_COH_DPIB 3:3 /* RWIVF */
#define NV_AZA_PRI_CYAA_COH_DPIB_NONCOHERENT 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAA_COH_DPIB_COHERENT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_CYAA_COH_ISTRM 4:4 /* RWIVF */
#define NV_AZA_PRI_CYAA_COH_ISTRM_NONCOHERENT 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAA_COH_ISTRM_COHERENT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_CYAA_COH_RIRB 5:5 /* RWIVF */
#define NV_AZA_PRI_CYAA_COH_RIRB_NONCOHERENT 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAA_COH_RIRB_COHERENT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_CYAB_IDLE_STRETCH 0x0010872c /* RW-4R */
#define NV_AZA_PRI_CYAB_IDLE_STRETCH_VALUE 31:0 /* RWIVF */
#define NV_AZA_PRI_CYAB_IDLE_STRETCH_VALUE_INIT 0x00000014 /* RWI-V */
#define NV_AZA_PRI_CYAC_RINTFL_DELAY 0x00108730 /* RW-4R */
#define NV_AZA_PRI_CYAC_RINTFL_DELAY_VALUE 15:0 /* RWIVF */
#define NV_AZA_PRI_CYAC_RINTFL_DELAY_VALUE_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK 0x00108748 /* RW-4R */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0 2:0 /* RWIVF */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_INIT 0x00000004 /* RWI-V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_1_FRAME 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_2_FRAMES 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_4_FRAMES 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_8_FRAMES 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_16_FRAMES 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_32_FRAMES 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_64_FRAMES 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR0_FULL 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1 10:8 /* RWIVF */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_INIT 0x00000004 /* RWI-V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_1_FRAME 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_2_FRAMES 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_4_FRAMES 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_8_FRAMES 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_16_FRAMES 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_32_FRAMES 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_64_FRAMES 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR1_FULL 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2 18:16 /* RWIVF */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_INIT 0x00000004 /* RWI-V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_1_FRAME 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_2_FRAMES 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_4_FRAMES 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_8_FRAMES 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_16_FRAMES 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_32_FRAMES 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_64_FRAMES 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR2_FULL 0x00000007 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3 26:24 /* RWIVF */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_INIT 0x00000004 /* RWI-V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_1_FRAME 0x00000000 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_2_FRAMES 0x00000001 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_4_FRAMES 0x00000002 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_8_FRAMES 0x00000003 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_16_FRAMES 0x00000004 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_32_FRAMES 0x00000005 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_64_FRAMES 0x00000006 /* RW--V */
#define NV_AZA_PRI_CYAD_STR_FIFO_WATERMARK_STR3_FULL 0x00000007 /* RW--V */
#define NV_AZA_PRI_SYNCH_BCLK_ADJ 0x00108734 /* RW-4R */
#define NV_AZA_PRI_SYNCH_BCLK_ADJ_N_VAL 15:0 /* RWIVF */
#define NV_AZA_PRI_SYNCH_BCLK_ADJ_N_VAL_INIT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_SYNCH_BCLK_ADJ_M_VAL 31:16 /* RWIVF */
#define NV_AZA_PRI_SYNCH_BCLK_ADJ_M_VAL_INIT 0x00000001 /* RWI-V */
#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS 0x00108738 /* R--4R */
#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRAME_CNT 19:0 /* R-IVF */
#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRAME_CNT_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRACT_CNT 31:20 /* R-IVF */
#define NV_AZA_PRI_SYNCH_ADJ_FRAME_POS_FRACT_CNT_INIT 0x00000002 /* R-I-V */
#define NV_AZA_PRI_STR0_FIFO_ADDR 0x00108760 /* RW-4R */
#define NV_AZA_PRI_STR0_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
#define NV_AZA_PRI_STR0_FIFO_ADDR_START_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_AZA_PRI_STR0_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
#define NV_AZA_PRI_STR0_FIFO_ADDR_END_ADDR_INIT 0x0000057f /* RWI-V */
#define NV_AZA_PRI_STR1_FIFO_ADDR 0x00108764 /* RW-4R */
#define NV_AZA_PRI_STR1_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
#define NV_AZA_PRI_STR1_FIFO_ADDR_START_ADDR_INIT 0x00000580 /* RWI-V */
#define NV_AZA_PRI_STR1_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
#define NV_AZA_PRI_STR1_FIFO_ADDR_END_ADDR_INIT 0x00000aff /* RWI-V */
#define NV_AZA_PRI_STR2_FIFO_ADDR 0x00108768 /* RW-4R */
#define NV_AZA_PRI_STR2_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
#define NV_AZA_PRI_STR2_FIFO_ADDR_START_ADDR_INIT 0x00000b00 /* RWI-V */
#define NV_AZA_PRI_STR2_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
#define NV_AZA_PRI_STR2_FIFO_ADDR_END_ADDR_INIT 0x0000107f /* RWI-V */
#define NV_AZA_PRI_STR3_FIFO_ADDR 0x0010876c /* RW-4R */
#define NV_AZA_PRI_STR3_FIFO_ADDR_START_ADDR 12:0 /* RWIVF */
#define NV_AZA_PRI_STR3_FIFO_ADDR_START_ADDR_INIT 0x00001080 /* RWI-V */
#define NV_AZA_PRI_STR3_FIFO_ADDR_END_ADDR 28:16 /* RWIVF */
#define NV_AZA_PRI_STR3_FIFO_ADDR_END_ADDR_INIT 0x000015ff /* RWI-V */
#define NV_AZA_PRI_DYNAMIC_STR_ADDR 0x00108770 /* RW-4R */
#define NV_AZA_PRI_DYNAMIC_STR_ADDR_EN 0:0 /* RWIVF */
#define NV_AZA_PRI_DYNAMIC_STR_ADDR_EN_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAE_IB_SDI0_FIFO 0x00108774 /* R--4R */
#define NV_AZA_PRI_CYAE_IB_SDI0_FIFO_WR_CNT 3:0 /* R-IVF */
#define NV_AZA_PRI_CYAE_IB_SDI0_FIFO_WR_CNT_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM 0x00108778 /* R--4R */
#define NV_AZA_PRI_CYAF_AZA_SM_SA_STATE 31:29 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_SA_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_STR3_REQ_STATE 28:27 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_STR3_REQ_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_STR2_REQ_STATE 26:25 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_STR2_REQ_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_STR1_REQ_STATE 24:23 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_STR1_REQ_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_STR0_REQ_STATE 22:21 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_STR0_REQ_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_GRANT_STATE 20:16 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_GRANT_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_DMA_STATE 14:12 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_DMA_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_OB3_BDL_STATE 11:9 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_OB3_BDL_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_OB2_BDL_STATE 8:6 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_OB2_BDL_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_OB1_BDL_STATE 5:3 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_OB1_BDL_STATE_INIT 0x00000000 /* R-I-V */
#define NV_AZA_PRI_CYAF_AZA_SM_OB0_BDL_STATE 2:0 /* R-IVF */
#define NV_AZA_PRI_CYAF_AZA_SM_OB0_BDL_STATE_INIT 0x00000000 /* R-I-V */
#endif // __ga102_dev_nv_aza_pri_h__

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include/ampere/ga102/dev_nv_p2p.h Normal file
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@@ -0,0 +1,250 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nv_p2p_h__
#define __ga102_dev_nv_p2p_h__
/* This file is autogenerated. Do not edit */
#define NV_P2P 0x0013AFFF:0x00139000 /* RW--D */
#define NV_P2P_PRIV_LEVEL_MASK 0x0013AFFC /* RW-4R */
#define NV_P2P_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
#define NV_P2P_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_P2P_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "nv_p2p_plm" /* */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
#define NV_P2P_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_P2P_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */
#define NV_P2P_WMBTAG_L(i) (0x00139040+(i)*64) /* R-I4A */
#define NV_P2P_WMBTAG_L__SIZE_1 8 /* */
#define NV_P2P_WMBTAG_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WMBTAG_L_PAGE_ADDR 20:0 /* R-IUF */
#define NV_P2P_WMBTAG_L_PAGE_ADDR_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WMBTAG_H(i) (0x00139044+(i)*64) /* RWI4A */
#define NV_P2P_WMBTAG_H__SIZE_1 8 /* */
#define NV_P2P_WMBTAG_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WMBTAG_H_KIND 7:0 /* R-IUF */
#define NV_P2P_WMBTAG_H_KIND_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WMBTAG_H_COMPTAGLINE 24:8 /* R-IUF */
#define NV_P2P_WMBTAG_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WMBTAG_H_PAGE_SIZE 25:25 /* R-IUF */
#define NV_P2P_WMBTAG_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ 26:26 /* RWIVF */
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ_ACTIVE 0x00000001 /* R---V */
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ_CLEAR 0x00000001 /* -W--C */
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE 27:27 /* RWIVF */
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE_ACTIVE 0x00000001 /* R---V */
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE_CLEAR 0x00000001 /* -W--C */
#define NV_P2P_WMB_ADDR_L(i) (0x00139048+(i)*64) /* RW-4A */
#define NV_P2P_WMB_ADDR_L__SIZE_1 8 /* */
#define NV_P2P_WMB_ADDR_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WMB_ADDR_L_ADDR 31:3 /* RWIUF */
#define NV_P2P_WMB_ADDR_L_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_WMB_ADDR_H(i) (0x0013904c+(i)*64) /* RW-4A */
#define NV_P2P_WMB_ADDR_H__SIZE_1 8 /* */
#define NV_P2P_WMB_ADDR_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WMB_ADDR_H_ADDR 31:0 /* RWIUF */
#define NV_P2P_WMB_ADDR_H_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_WMB_DATA_L(i) (0x00139050+(i)*64) /* RW-4A */
#define NV_P2P_WMB_DATA_L__SIZE_1 8 /* */
#define NV_P2P_WMB_DATA_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WMB_DATA_L_ADDR 31:16 /* RWIUF */
#define NV_P2P_WMB_DATA_L_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_WMB_DATA_H(i) (0x00139054+(i)*64) /* RW-4A */
#define NV_P2P_WMB_DATA_H__SIZE_1 8 /* */
#define NV_P2P_WMB_DATA_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WMB_DATA_H_ADDR 31:0 /* RWIUF */
#define NV_P2P_WMB_DATA_H_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RREQ_ADDR_L(i) (0x00139058+(i)*64) /* RW-4A */
#define NV_P2P_RREQ_ADDR_L__SIZE_1 8 /* */
#define NV_P2P_RREQ_ADDR_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RREQ_ADDR_L_ADDR 31:3 /* RWIUF */
#define NV_P2P_RREQ_ADDR_L_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RREQ_ADDR_H(i) (0x0013905c+(i)*64) /* RW-4A */
#define NV_P2P_RREQ_ADDR_H__SIZE_1 8 /* */
#define NV_P2P_RREQ_ADDR_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RREQ_ADDR_H_ADDR 31:0 /* RWIUF */
#define NV_P2P_RREQ_ADDR_H_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RREQ_CTRL(i) (0x00139060+(i)*64) /* RW-4A */
#define NV_P2P_RREQ_CTRL__SIZE_1 8 /* */
#define NV_P2P_RREQ_CTRL__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RREQ_CTRL_RREQ_MAX 9:0 /* RWIUF */
#define NV_P2P_RREQ_CTRL_RREQ_MAX_INIT 0x00000200 /* RWI-V */
#define NV_P2P_RREQ_CTRL_CPL_PENDING 25:16 /* R--VF */
#define NV_P2P_WMBOX_ADDR(i) (0x00139064+(i)*64) /* RW-4A */
#define NV_P2P_WMBOX_ADDR__SIZE_1 8 /* */
#define NV_P2P_WMBOX_ADDR__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WMBOX_ADDR_DIS 0:0 /* RWIUF */
#define NV_P2P_WMBOX_ADDR_DIS_DISABLED 0x00000001 /* RWI-V */
#define NV_P2P_WMBOX_ADDR_DIS_ENABLED 0x00000000 /* RW--V */
#define NV_P2P_WMBOX_ADDR_ADDR 18:1 /* RWIUF */
#define NV_P2P_WMBOX_ADDR_ADDR_INIT 0x0003ffff /* RWI-V */
#define NV_P2P_WREQMB_L(i) (0x00139068+(i)*64) /* R--4A */
#define NV_P2P_WREQMB_L__SIZE_1 8 /* */
#define NV_P2P_WREQMB_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WREQMB_L_PAGE_ADDR 20:0 /* R-IUF */
#define NV_P2P_WREQMB_L_PAGE_ADDR_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H(i) (0x0013906c+(i)*64) /* R--4A */
#define NV_P2P_WREQMB_H__SIZE_1 8 /* */
#define NV_P2P_WREQMB_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_WREQMB_H_KIND 7:0 /* R-IUF */
#define NV_P2P_WREQMB_H_KIND_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H_COMPTAGLINE 24:8 /* R-IUF */
#define NV_P2P_WREQMB_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_WREQMB_H_PAGE_SIZE 25:25 /* R-IUF */
#define NV_P2P_WREQMB_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RREQMB_L(i) (0x00139070+(i)*64) /* R--4A */
#define NV_P2P_RREQMB_L__SIZE_1 8 /* */
#define NV_P2P_RREQMB_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RREQMB_L_ADDR 31:0 /* R-IUF */
#define NV_P2P_RREQMB_L_ADDR_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RREQMB_H(i) (0x00139074+(i)*64) /* R--4A */
#define NV_P2P_RREQMB_H__SIZE_1 8 /* */
#define NV_P2P_RREQMB_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RREQMB_H_LEN 11:4 /* R-IUF */
#define NV_P2P_RREQMB_H_LEN_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RREQMB_H_COMPTAGLINE 29:13 /* R-IUF */
#define NV_P2P_RREQMB_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RREQMB_H_PAGE_SIZE 31:30 /* R-IUF */
#define NV_P2P_RREQMB_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RREQMB_0(i) (0x00139078+(i)*64) /* R--4A */
#define NV_P2P_RREQMB_0__SIZE_1 8 /* */
#define NV_P2P_RREQMB_0__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RREQMB_0_KIND 7:0 /* R-IUF */
#define NV_P2P_RREQMB_0_KIND_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RREQMB_0_NOTIFIER 8:8 /* R-IUF */
#define NV_P2P_RREQMB_0_NOTIFIER_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RREQMB_0_NOTIFIER_DATA 31:16 /* R-IUF */
#define NV_P2P_RREQMB_0_NOTIFIER_DATA_INIT 0x00000000 /* R-I-V */
#define NV_P2P_RCOMP_ADDR_L(i) (0x001392FC+(i)*64) /* RW-4A */
#define NV_P2P_RCOMP_ADDR_L__SIZE_1 8 /* */
#define NV_P2P_RCOMP_ADDR_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMP_ADDR_L_ADDR 31:7 /* RWIUF */
#define NV_P2P_RCOMP_ADDR_L_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RCOMP_ADDR_H(i) (0x00139300+(i)*64) /* RW-4A */
#define NV_P2P_RCOMP_ADDR_H__SIZE_1 8 /* */
#define NV_P2P_RCOMP_ADDR_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMP_ADDR_H_ADDR 31:0 /* RWIUF */
#define NV_P2P_RCOMP_ADDR_H_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RCOMP_LIMIT_L(i) (0x00139304+(i)*64) /* RW-4A */
#define NV_P2P_RCOMP_LIMIT_L__SIZE_1 8 /* */
#define NV_P2P_RCOMP_LIMIT_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMP_LIMIT_L_ADDR 31:0 /* RWIUF */
#define NV_P2P_RCOMP_LIMIT_L_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RCOMP_LIMIT_H(i) (0x00139308+(i)*64) /* RW-4A */
#define NV_P2P_RCOMP_LIMIT_H__SIZE_1 8 /* */
#define NV_P2P_RCOMP_LIMIT_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMP_LIMIT_H_ADDR 31:0 /* RWIUF */
#define NV_P2P_RCOMP_LIMIT_H_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RCOMP_NOTIFIER_L(i) (0x0013930c+(i)*64) /* RW-4A */
#define NV_P2P_RCOMP_NOTIFIER_L__SIZE_1 8 /* */
#define NV_P2P_RCOMP_NOTIFIER_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMP_NOTIFIER_L_ADDR 31:0 /* RWIUF */
#define NV_P2P_RCOMP_NOTIFIER_L_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_RCOMP_NOTIFIER_H(i) (0x00139310+(i)*64) /* RW-4A */
#define NV_P2P_RCOMP_NOTIFIER_H__SIZE_1 8 /* */
#define NV_P2P_RCOMP_NOTIFIER_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMP_NOTIFIER_H_ADDR 31:0 /* RWIUF */
#define NV_P2P_RCOMP_NOTIFIER_H_ADDR_INIT 0x00000000 /* RWI-V */
#define NV_P2P_CPU 0x00139500 /* RW-4R */
#define NV_P2P_CPU__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_CPU_CPU2PEER_MAP 7:0 /* RWIVF */
#define NV_P2P_CPU_CPU2PEER_MAP_INIT 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW 0x00139504 /* RW-4R */
#define NV_P2P_TRIGGER_READ_DW__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_TRIGGER_READ_DW_PEER0 1:0 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER0_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER0_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER0_DW2 0x00000002 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER1 3:2 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER1_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER1_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER1_DW2 0x00000002 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER2 5:4 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER2_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER2_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER2_DW2 0x00000002 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER3 7:6 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER3_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER3_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER3_DW2 0x00000002 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER4 9:8 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER4_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER4_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER4_DW2 0x00000002 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER5 11:10 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER5_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER5_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER5_DW2 0x00000002 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER6 13:12 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER6_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER6_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER6_DW2 0x00000002 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER7 15:14 /* RWIVF */
#define NV_P2P_TRIGGER_READ_DW_PEER7_DW0 0x00000000 /* RWI-V */
#define NV_P2P_TRIGGER_READ_DW_PEER7_DW1 0x00000001 /* RW--V */
#define NV_P2P_TRIGGER_READ_DW_PEER7_DW2 0x00000002 /* RW--V */
#define NV_P2P_RCOMPMB_0(i) (0x0013A000+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_0__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_0__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_0_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_0_VALUE_INIT 0x00000000 /* C---V */
#define NV_P2P_RCOMPMB_1(i) (0x0013A100+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_1__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_1__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_1_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_1_VALUE_INIT 0x00000000 /* C---V */
#define NV_P2P_RCOMPMB_2(i) (0x0013A200+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_2__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_2__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_2_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_2_VALUE_INIT 0x00000000 /* C---V */
#define NV_P2P_RCOMPMB_3(i) (0x0013A300+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_3__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_3__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_3_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_3_VALUE_INIT 0x00000000 /* C---V */
#define NV_P2P_RCOMPMB_4(i) (0x0013A400+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_4__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_4__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_4_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_4_VALUE_INIT 0x00000000 /* C---V */
#define NV_P2P_RCOMPMB_5(i) (0x0013A500+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_5__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_5__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_5_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_5_VALUE_INIT 0x00000000 /* C---V */
#define NV_P2P_RCOMPMB_6(i) (0x0013A600+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_6__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_6__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_6_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_6_VALUE_INIT 0x00000000 /* C---V */
#define NV_P2P_RCOMPMB_7(i) (0x0013A700+(i)*4) /* C--4A */
#define NV_P2P_RCOMPMB_7__SIZE_1 32 /* */
#define NV_P2P_RCOMPMB_7__PRIV_LEVEL_MASK 0x0013AFFC /* */
#define NV_P2P_RCOMPMB_7_VALUE 31:0 /* C--UF */
#define NV_P2P_RCOMPMB_7_VALUE_INIT 0x00000000 /* C---V */
#endif // __ga102_dev_nv_p2p_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __dev_nv_pcfg_xve_regmap_h__
#define __dev_nv_pcfg_xve_regmap_h__
/* This file is autogenerated. Do not edit */
#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000
/*
* <prefix>_MAP has 1 bit set for each dword register.
* <prefix>_COUNT has total number of set bits in <prefix>_MAP.
*/
#define NV_PCFG_XVE_REGISTER_VALID_COUNT 472
#define NV_PCFG_XVE_REGISTER_VALID_MAP { \
/* 0x00088000 */ 0xFFF1FFFF, 0x101FFF9F, \
/* 0x00088100 */ 0x3FFA3C7F, 0x00000000, \
/* 0x00088200 */ 0x03F00000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA1F, 0x00000000, \
/* 0x00088700 */ 0x00013FFF, 0x00000000, \
/* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \
/* 0x00088900 */ 0xFFFFFFFF, 0x002FFFFF, \
/* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \
/* 0x00088B00 */ 0x00000000, 0xFFFFF000, \
/* 0x00088C00 */ 0x0007BFE7, 0xFFC003FC, \
/* 0x00088D00 */ 0xFFFFFFFF, 0x7C1F3FFF, \
/* 0x00088E00 */ 0xFFFFFFFF, 0x00FFFFFF, \
/* 0x00088F00 */ 0x00000000, 0xFE000000 }
#define NV_PCFG_XVE_REGISTER_WR_COUNT 350
#define NV_PCFG_XVE_REGISTER_WR_MAP { \
/* 0x00088000 */ 0x3EF193FA, 0x1007C505, \
/* 0x00088100 */ 0x3FFA0828, 0x00000000, \
/* 0x00088200 */ 0x03200000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x80007EC0, 0x3F075007, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA10, 0x00000000, \
/* 0x00088700 */ 0x00013FFF, 0x00000000, \
/* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \
/* 0x00088900 */ 0xFFFC7804, 0x002FFFFF, \
/* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \
/* 0x00088B00 */ 0x00000000, 0xF8A54000, \
/* 0x00088C00 */ 0x00003C01, 0x3FC003FC, \
/* 0x00088D00 */ 0xFFFFFFFC, 0x701B2C3F, \
/* 0x00088E00 */ 0xFFFFFFF8, 0x00FFBFFF, \
/* 0x00088F00 */ 0x00000000, 0xFE000000 }
#endif // {__dev_nv_pcfg_xve_regmap_h__}

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nv_xve3g_fn_ppc_h__
#define __ga102_dev_nv_xve3g_fn_ppc_h__
/* This file is autogenerated. Do not edit */
#define NV_XVE_PPC 0x000001FF:0x00000000 /* RW--D */
#define NV_XVE_PPC_ID 0x00000000 /* R--4R */
#define NV_XVE_PPC_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE_PPC_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE_PPC_ID_DEVICE_CHIP 31:16 /* R-CVF */
#define NV_XVE_PPC_ID_DEVICE_CHIP_NO_USE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_ID_DEVICE_CHIP_I2C_TU102 0x00001AD7 /* R---V */
#define NV_XVE_PPC_ID_DEVICE_CHIP_I2C_TU104 0x00001AD9 /* R---V */
#define NV_XVE_PPC_ID_DEVICE_CHIP_I2C_TU106 0x00001ADB /* R---V */
#define NV_XVE_PPC_ID_DEVICE_CHIP_I2C_TU107 0x00001ADD /* R---V */
#define NV_XVE_PPC_ID_DEVICE_CHIP_I2C_TU117 0x00001ADD /* R---V */
#define NV_XVE_PPC_ID_DEVICE_CHIP_I2C_TU108 0x00001ADF /* R---V */
#define NV_XVE_PPC_ID_DEVICE_CHIP_I2C_TU116 0x00001AED /* R---V */
#define NV_XVE_PPC_DEV_CTRL 0x00000004 /* RW-4R */
#define NV_XVE_PPC_DEV_CTRL_CMD_IO_SPACE 0:0 /* R-IVF */
#define NV_XVE_PPC_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_CMD_MEMORY_SPACE 1:1 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEV_CTRL_CMD_BUS_MASTER 2:2 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_CMD_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEV_CTRL_CMD_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEV_CTRL_CMD_SPECIAL_CYCLE 3:3 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_CMD_SPECIAL_CYCLE_DISABLED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE 4:4 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE_DISABLED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_CMD_VGA_PALETTE_SNOOP 5:5 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_CMD_VGA_PALETTE_SNOOP_DISABLED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_CMD_PERR 6:6 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_CMD_PERR_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEV_CTRL_CMD_PERR_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEV_CTRL_CMD_IDSEL_STEP 7:7 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_CMD_IDSEL_STEP_DISABLED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_CMD_SERR 8:8 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_CMD_SERR_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEV_CTRL_CMD_SERR_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEV_CTRL_CMD_FAST_BACK2BACK 9:9 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_CMD_FAST_BACK2BACK_DISABLED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_CMD_INTERRUPT_DISABLE 10:10 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_CMD_INTERRUPT_DISABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_INTERRUPT 19:19 /* R-IVF */
#define NV_XVE_PPC_DEV_CTRL_STAT_INTERRUPT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_INTERRUPT_PENDING 0x00000001 /* R---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_CAPLIST 20:20 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_STAT_CAPLIST_NOT_PRESENT 0x00000000 /* ----V */
#define NV_XVE_PPC_DEV_CTRL_STAT_CAPLIST_PRESENT 0x00000001 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_66MHZ 21:21 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_STAT_66MHZ_INCAPABLE 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_66MHZ_CAPABLE 0x00000001 /* ----V */
#define NV_XVE_PPC_DEV_CTRL_STAT_FAST_BACK2BACK 23:23 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_STAT_FAST_BACK2BACK_INCAPABLE 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_FAST_BACK2BACK_CAPABLE 0x00000001 /* ----V */
#define NV_XVE_PPC_DEV_CTRL_STAT_MASTER_DATA_PERR 24:24 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_STAT_MASTER_DATA_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_MASTER_DATA_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_MASTER_DATA_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEV_CTRL_STAT_DEVSEL_TIMING 26:25 /* C--VF */
#define NV_XVE_PPC_DEV_CTRL_STAT_DEVSEL_TIMING_FAST 0x00000000 /* C---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_DEVSEL_TIMING_MEDIUM 0x00000001 /* ----V */
#define NV_XVE_PPC_DEV_CTRL_STAT_DEVSEL_TIMING_SLOW 0x00000002 /* ----V */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT 27:27 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT 28:28 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT 29:29 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_SERR 30:30 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_SERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_SERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_SIGNALED_SERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEV_CTRL_STAT_DETECTED_PERR 31:31 /* RWIVF */
#define NV_XVE_PPC_DEV_CTRL_STAT_DETECTED_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEV_CTRL_STAT_DETECTED_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_DEV_CTRL_STAT_DETECTED_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_REV_ID 0x00000008 /* C--4R */
#define NV_XVE_PPC_REV_ID_FIB 3:0 /* C--VF */
#define NV_XVE_PPC_REV_ID_FIB_ONE 0x00000001 /* C---V */
#define NV_XVE_PPC_REV_ID_FIB_TWO 0x00000002 /* ----V */
#define NV_XVE_PPC_REV_ID_MASK 7:4 /* C--VF */
#define NV_XVE_PPC_REV_ID_MASK_A 0x0000000A /* C---V */
#define NV_XVE_PPC_REV_ID_MASK_B 0x0000000B /* ----V */
#define NV_XVE_PPC_REV_ID_CLASS_CODE 31:8 /* C--VF */
#define NV_XVE_PPC_REV_ID_CLASS_CODE_I2C 0x000C8000 /* C---V */
#define NV_XVE_PPC_MISC_1 0x0000000C /* RW-4R */
#define NV_XVE_PPC_MISC_1_CACHE_LINE_SIZE 7:0 /* RWIVF */
#define NV_XVE_PPC_MISC_1_CACHE_LINE_SIZE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_MISC_1_MASTER_LATENCY_TIMER 15:8 /* C--VF */
#define NV_XVE_PPC_MISC_1_MASTER_LATENCY_TIMER_0_CLOCKS 0x00000000 /* C---V */
#define NV_XVE_PPC_MISC_1_HEADER_TYPE 23:16 /* C--VF */
#define NV_XVE_PPC_MISC_1_HEADER_TYPE_SINGLEFUNC 0x00000000 /* ----V */
#define NV_XVE_PPC_MISC_1_HEADER_TYPE_MULTIFUNC 0x00000080 /* C---V */
#define NV_XVE_PPC_MISC_1_BIST 31:24 /* C--VF */
#define NV_XVE_PPC_MISC_1_BIST_NULL 0x00000000 /* C---V */
#define NV_XVE_PPC_BAR0_LO 0x00000010 /* RW-4R */
#define NV_XVE_PPC_BAR0_LO_SPACE_TYPE 0:0 /* C--VF */
#define NV_XVE_PPC_BAR0_LO_SPACE_TYPE_MEMORY 0x00000000 /* C---V */
#define NV_XVE_PPC_BAR0_LO_SPACE_TYPE_IO 0x00000001 /* ----V */
#define NV_XVE_PPC_BAR0_LO_ADDRESS_TYPE 2:1 /* C--VF */
#define NV_XVE_PPC_BAR0_LO_ADDRESS_TYPE_32_BIT 0x00000000 /* C---V */
#define NV_XVE_PPC_BAR0_LO_ADDRESS_TYPE_20_BIT 0x00000001 /* ----V */
#define NV_XVE_PPC_BAR0_LO_ADDRESS_TYPE_64_BIT 0x00000002 /* ----V */
#define NV_XVE_PPC_BAR0_LO_PREFETCHABLE 3:3 /* C--VF */
#define NV_XVE_PPC_BAR0_LO_PREFETCHABLE_NOT 0x00000000 /* C---V */
#define NV_XVE_PPC_BAR0_LO_PREFETCHABLE_MERGABLE 0x00000001 /* ----V */
#define NV_XVE_PPC_BAR0_LO_BASE_ADDRESS 31:12 /* RWIVF */
#define NV_XVE_PPC_BAR0_LO_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_BAR0_HI 0x00000014 /* R--4R */
#define NV_XVE_PPC_BAR0_HI_BASE_ADDRESS 31:0 /* R-IVF */
#define NV_XVE_PPC_BAR0_HI_BASE_ADDRESS_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_BAR_RSVD(i) (0x00000018+(i)*4) /* C--4A */
#define NV_XVE_PPC_BAR_RSVD__SIZE_1 4 /* */
#define NV_XVE_PPC_BAR_RSVD_BITS 31:0 /* C--VF */
#define NV_XVE_PPC_BAR_RSVD_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_CARDBUS 0x00000028 /* C--4R */
#define NV_XVE_PPC_CARDBUS_PTR 31:0 /* C--VF */
#define NV_XVE_PPC_CARDBUS_PTR_0 0x00000000 /* C---V */
#define NV_XVE_PPC_SUBSYSTEM 0x0000002C /* R--4R */
#define NV_XVE_PPC_SUBSYSTEM_VENDOR_ID 15:0 /* R-CVF */
#define NV_XVE_PPC_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_SUBSYSTEM_ID_USER 19:16 /* R-CVF */
#define NV_XVE_PPC_SUBSYSTEM_ID_USER_NONE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_SUBSYSTEM_ID_NON_USER 31:20 /* R-CVF */
#define NV_XVE_PPC_SUBSYSTEM_ID_NON_USER_NONE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_ROM_RSVD 0x00000030 /* C--4R */
#define NV_XVE_PPC_ROM_RSVD_BITS 31:0 /* C--VF */
#define NV_XVE_PPC_ROM_RSVD_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_CAP_LIST 0x00000034 /* C--4R */
#define NV_XVE_PPC_CAP_LIST_CAP_PTR 7:0 /* C--VF */
#define NV_XVE_PPC_CAP_LIST_CAP_PTR_MSI 0x00000068 /* C---V */
#define NV_XVE_PPC_RSVD_0 0x00000038 /* C--4R */
#define NV_XVE_PPC_RSVD_0_BITS 31:0 /* C--VF */
#define NV_XVE_PPC_RSVD_0_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_INTR_GNT 0x0000003C /* RW-4R */
#define NV_XVE_PPC_INTR_GNT_INTR_LINE 7:0 /* RWIVF */
#define NV_XVE_PPC_INTR_GNT_INTR_LINE_IRQ0 0x00000000 /* RWI-V */
#define NV_XVE_PPC_INTR_GNT_INTR_LINE_IRQ1 0x00000001 /* RW--V */
#define NV_XVE_PPC_INTR_GNT_INTR_LINE_IRQ15 0x0000000F /* RW--V */
#define NV_XVE_PPC_INTR_GNT_INTR_LINE_UNKNOWN 0x000000FF /* RW--V */
#define NV_XVE_PPC_INTR_GNT_INTR_PIN 15:8 /* C--VF */
#define NV_XVE_PPC_INTR_GNT_INTR_PIN_INTD 0x00000004 /* C---V */
#define NV_XVE_PPC_INTR_GNT_MIN_GNT 23:16 /* C--VF */
#define NV_XVE_PPC_INTR_GNT_MIN_GNT_NO_REQUIREMENTS 0x00000000 /* C---V */
#define NV_XVE_PPC_INTR_GNT_MAX_LAT 31:24 /* C--VF */
#define NV_XVE_PPC_INTR_GNT_MAX_LAT_NO_REQUIREMENTS 0x00000000 /* C---V */
#define NV_XVE_PPC_MSI_CTRL 0x00000068 /* RW-4R */
#define NV_XVE_PPC_MSI_CTRL_RSVD 31:24 /* C--VF */
#define NV_XVE_PPC_MSI_CTRL_RSVD_0 0x00000000 /* C---V */
#define NV_XVE_PPC_MSI_CTRL_64BIT_CAP 23:23 /* C--VF */
#define NV_XVE_PPC_MSI_CTRL_64BIT_CAP_TRUE 0x00000001 /* C---V */
#define NV_XVE_PPC_MSI_CTRL_64BIT_CAP_FALSE 0x00000000 /* ----V */
#define NV_XVE_PPC_MSI_CTRL_MULT_EN 22:20 /* RWIVF */
#define NV_XVE_PPC_MSI_CTRL_MULT_EN_CODE0 0x00000000 /* RWI-V */
#define NV_XVE_PPC_MSI_CTRL_MULT_EN_CODE2 0x00000001 /* RW--V */
#define NV_XVE_PPC_MSI_CTRL_MULT_EN_CODE4 0x00000002 /* RW--V */
#define NV_XVE_PPC_MSI_CTRL_MULT_EN_CODE8 0x00000003 /* RW--V */
#define NV_XVE_PPC_MSI_CTRL_MULT_CAP 19:17 /* R-IVF */
#define NV_XVE_PPC_MSI_CTRL_MULT_CAP_CODE0 0x00000000 /* R-I-V */
#define NV_XVE_PPC_MSI_CTRL_MSI 16:16 /* RWIVF */
#define NV_XVE_PPC_MSI_CTRL_MSI_DISABLE 0x00000000 /* RWI-V */
#define NV_XVE_PPC_MSI_CTRL_MSI_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_PPC_MSI_CTRL_NEXT_PTR 15:8 /* C--VF */
#define NV_XVE_PPC_MSI_CTRL_NEXT_PTR_PCIEXP 0x00000078 /* C---V */
#define NV_XVE_PPC_MSI_CTRL_CAP_ID 7:0 /* C--VF */
#define NV_XVE_PPC_MSI_CTRL_CAP_ID_MSI 0x00000005 /* C---V */
#define NV_XVE_PPC_MSI_LOW_ADDR 0x0000006C /* RW-4R */
#define NV_XVE_PPC_MSI_LOW_ADDR_DWORD 31:2 /* RWIVF */
#define NV_XVE_PPC_MSI_LOW_ADDR_DWORD_0 0x00000000 /* RWI-V */
#define NV_XVE_PPC_MSI_LOW_ADDR_RSVD 1:0 /* C--VF */
#define NV_XVE_PPC_MSI_LOW_ADDR_RSVD_0 0x00000000 /* C---V */
#define NV_XVE_PPC_MSI_UPPER_ADDR 0x00000070 /* RW-4R */
#define NV_XVE_PPC_MSI_UPPER_ADDR_DWORD 31:0 /* RWIVF */
#define NV_XVE_PPC_MSI_UPPER_ADDR_DWORD_0 0x00000000 /* RWI-V */
#define NV_XVE_PPC_MSI_DATA 0x00000074 /* RW-4R */
#define NV_XVE_PPC_MSI_DATA_RSVD 31:16 /* R-IVF */
#define NV_XVE_PPC_MSI_DATA_RSVD_0 0x00000000 /* R-I-V */
#define NV_XVE_PPC_MSI_DATA_NON_RSVD 15:0 /* RWIVF */
#define NV_XVE_PPC_MSI_DATA_NON_RSVD_0 0x00000000 /* RWI-V */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY 0x00000078 /* R--4R */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID 7:0 /* C--VF */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID_INIT 0x00000010 /* C---V */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR 15:8 /* C--VF */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_PWR_MGMT 0x000000B4 /* C---V */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_VERSION 19:16 /* C--VF */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_VERSION_GEN1 0x00000001 /* ----V */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_VERSION_GEN2 0x00000002 /* C---V */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE 23:20 /* C--VF */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED 24:24 /* R-EVF */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED_INIT 0x00000000 /* R-E-V */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER 29:25 /* C--VF */
#define NV_XVE_PPC_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0 0x000000B4 /* R--4R */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D3_COLD 31:31 /* R-IVF */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D3_COLD_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D3_COLD_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D3_HOT 30:30 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D3_HOT_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D3_HOT_NOT_SUPPORTED 0x00000000 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D2 29:29 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D2_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D2_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D1 28:28 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D1_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D1_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D0 27:27 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D0_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_D0_NOT_SUPPORTED 0x00000000 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_D2 26:26 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_D2_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_D2_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_D1 25:25 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_D1_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_D1_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_AUX_CURRENT 24:22 /* R-CVF */
#define NV_XVE_PPC_PWR_MGMT_0_AUX_CURRENT_SELF_POWERED 0x00000000 /* R-C-V */
#define NV_XVE_PPC_PWR_MGMT_0_DSI 21:21 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_DSI_NOT_REQUIRED 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_PME_CLOCK 19:19 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_PME_CLOCK_NOT_REQUIRED 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_VERSION 18:16 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_VERSION_1 0x00000001 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_VERSION_2 0x00000002 /* ----V */
#define NV_XVE_PPC_PWR_MGMT_0_VERSION_3 0x00000003 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_NEXT_PTR 15:8 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_NEXT_PTR_NONE 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_0_CAP_ID 7:0 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_0_CAP_ID_POWER_MGMT 0x00000001 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_1 0x000000B8 /* RW-4R */
#define NV_XVE_PPC_PWR_MGMT_1_PME_DATA 31:24 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_1_PME_DATA_UNS 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_1_PME_BPCC 23:23 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_1_PME_BPCC_UNS 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_1_PME_B2B3 22:22 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_1_PME_B2B3_UNS 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_1_PME_STATUS 15:15 /* RWCVF */
#define NV_XVE_PPC_PWR_MGMT_1_PME_STATUS_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_PWR_MGMT_1_PME_STATUS_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_PWR_MGMT_1_PME_STATUS_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_PWR_MGMT_1_PME_DATA_SCALE 14:13 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_1_PME_DATA_SCALE_UNS 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_1_PME_DATA_SEL 12:9 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_1_PME_DATA_SEL_UNS 0x00000000 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_1_PME 8:8 /* RWCVF */
#define NV_XVE_PPC_PWR_MGMT_1_PME_DISABLE 0x00000000 /* RWC-V */
#define NV_XVE_PPC_PWR_MGMT_1_PME_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_PPC_PWR_MGMT_1_NO_SOFT_RESET 3:3 /* C--VF */
#define NV_XVE_PPC_PWR_MGMT_1_NO_SOFT_RESET_DISABLE 0x00000001 /* C---V */
#define NV_XVE_PPC_PWR_MGMT_1_PWR_STATE 1:0 /* RWIVF */
#define NV_XVE_PPC_PWR_MGMT_1_PWR_STATE_D0 0x00000000 /* RWI-V */
#define NV_XVE_PPC_PWR_MGMT_1_PWR_STATE_D1 0x00000001 /* RW--V */
#define NV_XVE_PPC_PWR_MGMT_1_PWR_STATE_D2 0x00000002 /* RW--V */
#define NV_XVE_PPC_PWR_MGMT_1_PWR_STATE_D3HOT 0x00000003 /* RW--V */
#define NV_XVE_PPC_DEVICE_CAPABILITY 0x0000007C /* R--4R */
#define NV_XVE_PPC_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE 2:0 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_128 0x00000000 /* ----V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_256 0x00000001 /* ----V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED 4:3 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE 5:5 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE_INIT 0x00000001 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY 8:6 /* R-XVF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY 11:9 /* R-XVF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_RSVD 14:12 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING 15:15 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING_INIT 0x00000001 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE 25:18 /* R-EVF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* R-E-V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE 27:26 /* R-EVF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* R-E-V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */
#define NV_XVE_PPC_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS 0x00000080 /* RW-4R */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE 0:0 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE 2:2 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE 7:5 /* RWEVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* RWE-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE 9:9 /* R-IVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE 10:10 /* RWCVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* RWC-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT 0x00000001 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE 14:12 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT 0x00000002 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED 20:20 /* R-IVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_LINK_CAPABILITIES 0x00000084 /* R--4R */
#define NV_XVE_PPC_LINK_CAPABILITIES_MAX_LINK_SPEED 3:0 /* R-XVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_MAX_LINK_WIDTH 9:4 /* R-XVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT 11:10 /* R-IVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT_INIT 0x00000003 /* R-I-V */
#define NV_XVE_PPC_LINK_CAPABILITIES_L0S_EXIT_LATENCY 14:12 /* R-XVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_L1_EXIT_LATENCY 17:15 /* R-XVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_CLOCK_PM 18:18 /* R-IVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_CLOCK_PM_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_LINK_CAPABILITIES_CLOCK_PM_DISABLE 0x00000000 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_CLOCK_PM_ENABLE 0x00000001 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING 19:19 /* C--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING 20:20 /* C--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION 21:21 /* C--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE 22:22 /* R-EVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_SUPPORTED 0x00000001 /* R-E-V */
#define NV_XVE_PPC_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_PORT_NUMBER 31:24 /* R-XVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL 1:0 /* RWEVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_INIT 0x00000000 /* RWE-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_DISABLE 0x00000000 /* RW--V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_DISABLE 0x00000002 /* RW--V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_ENABLE 0x00000003 /* RW--V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY 3:3 /* RWEVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_INIT 0x00000000 /* RWE-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_64B 0x00000000 /* RW--V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_128B 0x00000001 /* RW--V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_DISABLE 4:4 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_RETRAIN_LINK 5:5 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_RETRAIN_LINK_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION 6:6 /* RWEVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION_INIT 0x00000000 /* RWE-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_EXTENDED_SYNCH 7:7 /* RWEVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_EXTENDED_SYNCH_INIT 0x00000000 /* RWE-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_CLOCK_PM 8:8 /* RWEVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_CLOCK_PM_INIT 0x00000000 /* RWE-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN 10:10 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN 11:11 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_SPEED_2P5 0x00000001 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_SPEED_5P0 0x00000002 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_SPEED_8P0 0x00000003 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH 25:20 /* R--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X1 0x00000001 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X2 0x00000002 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X4 0x00000004 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X8 0x00000008 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X16 0x00000010 /* R---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_RSVD 26:26 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_TRAINING 27:27 /* R-IVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_TRAINING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON 28:28 /* R-EVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON_INIT 0x00000001 /* R-E-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_DLL_ACTIVE 29:29 /* R-IVF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_DLL_ACTIVE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT 30:30 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH 31:31 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES 0x0000008C /* C--4R */
#define NV_XVE_PPC_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT 0:0 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT 1:1 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT 2:2 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT 3:3 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT 4:4 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE 5:5 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE 6:6 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE 14:7 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE 16:15 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT 17:17 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT 18:18 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER 31:19 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS 0x00000090 /* C--4R */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE 0:0 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE 1:1 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE 2:2 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE 3:3 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE 4:4 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE 5:5 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL 7:6 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL 9:8 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL 10:10 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL 11:11 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE 12:12 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED 16:16 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED 17:17 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED 18:18 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED 19:19 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_COMMAND_COMPLETED 20:20 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE 21:21 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE 22:22 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS 23:23 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED 24:24 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2 0x0000009C /* R--4R */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES 3:0 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_A_AND_B 0x00000003 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE 4:4 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* ----V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ARI_FORWARDING 5:5 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ARI_FORWARDING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING 6:6 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING 11:11 /* R--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_TPH_COMPLETER 13:12 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_TPH_COMPLETER_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER 16:16 /* R--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER 17:17 /* R-EVF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED 0x00000001 /* R-E-V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_OBFF 19:18 /* R--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_OBFF_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_SGNL 0x00000001 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_WAKE_SGNL 0x00000002 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_WAKE_SGNL 0x00000003 /* R---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_EXTENDED_FMT 20:20 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_EXTENDED_FMT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX 21:21 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX 23:22 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_BITS 31:24 /* C--VF */
#define NV_XVE_PPC_DEVICE_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES 3:0 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_LO 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_HI 0x00000002 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_LO 0x00000005 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_HI 0x00000006 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_DEFAULT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE 4:4 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_ENABLED 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_DISABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE 5:5 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING 7:7 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE 8:8 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE 9:9 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE 12:12 /* RWIVF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_DISABLED 0x00000000 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE 14:13 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_BITS 31:15 /* C--VF */
#define NV_XVE_PPC_DEVICE_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2 0x000000A4 /* R-I4R */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R---V */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_BITS 31:25 /* C--VF */
#define NV_XVE_PPC_LINK_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2 0x000000A8 /* R--4R */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED 3:0 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_GEN2_PROTO_DISABLED 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE 4:4 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE 5:5 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_RVSD 6:6 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_RVSD_0 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN 9:7 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE 10:10 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS 11:11 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS 15:12 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_CUR_DEEMPHASIS_LEVEL 16:16 /* R--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE 17:17 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL 18:18 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL 19:19 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL 20:20 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST 21:21 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_BITS 31:22 /* C--VF */
#define NV_XVE_PPC_LINK_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CAPABILITIES_2 0x000000AC /* C--4R */
#define NV_XVE_PPC_SLOT_CAPABILITIES_2_BITS 31:0 /* C--VF */
#define NV_XVE_PPC_SLOT_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_2 0x000000B0 /* C--4R */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_2_BITS 31:0 /* C--VF */
#define NV_XVE_PPC_SLOT_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CAP_HDR 0x00000100 /* R--4R */
#define NV_XVE_PPC_AER_CAP_HDR_ID 15:0 /* C--VF */
#define NV_XVE_PPC_AER_CAP_HDR_ID_LINK_DEC 0x00000001 /* C---V */
#define NV_XVE_PPC_AER_CAP_HDR_ID_AER_DISABLED 0x00000000 /* ----V */
#define NV_XVE_PPC_AER_CAP_HDR_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_PPC_AER_CAP_HDR_ID_VERSION_1 0x00000001 /* ----V */
#define NV_XVE_PPC_AER_CAP_HDR_ID_VERSION_2 0x00000002 /* C---V */
#define NV_XVE_PPC_AER_CAP_HDR_ID_VERSION_AER_DISABLED 0x00000000 /* ----V */
#define NV_XVE_PPC_AER_CAP_HDR_ID_NEXT_PTR 31:20 /* R-IVF */
#define NV_XVE_PPC_AER_CAP_HDR_ID_NEXT_PTR_ARI 0x00000138 /* R-I-V */
#define NV_XVE_PPC_AER_CAP_HDR_ID_NEXT_PTR_GEN4 0x00000140 /* R---V */
#define NV_XVE_PPC_AER_CAP_HDR_ID_NEXT_PTR_NONE 0x00000000 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR 0x00000104 /* RW-4R */
#define NV_XVE_PPC_AER_UNCORR_ERR_RSVD 0:0 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_DLINK_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_DLINK_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_DLINK_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SURPRISE_DOWN_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_POISONED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_POISONED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_POISONED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_FC_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_FC_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_FC_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_ABORT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_ABORT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_CPL_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNEXP_CPL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNEXP_CPL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNEXP_CPL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_RCVR_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_RCVR_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_RCVR_OVERFLOW_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MALFORMED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MALFORMED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MALFORMED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_ECRC_ERROR 19:19 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_ECRC_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNSUPPORTED_REQ_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNSUPPORTED_REQ_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_UNSUPPORTED_REQ_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_UNCORR_ERR_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_INTERNAL_ERROR 22:22 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK 0x00000108 /* RW-4R */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_RSVD 0:0 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_SURPRISE_DOWN_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_POISONED_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_POISONED_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_CPL_ABORT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_CPL_ABORT_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_UNEXP_CPL_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_UNEXP_CPL_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_MALFORMED_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_MALFORMED_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_ECRC_ERR 19:19 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_ECRC_ERR_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_INTERNAL_ERROR 22:22 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR 0x0000010C /* RW-4R */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_RSVD 0:0 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN_INIT 0x00000001 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_POISONED_TLP_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_POISONED_TLP_FATAL 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_FATAL 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_CPL_ABORT_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_CPL_ABORT_FATAL 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_UNEXP_CPL_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_UNEXP_CPL_FATAL 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_ECRC_ERR 19:19 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_ECRC_ERR_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_FATAL 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR 22:22 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR_INIT 0x00000001 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE_PPC_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CORR_ERR 0x00000110 /* RW-4R */
#define NV_XVE_PPC_AER_CORR_ERR_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_RCV_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_CORR_ERR_RCV_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_CORR_ERR_RCV_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_DLLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_DLLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_CORR_ERR_BAD_DLLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_ROLLOVER_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_ROLLOVER_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_ROLLOVER_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_CORR_ERR_RPLY_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_CORR_ERR_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_CORR_ERR_INTERNAL_ERROR 14:14 /* C--VF */
#define NV_XVE_PPC_AER_CORR_ERR_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CORR_ERR_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_HEADER_LOG_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_CORR_ERR_HEADER_LOG_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_PPC_AER_CORR_ERR_HEADER_LOG_OVERFLOW_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_PPC_AER_CORR_ERR_MASK 0x00000114 /* RW-4R */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RCV_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RCV_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_BAD_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_BAD_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_BAD_DLLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_BAD_DLLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RPLY_ROLLOVER_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RPLY_ROLLOVER_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RPLY_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_RPLY_TIMEOUT_MASKED 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_NOT_MASKED 0x00000000 /* RW--V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_MASKED 0x00000001 /* RWC-V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_INTERNAL_ERROR 14:14 /* C--VF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_NOT_MASKED 0x00000000 /* RW--V */
#define NV_XVE_PPC_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_MASKED 0x00000001 /* RWC-V */
#define NV_XVE_PPC_AER_CAP_CNTL 0x00000118 /* RW-4R */
#define NV_XVE_PPC_AER_CAP_CNTL_ERR_PTR 4:0 /* R--VF */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_GEN_CAP 5:5 /* C--VF */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_GEN_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_GEN_EN 6:6 /* RWCVF */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_GEN_EN_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_GEN_EN_TRUE 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_CHK_CAP 7:7 /* C--VF */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_CHK_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_CHK_EN 8:8 /* RWCVF */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_CHK_EN_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_PPC_AER_CAP_CNTL_ECRC_CHK_EN_TRUE 0x00000001 /* RW--V */
#define NV_XVE_PPC_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP 9:9 /* C--VF */
#define NV_XVE_PPC_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN 10:10 /* C--VF */
#define NV_XVE_PPC_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN_FALSE 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT 11:11 /* C--VF */
#define NV_XVE_PPC_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_PPC_AER_HDR_LOG_DW0 0x0000011C /* R--4R */
#define NV_XVE_PPC_AER_HDR_LOG_DW0_0 31:0 /* R-CVF */
#define NV_XVE_PPC_AER_HDR_LOG_DW0_0_INIT 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_HDR_LOG_DW1 0x00000120 /* R--4R */
#define NV_XVE_PPC_AER_HDR_LOG_DW1_1 31:0 /* R-CVF */
#define NV_XVE_PPC_AER_HDR_LOG_DW1_1_INIT 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_HDR_LOG_DW2 0x00000124 /* R--4R */
#define NV_XVE_PPC_AER_HDR_LOG_DW2_2 31:0 /* R-CVF */
#define NV_XVE_PPC_AER_HDR_LOG_DW2_2_INIT 0x00000000 /* R-C-V */
#define NV_XVE_PPC_AER_HDR_LOG_DW3 0x00000128 /* R--4R */
#define NV_XVE_PPC_AER_HDR_LOG_DW3_3 31:0 /* R-CVF */
#define NV_XVE_PPC_AER_HDR_LOG_DW3_3_INIT 0x00000000 /* R-C-V */
#define NV_XVE_PPC_ARI_CAP0 0x00000138 /* R--4R */
#define NV_XVE_PPC_ARI_CAP0_CAPID 15:0 /* C--VF */
#define NV_XVE_PPC_ARI_CAP0_CAPID_EXT_CAP 0x0000000E /* C---V */
#define NV_XVE_PPC_ARI_CAP0_HDR0_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_PPC_ARI_CAP0_HDR0_ID_VERSION_1 0x00000001 /* C---V */
#define NV_XVE_PPC_ARI_CAP0_HDR0_ID_NEXT_PTR 31:20 /* R-IVF */
#define NV_XVE_PPC_ARI_CAP0_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* R---V */
#define NV_XVE_PPC_ARI_CAP0_HDR0_ID_NEXT_PTR_GEN4 0x00000140 /* R-I-V */
#define NV_XVE_PPC_ARI_CAP1 0x0000013C /* C--4R */
#define NV_XVE_PPC_ARI_CAP1_MFVC_FN_GRPS_CAP 0:0 /* C--VF */
#define NV_XVE_PPC_ARI_CAP1_MFVC_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE_PPC_ARI_CAP1_ACS_FN_GRPS_CAP 1:1 /* C--VF */
#define NV_XVE_PPC_ARI_CAP1_ACS_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE_PPC_ARI_CAP1_NXT_FN_NUM 15:8 /* C--VF */
#define NV_XVE_PPC_ARI_CAP1_NXT_FN_NUM_VAL 0x00000000 /* C---V */
#define NV_XVE_PPC_ARI_CAP1_MFVC_FN_GRPS_EN 16:16 /* C--VF */
#define NV_XVE_PPC_ARI_CAP1_MFVC_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE_PPC_ARI_CAP1_ACS_FN_GRPS_EN 17:17 /* C--VF */
#define NV_XVE_PPC_ARI_CAP1_ACS_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE_PPC_ARI_CAP1_FN_GRP 22:20 /* C--VF */
#define NV_XVE_PPC_ARI_CAP1_FN_GRP_ZERO 0x00000000 /* C---V */
#define NV_XVE_PPC_DL_FEATURE_EXT_CAP_HDR 0x00000140 /* C--4R */
#define NV_XVE_PPC_DL_FEATURE_EXT_CAP_HDR_CAPID 15:0 /* C--VF */
#define NV_XVE_PPC_DL_FEATURE_EXT_CAP_HDR_CAPID_EXT_CAP 0x00000025 /* C---V */
#define NV_XVE_PPC_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_PPC_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION_1 0x00000001 /* C---V */
#define NV_XVE_PPC_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR 31:20 /* C--VF */
#define NV_XVE_PPC_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* C---V */
#define NV_XVE_PPC_DL_FEATURE_CAP 0x00000144 /* R--4R */
#define NV_XVE_PPC_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP 0:0 /* R-EVF */
#define NV_XVE_PPC_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_PPC_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_PPC_DL_FEATURE_CAP_RSVDP 22:1 /* C--VF */
#define NV_XVE_PPC_DL_FEATURE_CAP_RSVDP_NULL 0x00000000 /* C---V */
#define NV_XVE_PPC_DL_FEATURE_CAP_EXCH_EN 31:31 /* R-EVF */
#define NV_XVE_PPC_DL_FEATURE_CAP_EXCH_EN_SET 0x00000001 /* R---V */
#define NV_XVE_PPC_DL_FEATURE_CAP_EXCH_EN_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_PPC_DL_FEATURE_STATUS 0x00000148 /* R--4R */
#define NV_XVE_PPC_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP 0:0 /* R-EVF */
#define NV_XVE_PPC_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_PPC_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_PPC_DL_FEATURE_STATUS_RSVDP 22:1 /* C--VF */
#define NV_XVE_PPC_DL_FEATURE_STATUS_RSVDP_NULL 0x00000000 /* C---V */
#define NV_XVE_PPC_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD 31:31 /* R-EVF */
#define NV_XVE_PPC_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_PPC_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_SET 0x00000001 /* R---V */
#define NV_XVE_PPC_CYA_FLR_RESET 0x000014C /* RW-4R */
#define NV_XVE_PPC_CYA_FLR_RESET_BUSY_OVERRIDE 0:0 /* RWCVF */
#define NV_XVE_PPC_CYA_FLR_RESET_BUSY_OVERRIDE_VAL 0x0000000 /* RWC-V */
#define NV_XVE_PPC_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH 8:1 /* RWCVF */
#define NV_XVE_PPC_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH_VAL 0x0000010 /* RWC-V */
#endif // __ga102_dev_nv_xve3g_fn_ppc_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nv_xve3g_fn_xusb_h__
#define __ga102_dev_nv_xve3g_fn_xusb_h__
/* This file is autogenerated. Do not edit */
#define NV_XVE_XUSB 0x000001FF:0x00000000 /* RW--D */
#define NV_XVE_XUSB_ID 0x00000000 /* R--4R */
#define NV_XVE_XUSB_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE_XUSB_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP 31:16 /* R-CVF */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_NO_USE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_XUSB_TU102 0x00001AD6 /* R---V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_XUSB_TU104 0x00001AD8 /* R---V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_XUSB_TU106 0x00001ADA /* R---V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_XUSB_TU107 0x00001ADC /* R---V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_XUSB_TU117 0x00001ADC /* R---V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_XUSB_TU108 0x00001ADE /* R---V */
#define NV_XVE_XUSB_ID_DEVICE_CHIP_XUSB_TU116 0x00001AEC /* R---V */
#define NV_XVE_XUSB_DEV_CTRL 0x00000004 /* RW-4R */
#define NV_XVE_XUSB_DEV_CTRL_CMD_IO_SPACE 0:0 /* R-IVF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_MEMORY_SPACE 1:1 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_BUS_MASTER 2:2 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_SPECIAL_CYCLE 3:3 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_SPECIAL_CYCLE_DISABLED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE 4:4 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE_DISABLED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_VGA_PALETTE_SNOOP 5:5 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_VGA_PALETTE_SNOOP_DISABLED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_PERR 6:6 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_PERR_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_PERR_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_IDSEL_STEP 7:7 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_IDSEL_STEP_DISABLED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_SERR 8:8 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_SERR_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_SERR_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_FAST_BACK2BACK 9:9 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_FAST_BACK2BACK_DISABLED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_CMD_INTERRUPT_DISABLE 10:10 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_CMD_INTERRUPT_DISABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_INTERRUPT 19:19 /* R-IVF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_INTERRUPT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_INTERRUPT_PENDING 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_CAPLIST 20:20 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_CAPLIST_NOT_PRESENT 0x00000000 /* ----V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_CAPLIST_PRESENT 0x00000001 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_66MHZ 21:21 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_66MHZ_INCAPABLE 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_66MHZ_CAPABLE 0x00000001 /* ----V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_FAST_BACK2BACK 23:23 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_FAST_BACK2BACK_INCAPABLE 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_FAST_BACK2BACK_CAPABLE 0x00000001 /* ----V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_MASTER_DATA_PERR 24:24 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_MASTER_DATA_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_MASTER_DATA_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_MASTER_DATA_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DEVSEL_TIMING 26:25 /* C--VF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DEVSEL_TIMING_FAST 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DEVSEL_TIMING_MEDIUM 0x00000001 /* ----V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DEVSEL_TIMING_SLOW 0x00000002 /* ----V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT 27:27 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT 28:28 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT 29:29 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_SERR 30:30 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_SERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_SERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_SIGNALED_SERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DETECTED_PERR 31:31 /* RWIVF */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DETECTED_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DETECTED_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEV_CTRL_STAT_DETECTED_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_REV_ID 0x00000008 /* C--4R */
#define NV_XVE_XUSB_REV_ID_FIB 3:0 /* C--VF */
#define NV_XVE_XUSB_REV_ID_FIB_ONE 0x00000001 /* C---V */
#define NV_XVE_XUSB_REV_ID_FIB_TWO 0x00000002 /* ----V */
#define NV_XVE_XUSB_REV_ID_MASK 7:4 /* C--VF */
#define NV_XVE_XUSB_REV_ID_MASK_A 0x0000000A /* C---V */
#define NV_XVE_XUSB_REV_ID_MASK_B 0x0000000B /* ----V */
#define NV_XVE_XUSB_REV_ID_CLASS_CODE 31:8 /* C--VF */
#define NV_XVE_XUSB_REV_ID_CLASS_CODE_USB3 0x000C0330 /* C---V */
#define NV_XVE_XUSB_MISC_1 0x0000000C /* RW-4R */
#define NV_XVE_XUSB_MISC_1_CACHE_LINE_SIZE 7:0 /* RWIVF */
#define NV_XVE_XUSB_MISC_1_CACHE_LINE_SIZE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_MISC_1_MASTER_LATENCY_TIMER 15:8 /* C--VF */
#define NV_XVE_XUSB_MISC_1_MASTER_LATENCY_TIMER_0_CLOCKS 0x00000000 /* C---V */
#define NV_XVE_XUSB_MISC_1_HEADER_TYPE 23:16 /* C--VF */
#define NV_XVE_XUSB_MISC_1_HEADER_TYPE_SINGLEFUNC 0x00000000 /* ----V */
#define NV_XVE_XUSB_MISC_1_HEADER_TYPE_MULTIFUNC 0x00000080 /* C---V */
#define NV_XVE_XUSB_MISC_1_BIST 31:24 /* C--VF */
#define NV_XVE_XUSB_MISC_1_BIST_NULL 0x00000000 /* C---V */
#define NV_XVE_XUSB_BAR0_LO 0x00000010 /* RW-4R */
#define NV_XVE_XUSB_BAR0_LO_SPACE_TYPE 0:0 /* C--VF */
#define NV_XVE_XUSB_BAR0_LO_SPACE_TYPE_MEMORY 0x00000000 /* C---V */
#define NV_XVE_XUSB_BAR0_LO_SPACE_TYPE_IO 0x00000001 /* ----V */
#define NV_XVE_XUSB_BAR0_LO_ADDRESS_TYPE 2:1 /* C--VF */
#define NV_XVE_XUSB_BAR0_LO_ADDRESS_TYPE_32_BIT 0x00000000 /* ----V */
#define NV_XVE_XUSB_BAR0_LO_ADDRESS_TYPE_20_BIT 0x00000001 /* ----V */
#define NV_XVE_XUSB_BAR0_LO_ADDRESS_TYPE_64_BIT 0x00000002 /* C---V */
#define NV_XVE_XUSB_BAR0_LO_PREFETCHABLE 3:3 /* C--VF */
#define NV_XVE_XUSB_BAR0_LO_PREFETCHABLE_NOT 0x00000000 /* ----V */
#define NV_XVE_XUSB_BAR0_LO_PREFETCHABLE_MERGABLE 0x00000001 /* C---V */
#define NV_XVE_XUSB_BAR0_LO_BASE_ADDRESS 31:18 /* RWIVF */
#define NV_XVE_XUSB_BAR0_LO_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_BAR0_HI 0x00000014 /* RW-4R */
#define NV_XVE_XUSB_BAR0_HI_BASE_ADDRESS 31:0 /* RWIVF */
#define NV_XVE_XUSB_BAR0_HI_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_BAR1 0x00000018 /* C--4R */
#define NV_XVE_XUSB_BAR1_RSVD 31:0 /* C--VF */
#define NV_XVE_XUSB_BAR1_RSVD_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_BAR2_LO 0x0000001C /* RW-4R */
#define NV_XVE_XUSB_BAR2_LO_SPACE_TYPE 0:0 /* C--VF */
#define NV_XVE_XUSB_BAR2_LO_SPACE_TYPE_MEMORY 0x00000000 /* C---V */
#define NV_XVE_XUSB_BAR2_LO_SPACE_TYPE_IO 0x00000001 /* ----V */
#define NV_XVE_XUSB_BAR2_LO_ADDRESS_TYPE 2:1 /* C--VF */
#define NV_XVE_XUSB_BAR2_LO_ADDRESS_TYPE_32_BIT 0x00000000 /* ----V */
#define NV_XVE_XUSB_BAR2_LO_ADDRESS_TYPE_20_BIT 0x00000001 /* ----V */
#define NV_XVE_XUSB_BAR2_LO_ADDRESS_TYPE_64_BIT 0x00000002 /* C---V */
#define NV_XVE_XUSB_BAR2_LO_PREFETCHABLE 3:3 /* C--VF */
#define NV_XVE_XUSB_BAR2_LO_PREFETCHABLE_NOT 0x00000000 /* ----V */
#define NV_XVE_XUSB_BAR2_LO_PREFETCHABLE_MERGABLE 0x00000001 /* C---V */
#define NV_XVE_XUSB_BAR2_LO_BASE_ADDRESS 31:16 /* RWIVF */
#define NV_XVE_XUSB_BAR2_LO_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_BAR2_HI 0x00000020 /* RW-4R */
#define NV_XVE_XUSB_BAR2_HI_BASE_ADDRESS 31:0 /* RWIVF */
#define NV_XVE_XUSB_BAR2_HI_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_BAR_RSVD(i) (0x00000024+(i)*4) /* C--4A */
#define NV_XVE_XUSB_BAR_RSVD__SIZE_1 1 /* */
#define NV_XVE_XUSB_BAR_RSVD_BITS 31:0 /* C--VF */
#define NV_XVE_XUSB_BAR_RSVD_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_CARDBUS 0x00000028 /* C--4R */
#define NV_XVE_XUSB_CARDBUS_PTR 31:0 /* C--VF */
#define NV_XVE_XUSB_CARDBUS_PTR_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_SUBSYSTEM 0x0000002C /* R--4R */
#define NV_XVE_XUSB_SUBSYSTEM_VENDOR_ID 15:0 /* R-CVF */
#define NV_XVE_XUSB_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_SUBSYSTEM_ID_USER 19:16 /* R-CVF */
#define NV_XVE_XUSB_SUBSYSTEM_ID_USER_NONE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_SUBSYSTEM_ID_NON_USER 31:20 /* R-CVF */
#define NV_XVE_XUSB_SUBSYSTEM_ID_NON_USER_NONE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_ROM_RSVD 0x00000030 /* C--4R */
#define NV_XVE_XUSB_ROM_RSVD_BITS 31:0 /* C--VF */
#define NV_XVE_XUSB_ROM_RSVD_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_CAP_LIST 0x00000034 /* C--4R */
#define NV_XVE_XUSB_CAP_LIST_CAP_PTR 7:0 /* C--VF */
#define NV_XVE_XUSB_CAP_LIST_CAP_PTR_MSI 0x00000068 /* C---V */
#define NV_XVE_XUSB_RSVD_0 0x00000038 /* C--4R */
#define NV_XVE_XUSB_RSVD_0_BITS 31:0 /* C--VF */
#define NV_XVE_XUSB_RSVD_0_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_INTR_GNT 0x0000003C /* RW-4R */
#define NV_XVE_XUSB_INTR_GNT_INTR_LINE 7:0 /* RWIVF */
#define NV_XVE_XUSB_INTR_GNT_INTR_LINE_IRQ0 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_INTR_GNT_INTR_LINE_IRQ1 0x00000001 /* RW--V */
#define NV_XVE_XUSB_INTR_GNT_INTR_LINE_IRQ15 0x0000000F /* RW--V */
#define NV_XVE_XUSB_INTR_GNT_INTR_LINE_UNKNOWN 0x000000FF /* RW--V */
#define NV_XVE_XUSB_INTR_GNT_INTR_PIN 15:8 /* C--VF */
#define NV_XVE_XUSB_INTR_GNT_INTR_PIN_INTC 0x00000003 /* C---V */
#define NV_XVE_XUSB_INTR_GNT_MIN_GNT 23:16 /* C--VF */
#define NV_XVE_XUSB_INTR_GNT_MIN_GNT_NO_REQUIREMENTS 0x00000000 /* C---V */
#define NV_XVE_XUSB_INTR_GNT_MAX_LAT 31:24 /* C--VF */
#define NV_XVE_XUSB_INTR_GNT_MAX_LAT_NO_REQUIREMENTS 0x00000000 /* C---V */
#define NV_XVE_XUSB_XHCI 0x00000060 /* RW-4R */
#define NV_XVE_XUSB_XHCI_SBRN 7:0 /* C--VF */
#define NV_XVE_XUSB_XHCI_SBRN_USB31 0x00000031 /* C---V */
#define NV_XVE_XUSB_XHCI_FLADJ_FLTV 13:8 /* RWIVF */
#define NV_XVE_XUSB_XHCI_FLADJ_FLTV_INIT 0x00000020 /* RWI-V */
#define NV_XVE_XUSB_XHCI_FLADJ_NFC 14:14 /* C--VF */
#define NV_XVE_XUSB_XHCI_FLADJ_NFC_NOT_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_XUSB_XHCI_DBESL 19:16 /* C--VF */
#define NV_XVE_XUSB_XHCI_DBESL_ZERO 0x00000000 /* C---V */
#define NV_XVE_XUSB_XHCI_DBESLD 23:20 /* C--VF */
#define NV_XVE_XUSB_XHCI_DBESLD_ZERO 0x00000000 /* C---V */
#define NV_XVE_XUSB_MSI_CTRL 0x00000068 /* RW-4R */
#define NV_XVE_XUSB_MSI_CTRL_RSVD 31:24 /* C--VF */
#define NV_XVE_XUSB_MSI_CTRL_RSVD_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_MSI_CTRL_64BIT_CAP 23:23 /* C--VF */
#define NV_XVE_XUSB_MSI_CTRL_64BIT_CAP_TRUE 0x00000001 /* C---V */
#define NV_XVE_XUSB_MSI_CTRL_64BIT_CAP_FALSE 0x00000000 /* ----V */
#define NV_XVE_XUSB_MSI_CTRL_MULT_EN 22:20 /* RWIVF */
#define NV_XVE_XUSB_MSI_CTRL_MULT_EN_CODE0 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_MSI_CTRL_MULT_EN_CODE2 0x00000001 /* RW--V */
#define NV_XVE_XUSB_MSI_CTRL_MULT_EN_CODE4 0x00000002 /* RW--V */
#define NV_XVE_XUSB_MSI_CTRL_MULT_EN_CODE8 0x00000003 /* RW--V */
#define NV_XVE_XUSB_MSI_CTRL_MULT_CAP 19:17 /* R-IVF */
#define NV_XVE_XUSB_MSI_CTRL_MULT_CAP_CODE0 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_MSI_CTRL_MSI 16:16 /* RWIVF */
#define NV_XVE_XUSB_MSI_CTRL_MSI_DISABLE 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_MSI_CTRL_MSI_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_XUSB_MSI_CTRL_NEXT_PTR 15:8 /* C--VF */
#define NV_XVE_XUSB_MSI_CTRL_NEXT_PTR_PCIEXP 0x00000078 /* C---V */
#define NV_XVE_XUSB_MSI_CTRL_CAP_ID 7:0 /* C--VF */
#define NV_XVE_XUSB_MSI_CTRL_CAP_ID_MSI 0x00000005 /* C---V */
#define NV_XVE_XUSB_MSI_LOW_ADDR 0x0000006C /* RW-4R */
#define NV_XVE_XUSB_MSI_LOW_ADDR_DWORD 31:2 /* RWIVF */
#define NV_XVE_XUSB_MSI_LOW_ADDR_DWORD_0 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_MSI_LOW_ADDR_RSVD 1:0 /* C--VF */
#define NV_XVE_XUSB_MSI_LOW_ADDR_RSVD_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_MSI_UPPER_ADDR 0x00000070 /* RW-4R */
#define NV_XVE_XUSB_MSI_UPPER_ADDR_DWORD 31:0 /* RWIVF */
#define NV_XVE_XUSB_MSI_UPPER_ADDR_DWORD_0 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_MSI_DATA 0x00000074 /* RW-4R */
#define NV_XVE_XUSB_MSI_DATA_RSVD 31:16 /* R-IVF */
#define NV_XVE_XUSB_MSI_DATA_RSVD_0 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_MSI_DATA_NON_RSVD 15:0 /* RWIVF */
#define NV_XVE_XUSB_MSI_DATA_NON_RSVD_0 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY 0x00000078 /* R--4R */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID 7:0 /* C--VF */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID_INIT 0x00000010 /* C---V */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR 15:8 /* C--VF */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_PWR_MGMT 0x000000B4 /* C---V */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_VERSION 19:16 /* C--VF */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_VERSION_GEN1 0x00000001 /* ----V */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_VERSION_GEN2 0x00000002 /* C---V */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE 23:20 /* C--VF */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED 24:24 /* R-EVF */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED_INIT 0x00000000 /* R-E-V */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER 29:25 /* C--VF */
#define NV_XVE_XUSB_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY 0x0000007C /* R--4R */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE 2:0 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_128 0x00000000 /* ----V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_256 0x00000001 /* ----V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED 4:3 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE 5:5 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE_INIT 0x00000001 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY 8:6 /* R-XVF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY 11:9 /* R-XVF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_RSVD 14:12 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING 15:15 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING_INIT 0x00000001 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE 25:18 /* R-EVF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* R-E-V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE 27:26 /* R-EVF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* R-E-V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS 0x00000080 /* RW-4R */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE 0:0 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE 2:2 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE 7:5 /* RWEVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* RWE-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE 9:9 /* R-IVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE 10:10 /* RWCVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT 0x00000001 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE 14:12 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT 0x00000002 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED 20:20 /* R-IVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_LINK_CAPABILITIES 0x00000084 /* R--4R */
#define NV_XVE_XUSB_LINK_CAPABILITIES_MAX_LINK_SPEED 3:0 /* R-XVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_MAX_LINK_WIDTH 9:4 /* R-XVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT 11:10 /* R-IVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT_INIT 0x00000003 /* R-I-V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_L0S_EXIT_LATENCY 14:12 /* R-XVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_L1_EXIT_LATENCY 17:15 /* R-XVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_CLOCK_PM 18:18 /* R-IVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_CLOCK_PM_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_CLOCK_PM_DISABLE 0x00000000 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_CLOCK_PM_ENABLE 0x00000001 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING 19:19 /* C--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING 20:20 /* C--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION 21:21 /* C--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE 22:22 /* R-EVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_SUPPORTED 0x00000001 /* R-E-V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_PORT_NUMBER 31:24 /* R-XVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL 1:0 /* RWEVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_INIT 0x00000000 /* RWE-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_DISABLE 0x00000000 /* RW--V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_DISABLE 0x00000002 /* RW--V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_ENABLE 0x00000003 /* RW--V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY 3:3 /* RWEVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_INIT 0x00000000 /* RWE-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_64B 0x00000000 /* RW--V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_128B 0x00000001 /* RW--V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_DISABLE 4:4 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_RETRAIN_LINK 5:5 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_RETRAIN_LINK_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION 6:6 /* RWEVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION_INIT 0x00000000 /* RWE-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_EXTENDED_SYNCH 7:7 /* RWEVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_EXTENDED_SYNCH_INIT 0x00000000 /* RWE-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_CLOCK_PM 8:8 /* RWEVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_CLOCK_PM_INIT 0x00000000 /* RWE-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN 10:10 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN 11:11 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_SPEED_2P5 0x00000001 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_SPEED_5P0 0x00000002 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_SPEED_8P0 0x00000003 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH 25:20 /* R--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X1 0x00000001 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X2 0x00000002 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X4 0x00000004 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X8 0x00000008 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X16 0x00000010 /* R---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_RSVD 26:26 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_TRAINING 27:27 /* R-IVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_TRAINING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON 28:28 /* R-EVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON_INIT 0x00000001 /* R-E-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_DLL_ACTIVE 29:29 /* R-IVF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_DLL_ACTIVE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT 30:30 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH 31:31 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES 0x0000008C /* C--4R */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT 0:0 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT 1:1 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT 2:2 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT 3:3 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT 4:4 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE 5:5 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE 6:6 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE 14:7 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE 16:15 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT 17:17 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT 18:18 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER 31:19 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS 0x00000090 /* C--4R */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE 0:0 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE 1:1 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE 2:2 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE 3:3 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE 4:4 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE 5:5 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL 7:6 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL 9:8 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL 10:10 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL 11:11 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE 12:12 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED 16:16 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED 17:17 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED 18:18 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED 19:19 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_COMMAND_COMPLETED 20:20 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE 21:21 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE 22:22 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS 23:23 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED 24:24 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2 0x0000009C /* R--4R */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES 3:0 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_A_AND_B 0x00000003 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE 4:4 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* ----V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ARI_FORWARDING 5:5 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ARI_FORWARDING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING 6:6 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING 11:11 /* R--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_TPH_COMPLETER 13:12 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_TPH_COMPLETER_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER 16:16 /* R--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER 17:17 /* R-EVF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED 0x00000001 /* R-E-V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_OBFF 19:18 /* R--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_OBFF_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_SGNL 0x00000001 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_WAKE_SGNL 0x00000002 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_WAKE_SGNL 0x00000003 /* R---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_EXTENDED_FMT 20:20 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_EXTENDED_FMT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX 21:21 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX 23:22 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_BITS 31:24 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES 3:0 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_LO 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_HI 0x00000002 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_LO 0x00000005 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_HI 0x00000006 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_DEFAULT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE 4:4 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_ENABLED 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_DISABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE 5:5 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING 7:7 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE 8:8 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE 9:9 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE 12:12 /* RWIVF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_DISABLED 0x00000000 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE 14:13 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_BITS 31:15 /* C--VF */
#define NV_XVE_XUSB_DEVICE_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2 0x000000A4 /* R-I4R */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R---V */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_BITS 31:25 /* C--VF */
#define NV_XVE_XUSB_LINK_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2 0x000000A8 /* R--4R */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED 3:0 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_GEN2_PROTO_DISABLED 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE 4:4 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE 5:5 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_RVSD 6:6 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_RVSD_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN 9:7 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE 10:10 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS 11:11 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS 15:12 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_CUR_DEEMPHASIS_LEVEL 16:16 /* R--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE 17:17 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL 18:18 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL 19:19 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL 20:20 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST 21:21 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_BITS 31:22 /* C--VF */
#define NV_XVE_XUSB_LINK_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_2 0x000000AC /* C--4R */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_2_BITS 31:0 /* C--VF */
#define NV_XVE_XUSB_SLOT_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_2 0x000000B0 /* C--4R */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_2_BITS 31:0 /* C--VF */
#define NV_XVE_XUSB_SLOT_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0 0x000000B4 /* R--4R */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D3_COLD 31:31 /* R-IVF */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D3_COLD_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D3_COLD_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D3_HOT 30:30 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D3_HOT_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D3_HOT_NOT_SUPPORTED 0x00000000 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D2 29:29 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D2_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D2_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D1 28:28 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D1_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D1_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D0 27:27 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D0_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_D0_NOT_SUPPORTED 0x00000000 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_D2 26:26 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_D2_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_D2_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_D1 25:25 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_D1_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_D1_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_AUX_CURRENT 24:22 /* R-CVF */
#define NV_XVE_XUSB_PWR_MGMT_0_AUX_CURRENT_SELF_POWERED 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_PWR_MGMT_0_DSI 21:21 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_DSI_NOT_REQUIRED 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_CLOCK 19:19 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_PME_CLOCK_NOT_REQUIRED 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_VERSION 18:16 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_VERSION_1 0x00000001 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_VERSION_2 0x00000002 /* ----V */
#define NV_XVE_XUSB_PWR_MGMT_0_VERSION_3 0x00000003 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_NEXT_PTR 15:8 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_NEXT_PTR_NONE 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_0_CAP_ID 7:0 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_0_CAP_ID_POWER_MGMT 0x00000001 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_1 0x000000B8 /* RW-4R */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_DATA 31:24 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_DATA_UNS 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_BPCC 23:23 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_BPCC_UNS 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_B2B3 22:22 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_B2B3_UNS 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_STATUS 15:15 /* RWCVF */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_STATUS_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_STATUS_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_STATUS_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_DATA_SCALE 14:13 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_DATA_SCALE_UNS 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_DATA_SEL 12:9 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_DATA_SEL_UNS 0x00000000 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME 8:8 /* RWCVF */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_DISABLE 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_PWR_MGMT_1_PME_ENABLE 0x00000001 /* RW--V */
#define NV_XVE_XUSB_PWR_MGMT_1_NO_SOFT_RESET 3:3 /* C--VF */
#define NV_XVE_XUSB_PWR_MGMT_1_NO_SOFT_RESET_DISABLE 0x00000001 /* C---V */
#define NV_XVE_XUSB_PWR_MGMT_1_PWR_STATE 1:0 /* RWIVF */
#define NV_XVE_XUSB_PWR_MGMT_1_PWR_STATE_D0 0x00000000 /* RWI-V */
#define NV_XVE_XUSB_PWR_MGMT_1_PWR_STATE_D1 0x00000001 /* RW--V */
#define NV_XVE_XUSB_PWR_MGMT_1_PWR_STATE_D2 0x00000002 /* RW--V */
#define NV_XVE_XUSB_PWR_MGMT_1_PWR_STATE_D3HOT 0x00000003 /* RW--V */
#define NV_XVE_XUSB_AER_CAP_HDR 0x00000100 /* R--4R */
#define NV_XVE_XUSB_AER_CAP_HDR_ID 15:0 /* C--VF */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_LINK_DEC 0x00000001 /* C---V */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_AER_DISABLED 0x00000000 /* ----V */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_VERSION_1 0x00000001 /* ----V */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_VERSION_2 0x00000002 /* C---V */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_VERSION_AER_DISABLED 0x00000000 /* ----V */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_NEXT_PTR 31:20 /* R-IVF */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_NEXT_PTR_ARI 0x00000138 /* R-I-V */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_NEXT_PTR_GEN4 0x00000140 /* R---V */
#define NV_XVE_XUSB_AER_CAP_HDR_ID_NEXT_PTR_NONE 0x00000000 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR 0x00000104 /* RW-4R */
#define NV_XVE_XUSB_AER_UNCORR_ERR_RSVD 0:0 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_DLINK_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_DLINK_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_DLINK_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SURPRISE_DOWN_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_POISONED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_POISONED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_POISONED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_FC_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_FC_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_FC_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_ABORT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_ABORT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_CPL_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNEXP_CPL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNEXP_CPL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNEXP_CPL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_RCVR_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_RCVR_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_RCVR_OVERFLOW_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MALFORMED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MALFORMED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MALFORMED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_ECRC_ERROR 19:19 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_ECRC_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNSUPPORTED_REQ_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNSUPPORTED_REQ_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_UNSUPPORTED_REQ_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_INTERNAL_ERROR 22:22 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_INTERNAL_ERROR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_INTERNAL_ERROR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_INTERNAL_ERROR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK 0x00000108 /* RW-4R */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_RSVD 0:0 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_SURPRISE_DOWN_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_POISONED_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_POISONED_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_CPL_ABORT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_CPL_ABORT_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_UNEXP_CPL_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_UNEXP_CPL_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_MALFORMED_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_MALFORMED_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_ECRC_ERR 19:19 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_ECRC_ERR_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_INTERNAL_ERROR 22:22 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_INTERNAL_ERROR_NOT_MASKED 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_INTERNAL_ERROR_MASKED 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR 0x0000010C /* RW-4R */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_RSVD 0:0 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN_INIT 0x00000001 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_POISONED_TLP_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_POISONED_TLP_FATAL 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_FATAL 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_CPL_ABORT_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_CPL_ABORT_FATAL 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_UNEXP_CPL_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_UNEXP_CPL_FATAL 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_ECRC_ERR 19:19 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_ECRC_ERR_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_FATAL 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR 22:22 /* RWCVF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR_FATAL 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE_XUSB_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_CORR_ERR 0x00000110 /* RW-4R */
#define NV_XVE_XUSB_AER_CORR_ERR_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_RCV_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_CORR_ERR_RCV_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_CORR_ERR_RCV_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_DLLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_DLLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_CORR_ERR_BAD_DLLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_ROLLOVER_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_ROLLOVER_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_ROLLOVER_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_CORR_ERR_RPLY_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_CORR_ERR_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_CORR_ERR_INTERNAL_ERROR 14:14 /* C--VF */
#define NV_XVE_XUSB_AER_CORR_ERR_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_CORR_ERR_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_HEADER_LOG_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_CORR_ERR_HEADER_LOG_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_XUSB_AER_CORR_ERR_HEADER_LOG_OVERFLOW_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK 0x00000114 /* RW-4R */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RCV_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RCV_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_BAD_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_BAD_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_BAD_DLLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_BAD_DLLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RPLY_ROLLOVER_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RPLY_ROLLOVER_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RPLY_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_RPLY_TIMEOUT_MASKED 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_NOT_MASKED 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_MASKED 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_INTERNAL_ERROR 14:14 /* C--VF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_NOT_MASKED 0x00000000 /* RW--V */
#define NV_XVE_XUSB_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_MASKED 0x00000001 /* RWC-V */
#define NV_XVE_XUSB_AER_CAP_CNTL 0x00000118 /* RW-4R */
#define NV_XVE_XUSB_AER_CAP_CNTL_ERR_PTR 4:0 /* R--VF */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_GEN_CAP 5:5 /* C--VF */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_GEN_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_GEN_EN 6:6 /* RWCVF */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_GEN_EN_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_GEN_EN_TRUE 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_CHK_CAP 7:7 /* C--VF */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_CHK_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_CHK_EN 8:8 /* RWCVF */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_CHK_EN_FALSE 0x00000000 /* RWC-V */
#define NV_XVE_XUSB_AER_CAP_CNTL_ECRC_CHK_EN_TRUE 0x00000001 /* RW--V */
#define NV_XVE_XUSB_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP 9:9 /* C--VF */
#define NV_XVE_XUSB_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN 10:10 /* C--VF */
#define NV_XVE_XUSB_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN_FALSE 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT 11:11 /* C--VF */
#define NV_XVE_XUSB_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE_XUSB_AER_HDR_LOG_DW0 0x0000011C /* R--4R */
#define NV_XVE_XUSB_AER_HDR_LOG_DW0_0 31:0 /* R-CVF */
#define NV_XVE_XUSB_AER_HDR_LOG_DW0_0_INIT 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_HDR_LOG_DW1 0x00000120 /* R--4R */
#define NV_XVE_XUSB_AER_HDR_LOG_DW1_1 31:0 /* R-CVF */
#define NV_XVE_XUSB_AER_HDR_LOG_DW1_1_INIT 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_HDR_LOG_DW2 0x00000124 /* R--4R */
#define NV_XVE_XUSB_AER_HDR_LOG_DW2_2 31:0 /* R-CVF */
#define NV_XVE_XUSB_AER_HDR_LOG_DW2_2_INIT 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_AER_HDR_LOG_DW3 0x00000128 /* R--4R */
#define NV_XVE_XUSB_AER_HDR_LOG_DW3_3 31:0 /* R-CVF */
#define NV_XVE_XUSB_AER_HDR_LOG_DW3_3_INIT 0x00000000 /* R-C-V */
#define NV_XVE_XUSB_ARI_CAP0 0x00000138 /* R--4R */
#define NV_XVE_XUSB_ARI_CAP0_CAPID 15:0 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP0_CAPID_EXT_CAP 0x0000000E /* C---V */
#define NV_XVE_XUSB_ARI_CAP0_HDR0_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP0_HDR0_ID_VERSION_1 0x00000001 /* C---V */
#define NV_XVE_XUSB_ARI_CAP0_HDR0_ID_NEXT_PTR 31:20 /* R-IVF */
#define NV_XVE_XUSB_ARI_CAP0_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* R---V */
#define NV_XVE_XUSB_ARI_CAP0_HDR0_ID_NEXT_PTR_GEN4 0x00000140 /* R-I-V */
#define NV_XVE_XUSB_ARI_CAP1 0x0000013C /* C--4R */
#define NV_XVE_XUSB_ARI_CAP1_MFVC_FN_GRPS_CAP 0:0 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP1_MFVC_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE_XUSB_ARI_CAP1_ACS_FN_GRPS_CAP 1:1 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP1_ACS_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE_XUSB_ARI_CAP1_NXT_FN_NUM 15:8 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP1_NXT_FN_NUM_VAL 0x00000003 /* C---V */
#define NV_XVE_XUSB_ARI_CAP1_MFVC_FN_GRPS_EN 16:16 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP1_MFVC_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE_XUSB_ARI_CAP1_ACS_FN_GRPS_EN 17:17 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP1_ACS_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE_XUSB_ARI_CAP1_FN_GRP 22:20 /* C--VF */
#define NV_XVE_XUSB_ARI_CAP1_FN_GRP_ZERO 0x00000000 /* C---V */
#define NV_XVE_XUSB_DL_FEATURE_EXT_CAP_HDR 0x00000140 /* C--4R */
#define NV_XVE_XUSB_DL_FEATURE_EXT_CAP_HDR_CAPID 15:0 /* C--VF */
#define NV_XVE_XUSB_DL_FEATURE_EXT_CAP_HDR_CAPID_EXT_CAP 0x00000025 /* C---V */
#define NV_XVE_XUSB_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_XUSB_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION_1 0x00000001 /* C---V */
#define NV_XVE_XUSB_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR 31:20 /* C--VF */
#define NV_XVE_XUSB_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* C---V */
#define NV_XVE_XUSB_DL_FEATURE_CAP 0x00000144 /* R--4R */
#define NV_XVE_XUSB_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP 0:0 /* R-EVF */
#define NV_XVE_XUSB_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_XUSB_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_XUSB_DL_FEATURE_CAP_RSVDP 22:1 /* C--VF */
#define NV_XVE_XUSB_DL_FEATURE_CAP_RSVDP_NULL 0x00000000 /* C---V */
#define NV_XVE_XUSB_DL_FEATURE_CAP_EXCH_EN 31:31 /* R-EVF */
#define NV_XVE_XUSB_DL_FEATURE_CAP_EXCH_EN_SET 0x00000001 /* R---V */
#define NV_XVE_XUSB_DL_FEATURE_CAP_EXCH_EN_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_XUSB_DL_FEATURE_STATUS 0x00000148 /* R--4R */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP 0:0 /* R-EVF */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_RSVDP 22:1 /* C--VF */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_RSVDP_NULL 0x00000000 /* C---V */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD 31:31 /* R-EVF */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_UNSET 0x00000000 /* R-E-V */
#define NV_XVE_XUSB_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_SET 0x00000001 /* R---V */
#define NV_XVE_XUSB_CYA_FLR_RESET 0x000014C /* RW-4R */
#define NV_XVE_XUSB_CYA_FLR_RESET_BUSY_OVERRIDE 0:0 /* RWCVF */
#define NV_XVE_XUSB_CYA_FLR_RESET_BUSY_OVERRIDE_VAL 0x0000000 /* RWC-V */
#define NV_XVE_XUSB_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH 8:1 /* RWCVF */
#define NV_XVE_XUSB_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH_VAL 0x0000010 /* RWC-V */
#endif // __ga102_dev_nv_xve3g_fn_xusb_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nv_xve3g_vf_h__
#define __ga102_dev_nv_xve3g_vf_h__
/* This file is autogenerated. Do not edit */
#define NV_XVE_VF 0x00000FFF:0x00000000 /* RW--D */
#define NV_XVE_VF_CFG_HDR0 0x00000000 /* R--4R */
#define NV_XVE_VF_CFG_HDR0_VENDOR 15:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR0_VENDOR_NA 0x0000FFFF /* C---V */
#define NV_XVE_VF_CFG_HDR0_DEVICE_CHIP 31:16 /* C--VF */
#define NV_XVE_VF_CFG_HDR0_DEVICE_CHIP_NA 0x0000FFFF /* C---V */
#define NV_XVE_VF_CFG_HDR1 0x00000004 /* RW-4R */
#define NV_XVE_VF_CFG_HDR1_RSVD 1:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR1_RSVD_NULL 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR1_BUS_MASTER 2:2 /* RWIVF */
#define NV_XVE_VF_CFG_HDR1_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_VF_CFG_HDR1_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_VF_CFG_HDR1_PARITY_ERR_RESP 6:6 /* R-IVF */
#define NV_XVE_VF_CFG_HDR1_PARITY_ERR_RESP_DISABLED 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_PARITY_ERR_RESP_ENABLED 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_SERR 8:8 /* R-IVF */
#define NV_XVE_VF_CFG_HDR1_SERR_DISABLED 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_SERR_ENABLED 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_INTERRUPT_DISABLE 10:10 /* C--VF */
#define NV_XVE_VF_CFG_HDR1_INTERRUPT_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR1_CAPLIST 20:20 /* C--VF */
#define NV_XVE_VF_CFG_HDR1_CAPLIST_NOT_PRESENT 0x00000000 /* ----V */
#define NV_XVE_VF_CFG_HDR1_CAPLIST_PRESENT 0x00000001 /* C---V */
#define NV_XVE_VF_CFG_HDR1_MASTER_DATA_PERR 24:24 /* RWIVF */
#define NV_XVE_VF_CFG_HDR1_MASTER_DATA_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_MASTER_DATA_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_MASTER_DATA_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_TARGET_ABORT 27:27 /* RWIVF */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_TARGET_ABORT 28:28 /* RWIVF */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_MASTER_ABORT 29:29 /* RWIVF */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_MASTER_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_MASTER_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_RECEIVED_MASTER_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_SERR 30:30 /* RWIVF */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_SERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_SERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_SIGNALED_SERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_CFG_HDR1_DETECTED_PERR 31:31 /* RWIVF */
#define NV_XVE_VF_CFG_HDR1_DETECTED_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR1_DETECTED_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_CFG_HDR1_DETECTED_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_CFG_HDR2 0x00000008 /* R--4R */
#define NV_XVE_VF_CFG_HDR2_REV_ID 3:0 /* R-CVF */
#define NV_XVE_VF_CFG_HDR2_REV_ID_ONE 0x00000001 /* R-C-V */
#define NV_XVE_VF_CFG_HDR2_REV_ID_MASK 7:4 /* R-CVF */
#define NV_XVE_VF_CFG_HDR2_REV_ID_MASK_A 0x0000000A /* R-C-V */
#define NV_XVE_VF_CFG_HDR2_CLASS_CODE 31:8 /* R-XVF */
#define NV_XVE_VF_CFG_HDR2_CLASS_CODE_VGA 0x00030000 /* R---V */
#define NV_XVE_VF_CFG_HDR2_CLASS_CODE_3D 0x00030200 /* R---V */
#define NV_XVE_VF_CFG_HDR2_CLASS_CODE_MULTIMEDIA 0x00048000 /* R---V */
#define NV_XVE_VF_CFG_HDR3 0x0000000C /* R--4R */
#define NV_XVE_VF_CFG_HDR3_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR3_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR4 0x00000010 /* R--4R */
#define NV_XVE_VF_CFG_HDR4_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR4_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR5 0x00000014 /* R--4R */
#define NV_XVE_VF_CFG_HDR5_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR5_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR6 0x00000018 /* R--4R */
#define NV_XVE_VF_CFG_HDR6_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR6_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR7 0x0000001C /* R--4R */
#define NV_XVE_VF_CFG_HDR7_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR7_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR8 0x00000020 /* R--4R */
#define NV_XVE_VF_CFG_HDR8_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR8_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR9 0x00000024 /* R--4R */
#define NV_XVE_VF_CFG_HDR9_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR9_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR10 0x00000028 /* R--4R */
#define NV_XVE_VF_CFG_HDR10_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR10_NULL_ZERO 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR11 0x0000002C /* R--4R */
#define NV_XVE_VF_CFG_HDR11_SUBSYSTEM_VENDOR_ID 15:0 /* R-IVF */
#define NV_XVE_VF_CFG_HDR11_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R-I-V */
#define NV_XVE_VF_CFG_HDR11_SUBSYSTEM_ID 31:16 /* R-CVF */
#define NV_XVE_VF_CFG_HDR11_SUBSYSTEM_ID_NULL 0x00000000 /* R-C-V */
#define NV_XVE_VF_CFG_HDR12 0x00000030 /* R--4R */
#define NV_XVE_VF_CFG_HDR12_ROM_BAR 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR12_ROM_BAR_NULL 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR13 0x00000034 /* R--4R */
#define NV_XVE_VF_CFG_HDR13_CAP_PTR 7:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR13_CAP_PTR_PCIE_CAP0 0x00000040 /* C---V */
#define NV_XVE_VF_CFG_HDR14 0x00000038 /* R--4R */
#define NV_XVE_VF_CFG_HDR14_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR14_NULL_VAL 0x00000000 /* C---V */
#define NV_XVE_VF_CFG_HDR15 0x0000003C /* R--4R */
#define NV_XVE_VF_CFG_HDR15_NULL 31:0 /* C--VF */
#define NV_XVE_VF_CFG_HDR15_NULL_VAL 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP0 0x00000040 /* R--4R */
#define NV_XVE_VF_PCIE_CAP0_LIST_CAPABILITY_ID 7:0 /* C--VF */
#define NV_XVE_VF_PCIE_CAP0_LIST_CAPABILITY_ID_INIT 0x00000010 /* C---V */
#define NV_XVE_VF_PCIE_CAP0_LIST_NEXT_CAPABILITY_PTR 15:8 /* C--VF */
#define NV_XVE_VF_PCIE_CAP0_LIST_NEXT_CAPABILITY_PTR_MSIX 0x0000007C /* C---V */
#define NV_XVE_VF_PCIE_CAP0_VERSION 19:16 /* C--VF */
#define NV_XVE_VF_PCIE_CAP0_VERSION_GEN2 0x00000002 /* C---V */
#define NV_XVE_VF_PCIE_CAP0_DEVICE_PORT_TYPE 23:20 /* C--VF */
#define NV_XVE_VF_PCIE_CAP0_DEVICE_PORT_TYPE_ENDPOINT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP0_SLOT_IMPLEMENTED 24:24 /* C--VF */
#define NV_XVE_VF_PCIE_CAP0_SLOT_IMPLEMENTED_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP0_INTERRUPT_MESSAGE_NUMBER 29:25 /* C--VF */
#define NV_XVE_VF_PCIE_CAP0_INTERRUPT_MESSAGE_NUMBER_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP1 0x00000044 /* R--4R */
#define NV_XVE_VF_PCIE_CAP1_MAX_PAYLOAD_SIZE 2:0 /* C--VF */
#define NV_XVE_VF_PCIE_CAP1_MAX_PAYLOAD_SIZE_256B 0x00000001 /* C---V */
#define NV_XVE_VF_PCIE_CAP1_EXTENDED_TAG_FIELD_SIZE 5:5 /* C--VF */
#define NV_XVE_VF_PCIE_CAP1_EXTENDED_TAG_FIELD_SIZE_TRUE 0x00000001 /* C---V */
#define NV_XVE_VF_PCIE_CAP1_ENDPOINT_L0S_ACCEPTABLE_LATENCY 8:6 /* R-XVF */
#define NV_XVE_VF_PCIE_CAP1_ENDPOINT_L1_ACCEPTABLE_LATENCY 11:9 /* R-XVF */
#define NV_XVE_VF_PCIE_CAP1_RSVD 14:12 /* C--VF */
#define NV_XVE_VF_PCIE_CAP1_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP1_ROLE_BASED_ERR_REPORTING 15:15 /* C--VF */
#define NV_XVE_VF_PCIE_CAP1_ROLE_BASED_ERR_REPORTING_INIT 0x00000001 /* C---V */
#define NV_XVE_VF_PCIE_CAP1_FUNCTION_LEVEL_RESET 28:28 /* C--VF */
#define NV_XVE_VF_PCIE_CAP1_FUNCTION_LEVEL_RESET_SUPPORTED 0x00000001 /* C---V */
#define NV_XVE_VF_PCIE_CAP2 0x00000048 /* RW-4R */
#define NV_XVE_VF_PCIE_CAP2_CORR_ERROR_REPORTING_ENABLE 0:0 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_FATAL_ERROR_REPORTING_ENABLE 2:2 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_ENABLE_RELAXED_ORDERING 4:4 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_ENABLE_RELAXED_ORDERING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE 7:5 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE_128B 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE_256B 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE_512B 0x00000002 /* R---V */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE_1024B 0x00000003 /* R---V */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE_2048B 0x00000004 /* R---V */
#define NV_XVE_VF_PCIE_CAP2_MAX_PAYLOAD_SIZE_4096B 0x00000005 /* R---V */
#define NV_XVE_VF_PCIE_CAP2_EXTENDED_TAG_FIELD_ENABLE 8:8 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_EXTENDED_TAG_FIELD_ENABLE_ENABLED 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP2_PHANTOM_FUNCTIONS_ENABLE 9:9 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_AUXILLARY_POWER_PM_ENABLE 10:10 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_ENABLE_NO_SNOOP 11:11 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_ENABLE_NO_SNOOP_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_MAX_READ_REQUEST_SIZE 14:12 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_MAX_READ_REQUEST_SIZE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_INITIATE_FN_LVL_RST 15:15 /* RWIVF */
#define NV_XVE_VF_PCIE_CAP2_INITIATE_FN_LVL_RST_INIT 0x00000000 /* RWI-V */
#define NV_XVE_VF_PCIE_CAP2_CORR_ERROR_DETECTED 16:16 /* RWIVF */
#define NV_XVE_VF_PCIE_CAP2_CORR_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_CORR_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_PCIE_CAP2_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */
#define NV_XVE_VF_PCIE_CAP2_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_NON_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_PCIE_CAP2_FATAL_ERROR_DETECTED 18:18 /* RWIVF */
#define NV_XVE_VF_PCIE_CAP2_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_PCIE_CAP2_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */
#define NV_XVE_VF_PCIE_CAP2_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP2_UNSUPP_REQUEST_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_PCIE_CAP2_TRANSACTIONS_PENDING 21:21 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP2_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP3 0x0000004C /* R--4R */
#define NV_XVE_VF_PCIE_CAP3_MAX_LINK_SPEED 3:0 /* R-XVF */
#define NV_XVE_VF_PCIE_CAP3_MAX_LINK_WIDTH 9:4 /* R-XVF */
#define NV_XVE_VF_PCIE_CAP3_ACTIVE_STATE_LINK_PM_SUPPORT 11:10 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP3_ACTIVE_STATE_LINK_PM_SUPPORT_INIT 0x00000003 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP3_L0S_EXIT_LATENCY 14:12 /* R-XVF */
#define NV_XVE_VF_PCIE_CAP3_L1_EXIT_LATENCY 17:15 /* R-XVF */
#define NV_XVE_VF_PCIE_CAP3_CLOCK_PM 18:18 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP3_CLOCK_PM_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP3_CLOCK_PM_DISABLE 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP3_CLOCK_PM_ENABLE 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP3_SURPRISE_DOWN_ERROR_REPORTING 19:19 /* C--VF */
#define NV_XVE_VF_PCIE_CAP3_SURPRISE_DOWN_ERROR_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP3_DLL_ACTIVE_REPORTING 20:20 /* C--VF */
#define NV_XVE_VF_PCIE_CAP3_DLL_ACTIVE_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP3_LINK_BANDWIDTH_NOTIFICATION 21:21 /* C--VF */
#define NV_XVE_VF_PCIE_CAP3_LINK_BANDWIDTH_NOTIFICATION_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP3_ASPM_OPTIONALITY_COMPLIANCE 22:22 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP3_ASPM_OPTIONALITY_COMPLIANCE_SUPPORTED 0x00000001 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP3_ASPM_OPTIONALITY_COMPLIANCE_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP3_PORT_NUMBER 31:24 /* R-XVF */
#define NV_XVE_VF_PCIE_CAP4 0x00000050 /* R--4R */
#define NV_XVE_VF_PCIE_CAP4_ACTIVE_STATE_LINK_PM_CONTROL 1:0 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP4_ACTIVE_STATE_LINK_PM_CONTROL_INIT 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP4_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_DISABLE 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_ENABLE 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_DISABLE 0x00000002 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_ENABLE 0x00000003 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_READ_COMPLETION_BOUNDARY 3:3 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_READ_COMPLETION_BOUNDARY_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP4_READ_COMPLETION_BOUNDARY_64B 0x00000000 /* ----V */
#define NV_XVE_VF_PCIE_CAP4_READ_COMPLETION_BOUNDARY_128B 0x00000001 /* ----V */
#define NV_XVE_VF_PCIE_CAP4_LINK_DISABLE 4:4 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_LINK_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP4_RETRAIN_LINK 5:5 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_RETRAIN_LINK_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP4_COMMON_CLOCK_CONFIGURATION 6:6 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP4_COMMON_CLOCK_CONFIGURATION_INIT 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP4_EXTENDED_SYNCH 7:7 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP4_EXTENDED_SYNCH_INIT 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP4_CLOCK_PM 8:8 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP4_CLOCK_PM_INIT 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP4_HW_AUTO_WIDTH_DISABLE 9:9 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP4_HW_AUTO_WIDTH_DISABLE_INIT 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP4_LINK_BANDWIDTH_MANAGEMENT_INTR_EN 10:10 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_LINK_BANDWIDTH_MANAGEMENT_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP4_LINK_AUTO_BANDWIDTH_INTR_EN 11:11 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_LINK_AUTO_BANDWIDTH_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP4_LINK_SPEED 19:16 /* R--VF */
#define NV_XVE_VF_PCIE_CAP4_LINK_SPEED_DEFAULT 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_LINK_SPEED_2P5 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_LINK_SPEED_5P0 0x00000002 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_LINK_SPEED_8P0 0x00000003 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_NEGOTIATED_LINK_WIDTH 25:20 /* R--VF */
#define NV_XVE_VF_PCIE_CAP4_NEGOTIATED_LINK_WIDTH_DEFAULT 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_NEGOTIATED_LINK_WIDTH_X1 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_NEGOTIATED_LINK_WIDTH_X2 0x00000002 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_NEGOTIATED_LINK_WIDTH_X4 0x00000004 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_NEGOTIATED_LINK_WIDTH_X8 0x00000008 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_NEGOTIATED_LINK_WIDTH_X16 0x00000010 /* R---V */
#define NV_XVE_VF_PCIE_CAP4_RSVD 26:26 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP4_LINK_TRAINING 27:27 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP4_LINK_TRAINING_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP4_SLOT_CLOCK_CONFIG 28:28 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP4_SLOT_CLOCK_CONFIG_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP4_DLL_ACTIVE 29:29 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP4_DLL_ACTIVE_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP4_LINK_BANDWIDTH_MANAGEMENT 30:30 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_LINK_BANDWIDTH_MANAGEMENT_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP4_LINK_AUTO_BANDWIDTH 31:31 /* C--VF */
#define NV_XVE_VF_PCIE_CAP4_LINK_AUTO_BANDWIDTH_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5 0x00000064 /* R--4R */
#define NV_XVE_VF_PCIE_CAP5_CPL_TIMEOUT_RANGES 3:0 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_CPL_TIMEOUT_RANGES_A_AND_B 0x00000003 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_CPL_TIMEOUT_DISABLE 4:4 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP5_CPL_TIMEOUT_DISABLE_SUPPORTED 0x00000001 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP5_ARI_FORWARDING 5:5 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_ARI_FORWARDING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_ATOMIC_OP_ROUTING 6:6 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_ATOMIC_OP_ROUTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_ATOMIC_COMPLETER_32BIT 7:7 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_ATOMIC_COMPLETER_64BIT 8:8 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_CAS_COMPLETER_128BIT 9:9 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_LATENCY_TOLERANCE_REPORTING 11:11 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_LATENCY_TOLERANCE_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_LATENCY_TOLERANCE_REPORTING_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE_VF_PCIE_CAP5_TPH_COMPLETER 13:12 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_TPH_COMPLETER_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_10_BIT_TAG_COMPLETER 16:16 /* R--VF */
#define NV_XVE_VF_PCIE_CAP5_10_BIT_TAG_COMPLETER_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_10_BIT_TAG_COMPLETER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_10_BIT_TAG_REQUESTER 17:17 /* R--VF */
#define NV_XVE_VF_PCIE_CAP5_10_BIT_TAG_REQUESTER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_10_BIT_TAG_REQUESTER_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_OBFF 19:18 /* R--VF */
#define NV_XVE_VF_PCIE_CAP5_OBFF_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_OBFF_SUPPORTED_MSG_SGNL 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_OBFF_SUPPORTED_WAKE_SGNL 0x00000002 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_OBFF_SUPPORTED_MSG_WAKE_SGNL 0x00000003 /* R---V */
#define NV_XVE_VF_PCIE_CAP5_EXTENDED_FMT 20:20 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_EXTENDED_FMT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_END_END_TLP_PREFIX 21:21 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_END_END_TLP_PREFIX_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_MAX_END_END_TLP_PREFIX 23:22 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_MAX_END_END_TLP_PREFIX_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP5_BITS 31:24 /* C--VF */
#define NV_XVE_VF_PCIE_CAP5_BITS_0 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6 0x00000068 /* R--4R */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_VAL 3:0 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_VAL_RANGE_A_LO 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_VAL_RANGE_A_HI 0x00000002 /* R---V */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_VAL_RANGE_B_LO 0x00000005 /* R---V */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_VAL_RANGE_B_HI 0x00000006 /* R---V */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_VAL_RANGE_DEFAULT 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_DISABLE 4:4 /* R-IVF */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_DISABLE_ENABLED 0x00000000 /* R-I-V */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_DISABLE_DISABLED 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP6_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP6_ARI_FORWARDING_ENABLE 5:5 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_ARI_FORWARDING_ENABLE_NA 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_ATOMIC_OP_REQUESTER_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_ATOMIC_OP_EGRESS_BLOCKING 7:7 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_ATOMIC_OP_EGRESS_BLOCKING_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_IDO_REQUEST_ENABLE 8:8 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_IDO_REQUEST_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_IDO_COMPLETION_ENABLE 9:9 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_IDO_COMPLETION_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_LTR_ENABLE 10:10 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_LTR_ENABLE_NA 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_10BIT_TAG_REQUESTER_ENABLE 12:12 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_10BIT_TAG_REQUESTER_ENABLE_UNSET 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_OBFF_ENABLE 14:13 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_OBFF_ENABLE_UNSET 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP6_END_END_TLP_PREFIX_BLOCKING 21:21 /* C--VF */
#define NV_XVE_VF_PCIE_CAP6_END_END_TLP_PREFIX_BLOCKING_NA 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP7 0x0000006C /* R--4R */
#define NV_XVE_VF_PCIE_CAP7_RSVD 0:0 /* C--VF */
#define NV_XVE_VF_PCIE_CAP7_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP7_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP7_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */
#define NV_XVE_VF_PCIE_CAP7_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */
#define NV_XVE_VF_PCIE_CAP7_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */
#define NV_XVE_VF_PCIE_CAP7_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP7_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3_GEN4 0x0000000F /* R---V */
#define NV_XVE_VF_PCIE_CAP7_CROSS_LINK_SUPPORT 8:8 /* C--VF */
#define NV_XVE_VF_PCIE_CAP7_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP7_RET_PRESENCE_DET_SUPP 23:23 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP7_RET_PRESENCE_DET_SUPP_SET 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP7_2RET_PRESENCE_DET_SUPP 24:24 /* R-EVF */
#define NV_XVE_VF_PCIE_CAP7_2RET_PRESENCE_DET_SUPP_SET 0x00000000 /* R-E-V */
#define NV_XVE_VF_PCIE_CAP7_RSVD1 31:25 /* C--VF */
#define NV_XVE_VF_PCIE_CAP7_RSVD1_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP8 0x00000070 /* R--4R */
#define NV_XVE_VF_PCIE_CAP8_CTRL_TARGET_LINK_SPEED 3:0 /* R-CVF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_TARGET_LINK_SPEED_INIT 0x00000003 /* R-C-V */
#define NV_XVE_VF_PCIE_CAP8_CTRL_ENTER_COMPLIANCE 4:4 /* R-CVF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_ENTER_COMPLIANCE_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_PCIE_CAP8_CTRL_HW_AUTO_SPEED_DISABLE 5:5 /* R-CVF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_HW_AUTO_SPEED_DISABLE_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_PCIE_CAP8_CTRL_SELECTABLE_DEEMPHASIS 6:6 /* C--VF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_SELECTABLE_DEEMPHASIS_RSVD 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP8_CTRL_TRANSMIT_MARGIN 9:7 /* R-CVF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_TRANSMIT_MARGIN_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_PCIE_CAP8_CTRL_ENTER_MODIFIED_COMPLIANCE 10:10 /* R-CVF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_ENTER_MODIFIED_COMPLIANCE_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_PCIE_CAP8_CTRL_COMPLIANCE_SOS 11:11 /* R-CVF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_COMPLIANCE_SOS_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_PCIE_CAP8_CTRL_COMPLIANCE_PRESET_DEEMPHASIS 15:12 /* R-CVF */
#define NV_XVE_VF_PCIE_CAP8_CTRL_COMPLIANCE_PRESET_DEEMPHASIS_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_PCIE_CAP8_CUR_DEEMPHASIS_LEVEL 16:16 /* R--VF */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_COMPLETE 17:17 /* C--VF */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_COMPLETE_NOT_DONE 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_PHASE1_SUCCESSFUL 18:18 /* C--VF */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_PHASE1_SUCCESSFUL_NOT_DONE 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_PHASE2_SUCCESSFUL 19:19 /* C--VF */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_PHASE2_SUCCESSFUL_NOT_DONE 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_PHASE3_SUCCESSFUL 20:20 /* C--VF */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_PHASE3_SUCCESSFUL_NOT_DONE 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_REQUEST 21:21 /* C--VF */
#define NV_XVE_VF_PCIE_CAP8_EQUALIZATION_REQUEST_NOT_SET 0x00000000 /* C---V */
#define NV_XVE_VF_PCIE_CAP8_RSVD 31:25 /* C--VF */
#define NV_XVE_VF_PCIE_CAP8_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_MSIX_CAP_HDR 0x0000007C /* RW-4R */
#define NV_XVE_VF_MSIX_CAP_HDR_ENABLE 31:31 /* RWIVF */
#define NV_XVE_VF_MSIX_CAP_HDR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE_VF_MSIX_CAP_HDR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE_VF_MSIX_CAP_HDR_FUNCTION_MASK 30:30 /* RWIVF */
#define NV_XVE_VF_MSIX_CAP_HDR_FUNCTION_MASK_MASKED 0x00000001 /* RW--V */
#define NV_XVE_VF_MSIX_CAP_HDR_FUNCTION_MASK_UNMASKED 0x00000000 /* RWI-V */
#define NV_XVE_VF_MSIX_CAP_HDR_RSVD 29:27 /* C--VF */
#define NV_XVE_VF_MSIX_CAP_HDR_RSVD_VAL 0x00000000 /* C---V */
#define NV_XVE_VF_MSIX_CAP_HDR_TABLE_SIZE 26:16 /* R-IVF */
#define NV_XVE_VF_MSIX_CAP_HDR_TABLE_SIZE_VF 189 /* R-I-V */
#define NV_XVE_VF_MSIX_CAP_HDR_NXT_PTR 15:8 /* C--VF */
#define NV_XVE_VF_MSIX_CAP_HDR_NXT_PTR_NULL 0x00000000 /* C---V */
#define NV_XVE_VF_MSIX_CAP_HDR_CAP_ID 7:0 /* C--VF */
#define NV_XVE_VF_MSIX_CAP_HDR_CAP_ID_MSIX 0x00000011 /* C---V */
#define NV_XVE_VF_MSIX_CAP_TABLE 0x00000080 /* R--4R */
#define NV_XVE_VF_MSIX_CAP_TABLE_OFFSET 31:0 /* R--VF */
#define NV_XVE_VF_MSIX_CAP_TABLE_OFFSET_VALUE 0x00010000 /* R---V */
#define NV_XVE_VF_MSIX_CAP_TABLE_BIR 2:0 /* R--VF */
#define NV_XVE_VF_MSIX_CAP_TABLE_BIR_BAR0 0x00000000 /* R---V */
#define NV_XVE_VF_MSIX_CAP_PBA 0x00000084 /* R--4R */
#define NV_XVE_VF_MSIX_CAP_PBA_OFFSET 31:0 /* R--VF */
#define NV_XVE_VF_MSIX_CAP_PBA_OFFSET_VALUE 0x00020000 /* R---V */
#define NV_XVE_VF_MSIX_CAP_PBA_BIR 2:0 /* R--VF */
#define NV_XVE_VF_MSIX_CAP_PBA_BIR_BAR0 0x00000000 /* R---V */
#define NV_XVE_VF_AER_CAP0_HDR 0x00000140 /* R--4R */
#define NV_XVE_VF_AER_CAP0_HDR_ID 15:0 /* C--VF */
#define NV_XVE_VF_AER_CAP0_HDR_ID_LINK_DEC 0x00000001 /* C---V */
#define NV_XVE_VF_AER_CAP0_HDR_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_VF_AER_CAP0_HDR_ID_VERSION_2 0x00000002 /* C---V */
#define NV_XVE_VF_AER_CAP0_HDR_ID_NEXT_PTR 31:20 /* C--VF */
#define NV_XVE_VF_AER_CAP0_HDR_ID_NEXT_PTR_NONE 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS 0x00000144 /* RW-4R */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_POISONED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_POISONED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_POISONED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_ABORT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_ABORT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_CPL_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNEXP_CPL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNEXP_CPL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNEXP_CPL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNSUPPORTED_REQ_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNSUPPORTED_REQ_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP1_UNCORR_ERR_STATUS_UNSUPPORTED_REQ_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK 0x00000148 /* C--4R */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_POISONED_TLP 12:12 /* C--VF */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_POISONED_TLP_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_CPL_TIMEOUT 14:14 /* C--VF */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_CPL_TIMEOUT_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_CPL_ABORT 15:15 /* C--VF */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_CPL_ABORT_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_UNEXP_CPL 16:16 /* C--VF */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_UNEXP_CPL_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_UNSUPPORTED_REQ 20:20 /* C--VF */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_UNSUPPORTED_REQ_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_VF_AER_CAP2_UNCORR_ERR_MASK_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR 0x0000014C /* C--4R */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_POISONED_TLP 12:12 /* C--VF */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_POISONED_TLP_NON_FATAL 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_CPL_TIMEOUT 14:14 /* C--VF */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_CPL_TIMEOUT_NON_FATAL 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_CPL_ABORT 15:15 /* C--VF */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_CPL_ABORT_NON_FATAL 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_UNEXP_CPL 16:16 /* C--VF */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_UNEXP_CPL_NON_FATAL 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_UNSUPPORTED_REQ 20:20 /* C--VF */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_NON_FATAL 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE_VF_AER_CAP3_UNCORR_ERR_SEVR_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS 0x00000150 /* RW-4R */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_HEADER_LOG_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_HEADER_LOG_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XVE_VF_AER_CAP4_CORR_ERR_STATUS_HEADER_LOG_OVERFLOW_CLEAR 0x00000001 /* -W--C */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK 0x00000154 /* C--4R */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_RCV_ERR 0:0 /* C--VF */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_RCV_ERR_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_BAD_TLP 6:6 /* C--VF */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_BAD_TLP_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_BAD_DLLP 7:7 /* C--VF */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_BAD_DLLP_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_RPLY_ROLLOVER 8:8 /* C--VF */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_RPLY_ROLLOVER_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_RPLY_TIMEOUT 12:12 /* C--VF */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_RPLY_TIMEOUT_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_ADVISORY_NONFATAL 13:13 /* C--VF */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_ADVISORY_NONFATAL_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_HEADER_LOG_OVERFLOW 15:15 /* C--VF */
#define NV_XVE_VF_AER_CAP5_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_NOT_MASKED 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP6_CNTL_REG 0x00000158 /* R--4R */
#define NV_XVE_VF_AER_CAP6_CNTL_REG_ERR_PTR 4:0 /* R--VF */
#define NV_XVE_VF_AER_CAP6_CNTL_REG_ECRC_GEN_EN 6:6 /* C--VF */
#define NV_XVE_VF_AER_CAP6_CNTL_REG_ECRC_GEN_EN_FALSE 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP6_CNTL_REG_ECRC_CHK_EN 8:8 /* C--VF */
#define NV_XVE_VF_AER_CAP6_CNTL_REG_ECRC_CHK_EN_FALSE 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP6_CNTL_REG_MULTIPLE_HDR_RECORDING_EN 10:10 /* C--VF */
#define NV_XVE_VF_AER_CAP6_CNTL_REG_MULTIPLE_HDR_RECORDING_EN_FALSE 0x00000000 /* C---V */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW0 0x0000015C /* R--4R */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW0_0 31:0 /* R-CVF */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW0_0_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW1 0x00000160 /* R--4R */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW1_1 31:0 /* R-CVF */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW1_1_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW2 0x00000164 /* R--4R */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW2_2 31:0 /* R-CVF */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW2_2_INIT 0x00000000 /* R-C-V */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW3 0x00000168 /* R--4R */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW3_3 31:0 /* R-IVF */
#define NV_XVE_VF_AER_CAP7_HDR_LOG_DW3_3_INIT 0x00000000 /* R-I-V */
#define NV_XVE_VF_ARI_CAP0 0x00000100 /* R--4R */
#define NV_XVE_VF_ARI_CAP0_CAPID 15:0 /* C--VF */
#define NV_XVE_VF_ARI_CAP0_CAPID_EXT_CAP 0x0000000E /* C---V */
#define NV_XVE_VF_ARI_CAP0_HDR0_ID_VERSION 19:16 /* C--VF */
#define NV_XVE_VF_ARI_CAP0_HDR0_ID_VERSION_1 0x00000001 /* C---V */
#define NV_XVE_VF_ARI_CAP0_HDR0_ID_NEXT_PTR 31:20 /* C--VF */
#define NV_XVE_VF_ARI_CAP0_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* C---V */
#define NV_XVE_VF_ARI_CAP1 0x00000104 /* R--4R */
#define NV_XVE_VF_ARI_CAP1_MFVC_FN_GRPS_CAP 0:0 /* C--VF */
#define NV_XVE_VF_ARI_CAP1_MFVC_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE_VF_ARI_CAP1_ACS_FN_GRPS_CAP 1:1 /* C--VF */
#define NV_XVE_VF_ARI_CAP1_ACS_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE_VF_ARI_CAP1_NXT_FN_NUM 15:8 /* C--VF */
#define NV_XVE_VF_ARI_CAP1_NXT_FN_NUM_VAL 0x00000001 /* C---V */
#define NV_XVE_VF_ARI_CAP1_MFVC_FN_GRPS_EN 16:16 /* C--VF */
#define NV_XVE_VF_ARI_CAP1_MFVC_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE_VF_ARI_CAP1_ACS_FN_GRPS_EN 17:17 /* C--VF */
#define NV_XVE_VF_ARI_CAP1_ACS_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE_VF_ARI_CAP1_FN_GRP 22:20 /* C--VF */
#define NV_XVE_VF_ARI_CAP1_FN_GRP_ZERO 0x00000000 /* C---V */
#endif // __ga102_dev_nv_xve3g_vf_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nvlphyctl_ip_h__
#define __ga102_dev_nvlphyctl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLPHYCTL 0x00002DFF:0x00002800 /* RW--D */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0 0x00002b10 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1 0x00002b14 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPHYCTL_COMMON_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8 0x00002800 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_ABORT_LEN 11:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_ABORT_LEN_INIT 0x00000376 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_S2T_DIS 12:12 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_S2T_DIS_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_T2S_DIS 13:13 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_T2S_DIS_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_DELAY 24:14 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_DELAY_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_LEN 31:25 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_LEN_INIT 0x00000054 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_8_RX_EQ_RESET_LEN_MINIMUM 0x0000002d /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7 0x00002818 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAREADY 7:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAREADY_INIT 0x00000082 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_DATAREADY 15:8 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_DATAREADY_INIT 0x00000055 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAEN 23:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_SLEEP_DATAEN_INIT 0x00000082 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_SLEEP 31:24 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_7_DATAEN_SLEEP_INIT 0x00000055 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6 0x0000281c /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6__PRIV_LEVEL_MASK 0x00002b14 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL 0:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_RXCAL_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN 3:3 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_NOT_COMPLETE 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_INIT_TRAIN_COMPLETE 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY 26:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_ZERO 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL 31:27 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_6_CDR_EN_DELAY_SCL_ZERO 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0 0x00002820 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_IDDQ_DIS 0:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_IDDQ_DIS_SLEEP 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_IDDQ_DIS_WAKE 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_SLEEP_DIS 1:1 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_SLEEP_DIS_SLEEP 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_SLEEP_DIS_WAKE 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_READY 3:3 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_READY_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_READY_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_EN 4:4 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_TX_DATA_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RXCAL_OVERLAP 8:8 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RXCAL_OVERLAP_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RXCAL_OVERLAP_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_IDDQ_DIS 9:9 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_IDDQ_DIS_SLEEP 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_IDDQ_DIS_WAKE 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_SLEEP_DIS 10:10 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_SLEEP_DIS_SLEEP 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_SLEEP_DIS_WAKE 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_DATA_EN 11:11 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_DATA_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_0_RX_DATA_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1 0x00002824 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_SETUP 7:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_SETUP_INIT 0x00000013 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_HOLD 15:8 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_HOLD_INIT 0x00000013 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_STROBE_PULSE 23:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_STROBE_PULSE_INIT 0x00000034 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_READ_DELAY 31:24 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_1_CFG_READ_DELAY_INIT 0x00000013 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2 0x00002828 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_IDDQ_SLEEP 7:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_IDDQ_SLEEP_INIT 0x00000055 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_IDDQ 15:8 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_IDDQ_INIT 0x00000015 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_RXCAL 23:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_SLEEP_RXCAL_INIT 0x00000082 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_DATAREADY_SLEEP 31:24 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_2_DATAREADY_SLEEP_INIT 0x00000055 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3 0x0000282c /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_IDDQ_STEP 7:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_IDDQ_STEP_MINIMUM 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP 15:8 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP_INIT 0x0000003c /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP_MINIMUM 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_SLEEP_STEP_MAXIMUM 0x000000ff /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_STEP 23:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_STEP_INIT 0x00000027 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_STEP_MINIMUM 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_DATAEN 31:24 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_3_RXCAL_DATAEN_MINIMUM 0x00000055 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4 0x00002830 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP 7:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP_INIT 0x0000003c /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP_MAXIMUM 0x000000ff /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAREADY_STEP_MINIMUM 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP 15:8 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP_INIT 0x0000003c /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP_MAXIMUM 0x000000ff /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_DATAEN_STEP_MINIMUM 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_EN_DONE 23:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_EN_DONE_INIT 0x0000003c /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_4_EN_DONE_MINIMUM 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_5 0x00002834 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_5__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_5_DATAREADY_DATAEN 15:8 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_CFG_CTL_5_DATAREADY_DATAEN_INIT 0x00000055 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0 0x00002838 /* R--4R */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0__PRIV_LEVEL_MASK 0x00002b14 /* */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_IDDQ_DIS_STS 0:0 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_SLEEP_DIS_STS 1:1 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RXCAL_DONE 2:2 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_READY_STS 3:3 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_TX_DATA_EN_STS 4:4 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_IDDQ_DIS_STS 5:5 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_SLEEP_DIS_STS 6:6 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_0_RX_DATA_EN_STS 7:7 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1 0x0000283c /* R--4R */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1__PRIV_LEVEL_MASK 0x00002b14 /* */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L0_BUSY 0:0 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L1_BUSY 1:1 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L2_BUSY 2:2 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L3_BUSY 3:3 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_CFG_L4_BUSY 4:4 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_RXEQ_DONE 19:16 /* R--VF */
#define NV_NVLPHYCTL_COMMON_CFG_STATUS_1_RXCAL_DONE 27:24 /* R--VF */
#define NV_NVLPHYCTL_COMMON_SPARE(i) (0x00002a80+(i)*0x4) /* RW-4A */
#define NV_NVLPHYCTL_COMMON_SPARE__SIZE_1 1 /* */
#define NV_NVLPHYCTL_COMMON_SPARE__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_SPARE_INIT_TRAIN_HW_CLEAR 0:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_SPARE_INIT_TRAIN_HW_CLEAR_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_SPARE_INIT_TRAIN_HW_CLEAR_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_SPARE_CYA_BUG_2706432 1:1 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_SPARE_CYA_BUG_2706432_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_SPARE_CYA_BUG_2706432_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_SPARE_FIELD 31:2 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_SPARE_FIELD_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_MULTICAST 0x00002b00 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_MULTICAST__PRIV_LEVEL_MASK 0x00002b14 /* */
#define NV_NVLPHYCTL_COMMON_MULTICAST_LANE_ENABLE 3:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_MULTICAST_LANE_ENABLE_INIT 0x0000000f /* RWE-V */
#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE 17:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_LOW_SELECTED_BUS 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_OR_ALL_BUSSES 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_AND_ALL_BUSSES 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_COMMON_MULTICAST_READ_MODE_ZEROS 0x00000003 /* RW--V */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0 0x00002b20 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0_DATA 31:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM0_DATA_INIT 0x0000baad /* RWE-V */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1 0x00002b24 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1__PRIV_LEVEL_MASK 0x00002b14 /* */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1_DATA 31:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_SCRATCH_PRIVMASK_COM1_DATA_INIT 0x0000baad /* RWE-V */
#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM 0x00002b30 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM__PRIV_LEVEL_MASK 0x00002b14 /* */
#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM_DATA 31:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_SCRATCH_WARM_COM_DATA_INIT 0x0000baad /* RWE-V */
#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM 0x00002b34 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM_DATA 31:0 /* RWIVF */
#define NV_NVLPHYCTL_COMMON_SCRATCH_COLD_COM_DATA_INIT 0x0000baad /* RWI-V */
#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL 0x00002b80 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE 3:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_32_CLKS 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_64_CLKS 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_128_CLKS 0x00000002 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_UPHYDS_TICK_CTRL_TIMER_BASE_256_CLKS 0x00000003 /* RW--V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG 0x00002b84 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TWAIT 15:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TWAIT_INIT 0x0000030d /* RWE-V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TPOLL 31:16 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CFG_TPOLL_INIT 0x0000011c /* RWE-V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL 0x00002b88 /* RW-4R */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL_MAX_ATTEMPTS 3:0 /* RWEVF */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL_MAX_ATTEMPTS_INIT 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_CTRL_MAX_ATTEMPTS_INFINITE 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS 0x00002b8c /* R--4R */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS__PRIV_LEVEL_MASK 0x00002b10 /* */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_ATTEMPT_COUNT 3:0 /* R-XVF */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_LANESFOUND 11:8 /* R--VF */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_LANESFOUND_NONE 0x00000000 /* R---V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_LANESFOUND_ALL 0x0000000f /* R---V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS 29:28 /* R--VF */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_INIT 0x00000000 /* R---V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_SEARCH 0x00000001 /* R---V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_FOUND 0x00000002 /* R---V */
#define NV_NVLPHYCTL_COMMON_LINK_RXDET_STATUS_STS_TIMEOUT 0x00000003 /* R---V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0(i) (0x00002868+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1(i) (0x0000286c+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1(i) (0x00002840+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ 0:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_PWR_UP 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_PWR_DOWN 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_OVRD 1:1 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_TERM_EN 2:2 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_TERM_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_TERM_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_EN 3:3 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_BYP 4:4 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_BYP_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_BYP_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_RDET_STATUS 6:6 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_MODE_OVRD 7:7 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_MODE_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_TX_MODE_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_MODE_OVRD 8:8 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_MODE_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_MODE_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_STATUS 15:14 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ 16:16 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_PWR_UP 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_PWR_DOWN 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_OVRD 17:17 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_EN 18:18 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_MODE 19:19 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_MODE_OHM50 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_TERM_MODE_OHM10K 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE 21:20 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE_HIGH_FREQ 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE_LOW_FREQ 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_MODE_DC 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_EN 22:22 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_TH 25:24 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_TH_NOMINAL 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_BYP 26:26 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_BYP_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_AUX_RX_IDLE_BYP_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_CFG_RESET 30:30 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_CFG_RESET_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_CFG_RESET_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_LANE_RESET 31:31 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_LANE_RESET_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_1_LANE_RESET_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2(i) (0x00002844+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ 0:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_PWR_UP 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_PWR_DOWN 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_OVRD 1:1 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP 5:4 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_PWR_DOWN 0x00000003 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_P2 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_P1 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_SLEEP_PWR_UP 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_READY 6:6 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_READY_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_READY_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_EN 7:7 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_DATA_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ 8:8 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_PWR_UP 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_PWR_DOWN 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_OVRD 9:9 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_IDDQ_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP 13:12 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_PWR_DOWN 0x00000003 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_P2 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_P1 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_SLEEP_PWR_UP 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_DATA_EN 15:15 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_DATA_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_DATA_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_PWR_OVRD 20:20 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_PWR_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_PWR_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_PWR_OVRD 21:21 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_PWR_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_PWR_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID 26:24 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_OVRD 27:27 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_TX_RATE_ID_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID 30:28 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_OVRD 31:31 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_2_RX_RATE_ID_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3(i) (0x00002848+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_DATA 1:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_DATA_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_DATA_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_READY 2:2 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_READY_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_READY_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_MODE 4:3 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_MODE_DIFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_MODE_SGL_END 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_OVRD 5:5 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_RATE_ID 8:6 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_RATE_ID_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_DATA 10:9 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE 12:11 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE_DIFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE_SGL_END 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_MODE_PWM_DIFF 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_EN 13:13 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_OVRD 14:14 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_BYP_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC 15:15 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OVRD 16:16 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_SYNC_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD 18:17 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_HOLD 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_ECTL 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_HSCTL 0x00000002 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_EOM_STATUS_MASK 19:19 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_EOM_STATUS_MASK_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_EN 20:20 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_HS_ACT_OVRD_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_EN 21:21 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_OVRD 23:23 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_CDR_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_EN 24:24 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_EN_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_EN_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_OVRD 27:27 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_RX_TERM_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_LOOP_OFF 28:28 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_LOOP_OFF_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_EN 29:29 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_EN_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_OVRD 30:30 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_PRECODE_OVRD_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_EN 31:31 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_3_TX_BYP_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4(i) (0x0000284c+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN 0:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_DONE 1:1 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN 4:4 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_TRAIN_DONE 5:5 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_DONE 9:9 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD 12:12 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_CAL_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD 13:13 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EQ_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD 14:14 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN 15:15 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_PRECODE_INV_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_4_RX_EOM_STATUS 31:16 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_5(i) (0x00002850+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_5__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_5__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_5_MISC_CTRL 7:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_5_MISC_CTRL_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_5_MISC_OUT 23:16 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6(i) (0x00002854+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDATA 15:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDATA_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_ADDR 25:16 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_SECURE 29:29 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_SECURE_INIT 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDS 30:30 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDS_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_WDS_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_RDS 31:31 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_RDS_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_6_CFG_RDS_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_7(i) (0x00002858+(i)*0x40) /* R--4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_7__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_7__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_7_CFG_RDATA 15:0 /* R--VF */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1(i) (0x00002860+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPOST 5:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPOST_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE1 11:8 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE1_INIT 0x00000004 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE2 18:16 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_FIR_CPRE2_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_RESERVED 23:23 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_RESERVED_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_AMP 29:24 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_ECTL_1_TX_DRV_AMP_INIT 0x00000027 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8(i) (0x00002864+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1 /* */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD 0:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN 1:1 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EOM_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE 27:27 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_TRAIN_MODE_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD 28:28 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD 29:29 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET 30:30 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_RX_EQ_RESET_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET 31:31 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_OFF 0x00000000 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_CTL_8_CDR_RESET_ON 0x00000001 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1(i) (0x00002870+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPOST 5:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPOST_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE1 11:8 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE1_INIT 0x00000004 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE2 18:16 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_FIR_CPRE2_INIT 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_PRECODE_EN 23:23 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_PRECODE_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_PRECODE_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_AMP 29:24 /* RWEVF */
#define NV_NVLPHYCTL_LANE_PAD_HSCTL_1_TX_DRV_AMP_INIT 0x00000027 /* RWE-V */
#define NV_NVLPHYCTL_LANE_SCRATCH_WARM(i) (0x00002874+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_SCRATCH_WARM__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_SCRATCH_WARM__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK1 /* */
#define NV_NVLPHYCTL_LANE_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NVLPHYCTL_LANE_SCRATCH_WARM_DATA_INIT 0x0000baad /* RWE-V */
#define NV_NVLPHYCTL_LANE_SCRATCH_COLD(i) (0x00002878+(i)*0x40) /* RW-4A */
#define NV_NVLPHYCTL_LANE_SCRATCH_COLD__SIZE_1 5 /* */
#define NV_NVLPHYCTL_LANE_SCRATCH_COLD__PRIV_LEVEL_MASK NV_NVLPHYCTL_LANE_PRIV_LEVEL_MASK0 /* */
#define NV_NVLPHYCTL_LANE_SCRATCH_COLD_DATA 31:0 /* RWIVF */
#define NV_NVLPHYCTL_LANE_SCRATCH_COLD_DATA_INIT 0x0000baad /* RWI-V */
#endif // __ga102_dev_nvlphyctl_ip_h__

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include/ampere/ga102/dev_nvlpllctl_ip.h Normal file
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@@ -0,0 +1,664 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nvlpllctl_ip_h__
#define __ga102_dev_nvlpllctl_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_NVLPLLCTL 0x000007FF:0x00000000 /* RW--D */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0 0x00000500 /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1 0x00000504 /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2 0x00000508 /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3 0x0000050c /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4 0x00000510 /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5 0x00000514 /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6 0x00000518 /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask6" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7 0x0000051c /* RW-4R */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1 0x00000000 /* RW-4R */
#define NV_NVLPLLCTL_PLL_CTL_1__PRIV_LEVEL_MASK 0x00000500 /* */
#define NV_NVLPLLCTL_PLL_CTL_1_IDDQ 0:0 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_IDDQ_PWR_DOWN 0x00000001 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_IDDQ_PWR_UP 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_SLEEP 2:1 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_SLEEP_PWR_DOWN 0x00000003 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_SLEEP_PWR_UP 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_ENABLE 3:3 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_ENABLE_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_ENABLE_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_PWR_OVRD 4:4 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_PWR_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_PWR_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_CFG_SEL 6:6 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_CFG_SEL_EXTERNAL 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_CFG_SEL_INTERNAL 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_BYPASS_EN 7:7 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_BYPASS_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_BYPASS_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID 10:8 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_SYM16 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_OVRD 11:11 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_LOCKDET_STATUS 15:15 /* R--VF */
#define NV_NVLPLLCTL_PLL_CTL_1_LOCKDET_STATUS_UNLOCK 0x00000000 /* R---V */
#define NV_NVLPLLCTL_PLL_CTL_1_LOCKDET_STATUS_LOCK 0x00000001 /* R---V */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLKBUF_EN 16:16 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLKBUF_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLKBUF_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_CFG_BUSY 17:17 /* R--VF */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_DRV_EN 18:18 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_DRV_EN_INIT 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_TCLKOUT_EN 20:20 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_TCLKOUT_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_TCLKOUT_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_PLL_CFG_RESET 30:30 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_PLL_CFG_RESET_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_1_PLL_CFG_RESET_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_PLL_RESET 31:31 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_1_PLL_RESET_OFF 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_1_PLL_RESET_ON 0x00000001 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_2 0x00000004 /* RW-4R */
#define NV_NVLPLLCTL_PLL_CTL_2__PRIV_LEVEL_MASK 0x00000500 /* */
#define NV_NVLPLLCTL_PLL_CTL_2_CAL_EN 0:0 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_2_CAL_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_2_CAL_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_2_CAL_DONE 1:1 /* R--VF */
#define NV_NVLPLLCTL_PLL_CTL_2_CAL_OVRD 2:2 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_2_CAL_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_2_CAL_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_EN 12:12 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_OVRD 15:15 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_OVRD_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_OVRD_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE 20:16 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE_MINIMUM 0x00000000 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE_NOMINAL 0x00000007 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE_MAXIMUM 0x0000000f /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_EN 23:23 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_EN_OFF 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_EN_ON 0x00000001 /* RW--V */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_VAL 28:24 /* R--VF */
#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_DONE 31:31 /* R--VF */
#define NV_NVLPLLCTL_PLL_CTL_3 0x00000008 /* RW-4R */
#define NV_NVLPLLCTL_PLL_CTL_3__PRIV_LEVEL_MASK 0x00000500 /* */
#define NV_NVLPLLCTL_PLL_CTL_3_MISC_OUT 15:0 /* R-XVF */
#define NV_NVLPLLCTL_PLL_CTL_3_MISC_CTRL 31:16 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_3_MISC_CTRL_INIT 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_4 0x0000000c /* RW-4R */
#define NV_NVLPLLCTL_PLL_CTL_4__PRIV_LEVEL_MASK 0x00000500 /* */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDATA 15:0 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDATA_INIT 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_ADDR 25:16 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_SECURE 29:29 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_SECURE_INIT 0x00000001 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDS 30:30 /* -WEVF */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDS_OFF 0x00000000 /* -WE-V */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDS_ON 0x00000001 /* -W--V */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_RDS 31:31 /* -WEVF */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_RDS_OFF 0x00000000 /* -WE-V */
#define NV_NVLPLLCTL_PLL_CTL_4_CFG_RDS_ON 0x00000001 /* -W--V */
#define NV_NVLPLLCTL_PLL_CTL_5 0x00000010 /* R--4R */
#define NV_NVLPLLCTL_PLL_CTL_5__PRIV_LEVEL_MASK 0x00000504 /* */
#define NV_NVLPLLCTL_PLL_CTL_5_CFG_RDATA 15:0 /* R--VF */
#define NV_NVLPLLCTL_PLL_CTL_6 0x00000014 /* RW-4R */
#define NV_NVLPLLCTL_PLL_CTL_6__PRIV_LEVEL_MASK 0x00000508 /* */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_SETUP 7:0 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_SETUP_INIT 0x00000005 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_HOLD 15:8 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_HOLD_INIT 0x00000005 /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_STROBE_PULSE 23:16 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_STROBE_PULSE_INIT 0x0000000d /* RWE-V */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_READ_DELAY 31:24 /* RWEVF */
#define NV_NVLPLLCTL_PLL_CTL_6_CFG_READ_DELAY_INIT 0x00000005 /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_WARM 0x000007c0 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_WARM_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_COLD 0x000007c4 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_COLD_DATA 31:0 /* RWIVF */
#define NV_NVLPLLCTL_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0 0x000007d0 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00000500 /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1 0x000007d4 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00000504 /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2 0x000007d8 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00000508 /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3 0x000007dc /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000050c /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4 0x000007e0 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00000510 /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5 0x000007e4 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00000514 /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6 0x000007e8 /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00000518 /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7 0x000007ec /* RW-4R */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000051c /* */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
#endif // __ga102_dev_nvlpllctl_ip_h__

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@@ -0,0 +1,417 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_pri_ringmaster_h__
#define __ga102_dev_pri_ringmaster_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_MASTER 0x1203ff:0x120000 /* RW--D */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK 0x001200a4 /* RW-4R */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ring_priv_level_wr_secure" /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS(i) (0x00120000+(i)*4) /* RW-4A */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS__SIZE_1 8 /* */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0 1:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0_VW 0x00000002 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0_PRIV_RW_VW 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1 4:3 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1_PRIV_RW 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1_PRIV_RW_VW 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2 7:6 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2_PRIV_RW_VW 0x00000003 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3 10:9 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3_PRIV_RW_VW 0x00000003 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4 13:12 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4_PRIV_RW_VW 0x00000003 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5 16:15 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5_VW 0x00000002 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5_PRIV_RW_VW 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6 19:18 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6_PRIV_RW 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6_PRIV_RW_VW 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7 22:21 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7_PRIV_RW_VW 0x00000003 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8 25:24 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8_PRIV_RW_VW 0x00000003 /* RWB-V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9 28:27 /* RWBVF */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9_PRIV_RW 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9_VW 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9_PRIV_RW_VW 0x00000003 /* RWB-V */
#define NV_PPRIV_MASTER_RING_STATUS 0x00120040 /* R--4R */
#define NV_PPRIV_MASTER_RING_STATUS_TOTAL_RING_SLOTS (8-1):0 /* R--VF */
#define NV_PPRIV_MASTER_RING_STATUS_ASYNC_FIFO_ENTRIES_USED 13:8 /* R--VF */
#define NV_PPRIV_MASTER_RING_STATUS_RD_WR_TRANSACTIONS_USED (16+8-1):16 /* R--VF */
#define NV_PPRIV_MASTER_RING_STATUS_VW_TRANSACTIONS_USED (24+8-1):24 /* R--VF */
#define NV_PPRIV_MASTER_RING_LOOP_CONFIG 0x00120044 /* RW-4R */
#define NV_PPRIV_MASTER_RING_LOOP_CONFIG__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_LOOP_CONFIG_WATERMARK 5:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_LOOP_CONFIG_WATERMARK_INIT 0x00000012 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND 0x0012004c /* RW-4R */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 0x00000002 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 0x00000003 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_AND_START_RING 0x00000004 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_TAG_ENUMERATE_AND_START_RING 0x00000005 /* RW--T */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 9:6 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_GPC 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_FBP 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYS 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_L2 0x00000004 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYSC 0x00000006 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_ALL 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_GPC 0x00000009 /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_FBP 0x0000000a /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYS 0x0000000b /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_L2 0x0000000c /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYSC 0x0000000e /* RW--V */
#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x00120048 /* RW-4R */
#define NV_PPRIV_MASTER_RING_COMMAND_DATA_START_RING_SEED 7:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_COMMAND_DATA_START_RING_SEED_INIT 0x00000053 /* RWB-V */
#define NV_PPRIV_MASTER_RING_START_RESULTS 0x00120050 /* R--4R */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_FAIL 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x00120058 /* R--4R */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP 31:16 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS 8:8 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSC 10:10 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSC_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT 0:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT 1:1 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT 2:2 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT 3:3 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT 4:4 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x0012005c /* R--4R */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC 31:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC_V 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK 0x001200a0 /* RW-4R */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ring_reset_priv_level_wr_secure" /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x00120060 /* RW-4R */
#define NV_PPRIV_MASTER_RING_GLOBAL_CTL__PRIV_LEVEL_MASK 0x001200a0 /* */
#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_DEBUG_MASTER 0x00120064 /* R--4R */
#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_OUT_STATE 5:0 /* R--VF */
#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_ALIVE 6:6 /* R--VF */
#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_IDLE 7:7 /* R--VF */
#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_IN_STATE 13:8 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_CONFIG 0x001200b0 /* RW-4R */
#define NV_PPRIV_MASTER_RING_RUN_CONFIG_IDLE_REVOLUTIONS_UNTIL_SHUTDOWN 7:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_CONFIG_IDLE_REVOLUTIONS_UNTIL_SHUTDOWN_INIT 0x00000004 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS 0x001200b4 /* R--4R */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_IDLE_REVOLUTIONS 7:0 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_FECS_AUTO_SHUTDOWN 8:8 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_HOST_AUTO_SHUTDOWN 9:9 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_PMU_AUTO_SHUTDOWN 10:10 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_SHUTDOWN 11:11 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_SHUTDOWN_ENABLED 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_SHUTDOWN_DISABLED 0x00000000 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_WAKEUP 16:16 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_WAKEUP_ENABLED 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_WAKEUP_DISABLED 0x00000000 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE 27:24 /* R--VF */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_SHUTTING_DOWN 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_ASLEEP 0x00000002 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_WAKEUP 0x00000004 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_AWAKE 0x00000008 /* R---V */
#define NV_PPRIV_MASTER_RING_RUN_SET 0x001200b8 /* RW-4R */
#define NV_PPRIV_MASTER_RING_RUN_SET__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_RUN_SET_FECS_AUTO_SHUTDOWN 8:8 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_SET_FECS_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_SET_FECS_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_SET_HOST_AUTO_SHUTDOWN 9:9 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_SET_HOST_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_SET_HOST_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_SET_PMU_AUTO_SHUTDOWN 10:10 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_SET_PMU_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_SET_PMU_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_SET_AUTO_WAKEUP 16:16 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_SET_AUTO_WAKEUP_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_SET_AUTO_WAKEUP_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_WAKEUP 24:24 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_WAKEUP_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_WAKEUP_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_SHUTDOWN 25:25 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_SHUTDOWN_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR 0x001200bc /* RW-4R */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_FECS_AUTO_SHUTDOWN 8:8 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_FECS_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_FECS_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_HOST_AUTO_SHUTDOWN 9:9 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_HOST_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_HOST_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_PMU_AUTO_SHUTDOWN 10:10 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_PMU_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_PMU_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_AUTO_WAKEUP 16:16 /* RWBVF */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_AUTO_WAKEUP_NONE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_RUN_CLEAR_AUTO_WAKEUP_TRIGGER 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS 0x00120070 /* R--4R */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_COUNT 4:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_COUNT_NONE 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_C_COUNT 24:20 /* R-BVF */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_C_COUNT_NONE 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x00120074 /* R--4R */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT_NONE 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x00120078 /* R--4R */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT_NONE 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_L2 0x0012006c /* R--4R */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_L2_COUNT 4:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_L2_COUNT_NONE 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_SYS_INSTANCE 0x0012007c /* R--4R */
#define NV_PPRIV_MASTER_RING_SYS_INSTANCE_ID 3:0 /* R-BVF */
#define NV_PPRIV_MASTER_RING_SYS_INSTANCE_ID_NONE 0x0000000f /* R-B-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG 0x00120080 /* RW-4R */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD 3:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_NO_CMD 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H 0x00000002 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H 0x00000003 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_C1 0x00000004 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_C1 0x00000005 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H_C1 0x00000006 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H_C1 0x00000007 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_C2 0x00000008 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_C2 0x00000009 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H_C2 0x0000000a /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H_C2 0x0000000b /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_C1_C2 0x0000000c /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_C1_C2 0x0000000d /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H_C1_C2 0x0000000e /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H_C1_C2 0x0000000f /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_READ 0:0 /* RWBVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_READ_DISABLE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_READ_ENABLE 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_H 1:1 /* RWBVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_H_DISABLE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_H_ENABLE 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C1 2:2 /* RWBVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C1_DISABLE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C1_ENABLE 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C2 3:3 /* RWBVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C2_DISABLE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C2_ENABLE 0x00000001 /* RW--T */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS 5:4 /* R-BVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_NOMATCH 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY 0x00000002 /* R---V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_SUCCESS 0x00000003 /* R---V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS_BIT 4:4 /* R-BVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS_BIT_NOMATCH 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS_BIT_SUCCESS 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_BIT 5:5 /* R-BVF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_BIT_IDLE 0x00000000 /* R-B-V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_BIT_BUSY 0x00000001 /* R---V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM 9:8 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM_FALSE 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM_TRUE 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM_NOT 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION 11:10 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_FALSE 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_TRUE 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_NOT 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_GROUP 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION 13:12 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_FALSE 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_TRUE 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_NOT 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_GROUP 0x00000003 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV 15:14 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV_FALSE 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV_TRUE 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV_NOT 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE 17:16 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE_FALSE 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE_TRUE 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE_NOT 0x00000002 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_WHICH 18:18 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_WHICH_FIRST 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_WHICH_ALL 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_LOOP 19:19 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_LOOP_ONCE 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_LOOP_INF 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER 0x00120084 /* RW-4R */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_SLOT_NUM (8-1):0 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_TARGET_STATION (8+8-1):8 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_SENDING_STATION (16+8-1):16 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_RSV 25:24 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_PAYLOAD_TYPE 31:26 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER 0x00120088 /* RW-4R */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_SLOT_NUM (7-1):0 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_UNUSED (8-1):7 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_RAMCHAIN_SIZE 8:8 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_TARGET_STATION 16:9 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_PHYS_ADDR 17:17 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_IR 18:18 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_SENDING_STATION 26:19 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_LOCAL_ORDERING 27:27 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_RC 28:28 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_RSV 30:29 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_HI 0x00120094 /* RW-4R */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_HI__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_HI_PAYLOAD_TYPE 5:0 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1 0x0012008c /* RW-4R */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_REG_ID 23:0 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_SUB_ID 31:24 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_HI 0x00120098 /* RW-4R */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_HI__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_HI_PRIV_LEVEL 1:0 /* RW-VF */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE2 0x00120090 /* RW-4R */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE2__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE2_BITS 31:0 /* RW-VF */
#define NV_PPRIV_MASTER_CG1 0x001200a8 /* RW-4R */
#define NV_PPRIV_MASTER_CG1_SLCG 0:0 /* RWBVF */
#define NV_PPRIV_MASTER_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_CG1_SLCG_DISABLED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_CYA_SETTINGS 0x001200ac /* RW-4R */
#define NV_PPRIV_MASTER_CYA_SETTINGS__PRIV_LEVEL_MASK 0x001200a4 /* */
#define NV_PPRIV_MASTER_CYA_SETTINGS_VWIRE_NO_WAKEUP 0:0 /* RWBVF */
#define NV_PPRIV_MASTER_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED 0x00000001 /* RWB-V */
#define NV_PPRIV_MASTER_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED 0x00000000 /* RW--V */
#define NV_PPRIV_MASTER_GPC_RS_MAP(i) (0x001200c0+(i)*4) /* RW-4A */
#define NV_PPRIV_MASTER_GPC_RS_MAP__SIZE_1 7 /* */
#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENABLE 31:31 /* RWBVF */
#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENABLE_FALSE 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_ID 8+1-1:8 /* RWBVF */
#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_ID_INIT 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_LOCAL_CLUSTER_ID 3-1:0 /* RWBVF */
#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_DEBUG 0x00120068 /* RW-4R */
#define NV_PPRIV_MASTER_RING_DEBUG_GPC_RS_MAP_STATUS (7-1):0 /* R--VF */
#define NV_PPRIV_MASTER_RING_DEBUG_GPC_RS_MAP_STATUS_INVALID 0x00000000 /* R---V */
#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_TIMEOUT 27:24 /* RWBVF */
#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_TIMEOUT_INIT 0x00000000 /* RWB-V */
#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_STATE 30:28 /* R--VF */
#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_STATE_INVALID 0x00000000 /* R---V */
#endif // __ga102_dev_pri_ringmaster_h__

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include/ampere/ga102/dev_pri_ringstation_control_fbp.h Normal file
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include/ampere/ga102/dev_pri_ringstation_control_gpc.h Normal file
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include/ampere/ga102/dev_pri_ringstation_control_sys.h Normal file
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@@ -0,0 +1,162 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_pri_ringstation_control_sys_h__
#define __ga102_dev_pri_ringstation_control_sys_h__
/* This file is autogenerated. Do not edit */
#define NV_PPRIV_RS_CTRL_SYS 0x1220ff:0x122000 /* RW--D */
#define NV_PPRIV_RS_CTRL_SYS_RING_STATION_SUBSTRATE 0x00122000 /* R--4R */
#define NV_PPRIV_RS_CTRL_SYS_RING_STATION_SUBSTRATE_PHYSICAL_LOCATION 4:0 /* R--VF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK 0x0012205c /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST 0x00122004 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST__PRIV_LEVEL_MASK 0x0012205c /* */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET 3:0 /* RWXVF */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_0 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_1 0x00000001 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_2 0x00000002 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_3 0x00000003 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_4 0x00000004 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_5 0x00000005 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_6 0x00000006 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_7 0x00000007 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_8 0x00000008 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_9 0x00000009 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_10 0x0000000a /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_11 0x0000000b /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_12 0x0000000c /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_13 0x0000000d /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_14 0x0000000e /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_WIRE_BUCKET_15 0x0000000f /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_FORCE 4:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_FORCE_ENABLE 0x00000001 /* RW--T */
#define NV_PPRIV_RS_CTRL_SYS_FORCE_VW_REBROADCAST_FORCE_DISABLE 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG(i) (0x00122008+(i)*4) /* RW-4A */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG__SIZE_1 16 /* */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG__PRIV_LEVEL_MASK 0x0012205c /* */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_TIMER 7:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_TIMER_RESET 0x0000000a /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_MAX_UPDATES 15:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_VIRTUAL_WIRE_CONFIG_MAX_UPDATES_RESET 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CG1 0x00122048 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG 1:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_ENABLED 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG_DISABLED 0x00000003 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS 0x0012204c /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS__PRIV_LEVEL_MASK 0x0012205c /* */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_NO_WAKEUP 0:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_MAX_UPDATES 1:1 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_MAX_UPDATES_DISABLED 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_CYA_SETTINGS_VWIRE_MAX_UPDATES_ENABLED 0x00000001 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK 0x00122050 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION 0x00122054 /* RW-4R */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION__PRIV_LEVEL_MASK 0x00122050 /* */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_TAG (5-1):0 /* RWBVF */
#define NV_PPRIV_RS_CTRL_SYS_RS_ENUMERATION_TAG_INIT 0x00000000 /* RWB-V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO(i) (0x001220c0+(i)*4) /* R--4A */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO__SIZE_1 7 /* */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENABLE 31:31 /* R-BVF */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENABLE_TRUE 0x00000001 /* R---V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENABLE_FALSE 0x00000000 /* R-B-V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_ID (8+1-1):8 /* R-BVF */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_ID_INIT 0x00000000 /* R-B-V */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID (3-1):0 /* R-BVF */
#define NV_PPRIV_RS_CTRL_SYS_GPC_RS_MAP_INFO_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT 0x00000000 /* R-B-V */
#endif // __ga102_dev_pri_ringstation_control_sys_h__

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@@ -0,0 +1,376 @@
/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_ram_h__
#define __ga102_dev_ram_h__
/* This file is autogenerated. Do not edit */
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
#define NV_RAMIN /* ----G */
#define NV_RAMIN_BASE_SHIFT 12 /* */
#define NV_RAMIN_ALLOC_SIZE 4096 /* */
#define NV_RAMIN_RAMFC (127*32+31):(0*32+0) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET (128*32+1):(128*32+0) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_INVALID 0x00000001 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_VOL (128*32+2):(128*32+2) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_MIN_MEM_GRANULE (128*32+3):(128*32+3) /* RWXUF */
#define NV_RAMIN_MIN_MEM_GRANULE_4KB 0x00000000 /* RW--V */
#define NV_RAMIN_MIN_MEM_GRANULE_64KB 0x00000001 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX (128*32+4):(128*32+4) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX_DISABLED 0x00000000 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX_ENABLED 0x00000001 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC (128*32+5):(128*32+5) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC_DISABLED 0x00000000 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC_ENABLED 0x00000001 /* RW--V */
#define NV_RAMIN_NUM_VA_BITS (128*32+11):(128*32+6) /* RWXUF */
#define NV_RAMIN_USE_NEW_PT_FORMAT (128*32+10):(128*32+10) /* RWXUF */
#define NV_RAMIN_USE_NEW_PT_FORMAT_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_USE_NEW_PT_FORMAT_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_USE_VER2_PT_FORMAT (128*32+10):(128*32+10) /* */
#define NV_RAMIN_USE_VER2_PT_FORMAT_FALSE 0x00000000 /* */
#define NV_RAMIN_USE_VER2_PT_FORMAT_TRUE 0x00000001 /* */
#define NV_RAMIN_BIG_PAGE_SIZE (128*32+11):(128*32+11) /* RWXUF */
#define NV_RAMIN_BIG_PAGE_SIZE_128KB 0x00000000 /* RW--V */
#define NV_RAMIN_BIG_PAGE_SIZE_64KB 0x00000001 /* RW--V */
#define NV_RAMIN_PAGE_DIR_BASE_LO (128*32+31):(128*32+12) /* RWXUF */
#define NV_RAMIN_PAGE_DIR_BASE_HI (129*32+31):(129*32+0) /* RWXUF */
#define NV_RAMIN_ENGINE_CS (132*32+3):(132*32+3) /* */
#define NV_RAMIN_ENGINE_CS_WFI 0x00000000 /* */
#define NV_RAMIN_ENGINE_CS_FG 0x00000001 /* */
#define NV_RAMIN_ENGINE_WFI_TARGET (132*32+1):(132*32+0) /* */
#define NV_RAMIN_ENGINE_WFI_TARGET_LOCAL_MEM 0x00000000 /* */
#define NV_RAMIN_ENGINE_WFI_TARGET_SYS_MEM_COHERENT 0x00000002 /* */
#define NV_RAMIN_ENGINE_WFI_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* */
#define NV_RAMIN_ENGINE_WFI_MODE (132*32+2):(132*32+2) /* */
#define NV_RAMIN_ENGINE_WFI_MODE_PHYSICAL 0x00000000 /* */
#define NV_RAMIN_ENGINE_WFI_MODE_VIRTUAL 0x00000001 /* */
#define NV_RAMIN_ENGINE_WFI_PTR_LO (132*32+31):(132*32+12) /* */
#define NV_RAMIN_ENGINE_WFI_PTR_HI (133*32+7):(133*32+0) /* */
#define NV_RAMIN_ENGINE_WFI_VEID (134*32+(6-1)):(134*32+0) /* */
#define NV_RAMIN_ENABLE_ATS (135*32+31):(135*32+31) /* RWXUF */
#define NV_RAMIN_ENABLE_ATS_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_ENABLE_ATS_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_PASID (135*32+(20-1)):(135*32+0) /* RWXUF */
#define NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO (136*32+31):(136*32+0) /* RWXUF */
#define NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI (137*32+(((49-1)-32))):(137*32+0) /* RWXUF */
#define NV_RAMIN_SC_PDB_VALID(i) (166*32+(i)):(166*32+(i)) /* RWXUF */
#define NV_RAMIN_SC_PDB_VALID__SIZE_1 64 /* */
#define NV_RAMIN_SC_PDB_VALID_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_SC_PDB_VALID_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET(i) ((168+(i)*4)*32+1):((168+(i)*4)*32+0) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET__SIZE_1 64 /* */
#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_INVALID 0x00000001 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL(i) ((168+(i)*4)*32+2):((168+(i)*4)*32+2) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL__SIZE_1 64 /* */
#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_SC_MIN_MEM_GRANULE(i) ((168+(i)*4)*32+3):((168+(i)*4)*32+3) /* RWXUF */
#define NV_RAMIN_SC_MIN_MEM_GRANULE__SIZE_1 64 /* */
#define NV_RAMIN_SC_MIN_MEM_GRANULE_4KB 0x00000000 /* RW--V */
#define NV_RAMIN_SC_MIN_MEM_GRANULE_64KB 0x00000001 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX(i) ((168+(i)*4)*32+4):((168+(i)*4)*32+4) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX__SIZE_1 64 /* */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_DISABLED 0x00000000 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_ENABLED 0x00000001 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC(i) ((168+(i)*4)*32+5):((168+(i)*4)*32+5) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC__SIZE_1 64 /* */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_DISABLED 0x00000000 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_ENABLED 0x00000001 /* RW--V */
#define NV_RAMIN_SC_NUM_VA_BITS(i) ((168+(i)*4)*32+11):((168+(i)*4)*32+6) /* RWXUF */
#define NV_RAMIN_SC_NUM_VA_BITS__SIZE_1 64 /* */
#define NV_RAMIN_SC_USE_VER2_PT_FORMAT(i) ((168+(i)*4)*32+10):((168+(i)*4)*32+10) /* RWXUF */
#define NV_RAMIN_SC_USE_VER2_PT_FORMAT__SIZE_1 64 /* */
#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_FALSE 0x00000000 /* RW--V */
#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_TRUE 0x00000001 /* RW--V */
#define NV_RAMIN_SC_BIG_PAGE_SIZE(i) ((168+(i)*4)*32+11):((168+(i)*4)*32+11) /* RWXUF */
#define NV_RAMIN_SC_BIG_PAGE_SIZE__SIZE_1 64 /* */
#define NV_RAMIN_SC_BIG_PAGE_SIZE_64KB 0x00000001 /* RW--V */
#define NV_RAMIN_SC_PAGE_DIR_BASE_LO(i) ((168+(i)*4)*32+31):((168+(i)*4)*32+12) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_LO__SIZE_1 64 /* */
#define NV_RAMIN_SC_PAGE_DIR_BASE_HI(i) ((169+(i)*4)*32+31):((169+(i)*4)*32+0) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_HI__SIZE_1 64 /* */
#define NV_RAMIN_SC_ENABLE_ATS(i) ((170+(i)*4)*32+31):((170+(i)*4)*32+31) /* RWXUF */
#define NV_RAMIN_SC_ENABLE_ATS__SIZE_1 64 /* */
#define NV_RAMIN_SC_PASID(i) ((170+(i)*4)*32+(20-1)):((170+(i)*4)*32+0) /* RWXUF */
#define NV_RAMIN_SC_PASID__SIZE_1 64 /* */
#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_0 ((168+0*4)*32+1):((168+0*4)*32+0) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_0 ((168+0*4)*32+2):((168+0*4)*32+2) /* RWXUF */
#define NV_RAMIN_SC_MIN_MEM_GRANULE_0 ((168+0*4)*32+3):((168+0*4)*32+3) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_0 ((168+0*4)*32+4):((168+0*4)*32+4) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_0 ((168+0*4)*32+5):((168+0*4)*32+5) /* RWXUF */
#define NV_RAMIN_SC_NUM_VA_BITS_0 ((168+0*4)*32+11):((168+0*4)*32+6) /* RWXUF */
#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_0 ((168+0*4)*32+10):((168+0*4)*32+10) /* RWXUF */
#define NV_RAMIN_SC_BIG_PAGE_SIZE_0 ((168+0*4)*32+11):((168+0*4)*32+11) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_LO_0 ((168+0*4)*32+31):((168+0*4)*32+12) /* RWXUF */
#define NV_RAMIN_SC_PAGE_DIR_BASE_HI_0 ((169+0*4)*32+31):((169+0*4)*32+0) /* RWXUF */
#define NV_RAMIN_SC_ENABLE_ATS_0 ((170+0*4)*32+31):((170+0*4)*32+31) /* RWXUF */
#define NV_RAMIN_SC_PASID_0 ((170+0*4)*32+(20-1)):((170+0*4)*32+0) /* RWXUF */
#define NV_RAMFC /* ----G */
#define NV_RAMFC_BASE_SHIFT 12 /* */
#define NV_RAMFC_SIZE_VAL 0x00000200 /* */
#define NV_RAMFC_HOST_STATE_SIZE_VAL 64 /* */
#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) /* RW-UF */
#define NV_RAMFC_MEM_OP_A (1*32+31):(1*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED2 (2*32+31):(2*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED3 (3*32+31):(3*32+0) /* RW-UF */
#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) /* RW-UF */
#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) /* RW-UF */
#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) /* RW-UF */
#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) /* RW-UF */
#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) /* RW-UF */
#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) /* RW-UF */
#define NV_RAMFC_REF (10*32+31):(10*32+0) /* RW-UF */
#define NV_RAMFC_RUNTIME (11*32+31):(11*32+0) /* RW-UF */
#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) /* RW-UF */
#define NV_RAMFC_ACQUIRE_DEADLINE (13*32+31):(13*32+0) /* RW-UF */
#define NV_RAMFC_SEM_ADDR_HI (14*32+31):(14*32+0) /* RW-UF */
#define NV_RAMFC_SEM_ADDR_LO (15*32+31):(15*32+0) /* RW-UF */
#define NV_RAMFC_SEM_PAYLOAD_LO (16*32+31):(16*32+0) /* RW-UF */
#define NV_RAMFC_SEM_EXECUTE (17*32+31):(17*32+0) /* RW-UF */
#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) /* RW-UF */
#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) /* RW-UF */
#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED21 (21*32+31):(21*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED22 (22*32+31):(22*32+0) /* RW-UF */
#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) /* RW-UF */
#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) /* RW-UF */
#define NV_RAMFC_MEM_OP_B (25*32+31):(25*32+0) /* RW-UF */
#define NV_RAMFC_PB_DATA3 (26*32+31):(26*32+0) /* RW-UF */
#define NV_RAMFC_HDR_SHADOW (27*32+31):(27*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED28 (28*32+31):(28*32+0) /* RW-UF */
#define NV_RAMFC_GP_CRC (29*32+31):(29*32+0) /* RW-UF */
#define NV_RAMFC_SPLITTER_REM_LINES (30*32+31):(30*32+0) /* RW-UF */
#define NV_RAMFC_SPLITTER_OFFSET_IN_LOWER (31*32+31):(31*32+0) /* RW-UF */
#define NV_RAMFC_SPLITTER_OFFSET_IN_UPPER (32*32+31):(32*32+0) /* RW-UF */
#define NV_RAMFC_PB_HEADER (33*32+31):(33*32+0) /* RW-UF */
#define NV_RAMFC_PB_COUNT (34*32+31):(34*32+0) /* RW-UF */
#define NV_RAMFC_PB_DATA0 (35*32+31):(35*32+0) /* RW-UF */
#define NV_RAMFC_PB_DATA1 (36*32+31):(36*32+0) /* RW-UF */
#define NV_RAMFC_SUBDEVICE (37*32+31):(37*32+0) /* RW-UF */
#define NV_RAMFC_PB_CRC (38*32+31):(38*32+0) /* RW-UF */
#define NV_RAMFC_SEM_PAYLOAD_HI (39*32+31):(39*32+0) /* RW-UF */
#define NV_RAMFC_MEM_OP_C (40*32+31):(40*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED41 (41*32+31):(41*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED42 (42*32+31):(42*32+0) /* RW-UF */
#define NV_RAMFC_TARGET (43*32+31):(43*32+0) /* RW-UF */
#define NV_RAMFC_RESERVED44 (44*32+31):(44*32+0) /* RW-UF */
#define NV_RAMFC_SPLITTER_REM_PIXELS (45*32+31):(45*32+0) /* RW-UF */
#define NV_RAMFC_SPLITTER_OFFSET_OUT_LOWER (46*32+31):(46*32+0) /* RW-UF */
#define NV_RAMFC_SPLITTER_OFFSET_OUT_UPPER (47*32+31):(47*32+0) /* RW-UF */
#define NV_RAMFC_METHOD(i) ((48+(i)*2)*32+31):((48+(i)*2)*32+0) /* RW-UF */
#define NV_RAMFC_METHOD__SIZE_1 4 /* */
#define NV_RAMFC_DATA(i) ((49+(i)*2)*32+31):((49+(i)*2)*32+0) /* RW-UF */
#define NV_RAMFC_DATA__SIZE_1 4 /* */
#define NV_RAMFC_METHOD0 (48*32+31):(48*32+0) /* RW-UF */
#define NV_RAMFC_DATA0 (49*32+31):(49*32+0) /* RW-UF */
#define NV_RAMFC_METHOD1 (50*32+31):(50*32+0) /* RW-UF */
#define NV_RAMFC_DATA1 (51*32+31):(51*32+0) /* RW-UF */
#define NV_RAMFC_METHOD2 (52*32+31):(52*32+0) /* RW-UF */
#define NV_RAMFC_DATA2 (53*32+31):(53*32+0) /* RW-UF */
#define NV_RAMFC_METHOD3 (54*32+31):(54*32+0) /* RW-UF */
#define NV_RAMFC_DATA3 (55*32+31):(55*32+0) /* RW-UF */
#define NV_RAMFC_SPARE56 (56*32+31):(56*32+0) /* RW-UF */
#define NV_RAMFC_HCE_CTRL (57*32+31):(57*32+0) /* RW-UF */
#define NV_RAMFC_ALLOWED_SYNCPOINTS (58*32+31):(58*32+0) /* RW-UF */
#define NV_RAMFC_GP_PEEK (59*32+31):(59*32+0) /* RW-UF */
#define NV_RAMFC_PB_DATA2 (60*32+31):(60*32+0) /* RW-UF */
#define NV_RAMFC_CONFIG (61*32+31):(61*32+0) /* RW-UF */
#define NV_RAMFC_INTR_NOTIFY (62*32+31):(62*32+0) /* RW-UF */
#define NV_RAMFC_SET_CHANNEL_INFO (63*32+31):(63*32+0) /* RW-UF */
#define NV_RAMFC_CHID (58*32+31):(58*32+0) /* */
#define NV_RAMFC_CHID_ID 11:0 /* */
#define NV_RAMFC_CE_METHOD_STATE(i) (((i)+64)*32+31):(((i)+64)*32+0) /* RW-UF */
#define NV_RAMFC_CE_METHOD_STATE__SIZE_1 42 /* */
#define NV_RAMFC_CE_METHOD_STATE_SHIFT 8 /* */
#define NV_RAMFC_HOST_FETCH_SIZE_VAL (64+42)*4
#define NV_RAMUSERD /* ----G */
#define NV_RAMUSERD_BASE_SHIFT 9 /* */
#define NV_RAMUSERD_CHAN_SIZE 512 /* */
#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) /* RW-UF */
#define NV_RAMUSERD_GET (17*32+31):(17*32+0) /* RW-UF */
#define NV_RAMUSERD_REF (18*32+31):(18*32+0) /* RW-UF */
#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) /* RW-UF */
#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RW-UF */
#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RW-UF */
#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) /* RW-UF */
#define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RW-UF */
#define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RW-UF */
#define NV_RAMRL_ENTRY_RANGE 0xF:0x00000000 /* RW--M */
#define NV_RAMRL_ENTRY /* ----G */
#define NV_RAMRL_ENTRY_SIZE 16 /* */
#define NV_RAMRL_ENTRY_BASE_SHIFT 10 /* */
#define NV_RAMRL_ENTRY_TYPE (0+0*32):(0+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_TYPE_CHAN 0x00000000 /* RW--V */
#define NV_RAMRL_ENTRY_TYPE_TSG 0x00000001 /* RW--V */
#define NV_RAMRL_ENTRY_ID (11+2*32):(0+2*32) /* RWXUF */
#define NV_RAMRL_ENTRY_ID_HW 10:0 /* RWXUF */
#define NV_RAMRL_ENTRY_ID_MAX (2048-1) /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_RUNQUEUE_SELECTOR (1+0*32):(1+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_INST_TARGET (5+0*32):(4+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_VID_MEM 0x00000000 /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET (7+0*32):(6+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_VID_MEM 0x00000000 /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_VID_MEM_NVLINK_COHERENT 0x00000001 /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI (31+1*32):(0+1*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (7+1*32):(0+1*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_CHID (11+2*32):(0+2*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_INST_PTR_LO (31+2*32):(12+2*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_INST_PTR_HI (31+3*32):(0+3*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_INST_PTR_HI_HW (7+3*32):(0+3*32) /* RWXUF */
#define NV_RAMRL_ENTRY_CHAN_INST_PTR_ALIGN_SHIFT 12 /* */
#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_ALIGN_SHIFT 8 /* */
#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_FB_BIND_SHIFT 28 /* */
#define NV_RAMRL_ENTRY_TSG_GFID (11+0*32):(4+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_TSG_TIMESLICE_SCALE (19+0*32):(16+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_TSG_TIMESLICE_SCALE_3 0x00000003 /* RWI-V */
#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT (31+0*32):(24+0*32) /* RWXUF */
#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */
#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT_1 0x00000000 /* RW--V */
#define NV_RAMRL_ENTRY_TSG_LENGTH (7+1*32):(0+1*32) /* RWXUF */
#define NV_RAMRL_ENTRY_TSG_LENGTH_INIT 0x00000000 /* RW--V */
#define NV_RAMRL_ENTRY_TSG_LENGTH_MIN 0x00000001 /* RW--V */
#define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000080 /* RW--V */
#define NV_RAMRL_ENTRY_TSG_TSGID (11+2*32):(0+2*32) /* RWXUF */
#define NV_FIFO_DMA_PB_ENTRY_SIZE 4 /* */
#define NV_FIFO_DMA /* ----G */
#define NV_FIFO_DMA_METHOD_ADDRESS_OLD 12:2 /* RWXUF */
#define NV_FIFO_DMA_METHOD_ADDRESS 11:0 /* RWXUF */
#define NV_FIFO_DMA_SUBDEVICE_MASK 15:4 /* RWXUF */
#define NV_FIFO_DMA_METHOD_SUBCHANNEL 15:13 /* RWXUF */
#define NV_FIFO_DMA_TERT_OP 17:16 /* RWXUF */
#define NV_FIFO_DMA_TERT_OP_GRP0_INC_METHOD 0x00000000 /* RW--V */
#define NV_FIFO_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK 0x00000001 /* RW--V */
#define NV_FIFO_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK 0x00000002 /* RW--V */
#define NV_FIFO_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK 0x00000003 /* RW--V */
#define NV_FIFO_DMA_TERT_OP_GRP2_NON_INC_METHOD 0x00000000 /* RW--V */
#define NV_FIFO_DMA_METHOD_COUNT_OLD 28:18 /* RWXUF */
#define NV_FIFO_DMA_METHOD_COUNT 28:16 /* RWXUF */
#define NV_FIFO_DMA_SEC_OP 31:29 /* RWXUF */
#define NV_FIFO_DMA_SEC_OP_GRP0_USE_TERT 0x00000000 /* RW--V */
#define NV_FIFO_DMA_SEC_OP_INC_METHOD 0x00000001 /* RW--V */
#define NV_FIFO_DMA_SEC_OP_GRP2_USE_TERT 0x00000002 /* RW--V */
#define NV_FIFO_DMA_SEC_OP_NON_INC_METHOD 0x00000003 /* RW--V */
#define NV_FIFO_DMA_SEC_OP_IMMD_DATA_METHOD 0x00000004 /* RW--V */
#define NV_FIFO_DMA_SEC_OP_ONE_INC 0x00000005 /* RW--V */
#define NV_FIFO_DMA_SEC_OP_RESERVED6 0x00000006 /* RW--V */
#define NV_FIFO_DMA_SEC_OP_END_PB_SEGMENT 0x00000007 /* RW--V */
#define NV_FIFO_DMA_INCR /* ----G */
#define NV_FIFO_DMA_INCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */
#define NV_FIFO_DMA_INCR_OPCODE_VALUE 0x00000001 /* ----V */
#define NV_FIFO_DMA_INCR_COUNT (0*32+28):(0*32+16) /* RWXUF */
#define NV_FIFO_DMA_INCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */
#define NV_FIFO_DMA_INCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */
#define NV_FIFO_DMA_INCR_DATA (1*32+31):(1*32+0) /* RWXUF */
#define NV_FIFO_DMA_NONINCR /* ----G */
#define NV_FIFO_DMA_NONINCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */
#define NV_FIFO_DMA_NONINCR_OPCODE_VALUE 0x00000003 /* ----V */
#define NV_FIFO_DMA_NONINCR_COUNT (0*32+28):(0*32+16) /* RWXUF */
#define NV_FIFO_DMA_NONINCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */
#define NV_FIFO_DMA_NONINCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */
#define NV_FIFO_DMA_NONINCR_DATA (1*32+31):(1*32+0) /* RWXUF */
#define NV_FIFO_DMA_ONEINCR /* ----G */
#define NV_FIFO_DMA_ONEINCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */
#define NV_FIFO_DMA_ONEINCR_OPCODE_VALUE 0x00000005 /* ----V */
#define NV_FIFO_DMA_ONEINCR_COUNT (0*32+28):(0*32+16) /* RWXUF */
#define NV_FIFO_DMA_ONEINCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */
#define NV_FIFO_DMA_ONEINCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */
#define NV_FIFO_DMA_ONEINCR_DATA (1*32+31):(1*32+0) /* RWXUF */
#define NV_FIFO_DMA_NOP 0x00000000 /* ----C */
#define NV_FIFO_DMA_IMMD /* ----G */
#define NV_FIFO_DMA_IMMD_ADDRESS 11:0 /* RWXUF */
#define NV_FIFO_DMA_IMMD_SUBCHANNEL 15:13 /* RWXUF */
#define NV_FIFO_DMA_IMMD_DATA 28:16 /* RWXUF */
#define NV_FIFO_DMA_IMMD_OPCODE 31:29 /* RWXUF */
#define NV_FIFO_DMA_IMMD_OPCODE_VALUE 0x00000004 /* ----V */
#define NV_FIFO_DMA_SET_SUBDEVICE_MASK /* ----G */
#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 /* RWXUF */
#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */
#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE 0x00000001 /* ----V */
#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK /* ----G */
#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 /* RWXUF */
#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */
#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE 0x00000002 /* ----V */
#define NV_FIFO_DMA_USE_SUBDEVICE_MASK /* ----G */
#define NV_FIFO_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */
#define NV_FIFO_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE 0x00000003 /* ----V */
#define NV_FIFO_DMA_ENDSEG_OPCODE 31:29 /* RWXUF */
#define NV_FIFO_DMA_ENDSEG_OPCODE_VALUE 0x00000007 /* ----V */
#define NV_FIFO_DMA_OPCODE (0*32+31):(0*32+29) /* RWXUF */
#define NV_FIFO_DMA_OPCODE_METHOD 0x00000000 /* ----V */
#define NV_FIFO_DMA_OPCODE_NONINC_METHOD 0x00000002 /* ----V */
#define NV_FIFO_DMA_OPCODE3_NONE 0x00000000 /* ----V */
#define NV_FIFO_DMA_OPCODE2 (0*32+1):(0*32+0) /* RWXUF */
#define NV_FIFO_DMA_OPCODE2_NONE 0x00000000 /* ----V */
#define NV_FIFO_DMA_DATA (1*32+31):(1*32+0) /* RWXUF */
#define NV_SUBCHAN /* ----G */
#define NV_SUBCHAN_CTX_SWITCH (0*32+31):(0*32+0) /* RWXUF */
#define NV_SUBCHAN_DMA_INSTANCE (1*32+15):(1*32+0) /* RWXUF */
#define NV_SUBCHAN_NOTIFY_INSTANCE (1*32+31):(1*32+16) /* RWXUF */
#define NV_SUBCHAN_MEMFMT_INSTANCE (2*32+15):(2*32+0) /* RWXUF */
#define NV_SUBCHAN_MEMFMT_LINEAR (2*32+16):(2*32+16) /* RWXUF */
#define NV_SUBCHAN_MEMFMT_LINEAR_OUT 0x00000000 /* RW--V */
#define NV_SUBCHAN_MEMFMT_LINEAR_IN 0x00000001 /* RW--V */
#define NV_DMA_PRIV (0*32+21):(0*32+20) /* RWXVF */
#define NV_DMA_PRIV_FROM_PTE 0x00000000 /* RW--V */
#define NV_DMA_PRIV_ANY 0x00000001 /* RW--V */
#define NV_DMA_PRIV_PRIVILEGED 0x00000002 /* RW--V */
#define NV_PRAMIN_DATA032(i) (0x00700000+(i)*4) /* RW-4A */
#define NV_PRAMIN_DATA032__SIZE_1 262144 /* */
#define NV_PRAMIN_DATA032_VALUE 31:0 /* RWXUF */
#define NV_PRAMIN_DATA016(i) (0x00700000+(i)*2) /* RW-2A */
#define NV_PRAMIN_DATA016__SIZE_1 524288 /* */
#define NV_PRAMIN_DATA016_VALUE 15:0 /* RWXUF */
#define NV_PRAMIN_DATA008(i) (0x00700000+(i)) /* RW-1A */
#define NV_PRAMIN_DATA008__SIZE_1 1048576 /* */
#define NV_PRAMIN_DATA008_VALUE 7:0 /* RWXUF */
#define NV_NOTIFY 0x0000000F:0x00000000 /* RW--M */
#define NV_NOTIFY_TIME_0 (0*32+31):(0*32+5) /* RWXUF */
#define NV_NOTIFY_TIME_1 (1*32+28):(1*32+0) /* RWXUF */
#define NV_NOTIFY_RETURN_VALUE (2*32+31):(2*32+0) /* RWXVF */
#define NV_NOTIFY_ERROR_CODE (3*32+15):(3*32+0) /* RWXUF */
#define NV_NOTIFY_STATUS (3*32+31):(3*32+24) /* RWXUF */
#define NV_NOTIFY_STATUS_COMPLETED 0x00000000 /* RW--V */
#define NV_NOTIFY_STATUS_IN_PROCESS 0x00000001 /* RW--V */
#define NV_RAMSEMAPHORE /* ----G */
#define NV_RAMSEMAPHORE_PAYLOAD (0*32+31):(0*32+0) /* RWXUF */
#define NV_RAMSEMAPHORE_PAYLOAD_HI (1*32+31):(1*32+0) /* RWXUF */
#define NV_RAMSEMAPHORE_TIMESTAMP_LO (2*32+31):(2*32+0) /* RWXUF */
#define NV_RAMSEMAPHORE_TIMESTAMP_HI (3*32+31):(3*32+0) /* RWXUF */
#define NV_MONITORED_FENCE 0x08:0x00 /* RW--M */
#define NV_MONITORED_FENCE_THRESHOLD_LOWER (31+0*32):(0+0*32) /* RWXUF */
#define NV_MONITORED_FENCE_THRESHOLD_UPPER (31+1*32):(0+1*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT 0x20:0x00 /* RW--M */
#define NV_MONITORED_FENCE_EXT_THRESHOLD_LOWER (31+0*32):(0+0*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_THRESHOLD_UPPER (31+1*32):(0+1*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_SIGNAL_ADDRESS_LOW (31+2*32):(2+2*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_SIGNAL_ADDRESS_HIGH (7+3*32):(0+3*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_EVENT_HANDLE (31+4*32):(0+4*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_ADDRESS_TYPE (4+6*32):(4+6*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_ADDRESS_TYPE_ABSOLUTE 0x0 /* RW-UV */
#define NV_MONITORED_FENCE_EXT_ADDRESS_TYPE_OFFSET 0x1 /* RW-UV */
#define NV_MONITORED_FENCE_EXT_SIGNAL_INTERRUPT (0+6*32):(0+6*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_SIGNAL_INTERRUPT_DISABLE 0x0 /* RW-UV */
#define NV_MONITORED_FENCE_EXT_SIGNAL_INTERRUPT_ENABLE 0x1 /* RW-UV */
#define NV_MONITORED_FENCE_EXT_SIGNAL_MEMORY_WRITE (1+6*32):(1+6*32) /* RWXUF */
#define NV_MONITORED_FENCE_EXT_SIGNAL_MEMORY_WRITE_DISABLE 0x0 /* RW-UV */
#define NV_MONITORED_FENCE_EXT_SIGNAL_MEMORY_WRITE_ENABLE 0x1 /* RW-UV */
#endif // __ga102_dev_ram_h__

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_runlist_h__
#define __ga102_dev_runlist_h__
/* This file is autogenerated. Do not edit */
#define NV_RUNLIST 0x000003ff:0x00000000 /* RW--D */
#define NV_CHRAM 0x00001fff:0x00000000 /* RW--D */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK 0x040 /* RW-4R */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RWI-V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_RUNLIST_INT_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_RUNLIST_INT_CYA_SPARE 0x044 /* RW-4R */
#define NV_RUNLIST_INT_CYA_SPARE__PRIV_LEVEL_MASK 0x040 /* */
#define NV_RUNLIST_INT_CYA_SPARE_DATA 31:0 /* RWIUF */
#define NV_RUNLIST_INT_CYA_SPARE_DATA_INIT 0x00000000 /* RWI-V */
#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE 0:0 /* */
#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE_VAL 1:1 /* */
#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE_VAL_1MTHD 0x00000000 /* */
#define NV_RUNLIST_INT_CYA_SPARE_FORCE_FE_MTHD_THROTTLE_VAL_2MTHD 0x00000001 /* */
#define NV_RUNLIST_INT_CYA_SPARE_RAMFC_SANITY_CHECK 8:8 /* */
#define NV_RUNLIST_CONFIG 0x000 /* RW-4R */
#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH 0:0 /* RWIVF */
#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH_WEAK 0x00000000 /* RWI-V */
#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH_STRONG 0x00000001 /* RW--V */
#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH 4:4 /* RWIVF */
#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH_WEAK 0x00000000 /* RW--V */
#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH_STRONG 0x00000001 /* RWI-V */
#define NV_RUNLIST_CONFIG_L2_EVICT 9:8 /* RWIVF */
#define NV_RUNLIST_CONFIG_L2_EVICT_FIRST 0x00000000 /* RWI-V */
#define NV_RUNLIST_CONFIG_L2_EVICT_NORMAL 0x00000001 /* RW--V */
#define NV_RUNLIST_CONFIG_L2_EVICT_LAST 0x00000002 /* RW--V */
#define NV_RUNLIST_CONFIG_SUBCH4 10:10 /* RWXVF */
#define NV_RUNLIST_CONFIG_SUBCH4_INACTIVE 0x00000000 /* RW--V */
#define NV_RUNLIST_CONFIG_SUBCH4_ACTIVE 0x00000001 /* RW--V */
#define NV_RUNLIST_CHANNEL_CONFIG 0x004 /* R--4R */
#define NV_RUNLIST_CHANNEL_CONFIG_NUM_CHANNELS_LOG2 3:0 /* C--UF */
#define NV_RUNLIST_CHANNEL_CONFIG_NUM_CHANNELS_LOG2_2K 11 /* C---V */
#define NV_RUNLIST_CHANNEL_CONFIG_CHRAM_BAR0_OFFSET 31:4 /* R-XVF */
#define NV_RUNLIST_DOORBELL_CONFIG 0x008 /* R--4R */
#define NV_RUNLIST_DOORBELL_CONFIG_ID 31:16 /* R-XVF */
#define NV_RUNLIST_FB_CONFIG 0x00C /* R--4R */
#define NV_RUNLIST_FB_CONFIG_FB_THREAD_ID 7:0 /* R-XVF */
#define NV_RUNLIST_FB_CONFIG_ESC_ID 15:8 /* R-XVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG(i) (0x300+(i)*4) /* RW-4A */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG__SIZE_1 64 /* */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK 11:0 /* */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK_HW 10:0 /* RWIVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK_HW_INIT 2047 /* RWI-V */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET 27:16 /* */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET_HW 26:16 /* RWIVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET_HW_INIT 0x0 /* RWI-V */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE 31:31 /* RWIVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE_TRUE 1 /* RW--V */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE_FALSE 0 /* RWI-V */
#define NV_RUNLIST_PBDMA_CONFIG(i) (0x010+(i)*4) /* R--4A */
#define NV_RUNLIST_PBDMA_CONFIG__SIZE_1 2 /* */
#define NV_RUNLIST_PBDMA_CONFIG_PBDMA_ID 7:0 /* R-XUF */
#define NV_RUNLIST_PBDMA_CONFIG_PBDMA_BAR0_OFFSET 25:10 /* R-XUF */
#define NV_RUNLIST_PBDMA_CONFIG_VALID 31:31 /* R-XUF */
#define NV_RUNLIST_PBDMA_CONFIG_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PBDMA_CONFIG_VALID_FALSE 0x00000000 /* R---V */
#define NV_RUNLIST_ACQ_PRETEST 0x020 /* RW-4R */
#define NV_RUNLIST_ACQ_PRETEST_TIMEOUT 7:0 /* RWIUF */
#define NV_RUNLIST_ACQ_PRETEST_TIMEOUT_8 0x00000008 /* RWI-V */
#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE 15:12 /* RWIUF */
#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE_0 0x00000000 /* RWI-V */
#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE_10 0x0000000a /* RW--V */
#define NV_RUNLIST_IDLE_FILTER 0x024 /* RW-4R */
#define NV_RUNLIST_IDLE_FILTER_PERIOD 7:0 /* RWIUF */
#define NV_RUNLIST_IDLE_FILTER_PERIOD_INIT 0x00000040 /* RWI-V */
#define NV_RUNLIST_IDLE_FILTER_PERIOD_8 0x00000008 /* RW--V */
#define NV_RUNLIST_IDLE_FILTER_PERIOD_32 0x00000020 /* RW--V */
#define NV_RUNLIST_USERD_WRITEBACK 0x028 /* RW-4R */
#define NV_RUNLIST_USERD_WRITEBACK_TIMER 7:0 /* RWIUF */
#define NV_RUNLIST_USERD_WRITEBACK_TIMER_DISABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_USERD_WRITEBACK_TIMER_SHORT 0x00000003 /* RW--V */
#define NV_RUNLIST_USERD_WRITEBACK_TIMER_100US 0x00000064 /* RWI-V */
#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE 15:12 /* RWIUF */
#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE_0 0x00000000 /* RWI-V */
#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE_SHORT 0x00000000 /* */
#define NV_RUNLIST_USERD_WRITEBACK_TIMESCALE_100US 0x00000000 /* */
#define NV_RUNLIST_ESCHED_CONFIG 0x02c /* C--4R */
#define NV_RUNLIST_ESCHED_CONFIG_ESCHED_CLASS_ID 15:0 /* C--UF */
#define NV_RUNLIST_ESCHED_CONFIG_ESCHED_CLASS_ID_VALUE 51055 /* C---V */
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */
#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */
#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */
#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */
#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */
#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_STATUS 12:8 /* */
#define NV_CHRAM_CHANNEL_STATUS_IDLE 0x00000000 /* */
#define NV_CHRAM_CHANNEL_STATUS_PENDING 0x00000001 /* */
#define NV_CHRAM_CHANNEL_STATUS_PENDING_CTX_RELOAD 0x00000003 /* */
#define NV_CHRAM_CHANNEL_STATUS_PENDING_ACQUIRE_FAIL 0x00000011 /* */
#define NV_CHRAM_CHANNEL_STATUS_PENDING_ACQUIRE_FAIL_CTX_RELOAD 0x00000013 /* */
#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY 0x00000004 /* */
#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY_AND_ENG_BUSY 0x0000000C /* */
#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY 0x00000008 /* */
#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING_ACQUIRE_FAIL 0x00000019 /* */
#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING 0x00000009 /* */
#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY_CTX_RELOAD 0x00000006 /* */
#define NV_CHRAM_CHANNEL_STATUS_PBDMA_BUSY_ENG_BUSY_CTX_RELOAD 0x0000000E /* */
#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_CTX_RELOAD 0x0000000A /* */
#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING_CTX_RELOAD 0x0000000B /* */
#define NV_CHRAM_CHANNEL_STATUS_ENG_BUSY_PENDING_ACQUIRE_FAIL_CTX_RELOAD 0x0000001B /* */
#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */
#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */
#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */
#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
#define NV_RUNLIST_SUBMIT_BASE_LO 0x080 /* RW-4R */
#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_LO 31:10 /* RWIUF */
#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_LO_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET 1:0 /* RWIVF */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_VID_MEM 0x0 /* RWI-V */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_SYS_MEM_COHERENT 0x2 /* RW--V */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_SYS_MEM_NONCOHERENT 0x3 /* RW--V */
#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_ALIGN_SHIFT 10 /* */
#define NV_RUNLIST_SUBMIT_BASE_HI 0x084 /* RW-4R */
#define NV_RUNLIST_SUBMIT_BASE_HI_PTR_HI 7:0 /* RWIUF */
#define NV_RUNLIST_SUBMIT_BASE_HI_PTR_HI_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT 0x088 /* RW-4R */
#define NV_RUNLIST_SUBMIT_LENGTH 15:0 /* RWIUF */
#define NV_RUNLIST_SUBMIT_LENGTH_ZERO 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT_LENGTH_MAX 0x0000ffff /* RW--V */
#define NV_RUNLIST_SUBMIT_OFFSET 31:16 /* RWIVF */
#define NV_RUNLIST_SUBMIT_OFFSET_ZERO 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT_INFO 0x08C /* R--4R */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID 13:0 /* */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_HW 10:0 /* R-IUF */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_HW_DEFAULT 0x00000000 /* R-I-V */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID 14:14 /* R-IUF */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_SUBMIT_INFO_PENDING 15:15 /* R-IVF */
#define NV_RUNLIST_SUBMIT_INFO_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_SUBMIT_INFO_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_OFFSET 31:16 /* R-IVF */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_OFFSET_ZERO 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK(i) (0x190+(i)*4) /* RW-4A */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
#define NV_RUNLIST_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
#define NV_RUNLIST_INTR_VECTORID(i) (0x160+(i)*4) /* RW-4A */
#define NV_RUNLIST_INTR_VECTORID__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_VECTORID__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_VECTORID_VECTOR 11:0 /* RWXUF */
#define NV_RUNLIST_INTR_VECTORID_GSP 30:30 /* RWIUF */
#define NV_RUNLIST_INTR_VECTORID_GSP_DISABLE 0 /* RW--V */
#define NV_RUNLIST_INTR_VECTORID_GSP_ENABLE 1 /* RWI-V */
#define NV_RUNLIST_INTR_VECTORID_CPU 31:31 /* RWIUF */
#define NV_RUNLIST_INTR_VECTORID_CPU_DISABLE 0 /* RW--V */
#define NV_RUNLIST_INTR_VECTORID_CPU_ENABLE 1 /* RWI-V */
#define NV_RUNLIST_INTR_RETRIGGER(i) (0x180+(i)*4) /* -W-4A */
#define NV_RUNLIST_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_RETRIGGER__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_RUNLIST_INTR_RETRIGGER_TRIGGER_TRUE 1 /* -W--V */
#define NV_RUNLIST_INTR_0 0x100 /* RW-4R */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_NOT_PENDING 0x00000000 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_PENDING 0x00000001 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_RESET 0x00000001 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_NOT_PENDING 0x00000000 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_PENDING 0x00000001 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_RESET 0x00000001 /* */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE 4:4 /* RWIVF */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE 5:5 /* RWXVF */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE 6:6 /* RWXVF */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWXVF */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_BAD_TSG 12:12 /* RWIVF */
#define NV_RUNLIST_INTR_0_BAD_TSG_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_BAD_TSG_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_BAD_TSG_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0 16:16 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0 17:17 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1 18:18 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1 19:19 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j_NOT_PENDING 0x00000000 /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j_PENDING 0x00000001 /* */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_EVENT 9:9 /* */
#define NV_RUNLIST_INTR_0_MASK_SET 0x110 /* RW-4R */
#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_MASK_CLEAR 0x118 /* RW-4R */
#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE(i) (0x120+(i)*8) /* RW-4A */
#define NV_RUNLIST_INTR_0_EN_SET_TREE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE 4:4 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE 5:5 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE 6:6 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG 12:12 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0 16:16 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0 17:17 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1 18:18 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1 19:19 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE(i) (0x140+(i)*8) /* RW-4A */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE 4:4 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE 5:5 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE 6:6 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG 12:12 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0 16:16 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0 17:17 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1 18:18 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1 19:19 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j_ENABLED 0x00000001 /* */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO(i) (0x224+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_PREV_TSGID 13:0 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_PREV_TSGID_DEFAULT 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE 15:14 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_LOAD 0x00000001 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_SAVE 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_SWITCH 0x00000003 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_NEXT_TSGID 29:16 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_NEXT_TSGID_DEFAULT 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS 31:30 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_AWAITING_ACK 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_ENG_WAS_RESET 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_ACK_RECEIVED 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_DROPPED_TIMEOUT 0x00000003 /* R---V */
#define NV_RUNLIST_INFO 0x108 /* R--4R */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM 0:0 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM 1:1 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM 4:4 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM 5:5 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_ENG_IDLE 8:8 /* R-IUF */
#define NV_RUNLIST_INFO_ENG_IDLE_FALSE 0x00000000 /* R---V */
#define NV_RUNLIST_INFO_ENG_IDLE_TRUE 0x00000001 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_IDLE 9:9 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_FALSE 0x00000000 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_TRUE 0x00000001 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS 10:10 /* R-IVF */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS_IDLE 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS_BUSY 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED 13:13 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG 0x174 /* R--4R */
#define NV_RUNLIST_INTR_BAD_TSG_CODE 3:0 /* R-IVF */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_NO_ERROR 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_ZERO_LENGTH_TSG 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_MAX_LENGTH_EXCEEDED 0x00000002 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_RUNLIST_OVERFLOW 0x00000003 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_EXPECTED_A_CHID_ENTRY 0x00000004 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_EXPECTED_A_TSG_HEADER 0x00000005 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_INVALID_RUNQUEUE 0x00000006 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG(i) (0x220+(i)*64) /* RW-4A */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD 30:0 /* RWIVF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD_INIT 0x003fffff /* RWI-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD_MAX 0x7fffffff /* RW--V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION 31:31 /* RWIVF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION_DISABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION_ENABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG 0x050 /* RW-4R */
#define NV_RUNLIST_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_RUNLIST_CG_IDLE_CG_DLY_CNT_INIT 0x00000000 /* RWI-V */
#define NV_RUNLIST_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */
#define NV_RUNLIST_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_RUNLIST_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_RUNLIST_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_RUNLIST_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_RUNLIST_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_RUNLIST_CG_WAKEUP_DLY_CNT_INIT 0x00000000 /* RWI-V */
#define NV_RUNLIST_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG 0x050 /* */
#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT 5:0 /* */
#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT_INIT 0x00000000 /* */
#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN 6:6 /* */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN__PROD 0x00000001 /* */
#define NV_RUNLIST_BLKCG_STATE_CG_EN 7:7 /* */
#define NV_RUNLIST_BLKCG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT_INIT 0x00000000 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_EN 14:14 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_EN__PROD 0x00000001 /* */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN 15:15 /* */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN__PROD 0x00000001 /* */
#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT 19:16 /* */
#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT_INIT 0x00000000 /* */
#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT 23:20 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT_INIT 0x0000000f /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL_INIT 0x00000000 /* */
#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN 28:28 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN 30:30 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN 31:31 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_CG1 0x054 /* RW-4R */
#define NV_RUNLIST_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_RUNLIST_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG 16:1 /* */
#define NV_RUNLIST_CG1_SLCG_ENABLED 0x00000000 /* */
#define NV_RUNLIST_CG1_SLCG_DISABLED 0x0000FFFF /* */
#define NV_RUNLIST_CG1_SLCG__PROD 0x00000000 /* */
#define NV_RUNLIST_CG1_SLCG_RLP 1:1 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_RLP_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_RLP_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_RLP__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_EVH 3:3 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_EVH_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_EVH_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_EVH__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_EISM 7:7 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_EISM_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_EISM_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_EISM__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_LB 8:8 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_LB_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_LB_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_LB__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_CTL 9:9 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_PBDMA_CTL_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_CTL_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_CTL__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_GP 10:10 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_PBDMA_GP_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_GP_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_GP__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_PB 11:11 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_PBDMA_PB_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_PB_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_PBDMA_PB__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PRI 13:13 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_PRI__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_CHSW 14:14 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_CHSW_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_CHSW_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_CHSW__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_XBAR 15:15 /* RWIVF */
#define NV_RUNLIST_CG1_SLCG_XBAR_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_CG1_SLCG_XBAR_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_CG1_SLCG_XBAR__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1 0x054 /* */
#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN 0:0 /* */
#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG 16:1 /* */
#define NV_RUNLIST_BLKCG1_SLCG_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_DISABLED 0x0000FFFF /* */
#define NV_RUNLIST_BLKCG1_SLCG__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_RLP 1:1 /* */
#define NV_RUNLIST_BLKCG1_SLCG_RLP_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_RLP_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_RLP__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EVH 3:3 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EVH_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EVH_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EVH__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EISM 7:7 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EISM_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EISM_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_EISM__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_LB 8:8 /* */
#define NV_RUNLIST_BLKCG1_SLCG_LB_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_LB_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_LB__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL 9:9 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP 10:10 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB 11:11 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PRI 13:13 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PRI_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PRI_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_PRI__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW 14:14 /* */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR 15:15 /* */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR_DISABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR__PROD 0x00000000 /* */
#define NV_RUNLIST_SLCG_MISC 0x05C /* RW-4R */
#define NV_RUNLIST_SLCG_MISC_EXTRA_BUSY_CLKS 3:0 /* RWIVF */
#define NV_RUNLIST_SLCG_MISC_EXTRA_BUSY_CLKS_ZERO 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTERNAL_DOORBELL 0x090 /* -W-4R */
#define NV_RUNLIST_INTERNAL_DOORBELL_CHID 11:0 /* */
#define NV_RUNLIST_INTERNAL_DOORBELL_CHID_HW 10:0 /* -WXUF */
#define NV_RUNLIST_INTERNAL_DOORBELL_GFID 21:16 /* -WXUF */
#define NV_RUNLIST_SCHED_DISABLE 0x094 /* RW-4R */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST 0:0 /* RWIVF */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_ENABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_DISABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_FALSE 0x00000000 /* */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_TRUE 0x00000001 /* */
#define NV_RUNLIST_PREEMPT 0x098 /* RW-4R */
#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */
#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */
#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */
#define NV_RUNLIST_ENGINE_STATUS0(i) (0x200+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS0__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS0_TSGID 11:0 /* */
#define NV_RUNLIST_ENGINE_STATUS0_TSGID_HW 10:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS 15:13 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_INVALID 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_VALID 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_SAVE 0x00000005 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_LOAD 0x00000006 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_SWITCH 0x00000007 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX 13:13 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_INVALID 0x00000000 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_VALID 0x00000001 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD 14:14 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD_NOT_IN_PROGRESS 0x00000000 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD_IN_PROGRESS 0x00000001 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXSW 15:15 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXSW_NOT_IN_PROGRESS 0x00000000 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXSW_IN_PROGRESS 0x00000001 /* */
#define NV_RUNLIST_ENGINE_STATUS0_NEXT_TSGID 27:16 /* */
#define NV_RUNLIST_ENGINE_STATUS0_NEXT_TSGID_HW 26:16 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD 29:29 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_FAULTED 30:30 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_FAULTED_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_FAULTED_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_ENGINE 31:31 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_ENGINE_IDLE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_ENGINE_BUSY 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS1(i) (0x204+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS1__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS1_GFID 5:0 /* R-XVF */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID 13:8 /* R-XVF */
#define NV_RUNLIST_ENGINE_STATUS1_INTR_ID 20:16 /* R-XVF */
#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID 30:30 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID 31:31 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL(i,j) (0x208+(i)*64+(j)*4) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL__SIZE_2 2 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_CHID 11:0 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_CHID_HW 10:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID 15:15 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_CHID 27:16 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_CHID_HW 26:16 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID 31:31 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG(i) (0x228+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN 0:0 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN_DISABLED 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN_ENABLED 0x00000001 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS 8:8 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI 12:12 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS 16:16 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI 20:20 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_ENGINE_ID 29:24 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_INST(i) (0x210+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_INST__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET 1:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_VALID 11:11 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_INST_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_INST_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_PTR_LO 31:12 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI(i) (0x214+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI_PTR_HI 31:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI_PTR_HI_ZERO 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST(i) (0x218+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET 1:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID 11:11 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_PTR_LO 31:12 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI(i) (0x21C+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI_PTR_HI 31:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI_PTR_HI_ZERO 0x00000000 /* R---V */
#define NV_RUNLIST_GLOBAL_PRI_RANGE_0 0xc1ffff:0xc00000 /* RW--M */
#define NV_CHRAM_GLOBAL_PRI_RANGE_0 0xd1ffff:0xc20000 /* RW--M */
#endif // __ga102_dev_runlist_h__

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