9509 lines
957 KiB
C
9509 lines
957 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_nvenc_pri_sw_h__
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#define __ga102_dev_nvenc_pri_sw_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PNVENC(dev) 0x001cafff+(dev)*16384:0x001c8000+(dev)*16384 /* RW--D */
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#define NV_PNVENC__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK(dev) (0x001c8280+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK(dev) (0x001c8284+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK(dev) (0x001c8288+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK(dev) (0x001c8290+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK(dev) (0x001c80e8+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK(dev) (0x001c8298+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x8 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK(dev) (0x001c829c+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK(dev) (0x001c83d0+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK(dev) (0x001c83f0+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK(dev) (0x001c83f4+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK(dev) (0x001c83f8+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK(dev) (0x001c83fc+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0xc /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0xc /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(dev,i) (0x001c83d8+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_2 2 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev,i) (0x001c818c+(dev)*16384+(i)*16) /* RW-4A */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_2 1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev,i) (0x001c82b0+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK(dev) (0x001c8194+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK(dev) (0x001c8198+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK(dev) (0x001c819c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK(dev) (0x001c81a0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK(dev) (0x001c81a4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK(dev) (0x001c81a8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK(dev) (0x001c81bc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK(dev) (0x001c81e0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK(dev) (0x001c81e4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK(dev) (0x001c81e8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK(dev) (0x001c81ec+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK(dev) (0x001c81f0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK(dev) (0x001c81f4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK(dev) (0x001c81f8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK(dev) (0x001c81fc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */
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#define NV_PNVENC_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK(dev) (0x001c8220+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x80000 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK(dev) (0x001c8224+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK(dev) (0x001c822c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSSET(dev) (0x001c8000+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_FALCON_IRQSSET__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_GPTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_WDTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_MTHD_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_CTXSW_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_HALT_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_EXTERR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_SWGEN0_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_SWGEN1_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ1_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ2_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ3_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ4_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ5_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ6_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ7_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */
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#define NV_PNVENC_FALCON_IRQSSET_EXT_EXTIRQ8_SET 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSSET_DMA_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR(dev) (0x001c8004+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_FALCON_IRQSCLR__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_GPTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_WDTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_MTHD_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_CTXSW_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_HALT_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXTERR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_SWGEN0_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_SWGEN1_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT 15:8 /* */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQSCLR_DMA_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQSTAT(dev) (0x001c8008+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_IRQSTAT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_GPTMR_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_GPTMR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_WDTMR_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_WDTMR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_MTHD_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_MTHD_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_CTXSW_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_CTXSW_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_HALT_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_HALT_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXTERR_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXTERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_SWGEN0_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_SWGEN0_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_SWGEN1_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_SWGEN1_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT 15:8 /* */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQSTAT_DMA_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQSTAT_DMA_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMODE(dev) (0x001c800c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IRQMODE__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQMODE__PRIV_LEVEL_MASK(dev) (0x001c8290+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IRQMODE__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_GPTMR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_WDTMR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_MTHD_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_MTHD_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_MTHD_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_CTXSW_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_HALT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_HALT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_HALT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXTERR_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_INIT 0xfc /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_DMA_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_DMA_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQMODE_LVL_DMA_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK(dev) (0x001c80e0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IRQSCMASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK__PRIV_LEVEL_MASK(dev) (0x001c81a4+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IRQSCMASK__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_GPTMR_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_GPTMR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_WDTMR_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_WDTMR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_MTHD_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_MTHD_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_CTXSW_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_CTXSW_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_HALT_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_HALT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXTERR_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXTERR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_ENABLE 0xff /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_DISABLE 0x00 /* RW--V */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 0x1 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0x0 /* */
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#define NV_PNVENC_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQSCMASK_DMA_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQSCMASK_DMA_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL(dev,i) (0x001c83e0+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FALCON_INTR_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL__SIZE_2 2 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_INTR_CTRL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_INTR_CTRL_VECTOR 11:0 /* RW-VF */
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#define NV_PNVENC_FALCON_INTR_CTRL_GFID 25:20 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_GFID_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_GSP 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_GSP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_GSP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_CTRL_CPU 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_INTR_CTRL_CPU_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_INTR_CTRL_CPU_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_INTR_RETRIGGER(dev,i) (0x001c83e8+(dev)*16384+(i)*4) /* -W-4A */
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#define NV_PNVENC_FALCON_INTR_RETRIGGER__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_INTR_RETRIGGER__SIZE_2 2 /* */
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#define NV_PNVENC_FALCON_INTR_RETRIGGER__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_INTR_RETRIGGER__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
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#define NV_PNVENC_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET(dev) (0x001c8010+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_FALCON_IRQMSET__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQMSET__PRIV_LEVEL_MASK(dev) (0x001c8290+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IRQMSET__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_GPTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_WDTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_MTHD_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_CTXSW_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_HALT 4:4 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_HALT_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXTERR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_SWGEN0_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_SWGEN1_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT 15:8 /* */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMSET_DMA 16:16 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMSET_DMA_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR(dev) (0x001c8014+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_FALCON_IRQMCLR__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQMCLR__PRIV_LEVEL_MASK(dev) (0x001c8290+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IRQMCLR__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_GPTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_WDTMR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_MTHD_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_CTXSW_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_HALT_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXTERR_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_SWGEN0_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_SWGEN1_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT 15:8 /* */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */
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#define NV_PNVENC_FALCON_IRQMCLR_DMA_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_IRQMASK(dev) (0x001c8018+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_IRQMASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_GPTMR_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_GPTMR_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_WDTMR_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_WDTMR_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_MTHD_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_MTHD_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_CTXSW_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_CTXSW_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_HALT_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_HALT_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXTERR_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXTERR_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_SWGEN0_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_SWGEN0_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_SWGEN1_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_SWGEN1_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT 15:8 /* */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
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#define NV_PNVENC_FALCON_IRQMASK_DMA_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IRQMASK_DMA_DISABLE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IRQDEST(dev) (0x001c801c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IRQDEST__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQDEST__PRIV_LEVEL_MASK(dev) (0x001c8290+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IRQDEST__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_GPTMR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_GPTMR_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_WDTMR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_WDTMR_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_MTHD_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_MTHD_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_MTHD_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_CTXSW_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_CTXSW_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_HALT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_HALT_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_HALT_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXTERR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXTERR_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT 15:8 /* */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_MTHD_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_HALT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST2(dev) (0x001c803c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IRQDEST2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQDEST2__PRIV_LEVEL_MASK(dev) (0x001c8290+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IRQDEST2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST2_HOST_DMA_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST2_HOST_DMA_FALCON 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST2_HOST_DMA_HOST 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */
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#define NV_PNVENC_FALCON_IRQDEST2_TARGET_DMA_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_GPTMRINT(dev) (0x001c8020+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_GPTMRINT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_GPTMRINT__PRIV_LEVEL_MASK(dev) (0x001c81a0+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_GPTMRINT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_GPTMRVAL(dev) (0x001c8024+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_GPTMRVAL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_GPTMRVAL__PRIV_LEVEL_MASK(dev) (0x001c81a0+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_GPTMRVAL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_GPTMRCTL(dev) (0x001c8028+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_GPTMRCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_GPTMRCTL__PRIV_LEVEL_MASK(dev) (0x001c81a0+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_GPTMRCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMREN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_PTIMER0(dev) (0x001c802c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_PTIMER0__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PTIMER0__PRIV_LEVEL_MASK(dev) (0x001c81bc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_PTIMER0__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PTIMER0_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_PTIMER1(dev) (0x001c8030+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_PTIMER1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PTIMER1__PRIV_LEVEL_MASK(dev) (0x001c81bc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_PTIMER1__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PTIMER1_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_WDTMRVAL(dev) (0x001c8034+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_WDTMRVAL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_WDTMRVAL__PRIV_LEVEL_MASK(dev) (0x001c829c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_WDTMRVAL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMRCTL(dev) (0x001c8038+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_WDTMRCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_WDTMRCTL__PRIV_LEVEL_MASK(dev) (0x001c829c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_WDTMRCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMREN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDDATA(dev) (0x001c8064+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_MTHDDATA__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDDATA__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_MTHDDATA__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */
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#define NV_PNVENC_FALCON_MTHDID(dev) (0x001c8068+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_MTHDID__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDID__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_MTHDID__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDID_ID 11:0 /* RWXVF */
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#define NV_PNVENC_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */
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#define NV_PNVENC_FALCON_MTHDID_PRIV 15:15 /* RWXVF */
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#define NV_PNVENC_FALCON_MTHDID_PRIV_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDID_PRIV_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_MTHDID_WPEND 16:16 /* R-XVF */
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#define NV_PNVENC_FALCON_MTHDID_WPEND_DONE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_MTHDID_WPEND_PENDING 0x1 /* R---V */
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#define NV_PNVENC_FALCON_MTHDWDAT(dev) (0x001c806c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_MTHDWDAT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDWDAT__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_MTHDWDAT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_MTHDCOUNT(dev) (0x001c8070+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_MTHDCOUNT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */
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#define NV_PNVENC_FALCON_MTHDCOUNT_COUNT_INIT 0x0000 /* R-I-V */
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#define NV_PNVENC_FALCON_MTHDPOP(dev) (0x001c8074+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_FALCON_MTHDPOP__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDPOP__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_MTHDPOP__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDPOP_POP 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_MTHDPOP_POP_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_MTHDPOP_POP_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_MTHDRAMSZ(dev) (0x001c8078+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_MTHDRAMSZ__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */
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#define NV_PNVENC_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_FALCON_CURCTX(dev) (0x001c8050+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_CURCTX__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CURCTX__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CURCTX__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_CURCTX_CTXVLD_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_CURCTX_CTXVLD_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CURCTX_CTXVLD_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PNVENC_FALCON_CURCTX_CTXTGT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PNVENC_FALCON_CURCTX_CTXPTR_INIT 0x0000000 /* RWI-V */
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#define NV_PNVENC_FALCON_NXTCTX(dev) (0x001c8054+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_NXTCTX__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_NXTCTX__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_NXTCTX__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_NXTCTX_CTXVLD_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_NXTCTX_CTXVLD_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_NXTCTX_CTXVLD_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PNVENC_FALCON_NXTCTX_CTXTGT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PNVENC_FALCON_NXTCTX_CTXPTR_INIT 0x0000000 /* RWI-V */
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#define NV_PNVENC_FALCON_CTXACK(dev) (0x001c8058+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_FALCON_CTXACK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CTXACK__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CTXACK__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_CTXACK_SAVE_ACK_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_CTXACK_SAVE_ACK_CLEAR 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_CTXACK_REST_ACK_SET 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_CTXACK_REST_ACK_CLEAR 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_CURCTX2(dev) (0x001c83c8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_CURCTX2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CURCTX2__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CURCTX2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CURCTX2_CTXGFID 5:0 /* RWIVF */
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#define NV_PNVENC_FALCON_CURCTX2_CTXGFID_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_NXTCTX2(dev) (0x001c83cc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_NXTCTX2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_NXTCTX2__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_NXTCTX2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_NXTCTX2_CTXGFID 5:0 /* RWIVF */
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#define NV_PNVENC_FALCON_NXTCTX2_CTXGFID_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_MAILBOX0(dev) (0x001c8040+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_MAILBOX0__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_MAILBOX1(dev) (0x001c8044+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_MAILBOX1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_ITFEN(dev) (0x001c8048+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ITFEN__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ITFEN__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_ITFEN__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_ITFEN_CTXEN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_ITFEN_CTXEN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ITFEN_CTXEN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_ITFEN_MTHDEN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_ITFEN_MTHDEN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ITFEN_MTHDEN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */
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#define NV_PNVENC_FALCON_ITFEN_PRIV_POSTWR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_ITFEN_CTXSW_NACK_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ITFEN_CTXSW_NACK_FALSE 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */
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#define NV_PNVENC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IDLESTATE(dev) (0x001c804c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IDLESTATE__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE__PRIV_LEVEL_MASK(dev) (0x001c81e0+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IDLESTATE__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */
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#define NV_PNVENC_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */
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#define NV_PNVENC_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */
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#define NV_PNVENC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_FHSTATE(dev) (0x001c805c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_FHSTATE__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_FHSTATE__PRIV_LEVEL_MASK(dev) (0x001c81e4+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_FHSTATE__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */
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#define NV_PNVENC_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */
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#define NV_PNVENC_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */
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#define NV_PNVENC_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */
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#define NV_PNVENC_FALCON_FHSTATE_STALL_REQ_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_FHSTATE_STALL_REQ_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_PRIVSTATE(dev) (0x001c8060+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_PRIVSTATE__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE__PRIV_LEVEL_MASK(dev) (0x001c83d0+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_PRIVSTATE__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_PRIV_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_VPR_FORCE_STICKY 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_PRIVSTATE_VPR_FORCE_STICKY_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_SFTRESET(dev) (0x001c807c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SFTRESET__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SFTRESET__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_SFTRESET__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SFTRESET_EXT 0:0 /* RWXVF */
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#define NV_PNVENC_FALCON_SFTRESET_EXT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_SFTRESET_EXT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL(dev) (0x001c80a4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ENGCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */
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#define NV_PNVENC_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */
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#define NV_PNVENC_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */
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#define NV_PNVENC_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */
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#define NV_PNVENC_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */
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#define NV_PNVENC_FALCON_ENGCTL_STALLREQ_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_ENGCTL_STALLREQ_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */
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#define NV_PNVENC_FALCON_ENGCTL_STALLACK_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_ENGCTL_STALLACK_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_ADDR(dev) (0x001c80ac+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ADDR__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_ADDR__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ADDR_LSB 5:0 /* RWIVF */
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#define NV_PNVENC_FALCON_ADDR_LSB_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_ADDR_MSB 11:6 /* RWIVF */
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#define NV_PNVENC_FALCON_ADDR_MSB_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_ADDR_EXT 11:0 /* */
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#define NV_PNVENC_FALCON_DMACTL(dev) (0x001c810c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMACTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMACTL__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMACTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMACTL_REQUIRE_CTX_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
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#define NV_PNVENC_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
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#define NV_PNVENC_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */
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#define NV_PNVENC_FALCON_DMATRFBASE(dev) (0x001c8110+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMATRFBASE__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFBASE__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMATRFBASE__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_DMATRFMOFFS(dev) (0x001c8114+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMATRFMOFFS__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMATRFMOFFS_OFFS_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_DMATRFCMD(dev) (0x001c8118+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMATRFCMD__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFCMD__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMATRFCMD__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
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#define NV_PNVENC_FALCON_DMATRFCMD_FULL_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMATRFCMD_FULL_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
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#define NV_PNVENC_FALCON_DMATRFCMD_IDLE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMATRFCMD_IDLE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
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#define NV_PNVENC_FALCON_DMATRFCMD_IMEM_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMATRFCMD_IMEM_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_WRITE_TRUE 0x1 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_WRITE_FALSE 0x0 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_NOTIFY_TRUE 0x1 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_NOTIFY_FALSE 0x0 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SIZE_4B 0x0 /* RW--V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SIZE_8B 0x1 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SIZE_16B 0x2 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SIZE_32B 0x3 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SIZE_64B 0x4 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SIZE_128B 0x5 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SIZE_256B 0x6 /* RW--V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
|
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#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x1 /* RW--V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x0 /* RW--V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_ERROR_TRUE 0x1 /* R---V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_ERROR_FALSE 0x0 /* R-I-V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x1 /* RW--V */
|
|
#define NV_PNVENC_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x0 /* RW--V */
|
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#define NV_PNVENC_FALCON_DMATRFFBOFFS(dev) (0x001c811c+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_FALCON_DMATRFFBOFFS__SIZE_1 1 /* */
|
|
#define NV_PNVENC_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
|
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#define NV_PNVENC_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB(dev) (0x001c8120+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMAPOLL_FB__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP(dev) (0x001c8124+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMAPOLL_CP__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMATRFBASE1(dev) (0x001c8128+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMATRFBASE1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMATRFBASE1_BASE_INIT 0x000 /* RWI-V */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_LOW(dev) (0x001c82c0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_LOW__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_HIGH(dev) (0x001c82c4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_HIGH__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_LOW(dev) (0x001c82c8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_LOW__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_HIGH(dev) (0x001c82cc+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_HIGH__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_LOW(dev) (0x001c82d0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_LOW__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_HIGH(dev) (0x001c82d4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_HIGH__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_LOW(dev) (0x001c82d8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_LOW__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_HIGH(dev) (0x001c82dc+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_HIGH__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CTL(dev) (0x001c82e0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMAINFO_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_HIGH(dev) (0x001c82e4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_HIGH__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_LOW(dev) (0x001c82e8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_LOW__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK(dev) (0x001c8190+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_IMEMC(dev,i) (0x001c8180+(dev)*16384+(i)*16) /* RW-4A */
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#define NV_PNVENC_FALCON_IMEMC__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEMC__SIZE_2 1 /* */
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#define NV_PNVENC_FALCON_IMEMC__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_IMEMC__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEMC_OFFS_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEMC_BLK 23:8 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEMC_BLK_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEMC_AINCW_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEMC_AINCW_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IMEMC_AINCW_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEMC_AINCR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEMC_AINCR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IMEMC_AINCR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
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#define NV_PNVENC_FALCON_IMEMC_SECURE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
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#define NV_PNVENC_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
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#define NV_PNVENC_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
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#define NV_PNVENC_FALCON_IMEMC_SEC_LOCK_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_IMEMC_SEC_LOCK_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_IMEMD(dev,i) (0x001c8184+(dev)*16384+(i)*16) /* RW-4A */
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#define NV_PNVENC_FALCON_IMEMD__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEMD__SIZE_2 1 /* */
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#define NV_PNVENC_FALCON_IMEMD__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_IMEMD__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEMD_DATA 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_IMEMT(dev,i) (0x001c8188+(dev)*16384+(i)*16) /* RW-4A */
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#define NV_PNVENC_FALCON_IMEMT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEMT__SIZE_2 1 /* */
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#define NV_PNVENC_FALCON_IMEMT__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_IMEMT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEMT_TAG 15:0 /* RWXVF */
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#define NV_PNVENC_FALCON_DMEMC(dev,i) (0x001c81c0+(dev)*16384+(i)*8) /* RW-4A */
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#define NV_PNVENC_FALCON_DMEMC__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEMC__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_DMEMC__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_DMEMC__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEMC_ADDRESS_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEMC_OFFS 7:2 /* */
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#define NV_PNVENC_FALCON_DMEMC_OFFS_INIT 0x00 /* */
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#define NV_PNVENC_FALCON_DMEMC_BLK 23:8 /* */
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#define NV_PNVENC_FALCON_DMEMC_BLK_INIT 0x0000 /* */
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#define NV_PNVENC_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEMC_AINCW_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEMC_AINCW_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_AINCW_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEMC_AINCR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEMC_AINCR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_AINCR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEMC_SETTAG_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEMC_SETTAG_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_SETTAG_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEMC_SETLVL_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEMC_SETLVL_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_SETLVL_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_VA 28:28 /* RWIVF */
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#define NV_PNVENC_FALCON_DMEMC_VA_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DMEMC_VA_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_VA_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMEMC_MISS 29:29 /* R-IVF */
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#define NV_PNVENC_FALCON_DMEMC_MISS_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMEMC_MISS_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
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#define NV_PNVENC_FALCON_DMEMC_MULTIHIT_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMEMC_MULTIHIT_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
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#define NV_PNVENC_FALCON_DMEMC_LVLERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_DMEMC_LVLERR_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_DMEMD(dev,i) (0x001c81c4+(dev)*16384+(i)*8) /* RW-4A */
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#define NV_PNVENC_FALCON_DMEMD__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEMD__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_DMEMD__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_DMEMD__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEMD_DATA 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_DMEMT(dev,i) (0x001c8210+(dev)*16384+(i)*4) /* -W-4A */
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#define NV_PNVENC_FALCON_DMEMT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEMT__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_DMEMT__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_DMEMT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEMT_TAG 15:0 /* -WXVF */
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#define NV_PNVENC_FALCON_DMEML(dev,i) (0x001c82a0+(dev)*16384+(i)*4) /* -W-4A */
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#define NV_PNVENC_FALCON_DMEML__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEML__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_DMEML__PRIV_LEVEL_MASK(dev) NV_PNVENC_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(dev) /* */
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#define NV_PNVENC_FALCON_DMEML__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEML_LVL 2:0 /* -WXVF */
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#define NV_PNVENC_FALCON_DMEM_DUMMY(dev) (0x001c8258+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_DMEM_DUMMY__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK(dev) (0x001c8284+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PNVENC_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PNVENC_FALCON_IMEM_DUMMY(dev) (0x001c81b4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_IMEM_DUMMY__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK(dev) (0x001c8280+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PNVENC_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0(dev,i) (0x001c8300+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK(dev) (0x001c83f0+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1(dev,i) (0x001c8310+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK(dev) (0x001c83f4+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2(dev,i) (0x001c8320+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK(dev) (0x001c83f8+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3(dev,i) (0x001c8330+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_2 4 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK(dev) (0x001c83fc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_PRGNVER(dev) (0x001c83d4+(dev)*16384) /* R-I4A */
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#define NV_PNVENC_FALCON_PRGNVER__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */
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#define NV_PNVENC_FALCON_PRGNVER_MAJOR_DEFT 0x2 /* R-I-V */
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#define NV_PNVENC_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */
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#define NV_PNVENC_FALCON_PRGNVER_MINOR_DEFT 0x0000 /* R-I-V */
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#define NV_PNVENC_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */
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#define NV_PNVENC_FALCON_PRGNVER_BUGFIX_DEFT 0x0000 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG(dev) (0x001c8108+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_HWCFG__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */
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#define NV_PNVENC_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */
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#define NV_PNVENC_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG1(dev) (0x001c812c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_HWCFG1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_INIT 0x6 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_1_0 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_2_0 0x2 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_3_0 0x3 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_4_0 0x4 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_5_0 0x5 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_6_0 0x6 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_7_0 0x7 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x2 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x2 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x3 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x2 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x3 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_IMEM_PORTS_INIT 0x1 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_PORTS_INIT 0x1 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_TAG_WIDTH_INIT 0x10 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x1 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x1 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */
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#define NV_PNVENC_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2(dev) (0x001c80f4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_HWCFG2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_HWCFG2_SHA 0:0 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_SHA_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_SHA_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_BMEM 1:1 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_BMEM_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_BMEM_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_PKCBOOT_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_PKCBOOT_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_DBGMODE_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_DBGMODE_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_KMEM 4:4 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_KMEM_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_KMEM_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_VHR 7:7 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_VHR_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_VHR_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_HS 8:8 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_HS_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_HS_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_SECUREBUS_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_SECUREBUS_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_HWCFG3(dev) (0x001c8278+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_HWCFG3__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */
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#define NV_PNVENC_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */
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#define NV_PNVENC_FALCON_CGCTL(dev) (0x001c80a0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_CGCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_CGCTL_CG_OVERRIDE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2(dev) (0x001c8134+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FALCON_CG2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CG2__PRIV_LEVEL_MASK(dev) (0x001c81e8+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CG2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CG2_SLCG 17:1 /* */
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#define NV_PNVENC_FALCON_CG2_SLCG_ENABLED 0x00000 /* */
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#define NV_PNVENC_FALCON_CG2_SLCG_DISABLED 0x1ffff /* */
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#define NV_PNVENC_FALCON_CG2_SLCG__PROD 0x000a0 /* */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
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#define NV_PNVENC_FALCON_CG2_SLCG_FBIF_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CG2_SLCG_FBIF_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL(dev) (0x001c8240+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SCTL__PRIV_LEVEL_MASK(dev) (0x001c8298+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_SCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SCTL_LSMODE 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_LSMODE_FALSE 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_LSMODE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_HSMODE 1:1 /* R--VF */
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#define NV_PNVENC_FALCON_SCTL_HSMODE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_SCTL_HSMODE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_LSMODE_LEVEL_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_UCODE_LEVEL 5:4 /* */
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#define NV_PNVENC_FALCON_SCTL_UCODE_LEVEL_INIT 0x0 /* */
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#define NV_PNVENC_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL_AUTH_EN_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_SCTL_AUTH_EN_FALSE 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL1(dev) (0x001c8250+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SCTL1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SCTL1__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_SCTL1__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL1_CSBLVL_MASK_INIT 0x3 /* RWI-V */
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#define NV_PNVENC_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */
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#define NV_PNVENC_FALCON_SCTL1_EXTLVL_MASK_INIT 0x3 /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL(dev) (0x001c80e4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_HSCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_HSCTL__PRIV_LEVEL_MASK(dev) (0x001c80e8+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_HSCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_TRACEPC_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_TRACEPC_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_HSCTL_SP_MIN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_HSCTL_SP_MIN_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_OS(dev) (0x001c8080+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_OS__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_OS_VERSION 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_RM(dev) (0x001c8084+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_RM__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_RM_CONFIG 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_SOFT_PM(dev) (0x001c8088+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SOFT_PM__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SOFT_PM__PRIV_LEVEL_MASK(dev) (0x001c81ec+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_SOFT_PM__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */
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#define NV_PNVENC_FALCON_SOFT_PM_TRIGGER_START_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */
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#define NV_PNVENC_FALCON_SOFT_PM_TRIGGER_END_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SOFT_PM_PROBE_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_SOFT_MODE(dev) (0x001c808c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SOFT_MODE__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SOFT_MODE__PRIV_LEVEL_MASK(dev) (0x001c81ec+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_SOFT_MODE__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SOFT_MODE_PROBE_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM(dev) (0x001c80a8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_PMM__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PMM__PRIV_LEVEL_MASK(dev) (0x001c81ec+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_PMM__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_CODE 0x01 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x02 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x03 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x04 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x05 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_IPND 0x06 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x07 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_SB 0x08 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x09 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0a /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0b /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0c /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0d /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0e /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0f /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x10 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x11 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x4 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x5 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x4 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x5 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x6 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x7 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x9 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0xa /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0xb /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM_FBIF_DSTAT_SEL_FB_BSY 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_DSTAT_SEL_RDAT_WAIT 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_DSTAT_SEL_FB_BSY_SC 0x4 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_DSTAT_SEL_RDAT_WAIT_SC 0x5 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_WREQ 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x4 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x5 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RREQ 0x6 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x7 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_WREQ_SC 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x9 /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0xa /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0xb /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0xc /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0xd /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_RREQ_SC 0xe /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0xf /* RW--V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */
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#define NV_PNVENC_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DEBUG1(dev) (0x001c8090+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DEBUG1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DEBUG1__PRIV_LEVEL_MASK(dev) (0x001c8294+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DEBUG1__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x0040 /* RWI-V */
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#define NV_PNVENC_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */
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#define NV_PNVENC_FALCON_DEBUG1_CTXSW_MODE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */
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#define NV_PNVENC_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */
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#define NV_PNVENC_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DEBUGINFO(dev) (0x001c8094+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DEBUGINFO__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_SP_MIN(dev) (0x001c8270+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_SP_MIN__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SP_MIN__PRIV_LEVEL_MASK(dev) (0x001c81f0+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_SP_MIN__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_SP_MIN_VALUE_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_EXCI(dev) (0x001c80d0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_EXCI__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_EXCI__PRIV_LEVEL_MASK(dev) (0x001c81f4+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_EXCI__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_EXCI_EXPC 19:0 /* R-XVF */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_TRAP0 0x00 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_TRAP1 0x01 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_TRAP2 0x02 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_TRAP3 0x03 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_ILL_INS 0x08 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_INV_INS 0x09 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_MISS_INS 0x0a /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0b /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0d /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0f /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x10 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x11 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x12 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x13 /* R---V */
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#define NV_PNVENC_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */
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#define NV_PNVENC_FALCON_EXCI2(dev) (0x001c80bc+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_EXCI2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_EXCI2__PRIV_LEVEL_MASK(dev) (0x001c81f4+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_EXCI2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */
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#define NV_PNVENC_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */
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#define NV_PNVENC_FALCON_SVEC_SPR(dev) (0x001c80d4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_SVEC_SPR__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR__PRIV_LEVEL_MASK(dev) (0x001c81f8+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_SVEC_SPR__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */
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#define NV_PNVENC_FALCON_SVEC_SPR_SIGPASS_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_SVEC_SPR_SIGPASS_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_CPUCTL(dev) (0x001c8100+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_CPUCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CPUCTL__PRIV_LEVEL_MASK(dev) (0x001c8288+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CPUCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
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#define NV_PNVENC_FALCON_CPUCTL_IINVAL_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_IINVAL_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_CPUCTL_STARTCPU_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_STARTCPU_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
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#define NV_PNVENC_FALCON_CPUCTL_SRESET_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_SRESET_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
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#define NV_PNVENC_FALCON_CPUCTL_HRESET_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_HRESET_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
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#define NV_PNVENC_FALCON_CPUCTL_HALTED_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_CPUCTL_HALTED_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
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#define NV_PNVENC_FALCON_CPUCTL_STOPPED_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_CPUCTL_STOPPED_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS_EN_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS_EN_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS_EN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS(dev) (0x001c8130+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x1 /* -W--V */
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#define NV_PNVENC_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x0 /* -W--V */
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#define NV_PNVENC_FALCON_STACKCFG(dev) (0x001c8138+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_STACKCFG__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_STACKCFG__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_STACKCFG__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */
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#define NV_PNVENC_FALCON_STACKCFG_BOTTOM_INIT 0x000000 /* RW--V */
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#define NV_PNVENC_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_STACKCFG_SPEXC_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_STACKCFG_SPEXC_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_STACKCFG_SPEXC_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_BOOTVEC(dev) (0x001c8104+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_BOOTVEC__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC__PRIV_LEVEL_MASK(dev) (0x001c8194+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_BOOTVEC__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL(dev) (0x001c8254+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DBGCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DBGCTL__PRIV_LEVEL_MASK(dev) (0x001c81a8+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DBGCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DBGCTL_VAL 9:0 /* */
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#define NV_PNVENC_FALCON_DBGCTL_VAL_INIT 0x000 /* */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_TRACE_MODE_FULL 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_TRACE_MODE_STACK 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_DBGCTL_CYA 31:16 /* RWIVF */
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#define NV_PNVENC_FALCON_DBGCTL_CYA_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_FALCON_DBGCTL_CYA_ENABLE 0x8afe /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT1(dev) (0x001c8098+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IBRKPT1__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT1__PRIV_LEVEL_MASK(dev) (0x001c81fc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IBRKPT1__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT1_PC 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT1_PC_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT1_SUPPRESS_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT1_SKIP_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT1_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT1_SKIP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT1_EN 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT1_EN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT1_EN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT1_EN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT2(dev) (0x001c809c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IBRKPT2__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT2__PRIV_LEVEL_MASK(dev) (0x001c81fc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IBRKPT2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT2_PC 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT2_PC_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT2_SUPPRESS_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT2_SKIP_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT2_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT2_SKIP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT2_EN 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT2_EN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT2_EN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT2_EN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT3(dev) (0x001c80b0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IBRKPT3__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT3__PRIV_LEVEL_MASK(dev) (0x001c81fc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IBRKPT3__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT3_PC 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT3_PC_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT3_SUPPRESS_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT3_SKIP_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT3_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT3_SKIP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT3_EN 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT3_EN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT3_EN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT3_EN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT4(dev) (0x001c80b4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IBRKPT4__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT4__PRIV_LEVEL_MASK(dev) (0x001c81fc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IBRKPT4__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT4_PC 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT4_PC_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT4_SUPPRESS_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT4_SKIP_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT4_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT4_SKIP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT4_EN 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT4_EN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT4_EN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT4_EN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT5(dev) (0x001c80b8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IBRKPT5__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT5__PRIV_LEVEL_MASK(dev) (0x001c81fc+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IBRKPT5__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IBRKPT5_PC 23:0 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT5_PC_INIT 0x000000 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT5_SUPPRESS_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT5_SKIP_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT5_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT5_SKIP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT5_EN 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_IBRKPT5_EN_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_IBRKPT5_EN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IBRKPT5_EN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD(dev) (0x001c8200+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ICD_CMD__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_CMD__PRIV_LEVEL_MASK(dev) (0x001c8220+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_ICD_CMD__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_STOP 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_RUN 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_JRUN 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_RUNB 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_JRUNB 0x4 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_STEP 0x5 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_JSTEP 0x6 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_EMASK 0x7 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_RREG 0x8 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_WREG 0x9 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_RDM 0xa /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_WDM 0xb /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_RCM 0xc /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_WCM 0xd /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_RSTAT 0xe /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_OPC_SBU 0xf /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_SZ_B 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_SZ_HW 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_SZ_W 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG0 0x00 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG1 0x01 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG2 0x02 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG3 0x03 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG4 0x04 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG5 0x05 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG6 0x06 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG7 0x07 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG8 0x08 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG9 0x09 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG10 0x0a /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG11 0x0b /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG12 0x0c /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG13 0x0d /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG14 0x0e /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_REG15 0x0f /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_IV0 0x10 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_IV1 0x11 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_EV 0x13 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_SP 0x14 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_PC 0x15 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_IMB 0x16 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_DMB 0x17 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_CSW 0x18 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_CCR 0x19 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_SEC 0x1a /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_CTX 0x1b /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_EXCI 0x1c /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_SEC1 0x1e /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_IMB1 0x1e /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_DMB1 0x1f /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_RSTAT0 0x00 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_RSTAT1 0x01 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_RSTAT2 0x02 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_RSTAT3 0x03 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_RSTAT4 0x04 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_RSTAT5 0x05 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_WB0 0x00 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_WB1 0x01 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_WB2 0x02 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_IDX_WB3 0x03 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */
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#define NV_PNVENC_FALCON_ICD_CMD_ERROR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_ICD_CMD_ERROR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */
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#define NV_PNVENC_FALCON_ICD_CMD_RDVLD_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FALCON_ICD_CMD_RDVLD_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FALCON_ICD_CMD_PARM 31:16 /* */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK 31:16 /* */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_ADDR(dev) (0x001c8204+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ICD_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_ADDR__PRIV_LEVEL_MASK(dev) (0x001c8220+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_ICD_ADDR__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_WDATA(dev) (0x001c8208+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_ICD_WDATA__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_WDATA__PRIV_LEVEL_MASK(dev) (0x001c8220+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_ICD_WDATA__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_ICD_RDATA(dev) (0x001c820c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_ICD_RDATA__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA__PRIV_LEVEL_MASK(dev) (0x001c8220+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_ICD_RDATA__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 0x2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 0x2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 0x2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 0x2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 0x2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 0x3 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 0x4 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 0x5 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 0x6 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 0x7 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 0x2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 0x3 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 0x2 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 0x1 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0x0 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */
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#define NV_PNVENC_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */
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#define NV_PNVENC_FALCON_RSTAT0(dev) (0x001c80d8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_RSTAT0__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_RSTAT0__PRIV_LEVEL_MASK(dev) (0x001c8224+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_RSTAT0__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_VALID 28:28 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3(dev) (0x001c80dc+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_RSTAT3__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */
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#define NV_PNVENC_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */
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#define NV_PNVENC_FALCON_TRACEIDX(dev) (0x001c8148+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_TRACEIDX__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TRACEIDX__PRIV_LEVEL_MASK(dev) (0x001c819c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_TRACEIDX__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */
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#define NV_PNVENC_FALCON_TRACEIDX_CNT_INIT 0x00 /* R-I-V */
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#define NV_PNVENC_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */
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#define NV_PNVENC_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */
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#define NV_PNVENC_FALCON_TRACEIDX_IDX_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_FALCON_TRACEPC(dev) (0x001c814c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_TRACEPC__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TRACEPC__PRIV_LEVEL_MASK(dev) (0x001c819c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_TRACEPC__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TRACEPC_PC 23:0 /* R--VF */
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#define NV_PNVENC_FALCON_TRACEINFO(dev) (0x001c817c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_TRACEINFO__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TRACEINFO__PRIV_LEVEL_MASK(dev) (0x001c819c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_TRACEINFO__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */
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#define NV_PNVENC_FALCON_IMCTL(dev) (0x001c8140+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IMCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMCTL__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IMCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PNVENC_FALCON_IMCTL_CMD 26:24 /* RWXVF */
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#define NV_PNVENC_FALCON_IMCTL_CMD_NOP 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMCTL_CMD_IMINV 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_IMCTL_CMD_IMBLK 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_IMCTL_CMD_IMTAG 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x4 /* RW--V */
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#define NV_PNVENC_FALCON_IMCTL_DEBUG(dev) (0x001c815c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IMCTL_DEBUG__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PNVENC_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */
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#define NV_PNVENC_FALCON_IMCTL_DEBUG_CMD_NOP 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_IMSTAT(dev) (0x001c8144+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_IMSTAT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMSTAT__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_IMSTAT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_IMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_DMCTL(dev) (0x001c8260+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMCTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMCTL__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMCTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PNVENC_FALCON_DMCTL_CMD 26:24 /* RWXVF */
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#define NV_PNVENC_FALCON_DMCTL_CMD_NOP 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_DMCTL_CMD_DMINV 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_DMCTL_CMD_DMBLK 0x2 /* RW--V */
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#define NV_PNVENC_FALCON_DMCTL_CMD_DMTAG 0x3 /* RW--V */
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#define NV_PNVENC_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x4 /* RW--V */
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#define NV_PNVENC_FALCON_DMCTL_CMD_DMCLEAN 0x5 /* RW--V */
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#define NV_PNVENC_FALCON_DMCTL_CMD_DMLVL 0x6 /* RW--V */
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#define NV_PNVENC_FALCON_DMSTAT(dev) (0x001c8264+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMSTAT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMSTAT__PRIV_LEVEL_MASK(dev) (0x001c828c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMSTAT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PNVENC_FALCON_DMVACTL(dev) (0x001c8268+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_DMVACTL__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMVACTL__PRIV_LEVEL_MASK(dev) (0x001c8198+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_DMVACTL__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */
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#define NV_PNVENC_FALCON_DMVACTL_BOUND_INIT 0x00000080 /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERRSTAT(dev) (0x001c8244+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FALCON_CSBERRSTAT__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK(dev) (0x001c822c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */
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#define NV_PNVENC_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERRSTAT_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERRSTAT_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERRSTAT_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */
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#define NV_PNVENC_FALCON_CSBERRSTAT_VALID_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FALCON_CSBERRSTAT_VALID_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERRSTAT_VALID_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FALCON_CSBERR_ADDR(dev) (0x001c824c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_CSBERR_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK(dev) (0x001c822c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FALCON_CSBERR_INFO(dev) (0x001c8248+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FALCON_CSBERR_INFO__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK(dev) (0x001c822c+(dev)*16384) /* */
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#define NV_PNVENC_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* RWI4A */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0xf /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0xf /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x8 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x0 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0xfffff /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG(dev,i) (0x001c8800+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_FBIF_TRANSCFG__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_TRANSCFG__SIZE_2 8 /* */
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#define NV_PNVENC_FBIF_TRANSCFG__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_TRANSCFG__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_TARGET_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x0 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x1 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x2 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_MEM_TYPE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x0 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x1 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_WR_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x0 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x1 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x2 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_RD_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x0 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x1 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x2 /* R---V */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK0_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK0_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK0_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK1_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_WACHK1_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK0_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK0_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK0_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK1_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_RACHK1_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_TRANSCFG_ENGINE_ID_FLAG 16:16 /* RWIVF */
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#define NV_PNVENC_FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_TRANSCFG_ENGINE_ID_FLAG_OWN 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_INSTBLK(dev) (0x001c8820+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_INSTBLK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_INSTBLK_PTR 27:0 /* R--VF */
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#define NV_PNVENC_FBIF_INSTBLK_TARGET 29:28 /* R--VF */
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#define NV_PNVENC_FBIF_INSTBLK_TARGET_LOCAL_FB 0x0 /* R---V */
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#define NV_PNVENC_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x1 /* R---V */
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#define NV_PNVENC_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x2 /* R---V */
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#define NV_PNVENC_FBIF_BIND_STATUS(dev) (0x001c8828+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_BIND_STATUS__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_BIND_STATUS_STATUS 1:0 /* R-IVF */
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#define NV_PNVENC_FBIF_BIND_STATUS_STATUS_NOT_BIND 0x0 /* R-I-V */
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#define NV_PNVENC_FBIF_BIND_STATUS_STATUS_BOUND 0x2 /* R---V */
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#define NV_PNVENC_FBIF_BIND_STATUS_GFID 9:4 /* R--VF */
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#define NV_PNVENC_FBIF_BIND_STATUS_GFID_INIT 0x00 /* R---V */
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#define NV_PNVENC_FBIF_BIND_STATUS_ENGINE_ID 23:16 /* R--VF */
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#define NV_PNVENC_FBIF_CTL(dev) (0x001c8824+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FBIF_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_CTL_FLUSH 0:0 /* RW-VF */
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#define NV_PNVENC_FBIF_CTL_FLUSH_SET 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_FLUSH_CLEAR 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */
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#define NV_PNVENC_FBIF_CTL_INVAL_CONTEXT_SET 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */
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#define NV_PNVENC_FBIF_CTL_CLR_BWCOUNT_SET 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_ENABLE 4:4 /* RWIVF */
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#define NV_PNVENC_FBIF_CTL_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_CTL_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */
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#define NV_PNVENC_FBIF_CTL_CLR_IDLEWDERR_SET 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_RESET 6:6 /* RW-VF */
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#define NV_PNVENC_FBIF_CTL_RESET_SET 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_RESET_CLEAR 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
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#define NV_PNVENC_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_IDLE 8:8 /* R--VF */
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#define NV_PNVENC_FBIF_CTL_IDLE_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FBIF_CTL_IDLE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */
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#define NV_PNVENC_FBIF_CTL_IDLEWDERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FBIF_CTL_IDLEWDERR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_CTL_SRTOUT 10:10 /* R--VF */
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#define NV_PNVENC_FBIF_CTL_SRTOUT_TRUE 0x1 /* R---V */
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#define NV_PNVENC_FBIF_CTL_SRTOUT_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */
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#define NV_PNVENC_FBIF_CTL_CLR_SRTOUT_SET 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_CLR_SRTOUT_CLEAR 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */
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#define NV_PNVENC_FBIF_CTL_SRTOVAL_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_THROTTLE(dev) (0x001c882c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FBIF_THROTTLE__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_PNVENC_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x064 /* RWI-V */
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#define NV_PNVENC_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_PNVENC_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x000 /* RWI-V */
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#define NV_PNVENC_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_PNVENC_FBIF_THROTTLE_LEAK_SIZE_16B 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_THROTTLE_LEAK_SIZE_32B 0x1 /* RW--V */
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#define NV_PNVENC_FBIF_THROTTLE_LEAK_SIZE_64B 0x2 /* RWI-V */
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#define NV_PNVENC_FBIF_THROTTLE_LEAK_SIZE_128B 0x3 /* RW--V */
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#define NV_PNVENC_FBIF_REGIONCFG(dev) (0x001c886c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FBIF_REGIONCFG__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_REGIONCFG__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_REGIONCFG_T0 3:0 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T0_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_T1 7:4 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_T2 11:8 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T2_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_T3 15:12 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T3_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_T4 19:16 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T4_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_T5 23:20 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T5_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_T6 27:24 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T6_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_REGIONCFG_T7 31:28 /* RWIVF */
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#define NV_PNVENC_FBIF_REGIONCFG_T7_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_FBIF_CG1(dev) (0x001c8874+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FBIF_CG1__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_CG1_SLCG 3:0 /* */
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#define NV_PNVENC_FBIF_CG1_SLCG_ENABLED 0x0 /* */
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#define NV_PNVENC_FBIF_CG1_SLCG_DISABLED 0xf /* */
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#define NV_PNVENC_FBIF_CG1_SLCG__PROD 0x0 /* */
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#define NV_PNVENC_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */
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#define NV_PNVENC_FBIF_CG1_SLCG_MSD0_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CG1_SLCG_MSD0_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */
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#define NV_PNVENC_FBIF_CG1_SLCG_MSD1_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CG1_SLCG_MSD1_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */
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#define NV_PNVENC_FBIF_CG1_SLCG_FB0_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CG1_SLCG_FB0_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */
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#define NV_PNVENC_FBIF_CG1_SLCG_FB1_ENABLED 0x0 /* RW--V */
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#define NV_PNVENC_FBIF_CG1_SLCG_FB1_DISABLED 0x1 /* RWI-V */
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#define NV_PNVENC_FBIF_ACHK_BLK(dev,i) (0x001c8830+(dev)*16384+(i)*8) /* RW-4A */
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#define NV_PNVENC_FBIF_ACHK_BLK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_ACHK_BLK__SIZE_2 2 /* */
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#define NV_PNVENC_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */
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#define NV_PNVENC_FBIF_ACHK_CTL(dev,i) (0x001c8834+(dev)*16384+(i)*8) /* RW-4A */
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#define NV_PNVENC_FBIF_ACHK_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_ACHK_CTL__SIZE_2 2 /* */
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#define NV_PNVENC_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */
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#define NV_PNVENC_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */
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#define NV_PNVENC_FBIF_ACHK_CTL_TYPE_INSIDE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x1 /* R---V */
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#define NV_PNVENC_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */
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#define NV_PNVENC_FBIF_ACHK_CTL_STATE_DISABLE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_ACHK_CTL_STATE_ENABLE 0x1 /* R---V */
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#define NV_PNVENC_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */
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#define NV_PNVENC_FBIF_DBG_STAT0(dev) (0x001c8840+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_DBG_STAT0__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_STAT0__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_DBG_STAT0__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE 3:0 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_IDLE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_CHECK 0x1 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_ALLOC 0x2 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_ISSUE 0x3 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_WDAT 0x4 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_FLT_FLUSH 0x5 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_HALT 0x6 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_INST 0x7 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_INST_ACK 0x8 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_OBJ 0x9 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DSP_STATE_FLUSH 0xa /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_INST_VLD 4:4 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_INST_BOUND 5:5 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_RICF_HAS_DATA 6:6 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_ARQ_HAS_DATA 7:7 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_MRQ_HAS_DATA 8:8 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_FAULT_OR_HALT 9:9 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_ORQ_NOT_FULL 10:10 /* R-IUF */
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#define NV_PNVENC_FBIF_DBG_STAT0_ORQ_NOT_FULL_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_FBIF_DBG_STAT0_ORQ_NOT_FULL_FLASE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_FLUSH_OUTSTANDING 11:11 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_DISPATCH_IDLE 12:12 /* R-IUF */
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#define NV_PNVENC_FBIF_DBG_STAT0_DISPATCH_IDLE_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_FBIF_DBG_STAT0_DISPATCH_IDLE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_MWF_FSM_STATE 17:16 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_MWF_FSM_STATE_IDLE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_MWF_FSM_STATE_COMMIT 0x1 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_MWF_FSM_STATE_ROLLBACK 0x2 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT0_MWF_HAS_DATA 18:18 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_MWF_COMMIT_COUNT 24:19 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_STALL_RQQ_FULL 25:25 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_STALL_WDF_FULL 26:26 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_STALL_FB_BUSY 27:27 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_STALL_ORQ_FULL 28:28 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_STALL_RDM_ALLOC 29:29 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_STALL_RDM_PORTQ 30:30 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT0_STALL_RDM_CLIENT 31:31 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1(dev) (0x001c8844+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_DBG_STAT1__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_STAT1__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_DBG_STAT1__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_STAT1_FLT_STATE 1:0 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FLT_FAULTED 2:2 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FLT_BUSY 3:3 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_ACKF_HAS_DATA 4:4 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_ORQ_HAS_DATA 5:5 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_ALL_READS_DONE 6:6 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FBR_IDLE 8:8 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FBR_FAULTED 9:9 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FBR_FB_BUSY 10:10 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FBR_PKT2FB_VLD 11:11 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FBR_RCV_DATA_VALID 12:12 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_FBR_RCV_DATA_TYPE 15:14 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_WDF_FSM_STATE 17:16 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_WDF_FSM_STATE_IDLE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT1_WDF_FSM_STATE_COMMIT 0x1 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT1_WDF_FSM_STATE_ROLLBACK 0x2 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT1_WDF_HAS_DATA 18:18 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_WDF_COMMIT_COUNT 23:19 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDM_STATE 25:24 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDM_STATE_IDLE 0x0 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDM_STATE_WAITBUF 0x1 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDM_STATE_SAVEBUF 0x2 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDM_ANY_READY 26:26 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDM_DAQ_HAS_DATA 27:27 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDM_DEALLOC_COUNT 30:28 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT1_RDATA_WAIT 31:31 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT2(dev) (0x001c8848+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_DBG_STAT2__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_STAT2__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_DBG_STAT2__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_STAT2_FAULTED_PORTID 5:0 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT2_FAULTED_SUBID 12:6 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT2_FAULTED_SRCQ 13:13 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_STAT2_FAULTED_SRCQ_ARQ 0x1 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT2_FAULTED_SRCQ_MRQ 0x0 /* R---V */
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#define NV_PNVENC_FBIF_DBG_STAT2_FAULTED_VLD 14:14 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_LO(dev) (0x001c8850+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_LO__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_LO_DATA 31:0 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_HI(dev) (0x001c8854+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_HI__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_RDCOUNT_HI_DATA 31:0 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_LO(dev) (0x001c8858+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_LO__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_LO_DATA 31:0 /* R--UF */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_HI(dev) (0x001c885c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_HI__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK(dev) (0x001c8870+(dev)*16384) /* */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_DBG_WRCOUNT_HI_DATA 31:0 /* R--UF */
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#define NV_PNVENC_FBIF_BW_ALLOC(dev) (0x001c884c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FBIF_BW_ALLOC__SIZE_1 1 /* */
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#define NV_PNVENC_FBIF_BW_ALLOC_VAL 31:0 /* */
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#define NV_PNVENC_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */
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#define NV_PNVENC_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */
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#define NV_PNVENC_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */
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#define NV_PNVENC_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */
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#define NV_PNVENC_RMVP_BASE(dev) (0x001c8900+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RMVP_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_RMVP_BASE_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_RMVP_STRIDE_IN_MB(dev) (0x001c8904+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RMVP_STRIDE_IN_MB__SIZE_1 1 /* */
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#define NV_PNVENC_RMVP_STRIDE_IN_MB_VAL 12:0 /* RWXUF */
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#define NV_PNVENC_RMVP_MB_WIDTH(dev) (0x001c8908+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RMVP_MB_WIDTH__SIZE_1 1 /* */
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#define NV_PNVENC_RMVP_MB_WIDTH_VAL 12:0 /* RWXUF */
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#define NV_PNVENC_RMVP_MB_WIDTH_CTBSIZE 17:16 /* RWIUF */
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#define NV_PNVENC_RMVP_MB_WIDTH_CTBSIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_RMVP_MB_WIDTH_CTBSIZE_16X16 0x0 /* RW--V */
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#define NV_PNVENC_RMVP_MB_WIDTH_CTBSIZE_32X32 0x1 /* RW--V */
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#define NV_PNVENC_RMVP_MB_WIDTH_CTBSIZE_64X64 0x2 /* RW--V */
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#define NV_PNVENC_RMVP_MB_HEIGHT(dev) (0x001c890c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RMVP_MB_HEIGHT__SIZE_1 1 /* */
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#define NV_PNVENC_RMVP_MB_HEIGHT_VAL 12:0 /* RWXUF */
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#define NV_PNVENC_RMVP_CTL(dev) (0x001c8910+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RMVP_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_RMVP_CTL_START 0:0 /* RWXUF */
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#define NV_PNVENC_RMVP_CTL_SOURCE_HALF_SCALED 3:1 /* RWIUF */
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#define NV_PNVENC_RMVP_CTL_SOURCE_HALF_SCALED_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_RMVP_CTL_SOURCE_HALF_SCALED_ORIGINA 0x0 /* RW--V */
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#define NV_PNVENC_RMVP_CTL_SOURCE_HALF_SCALED_HALF 0x1 /* RW--V */
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#define NV_PNVENC_RMVP_CTL_SOURCE_HALF_SCALED_QUARTER 0x2 /* RW--V */
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#define NV_PNVENC_RMVP_CTL_SOURCE_HALF_SCALED_EIGHTH 0x3 /* RW--V */
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#define NV_PNVENC_RMVP_CTL_SOURCE_HALF_SCALED_SIXTEENTH 0x4 /* RW--V */
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#define NV_PNVENC_RMVP_CTL_START_ADDR_OFFSET 5:4 /* RWIUF */
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#define NV_PNVENC_RMVP_CTL_START_ADDR_OFFSET_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_RMVP_DBG(dev) (0x001c8914+(dev)*16384) /* R--4A */
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#define NV_PNVENC_RMVP_DBG__SIZE_1 1 /* */
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#define NV_PNVENC_RMVP_DBG_RDMA_RDVLD 0:0 /* R--VF */
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#define NV_PNVENC_RMVP_DBG_RDMA_WNUM 3:1 /* R--VF */
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#define NV_PNVENC_RMVP_DBG_ALLOC_CNT 6:4 /* R--VF */
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#define NV_PNVENC_RMVP_DBG_FULL_CNT 9:7 /* R--VF */
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#define NV_PNVENC_RMVP_DBG_OPKT_VLD 10:10 /* R--VF */
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#define NV_PNVENC_RMVP_DBG_OPKT_RDY 11:11 /* R--VF */
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#define NV_PNVENC_RMVP_DBG_IDLE 12:12 /* R--VF */
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#define NV_PNVENC_WMVP_BASE(dev) (0x001c8980+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_WMVP_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_WMVP_BASE_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_WMVP_CTL(dev) (0x001c8984+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_WMVP_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_WMVP_CTL_START 0:0 /* -WIVF */
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#define NV_PNVENC_WMVP_CTL_START_INIT 0x0 /* -WI-V */
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#define NV_PNVENC_WMVP_CTL_RST_DMA 1:1 /* -WIVF */
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#define NV_PNVENC_WMVP_CTL_RST_DMA_INIT 0x1 /* -WI-V */
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#define NV_PNVENC_WMVP_STRIDE(dev) (0x001c8988+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_WMVP_STRIDE__SIZE_1 1 /* */
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#define NV_PNVENC_WMVP_STRIDE_VAL 12:0 /* RWXUF */
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#define NV_PNVENC_WMVP_STRIDE_START_ADDR_OFFSET 14:13 /* RWXUF */
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#define NV_PNVENC_WMVP_MB_WIDTH(dev) (0x001c898c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_WMVP_MB_WIDTH__SIZE_1 1 /* */
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#define NV_PNVENC_WMVP_MB_WIDTH_VAL 12:0 /* RWXUF */
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#define NV_PNVENC_WMVP_MB_WIDTH_CTBSIZE 17:16 /* RWIUF */
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#define NV_PNVENC_WMVP_MB_WIDTH_CTBSIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_WMVP_MB_WIDTH_CTBSIZE_16X16 0x0 /* RW--V */
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#define NV_PNVENC_WMVP_MB_WIDTH_CTBSIZE_32X32 0x1 /* RW--V */
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#define NV_PNVENC_WMVP_MB_WIDTH_CTBSIZE_64X64 0x2 /* RW--V */
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#define NV_PNVENC_WMVP_MB_HEIGHT(dev) (0x001c8990+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_WMVP_MB_HEIGHT__SIZE_1 1 /* */
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#define NV_PNVENC_WMVP_MB_HEIGHT_VAL 12:0 /* RWXUF */
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#define NV_PNVENC_WMVP_DBG(dev) (0x001c8994+(dev)*16384) /* R--4A */
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#define NV_PNVENC_WMVP_DBG__SIZE_1 1 /* */
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#define NV_PNVENC_WMVP_DBG_ACKCNT 1:0 /* R--VF */
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#define NV_PNVENC_WMVP_DBG_STATE 4:2 /* R--VF */
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#define NV_PNVENC_WMVP_DBG_MBX 17:5 /* R--VF */
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#define NV_PNVENC_WMVP_DBG_MBY 29:18 /* R--VF */
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#define NV_PNVENC_WMVP_DBG_WA 31:30 /* R--VF */
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#define NV_PNVENC_FRAME_CONFIG(dev) (0x001c9800+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_FRAME_CONFIG__SIZE_1 1 /* */
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#define NV_PNVENC_FRAME_CONFIG_FRAME_TYPE 1:0 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_FRAME_TYPE_P_FRAME 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_FRAME_TYPE_B_FRAME 0x1 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_FRAME_TYPE_I_FRAME 0x2 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_REF_MPEC_NAL_REF_IDC 9:8 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_REF_MPEC_NAL_REF_IDC_NONREF 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_REF_MPEC_NAL_REF_IDC_REF 0x3 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_FRAME_TYPE_IDR 10:10 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_FRAME_TYPE_IDR_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_FRAME_TYPE_IDR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_FIELD_PIC_FLAG 11:11 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_FIELD_PIC_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_FIELD_PIC_FLAG_FRAME_MODE 0x0 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_FIELD_PIC_FLAG_FIELD_MODE 0x1 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_BOTTOM_FIELD_FLAG 12:12 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_BOTTOM_FIELD_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_BOTTOM_FIELD_FLAG_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_BOTTOM_FIELD_FLAG_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_COLOUR_PLANE_ID 14:13 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_COLOUR_PLANE_ID_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_H265_NAL_UNIT_TYPE 20:15 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_H265_NAL_UNIT_TYPE_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_MEONLY 21:21 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_MEONLY_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_MEONLY_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_MEONLY_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_FRAME_CONFIG_H265_NUH_TEMPORAL_ID_PLUS1 25:22 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_H265_NUH_TEMPORAL_ID_PLUS1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CONFIG_H265_NUH_LAYER_ID 31:26 /* RWIUF */
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#define NV_PNVENC_FRAME_CONFIG_H265_NUH_LAYER_ID_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_DELTA_PIC_ORDER_CNT_BOTTOM(dev) (0x001c9804+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_DELTA_PIC_ORDER_CNT_BOTTOM__SIZE_1 1 /* */
|
|
#define NV_PNVENC_DELTA_PIC_ORDER_CNT_BOTTOM_CNT 31:0 /* RWIUF */
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#define NV_PNVENC_DELTA_PIC_ORDER_CNT_BOTTOM_CNT_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_FRAME_SIZE(dev) (0x001c9808+(dev)*16384) /* RW-4A */
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|
#define NV_PNVENC_FRAME_SIZE__SIZE_1 1 /* */
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|
#define NV_PNVENC_FRAME_SIZE_WIDTH 12:0 /* RWIUF */
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#define NV_PNVENC_FRAME_SIZE_WIDTH_DEFAULT 0x0000 /* RWI-V */
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|
#define NV_PNVENC_FRAME_SIZE_HEIGHT 28:16 /* RWIUF */
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#define NV_PNVENC_FRAME_SIZE_HEIGHT_DEFAULT 0x0000 /* RWI-V */
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|
#define NV_PNVENC_SEQ_PARAMETERS(dev) (0x001c980c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_SEQ_PARAMETERS__SIZE_1 1 /* */
|
|
#define NV_PNVENC_SEQ_PARAMETERS_PIC_ORDER_CNT_TYPE 1:0 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_PIC_ORDER_CNT_TYPE_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_FRAME_MBS_ONLY 2:2 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_FRAME_MBS_ONLY_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_DIRECT_8X8_INFERENCE_FLAG 3:3 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_DIRECT_8X8_INFERENCE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC 5:4 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_MONOCHROME 0x0 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_420 0x1 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_422 0x2 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_444 0x3 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_SEPARATE_COLOUR_PLANE_FLAG 6:6 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_SEPARATE_COLOUR_PLANE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_SEPARATE_COLOUR_PLANE_FLAG_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_SEPARATE_COLOUR_PLANE_FLAG_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_INVALID 7:7 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_INVALID_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_INVALID_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_INVALID_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 11:8 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_LOG2_MAX_FRAME_NUM_MINUS4 15:12 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_LOG2_MAX_FRAME_NUM_MINUS4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_CODEC_MODE 18:16 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_CODEC_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_CODEC_MODE_H264 0x0 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CODEC_MODE_MPEG4 0x1 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CODEC_MODE_VP8 0x2 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CODEC_MODE_H265 0x5 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_CODEC_MODE_VP9 0x6 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_QPPRIME_Y_ZERO_TRANS_BYPASS 19:19 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_QPPRIME_Y_ZERO_TRANS_BYPASS_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_QPPRIME_Y_ZERO_TRANS_BYPASS_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_QPPRIME_Y_ZERO_TRANS_BYPASS_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_BIT_DEPTH_MINUS8 23:20 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_BIT_DEPTH_MINUS8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_BIT_DEPTH_MINUS8_MAIN10 0x2 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_H265_MODE_DECISION_ONLY 24:24 /* RWIUF */
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#define NV_PNVENC_SEQ_PARAMETERS_H265_MODE_DECISION_ONLY_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SEQ_PARAMETERS_H265_MODE_DECISION_ONLY_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_SEQ_PARAMETERS_H265_MODE_DECISION_ONLY_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_FRAME_ID(dev) (0x001c9810+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_FRAME_ID__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MPEC_FRAME_ID_H264_FRAME_NUM 15:0 /* RWIUF */
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#define NV_PNVENC_MPEC_FRAME_ID_H264_FRAME_NUM_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEC_FRAME_ID_PIC_ORDER_CNT_LSB 31:16 /* RWIUF */
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#define NV_PNVENC_MPEC_FRAME_ID_PIC_ORDER_CNT_LSB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PIC_PARAMETERS(dev) (0x001c9814+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PIC_PARAMETERS__SIZE_1 1 /* */
|
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#define NV_PNVENC_PIC_PARAMETERS_ENTROPY_CODING_MODE 0:0 /* RWIUF */
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#define NV_PNVENC_PIC_PARAMETERS_ENTROPY_CODING_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PIC_PARAMETERS_ENTROPY_CODING_MODE_CAVLC 0x0 /* RW--V */
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#define NV_PNVENC_PIC_PARAMETERS_ENTROPY_CODING_MODE_CABAC 0x1 /* RW--V */
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#define NV_PNVENC_PIC_PARAMETERS_PIC_ORDER_PRESENT 1:1 /* RWIUF */
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#define NV_PNVENC_PIC_PARAMETERS_PIC_ORDER_PRESENT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PIC_PARAMETERS_CONSTRAINED_INTRA_PRED 2:2 /* RWIUF */
|
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#define NV_PNVENC_PIC_PARAMETERS_CONSTRAINED_INTRA_PRED_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PIC_PARAMETERS_TRANSFORM_8X8_MODE_FLAG 3:3 /* RWIUF */
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#define NV_PNVENC_PIC_PARAMETERS_TRANSFORM_8X8_MODE_FLAG_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_PIC_PARAMETERS_TRANSFORM_8X8_MODE_FLAG_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_PIC_PARAMETERS_TRANSFORM_8X8_MODE_FLAG_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_PIC_PARAMETERS_PIC_INIT_QP_MINUS26 9:4 /* RWIUF */
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#define NV_PNVENC_PIC_PARAMETERS_PIC_INIT_QP_MINUS26_VALUE 0x00 /* RWI-V */
|
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#define NV_PNVENC_PIC_PARAMETERS_CHROMA_QP_INDEX 16:12 /* RWIUF */
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#define NV_PNVENC_PIC_PARAMETERS_CHROMA_QP_INDEX_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_PIC_PARAMETERS_SECOND_CHROMA_QP_INDEX 24:20 /* RWIUF */
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#define NV_PNVENC_PIC_PARAMETERS_SECOND_CHROMA_QP_INDEX_DEFAULT 0x00 /* RWI-V */
|
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#define NV_PNVENC_PIC_PARAMETERS_WEIGHTED_PRED_FLAG 25:25 /* RWIUF */
|
|
#define NV_PNVENC_PIC_PARAMETERS_WEIGHTED_PRED_FLAG_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_PIC_PARAMETERS_WEIGHTED_BIPRED_IDC 27:26 /* RWIUF */
|
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#define NV_PNVENC_PIC_PARAMETERS_WEIGHTED_BIPRED_IDC_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_PIC_PARAM_SET_ID(dev) (0x001c9818+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_PIC_PARAM_SET_ID__SIZE_1 1 /* */
|
|
#define NV_PNVENC_PIC_PARAM_SET_ID_PIC_PARAM_SET_ID 7:0 /* RWIUF */
|
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#define NV_PNVENC_PIC_PARAM_SET_ID_PIC_PARAM_SET_ID_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_NUM_REF_IDX_ACTIVE(dev) (0x001c981c+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_NUM_REF_IDX_ACTIVE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_NUM_REF_IDX_ACTIVE_NUM_REF_IDX_L0_ACTIVE_MINUS1 4:0 /* RWIUF */
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#define NV_PNVENC_NUM_REF_IDX_ACTIVE_NUM_REF_IDX_L0_ACTIVE_MINUS1_DEFAULT 0x00 /* RWI-V */
|
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#define NV_PNVENC_NUM_REF_IDX_ACTIVE_NUM_REF_IDX_L1_ACTIVE_MINUS1 12:8 /* RWIUF */
|
|
#define NV_PNVENC_NUM_REF_IDX_ACTIVE_NUM_REF_IDX_L1_ACTIVE_MINUS1_DEFAULT 0x00 /* RWI-V */
|
|
#define NV_PNVENC_NUM_REF_IDX_ACTIVE_NUM_REF_IDX_ACTIVE_OVERRIDE_FLAG 16:16 /* RWIUF */
|
|
#define NV_PNVENC_NUM_REF_IDX_ACTIVE_NUM_REF_IDX_ACTIVE_OVERRIDE_FLAG_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_IDR_PIC_ID(dev) (0x001c9820+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_IDR_PIC_ID__SIZE_1 1 /* */
|
|
#define NV_PNVENC_IDR_PIC_ID_IDR_PIC_ID_VALUE 15:0 /* RWIUF */
|
|
#define NV_PNVENC_IDR_PIC_ID_IDR_PIC_ID_VALUE_DEFAULT 0x0000 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL(dev) (0x001c9824+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_FRAME_CTRL__SIZE_1 1 /* */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_SLICE_ALPHA_C0_OFFSET_DIV2 3:0 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_SLICE_ALPHA_C0_OFFSET_DIV2_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_SLICE_BETA_OFFSET_DIV2 7:4 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_SLICE_BETA_OFFSET_DIV2_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG 8:8 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG_OFF 0x0 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG_ON 0x1 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_MPEB_RECON_OUTPUT 9:9 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_MPEB_RECON_OUTPUT_DISABLE 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_MPEB_RECON_OUTPUT_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_DISABLE_DEBLOCKING_FILTER_IDC 11:10 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_DISABLE_DEBLOCKING_FILTER_IDC_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE_ACROSS_SLICE 0x0 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_DISABLE_DEBLOCKING_FILTER_IDC_DISABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_DISABLE_DEBLOCKING_FILTER_IDC_ENABLE_NOT_ACROSS_SLICE 0x2 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_CABAC_INIT_IDC 13:12 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_CABAC_INIT_IDC_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_CABAC_ZERO_WORD_ENABLE 14:14 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_CABAC_ZERO_WORD_ENABLE_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_CABAC_ZERO_WORD_ENABLE_OFF 0x0 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_CABAC_ZERO_WORD_ENABLE_ON 0x1 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_B_DIRECT_MODE 17:16 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_B_DIRECT_MODE_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_B_DIRECT_MODE_TEMPORAL 0x0 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_B_DIRECT_MODE_SPATIAL 0x1 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_B_DIRECT_MODE_DISABLE 0x2 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_OUTPUT_SUBSAMPLING 18:18 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_OUTPUT_SUBSAMPLING_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_FRAME_CTRL_OUTPUT_SUBSAMPLING_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_OUTPUT_SUBSAMPLING_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_FRAME_CTRL_ACCURATE_SKIP 19:19 /* RWIUF */
|
|
#define NV_PNVENC_FRAME_CTRL_ACCURATE_SKIP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_FRAME_CTRL_ACCURATE_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_FRAME_CTRL_ACCURATE_SKIP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEB_MISC_CTRL(dev) (0x001c9828+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_MISC_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_MISC_CTRL_LUMA_STRIDE 12:0 /* RWIVF */
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#define NV_PNVENC_MPEB_MISC_CTRL_LUMA_STRIDE_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_MISC_CTRL_CHROMA_STRIDE 29:16 /* RWIVF */
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#define NV_PNVENC_MPEB_MISC_CTRL_CHROMA_STRIDE_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_INTERNAL_BIAS_MULTIPLIER(dev) (0x001c982c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_INTERNAL_BIAS_MULTIPLIER__SIZE_1 1 /* */
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#define NV_PNVENC_INTERNAL_BIAS_MULTIPLIER_I4X4 7:0 /* RWIUF */
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#define NV_PNVENC_INTERNAL_BIAS_MULTIPLIER_I4X4_DEFAULT 0x18 /* RWI-V */
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#define NV_PNVENC_INTERNAL_BIAS_MULTIPLIER_MOST_PROBABLE 14:10 /* RWIUF */
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#define NV_PNVENC_INTERNAL_BIAS_MULTIPLIER_MOST_PROBABLE_DEFAULT 0x04 /* RWI-V */
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#define NV_PNVENC_QPP_CTRL(dev) (0x001c9830+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_QPP_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_QPP_CTRL_QPP_MODE 1:0 /* RWIUF */
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#define NV_PNVENC_QPP_CTRL_QPP_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_QPP_CTRL_QPP_MODE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_QPP_CTRL_QPP_MODE_QPP_8X8 0x1 /* RW--V */
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#define NV_PNVENC_QPP_CTRL_QPP_MODE_QPP_16X16 0x2 /* RW--V */
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#define NV_PNVENC_QPP_CTRL_LUMA_8X8_COST 7:4 /* RWIUF */
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#define NV_PNVENC_QPP_CTRL_LUMA_8X8_COST_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_QPP_CTRL_CHROMA_8X8_COST 11:8 /* RWIUF */
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#define NV_PNVENC_QPP_CTRL_CHROMA_8X8_COST_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_QPP_CTRL_LUMA_16X16_COST 15:12 /* RWIUF */
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#define NV_PNVENC_QPP_CTRL_LUMA_16X16_COST_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_QPP_CTRL_RUN_VECTOR 31:16 /* RWIUF */
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#define NV_PNVENC_QPP_CTRL_RUN_VECTOR_DEFAULT 0x056b /* RWI-V */
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#define NV_PNVENC_QPP_8X8_VECTOR0(dev) (0x001c9834+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_QPP_8X8_VECTOR0__SIZE_1 1 /* */
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#define NV_PNVENC_QPP_8X8_VECTOR0_RUN_VECTOR_HIGH16 31:16 /* RWIUF */
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#define NV_PNVENC_QPP_8X8_VECTOR0_RUN_VECTOR_HIGH16_DEFAULT 0xffaa /* RWI-V */
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#define NV_PNVENC_QPP_8X8_VECTOR0_RUN_VECTOR_LOW16 15:0 /* RWIUF */
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#define NV_PNVENC_QPP_8X8_VECTOR0_RUN_VECTOR_LOW16_DEFAULT 0xaaff /* RWI-V */
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#define NV_PNVENC_QPP_8X8_VECTOR1(dev) (0x001c9838+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_QPP_8X8_VECTOR1__SIZE_1 1 /* */
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#define NV_PNVENC_QPP_8X8_VECTOR1_RUN_VECTOR 15:0 /* RWIUF */
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#define NV_PNVENC_QPP_8X8_VECTOR1_RUN_VECTOR_DEFAULT 0x000f /* RWI-V */
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#define NV_PNVENC_IPCM_CTRL(dev) (0x001c983c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_IPCM_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_IPCM_CTRL_IPCM_REWIND 0:0 /* RWIUF */
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#define NV_PNVENC_IPCM_CTRL_IPCM_REWIND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_IPCM_CTRL_IPCM_REWIND_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_IPCM_CTRL_IPCM_REWIND_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_IPCM_CTRL_IPCM_ZERO_COEF_MAP 15:8 /* RWIUF */
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#define NV_PNVENC_IPCM_CTRL_IPCM_ZERO_COEF_MAP_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL(dev) (0x001c9840+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_SLICE_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_SLICE_CTRL_MODE 0:0 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL_MODE_MBLK 0x0 /* RW--V */
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#define NV_PNVENC_SLICE_CTRL_MODE_BYTE 0x1 /* RW--V */
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#define NV_PNVENC_SLICE_CTRL_SLICE_HEADER 1:1 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_SLICE_HEADER_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_SLICE_CTRL_SLICE_HEADER_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL_ENABLE_P_SKIP 2:2 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_ENABLE_P_SKIP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL_ENABLE_P_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_SLICE_CTRL_ENABLE_B_SKIP 3:3 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_ENABLE_B_SKIP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL_ENABLE_B_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_SLICE_CTRL_MODE_COUNT 28:4 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_MODE_COUNT_DEFAULT 0x0000000 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL_E4BYTE_STARTCODE 29:29 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_E4BYTE_STARTCODE_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL_E4BYTE_STARTCODE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_SLICE_CTRL_H265_DEPENDENT_SLICE_FLAG 30:30 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_H265_DEPENDENT_SLICE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_SLICE_CTRL_H264_SKIPREWIND_CYA 31:31 /* RWIUF */
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#define NV_PNVENC_SLICE_CTRL_H264_SKIPREWIND_CYA_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_SLICE_STAT(dev) (0x001c9844+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_SLICE_STAT__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_SLICE_STAT_SLICE_HEADER_BIT_LENGTH 15:0 /* R-IUF */
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#define NV_PNVENC_MPEC_SLICE_STAT_SLICE_HEADER_BIT_LENGTH_INIT 0x0000 /* R-I-V */
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#define NV_PNVENC_MPEC_MB_CNT(dev) (0x001c9848+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_MB_CNT__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_MB_CNT_MB_CNT 31:0 /* R-IUF */
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#define NV_PNVENC_MPEC_MB_CNT_MB_CNT_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_MPEC_MB_CNT_CTB_CNT 31:0 /* R--UF */
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#define NV_PNVENC_MPEC_MB_CNT_CTB_CNT_DEFAULT 0x00000000 /* R---V */
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#define NV_PNVENC_MPEC_WRDMA_BASE(dev) (0x001c984c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WRDMA_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MPEC_WRDMA_BASE_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEC_WRDMA_BASEL(dev) (0x001c9850+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WRDMA_BASEL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA_BASEL_BYTE_ADDR 7:0 /* RWIUF */
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#define NV_PNVENC_MPEC_WRDMA_BASEL_BYTE_ADDR_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_WRDMA_SIZE(dev) (0x001c9854+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WRDMA_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA_SIZE_SIZE 31:7 /* RWIUF */
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#define NV_PNVENC_MPEC_WRDMA_SIZE_SIZE_INIT 0x0000000 /* RWI-V */
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#define NV_PNVENC_MPEC_WRDMA_OFFSET(dev) (0x001c9858+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_WRDMA_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA_OFFSET_OFFSET 31:7 /* R-IUF */
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#define NV_PNVENC_MPEC_WRDMA_OFFSET_OFFSET_INIT 0x0000000 /* R-I-V */
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#define NV_PNVENC_MPEC_WRDMA_CTRL(dev) (0x001c985c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WRDMA_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA_CTRL_FLUSH 0:0 /* RWIUF */
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#define NV_PNVENC_MPEC_WRDMA_CTRL_FLUSH_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_ACTIVE(dev) (0x001c9860+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_ACTIVE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_ACTIVE_STATUS 0:0 /* RWIUF */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_ACTIVE_STATUS_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_ACTIVE_STATUS_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_BASE(dev) (0x001c9864+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MPEC_COLOC_WRDMA_BASE_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEB_INTR(dev) (0x001c9868+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_INTR__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_INTEN(dev) (0x001c986c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_INTEN__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_INTR(dev) (0x001c9870+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_INTR__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_INTR_WRDMA 0:0 /* RWIUF */
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#define NV_PNVENC_MPEC_INTR_WRDMA_ACTIVE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTR_WRDMA_DEACTIVE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTR_SLICE_DONE 1:1 /* RWIUF */
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#define NV_PNVENC_MPEC_INTR_SLICE_DONE_ACTIVE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTR_SLICE_DONE_DEACTIVE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTR_STAT_MB_THRESHOLD 3:3 /* RWIUF */
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#define NV_PNVENC_MPEC_INTR_STAT_MB_THRESHOLD_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTR_STAT_MB_THRESHOLD_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTR_WRDMA1 4:4 /* RWIUF */
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#define NV_PNVENC_MPEC_INTR_WRDMA1_ACTIVE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTR_WRDMA1_DEACTIVE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTR_STAT 5:5 /* RWIUF */
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#define NV_PNVENC_MPEC_INTR_STAT_ACTIVE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTR_STAT_DEACTIVE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTR_MPEB_COEFF 6:6 /* RWIUF */
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#define NV_PNVENC_MPEC_INTR_MPEB_COEFF_OVRFLOW 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTR_MPEB_COEFF_NORMAL 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTR_FBACK_FLUSH_DONE 7:7 /* RWIUF */
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#define NV_PNVENC_MPEC_INTR_FBACK_FLUSH_DONE_ACTIVE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTR_FBACK_FLUSH_DONE_DEACTIVE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTEN(dev) (0x001c9874+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_INTEN__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_INTEN_WRDMA 0:0 /* RWIUF */
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#define NV_PNVENC_MPEC_INTEN_WRDMA_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTEN_WRDMA_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTEN_SLICE_DONE 1:1 /* RWIUF */
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#define NV_PNVENC_MPEC_INTEN_SLICE_DONE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTEN_SLICE_DONE_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTEN_STAT_MB_THRESHOLD 3:3 /* RWIUF */
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#define NV_PNVENC_MPEC_INTEN_STAT_MB_THRESHOLD_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTEN_STAT_MB_THRESHOLD_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTEN_WRDMA1 4:4 /* RWIUF */
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#define NV_PNVENC_MPEC_INTEN_WRDMA1_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTEN_WRDMA1_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTEN_STAT 5:5 /* RWIUF */
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#define NV_PNVENC_MPEC_INTEN_STAT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTEN_STAT_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTEN_MPEB_COEFF 6:6 /* RWIUF */
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#define NV_PNVENC_MPEC_INTEN_MPEB_COEFF_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTEN_MPEB_COEFF_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_INTEN_FBACK_FLUSH_DONE 7:7 /* RWIUF */
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#define NV_PNVENC_MPEC_INTEN_FBACK_FLUSH_DONE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_INTEN_FBACK_FLUSH_DONE_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_MPEB_LUMA_BASE(dev) (0x001c9878+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_LUMA_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_LUMA_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MPEB_LUMA_BASE_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEB_CHROMA_BASE(dev) (0x001c9880+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_CHROMA_BASE__SIZE_1 1 /* */
|
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#define NV_PNVENC_MPEB_CHROMA_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MPEB_CHROMA_BASE_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0(dev) (0x001c9884+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0__SIZE_1 1 /* */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_0 0:0 /* RWIUF */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_0 4:1 /* RWIUF */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_1 8:8 /* RWIUF */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_1 12:9 /* RWIUF */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_2 16:16 /* RWIUF */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_2 20:17 /* RWIUF */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_2_DEFAULT 0x0 /* RWI-V */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_3 24:24 /* RWIUF */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_BOTFIELD_3_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_3 28:25 /* RWIUF */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_0_REFIDX_3_DEFAULT 0x0 /* RWI-V */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_1(dev) (0x001c9888+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1__SIZE_1 1 /* */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_4 0:0 /* RWIUF */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_4_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_4 4:1 /* RWIUF */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_4_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_5 8:8 /* RWIUF */
|
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#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_5_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_5 12:9 /* RWIUF */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_5_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_6 16:16 /* RWIUF */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_6_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_6 20:17 /* RWIUF */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_6_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_7 24:24 /* RWIUF */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_BOTFIELD_7_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_7 28:25 /* RWIUF */
|
|
#define NV_PNVENC_HH_L0_REFPIC_MAP_1_REFIDX_7_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HH_L1_REFPIC_MAP_0(dev) (0x001c988c+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_HH_L1_REFPIC_MAP_0__SIZE_1 1 /* */
|
|
#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_0 0:0 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_0 4:1 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_1 8:8 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_1 12:9 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_2 16:16 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_2 20:17 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_3 24:24 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_BOTFIELD_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_3 28:25 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_0_REFIDX_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1(dev) (0x001c9890+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1__SIZE_1 1 /* */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_4 0:0 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_4 4:1 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_5 8:8 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_5 12:9 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_6 16:16 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_6 20:17 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_7 24:24 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_BOTFIELD_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_7 28:25 /* RWIUF */
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#define NV_PNVENC_HH_L1_REFPIC_MAP_1_REFIDX_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI4(dev,i) (0x001c9894+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI4__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI4__SIZE_2 8 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI4_DZ1 19:10 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI4_DZ1_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI4_DZ2 9:0 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI4_DZ2_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP4(dev,i) (0x001c98b4+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP4__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP4__SIZE_2 8 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP4_DZ1 19:10 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP4_DZ1_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP4_DZ2 9:0 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP4_DZ2_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_C4X4(dev) (0x001c98d4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_C4X4__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_C4X4_I 19:10 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_C4X4_I_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_C4X4_P 9:0 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_C4X4_P_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI8(dev,i) (0x001c98d8+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI8__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI8__SIZE_2 8 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI8_DZ1 19:10 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI8_DZ1_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI8_DZ2 9:0 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YI8_DZ2_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP8(dev,i) (0x001c98f8+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP8__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP8__SIZE_2 8 /* */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP8_DZ1 19:10 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP8_DZ1_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP8_DZ2 9:0 /* RWIUF */
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#define NV_PNVENC_MPEB_QUANT_DEADZONE_YP8_DZ2_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_STAT_CTRL(dev) (0x001c991c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_STAT_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_CTRL_MB_THRESHOLD 31:0 /* RWIUF */
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#define NV_PNVENC_STAT_CTRL_MB_THRESHOLD_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_STAT_CTRL_CTB_THRESHOLD 31:0 /* RW-UF */
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#define NV_PNVENC_STAT_CTRL_CTB_THRESHOLD_DEFAULT 0x00000000 /* R---V */
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#define NV_PNVENC_STAT_INTRA_RESIDUAL_BITS(dev) (0x001c9920+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTRA_RESIDUAL_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTRA_RESIDUAL_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTER_RESIDUAL_BITS(dev) (0x001c9924+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTER_RESIDUAL_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTER_RESIDUAL_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTRA_MODE_BITS(dev) (0x001c9928+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTRA_MODE_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTRA_MODE_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTER_MODE_BITS(dev) (0x001c992c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTER_MODE_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTER_MODE_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_IPCM_BITS(dev) (0x001c9930+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_IPCM_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_IPCM_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_TOTAL_BITS(dev) (0x001c9934+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_TOTAL_CABAC_BINS(dev) (0x001c9938+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_CABAC_BINS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_CABAC_BINS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_CUM_INTRA_COST(dev) (0x001c993c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_CUM_INTRA_COST__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_CUM_INTRA_COST_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_CUM_INTER_COST(dev) (0x001c9940+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_CUM_INTER_COST__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_CUM_INTER_COST_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_CUM_IPCM_COST(dev) (0x001c9944+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_CUM_IPCM_COST__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_CUM_IPCM_COST_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_CUM_SKIP_COST(dev) (0x001c9948+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_CUM_SKIP_COST__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_CUM_SKIP_COST_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTRA_MB_NUM(dev) (0x001c994c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTRA_MB_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTRA_MB_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTER_MB_NUM(dev) (0x001c9950+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTER_MB_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTER_MB_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_SKIP_MB_NUM(dev) (0x001c9954+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_SKIP_MB_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_SKIP_MB_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_IPCM_MB_NUM(dev) (0x001c9958+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_IPCM_MB_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_IPCM_MB_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_TYPE1_BIT_COUNT(dev) (0x001c995c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TYPE1_BIT_COUNT__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TYPE1_BIT_COUNT_CNT 31:0 /* R--UF */
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#define NV_PNVENC_DBF_DMA_CTRL(dev) (0x001c9960+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_DBF_DMA_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_DBF_DMA_CTRL_START 0:0 /* -W-VF */
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#define NV_PNVENC_MPEB_PIPE_STATUS(dev) (0x001c9964+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEB_PIPE_STATUS__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_PIPE_STATUS_IPRED_IDLE 0:0 /* R-IUF */
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#define NV_PNVENC_MPEB_PIPE_STATUS_IPRED_IDLE_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_MPEB_PIPE_STATUS_IPRED_IDLE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_MPEB_PIPE_STATUS_QBUF_IDLE 1:1 /* R-IUF */
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#define NV_PNVENC_MPEB_PIPE_STATUS_QBUF_IDLE_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_MPEB_PIPE_STATUS_QBUF_IDLE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_MPEB_PIPE_STATUS_DBFBUF_IDLE 2:2 /* R-IUF */
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#define NV_PNVENC_MPEB_PIPE_STATUS_DBFBUF_IDLE_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_MPEB_PIPE_STATUS_DBFBUF_IDLE_FALSE 0x0 /* R---V */
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#define NV_PNVENC_MPEB_PIPE_STATUS_DBFDMA_READY 3:3 /* R-IUF */
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#define NV_PNVENC_MPEB_PIPE_STATUS_DBFDMA_READY_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_MPEB_PIPE_STATUS_DBFDMA_READY_FALSE 0x0 /* R---V */
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#define NV_PNVENC_MPEB_DEBUG1(dev) (0x001c996c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEB_DEBUG1__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_PARAM_BUF0_STATE 1:0 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_PARAM_BUF1_STATE 3:2 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_LUMA_BUF0_STATE 5:4 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_LUMA_BUF1_STATE 7:6 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_LUMA_BUF2_STATE 9:8 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_LUMA_BUF3_STATE 11:10 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_CHRO_BUF0_STATE 13:12 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_CHRO_BUF1_STATE 15:14 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG1_RECBUF_CHRO_BUF2_STATE 17:16 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG2(dev) (0x001c9970+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEB_DEBUG2__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_DEBUG2_IPRED_STATE 4:0 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG2_AUX_STATE 10:5 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG2_CBUF_RDY 11:11 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG2_QBUF_RDY 12:12 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG2_NBBUF_RDY 13:13 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG2_PBUF_RDY 14:14 /* R-XUF */
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#define NV_PNVENC_MPEB_DEBUG2_DBF_RDY 15:15 /* R-XUF */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL(dev) (0x001c9974+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL_FLAG 0:0 /* RWIVF */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL_FLAG_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL_FLAG_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL_FLAG_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL_LIMIT 16:1 /* RWIVF */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL_LIMIT_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_INTRA_SAT_CTRL_LIMIT_13BITS 0x080f /* RW--V */
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#define NV_PNVENC_MPEC_CMD_CONFIG(dev) (0x001c9978+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_CMD_CONFIG__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_CMD_CONFIG_REF_PIC_REORDER_L0_CMDCOUNT 3:0 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_REF_PIC_REORDER_L0_CMDCOUNT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_REF_PIC_REORDER_L1_CMDCOUNT 7:4 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_REF_PIC_REORDER_L1_CMDCOUNT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_MMCO_CMDCOUNT 11:8 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_MMCO_CMDCOUNT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_NO_OUTPUT_OF_PRIOR_PIC_FLAG 12:12 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_NO_OUTPUT_OF_PRIOR_PIC_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_LONG_TERM_REFERENCE_FLAG 13:13 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_LONG_TERM_REFERENCE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_PIC_OUTPUT_FLAG 14:14 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_PIC_OUTPUT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_SHORT_TERM_REF_PIC_SET_SPS_FLAG 15:15 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_SHORT_TERM_REF_PIC_SET_SPS_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_REF_PIC_LIST_MODIFICATION_FLAG_L0 16:16 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_REF_PIC_LIST_MODIFICATION_FLAG_L0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_REF_PIC_LIST_MODIFICATION_FLAG_L1 17:17 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_REF_PIC_LIST_MODIFICATION_FLAG_L1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_NUM_POC_TOTAL_CURR 22:18 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_NUM_POC_TOTAL_CURR_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_LONG_TERM_REF_PICS_PRESENT_FLAG 23:23 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_LONG_TERM_REF_PICS_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_LISTS_MODIFICATION_PRESENT_FLAG 24:24 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_LISTS_MODIFICATION_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_SHORT_TERM_REF_PIC_SET_IDX 30:25 /* RWIUF */
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#define NV_PNVENC_MPEC_CMD_CONFIG_H265_SHORT_TERM_REF_PIC_SET_IDX_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0_(dev,i) (0x001c997c+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0___SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0___SIZE_2 8 /* */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__PIC_NUM_IDC 2:0 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__PIC_NUM_IDC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__ABS_DIFF_PIC_NUM_MINUS1 19:3 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__ABS_DIFF_PIC_NUM_MINUS1_DEFAULT 0x00000 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__LONG_TERM_PIC_NUM 23:20 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__LONG_TERM_PIC_NUM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__ABS_DIFF_VIEW_IDX_MINUS1 27:24 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L0__ABS_DIFF_VIEW_IDX_MINUS1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1_(dev,i) (0x001c99a0+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1___SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1___SIZE_2 8 /* */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__PIC_NUM_IDC 2:0 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__PIC_NUM_IDC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__ABS_DIFF_PIC_NUM_MINUS1 19:3 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__ABS_DIFF_PIC_NUM_MINUS1_DEFAULT 0x00000 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__LONG_TERM_PIC_NUM 23:20 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__LONG_TERM_PIC_NUM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__ABS_DIFF_VIEW_IDX_MINUS1 27:24 /* RWIUF */
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#define NV_PNVENC_MPEC_REF_PIC_REORDER_L1__ABS_DIFF_VIEW_IDX_MINUS1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST_(dev,i) (0x001c99c4+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST___SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST___SIZE_2 8 /* */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__OPCODE 2:0 /* RWIUF */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__OPCODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__DIFF_PIC_NUMS_MINUS1 19:3 /* RWIUF */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__DIFF_PIC_NUMS_MINUS1_DEFAULT 0x00000 /* RWI-V */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__LT_PIC_NUM 22:20 /* RWIUF */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__LT_PIC_NUM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__LT_FRM_IDX 25:23 /* RWIUF */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__LT_FRM_IDX_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__MAX_LT_FRM_IDX_PLUS1 29:26 /* RWIUF */
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#define NV_PNVENC_MPEC_MMCO_CMD_LIST__MAX_LT_FRM_IDX_PLUS1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER(dev) (0x001c99e4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_STEREO_MVC_ENABLE 0:0 /* RWIUF */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_STEREO_MVC_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_STEREO_MVC_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_STEREO_MVC_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_BASE_VIEW 1:1 /* RWIUF */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_BASE_VIEW_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_BASE_VIEW_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_BASE_VIEW_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_PRIORITY_ID 7:2 /* RWIUF */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_PRIORITY_ID_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_VIEW_ID 17:8 /* RWIUF */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_VIEW_ID_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_TEMPORAL_ID 20:18 /* RWIUF */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_TEMPORAL_ID_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_ANCHOR_PIC_FLAG 21:21 /* RWIUF */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_ANCHOR_PIC_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_ANCHOR_PIC_FLAG_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_ANCHOR_PIC_FLAG_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_INTER_VIEW_FLAG 22:22 /* RWIUF */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_INTER_VIEW_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_INTER_VIEW_FLAG_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MPEC_MVC_NAL_HEADER_INTER_VIEW_FLAG_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MPEC_DEBUG_IF(dev) (0x001c99e8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_DEBUG_IF__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_DEBUG_IF_FBIFDMWR_IDLE 0:0 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_BITPKR_PKBUSY 1:1 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_BITPKR_STATE 5:2 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_QUANT_ALL_VLD 6:6 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_START_PARAM_BEAT 7:7 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_HIST2MPEC_BEAT 8:8 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_COLOC_FBIF_BLKED 9:9 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_COLOC_IDLE 10:10 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_COLOC_WRFBIF_IDLE 11:11 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_FBIF_WR_RDY 12:12 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_COLOC_FBIF_WR_RDY 13:13 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_B2C_PARAM_PVLD 14:14 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_B2C_PARAM_PRDY 15:15 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_B2C_QUANT_PVLD 16:16 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_B2C_QUANT_PRDY 17:17 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_C2B_PARAM_PVLD 18:18 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_C2B_PARAM_PRDY 19:19 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_H264_MB_TYPE 21:20 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_IF_H264_SM_STATE 26:22 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT(dev) (0x001c99ec+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_DEBUG_STAT__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_DEBUG_STAT_DMABUF_FULL 0:0 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT_PKT_SIZE_EXCEED 1:1 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT_IPCM_SIZE_EXCEED 2:2 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT_FIRSTMBINSLICE 3:3 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT_REWIND_NEW_PKT 4:4 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT_BITS_TO_POP 20:5 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT_STATE 24:21 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_STAT_PRED_STATE 28:25 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_H264(dev) (0x001c99f0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_DEBUG_H264__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_DEBUG_H264_CAVLC_SM 3:0 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_H264_CAVLC_MBHDR_ST 8:4 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_H264_CAVLC_MBDAT_ST 11:9 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_H264_CABAC_SM 16:12 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_H264_CABAC_MBHDR_ST 22:17 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_H264_CABAC_MBDAT_ST 27:23 /* R-XUF */
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#define NV_PNVENC_MPEC_DEBUG_H264_CABAC_PSTATE_SM 31:28 /* R-XUF */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL(dev) (0x001c99f4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL_FLAG 0:0 /* RWIVF */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL_FLAG_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL_FLAG_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL_FLAG_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL_LIMIT 16:1 /* RWIVF */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL_LIMIT_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_QUANT_INTER_SAT_CTRL_LIMIT_13BITS 0x080f /* RW--V */
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#define NV_PNVENC_VP8_FRAME_SIZE(dev) (0x001c99f8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_FRAME_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_FRAME_SIZE_WIDTH 13:0 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_SIZE_WIDTH_DEFUALT 0x0000 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_SIZE_HORIZ_SCALE 15:14 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_SIZE_HORIZ_SCALE_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_SIZE_HEIGHT 29:16 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_SIZE_HEIGHT_DEFUALT 0x0000 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_SIZE_VERT_SCALE 31:30 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_SIZE_VERT_SCALE_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM(dev) (0x001c99fc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_FRAME_PARAM__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_FRAME_PARAM_FRAME_TYPE 0:0 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_FRAME_TYPE_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_FRAME_TYPE_KEYFRAME 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_FRAME_TYPE_INTERFRAME 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_VERSION 3:1 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_VERSION_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SHOW_FRAME 4:4 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_SHOW_FRAME_DEFUALT 0x1 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SHOW_FRAME_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SHOW_FRAME_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_CLR_TYPE 5:5 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_CLR_TYPE_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_CLAMP_TYPE 6:6 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_CLAMP_TYPE_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_EN 7:7 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_EN_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_EN_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_EN_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_MAP 8:8 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_MAP_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_MAP_NOUPDATE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_MAP_UPDATE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_DATA 9:9 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_DATA_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_DATA_NOUPDATL 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_UPD_DATA_UPDATE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_MODE 10:10 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_MODE_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_MODE_DELTA_VAL 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_MODE_ABS_VAL 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_MULTI_TOKEN_PRTN 12:11 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_MULTI_TOKEN_PRTN_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_REFRESH_PROBS 13:13 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_REFRESH_PROBS_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_REFRESH_PROBS_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_REFRESH_PROBS_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_MB_NO_COEFF_SKIP 14:14 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_MB_NO_COEFF_SKIP_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_MB_NO_COEFF_SKIP_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_MB_NO_COEFF_SKIP_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_YMODE_PROBS 15:15 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_YMODE_PROBS_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_YMODE_PROBS_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_YMODE_PROBS_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_UVMODE_PROBS 16:16 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_UVMODE_PROBS_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_UVMODE_PROBS_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_UPD_UVMODE_PROBS_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_QINDEX_UPDATE_FLAG 20:17 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_QINDEX_UPDATE_FLAG_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_LF_UPDATE_FLAG 24:21 /* RWIUF */
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#define NV_PNVENC_VP8_FRAME_PARAM_SEG_LF_UPDATE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_QINDEX(dev) (0x001c9a00+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_SEG_QINDEX__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG0_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG1_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG2_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG3 31:24 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_QINDEX_SEG3_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_FLTLVL(dev) (0x001c9a04+(dev)*16384) /* RW-4A */
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|
#define NV_PNVENC_VP8_SEG_FLTLVL__SIZE_1 1 /* */
|
|
#define NV_PNVENC_VP8_SEG_FLTLVL_SEG0 6:0 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_FLTLVL_SEG0_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_FLTLVL_SEG1 14:8 /* RWIUF */
|
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#define NV_PNVENC_VP8_SEG_FLTLVL_SEG1_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_FLTLVL_SEG2 22:16 /* RWIUF */
|
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#define NV_PNVENC_VP8_SEG_FLTLVL_SEG2_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_FLTLVL_SEG3 30:24 /* RWIUF */
|
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#define NV_PNVENC_VP8_SEG_FLTLVL_SEG3_DEFUALT 0x00 /* RWI-V */
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|
#define NV_PNVENC_VP8_LOOPFILTER(dev) (0x001c9a08+(dev)*16384) /* RW-4A */
|
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#define NV_PNVENC_VP8_LOOPFILTER__SIZE_1 1 /* */
|
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#define NV_PNVENC_VP8_LOOPFILTER_TYPE 0:0 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_TYPE_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_TYPE_NORMALE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_LOOPFILTER_TYPE_SIMPLE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_EN 1:1 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_EN_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_EN_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_EN_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_UPD 2:2 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_UPD_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_UPD_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_LOOPFILTER_DELTA_UPD_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_LOOPFILTER_LEVEL 13:8 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_LEVEL_DEFUALT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_SHARPNESS 18:16 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_SHARPNESS_DEFUALT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA(dev) (0x001c9a0c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG3 31:24 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_REF_DELTA_SEG3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA(dev) (0x001c9a10+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG3 31:24 /* RWIUF */
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#define NV_PNVENC_VP8_LOOPFILTER_MODE_DELTA_SEG3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_QUANT(dev) (0x001c9a14+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_QUANT__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_QUANT_BASE_QINDEX 6:0 /* RWIUF */
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#define NV_PNVENC_VP8_QUANT_BASE_QINDEX_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_QUANT_Y1DC_DELTA 11:7 /* RWIUF */
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#define NV_PNVENC_VP8_QUANT_Y1DC_DELTA_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_QUANT_Y2DC_DELTA 16:12 /* RWIUF */
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#define NV_PNVENC_VP8_QUANT_Y2DC_DELTA_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_QUANT_Y2AC_DELTA 21:17 /* RWIUF */
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#define NV_PNVENC_VP8_QUANT_Y2AC_DELTA_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_QUANT_UVDC_DELTA 26:22 /* RWIUF */
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#define NV_PNVENC_VP8_QUANT_UVDC_DELTA_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_QUANT_UVAC_DELTA 31:27 /* RWIUF */
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#define NV_PNVENC_VP8_QUANT_UVAC_DELTA_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME(dev) (0x001c9a18+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_REFFRAME__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_LAST 0:0 /* RWIUF */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_LAST_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_LAST_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_LAST_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_GF 1:1 /* RWIUF */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_GF_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_GF_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_GF_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_ARF 2:2 /* RWIUF */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_ARF_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_ARF_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_REFRESH_ARF_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_GF 5:4 /* RWIUF */
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#define NV_PNVENC_VP8_REFFRAME_COPY_GF_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_GF_NONE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_GF_FROM_LAST 0x1 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_GF_FROM_ARF 0x2 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_ARF 7:6 /* RWIUF */
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#define NV_PNVENC_VP8_REFFRAME_COPY_ARF_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_ARF_NONE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_ARF_FROM_LAST 0x1 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_COPY_ARF_FROM_GF 0x2 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_GF 8:8 /* RWIUF */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_GF_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_GF_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_GF_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_ARF 9:9 /* RWIUF */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_ARF_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_ARF_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_VP8_REFFRAME_SIGN_ARF_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_VP8_MPECRAM_CURR_OFFSET(dev) (0x001c9a1c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_MPECRAM_CURR_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_MPECRAM_CURR_OFFSET_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_VP8_MPECRAM_CURR_OFFSET_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_VP8_MPECRAM_ADDR(dev) (0x001c9a20+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_MPECRAM_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS3 31:24 /* RWIUF */
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#define NV_PNVENC_VP8_MPECRAM_ADDR_COEF_MV_PROBS3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_PROBS(dev) (0x001c9a24+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_SEG_PROBS__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_SEG_PROBS_PROB0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_PROBS_PROB0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_PROBS_PROB1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_PROBS_PROB1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_SEG_PROBS_PROB2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_SEG_PROBS_PROB2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_YMODE_PROBS(dev) (0x001c9a28+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_YMODE_PROBS__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB3 31:24 /* RWIUF */
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#define NV_PNVENC_VP8_YMODE_PROBS_PROB3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_UVMODE_PROBS(dev) (0x001c9a2c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_UVMODE_PROBS__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_UVMODE_PROBS_PROB0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_UVMODE_PROBS_PROB0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_UVMODE_PROBS_PROB1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_UVMODE_PROBS_PROB1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_UVMODE_PROBS_PROB2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_UVMODE_PROBS_PROB2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_UVMODE_PROBS_SKIP 31:24 /* RWIUF */
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#define NV_PNVENC_VP8_UVMODE_PROBS_SKIP_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_REF_PROBS(dev) (0x001c9a30+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_REF_PROBS__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_REF_PROBS_PROB0 7:0 /* RWIUF */
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#define NV_PNVENC_VP8_REF_PROBS_PROB0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_REF_PROBS_PROB1 15:8 /* RWIUF */
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#define NV_PNVENC_VP8_REF_PROBS_PROB1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_REF_PROBS_PROB2 23:16 /* RWIUF */
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#define NV_PNVENC_VP8_REF_PROBS_PROB2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_Y(dev) (0x001c9a34+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_Y__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_Y_DATA 31:0 /* RWIUF */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_Y_DATA_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_X(dev) (0x001c9a38+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_X__SIZE_1 1 /* */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_X_DATA 31:0 /* RWIUF */
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#define NV_PNVENC_VP8_MV_PROBS_UPD_X_DATA_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEC_WRDMA1_BASE(dev) (0x001c9a3c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WRDMA1_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA1_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MPEC_WRDMA1_BASE_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEC_WRDMA1_BASEL(dev) (0x001c9a40+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WRDMA1_BASEL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA1_BASEL_BYTE_ADDR 7:0 /* RWIUF */
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#define NV_PNVENC_MPEC_WRDMA1_BASEL_BYTE_ADDR_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_WRDMA1_SIZE(dev) (0x001c9a44+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WRDMA1_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA1_SIZE_SIZE 31:7 /* RWIUF */
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#define NV_PNVENC_MPEC_WRDMA1_SIZE_SIZE_INIT 0x0000000 /* RWI-V */
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#define NV_PNVENC_MPEC_WRDMA1_OFFSET(dev) (0x001c9a48+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_WRDMA1_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA1_OFFSET_OFFSET 31:7 /* R-IUF */
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#define NV_PNVENC_MPEC_WRDMA1_OFFSET_OFFSET_INIT 0x0000000 /* R-I-V */
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#define NV_PNVENC_MPEC_STATE_BASE(dev) (0x001c9a4c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_STATE_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_STATE_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MPEC_STATE_BASE_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEC_STATE_BASEL(dev) (0x001c9a50+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_STATE_BASEL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_STATE_BASEL_BYTE_ADDR 7:0 /* RWIUF */
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#define NV_PNVENC_MPEC_STATE_BASEL_BYTE_ADDR_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_STATE_SIZE(dev) (0x001c9a54+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_STATE_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_STATE_SIZE_SIZE 31:7 /* RWIUF */
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#define NV_PNVENC_MPEC_STATE_SIZE_SIZE_INIT 0x0000000 /* RWI-V */
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#define NV_PNVENC_MPEC_STATE_OFFSET(dev) (0x001c9a58+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_STATE_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_STATE_OFFSET_OFFSET 31:7 /* R-IUF */
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#define NV_PNVENC_MPEC_STATE_OFFSET_OFFSET_INIT 0x0000000 /* R-I-V */
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#define NV_PNVENC_MPEC_WRDMA_ACK_OFFSET(dev) (0x001c9a5c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_WRDMA_ACK_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WRDMA_ACK_OFFSET_OFFSET 23:0 /* R-IUF */
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#define NV_PNVENC_MPEC_WRDMA_ACK_OFFSET_OFFSET_INIT 0x000000 /* R-I-V */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y1(dev,i) (0x001c9a60+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y1__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y1__SIZE_2 4 /* */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y1_DC 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y1_DC_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y1_AC 31:16 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y1_AC_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y2(dev,i) (0x001c9a70+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y2__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y2__SIZE_2 4 /* */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y2_DC 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y2_DC_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y2_AC 31:16 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_QUANT_Y2_AC_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_QUANT_UV(dev,i) (0x001c9a80+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_QUANT_UV__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_QUANT_UV__SIZE_2 4 /* */
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#define NV_PNVENC_MPEB_VP8_QUANT_UV_DC 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_QUANT_UV_DC_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_QUANT_UV_AC 31:16 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_QUANT_UV_AC_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC(dev,i) (0x001c9a90+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC__SIZE_2 4 /* */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC_Y1 8:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC_Y1_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC_Y2 17:9 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC_Y2_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC_UV 26:18 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_IQUANT_DC_UV_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC(dev,i) (0x001c9aa0+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC__SIZE_2 4 /* */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC_Y1 8:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC_Y1_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC_Y2 17:9 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC_Y2_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC_UV 26:18 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_IQUANT_AC_UV_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_LAMBDA(dev,i) (0x001c9ab0+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_LAMBDA__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_LAMBDA__SIZE_2 2 /* */
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#define NV_PNVENC_MPEB_VP8_LAMBDA_SEGA 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_LAMBDA_SEGA_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_LAMBDA_SEGB 31:16 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_LAMBDA_SEGB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_FLTLVL(dev) (0x001c9ab8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_FLTLVL__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG0 5:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG1 13:8 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG2 21:16 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG3 29:24 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_FLTLVL_SEG3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_ADDR(dev) (0x001c9abc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_ADDR_IDX2 2:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_ADDR_IDX2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_ADDR_IDX1 22:16 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_ADDR_IDX1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_DATA(dev) (0x001c9ac0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_DATA__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_DATA_LO 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_DATA_LO_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_DATA_HI 31:16 /* RWIUF */
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#define NV_PNVENC_MPEB_VP8_COSTRAM_DATA_HI_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEC_H264_STAT_SLICE_BITS(dev) (0x001c9ac4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_H264_STAT_SLICE_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_H264_STAT_SLICE_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_MPEC_H264_STAT_SLICE_BITS_H265_CNT 31:0 /* R--UF */
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#define NV_PNVENC_MPEB_CHROMA_V_BASE(dev) (0x001c9ac8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_CHROMA_V_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_CHROMA_V_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MPEB_CHROMA_V_BASE_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEB_STAT_TOTAL_INTRA_COST(dev) (0x001c9acc+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEB_STAT_TOTAL_INTRA_COST__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_STAT_TOTAL_INTRA_COST_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_MPEB_STAT_TOTAL_INTRA_COST_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS(dev) (0x001c9ad0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_SEQ_PARAMETERS__SIZE_1 1 /* */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_CHROMA_FORMAT_IDC 1:0 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_CHROMA_FORMAT_IDC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SEPARATE_COLOUR_PLANE_FLAG 2:2 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SEPARATE_COLOUR_PLANE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_PCM_ENABLED_FLAG 3:3 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_PCM_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 7:4 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MIN_CU_SIZE_MINUS3 10:9 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MIN_CU_SIZE_MINUS3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_DIFF_MAX_MIN_CU_SIZE 12:11 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_DIFF_MAX_MIN_CU_SIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MIN_TRAFO_SIZE_MINUS2 14:13 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MIN_TRAFO_SIZE_MINUS2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_DIFF_MAX_MIN_TRAFO_SIZE 16:15 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_DIFF_MAX_MIN_TRAFO_SIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MIN_PCM_CU_SIZE_MINUS3 18:17 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_MIN_PCM_CU_SIZE_MINUS3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_DIFF_MAX_MIN_PCM_CU_SIZE 20:19 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_LOG2_DIFF_MAX_MIN_PCM_CU_SIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_MAX_XFORM_HIERARCHY_DEPTH_INTER 23:21 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_MAX_XFORM_HIERARCHY_DEPTH_INTER_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_MAX_XFORM_HIERARCHY_DEPTH_INTRA 26:24 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_MAX_XFORM_HIERARCHY_DEPTH_INTRA_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SAO_ENABLED_FLAG 27:27 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SAO_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SPS_TEMPORAL_MVP_ENABLED_FLAG 28:28 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SPS_TEMPORAL_MVP_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SPS_STRONG_INTRA_SMOOTHING_ENABLE_FLAG 29:29 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_SPS_STRONG_INTRA_SMOOTHING_ENABLE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_PCM_LOOP_FILTER_DISABLED_FLAG 30:30 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_PCM_LOOP_FILTER_DISABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_PCM_LOOP_FILTER_DISABLED_FLAG_NO 0x0 /* RW--V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_PCM_LOOP_FILTER_DISABLED_FLAG_YES 0x1 /* RW--V */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_AMP_ENABLED_FLAG 31:31 /* RWIUF */
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#define NV_PNVENC_H265_SEQ_PARAMETERS_AMP_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS(dev) (0x001c9ad4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_PIC_PARAMETERS__SIZE_1 1 /* */
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#define NV_PNVENC_H265_PIC_PARAMETERS_SIGN_DATA_HIDING_FLAG 0:0 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_SIGN_DATA_HIDING_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_CABAC_INIT_PRESENT_FLAG 1:1 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_CABAC_INIT_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_PIC_INIT_QP_MINUS26 7:2 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_PIC_INIT_QP_MINUS26_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_TRANSFORM_SKIP_ENABLED_FLAG 8:8 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_TRANSFORM_SKIP_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_CU_QP_DELTA_ENALBED_FLAG 9:9 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_CU_QP_DELTA_ENALBED_FLAG_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DIFF_CU_QP_DELTA_DEPTH 11:10 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DIFF_CU_QP_DELTA_DEPTH_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_SLICE_LEVEL_CHROMA_QP_OFFSETS_PRESENT_FLAG 12:12 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_SLICE_LEVEL_CHROMA_QP_OFFSETS_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_OUTPUT_FLAG_PRESENT_FLAG 15:15 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_OUTPUT_FLAG_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_TRANSQUANT_BYPASS_ENABLED_FLAG 16:16 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_TRANSQUANT_BYPASS_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEPENDENT_SLICE_ENABLED_FLAG 17:17 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEPENDENT_SLICE_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_TILES_ENABLED_FLAG 18:18 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_TILES_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_ENTROPY_CODING_SYNC_ENABLED_FLAG 19:19 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_ENTROPY_CODING_SYNC_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG 20:20 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG 21:21 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG 22:22 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_PPS_DISABLE_DEBLOCKING_FILTER_FLAG 23:23 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_PPS_DISABLE_DEBLOCKING_FILTER_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG 24:24 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_LOG2_PARALLEL_MERGE_LEVEL_MINUS2 27:25 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_LOG2_PARALLEL_MERGE_LEVEL_MINUS2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_PIC_PARAMETERS_NUM_EXTRA_SLICE_HEADER_BITS 30:28 /* RWIUF */
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#define NV_PNVENC_H265_PIC_PARAMETERS_NUM_EXTRA_SLICE_HEADER_BITS_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL(dev) (0x001c9ad8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_FRAME_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_SAO_LUMA_FLAG 0:0 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_SAO_LUMA_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_SAO_CHROMA_FLAG 1:1 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_SAO_CHROMA_FLAG_DETAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_TEMPORAL_MVP_ENABLE_FLAG 2:2 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_TEMPORAL_MVP_ENABLE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_MVD_L1_ZERO_FLAG 3:3 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_MVD_L1_ZERO_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_COLLOCATED_FROM_L0_FLAG 4:4 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_COLLOCATED_FROM_L0_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_COLLOCATED_REF_IDX 7:5 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_COLLOCATED_REF_IDX_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_FIVE_MINUS_MAX_NUM_MERGE_CAND 10:8 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_FIVE_MINUS_MAX_NUM_MERGE_CAND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_CB_QP_OFFSET 15:11 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_CB_QP_OFFSET_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_CR_QP_OFFSET 20:16 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_CR_QP_OFFSET_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG 21:21 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_NO 0x0 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG_YES 0x1 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_FLAG 22:22 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_FLAG_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_DEBLOCKING_FILTER_OVERRIDE_FLAG_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_DEBLOCKING_FILTER_DISABLED_FLAG 23:23 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_YES 0x0 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_DEBLOCKING_FILTER_DISABLED_FLAG_NO 0x1 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_PPS_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG 24:24 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_PPS_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_PPS_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG_NO 0x0 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_PPS_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG_YES 0x1 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG 25:25 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG_NO 0x0 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_SLICE_LOOP_FILTER_ACROSS_SLICE_ENABLED_FLAG_YES 0x1 /* RW--V */
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#define NV_PNVENC_H265_FRAME_CTRL_CEIL_LOG2_PIC_SIZE_IN_CTBS 31:26 /* RWIUF */
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#define NV_PNVENC_H265_FRAME_CTRL_CEIL_LOG2_PIC_SIZE_IN_CTBS_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0(dev) (0x001c9adc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0__SIZE_1 1 /* */
|
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_0 2:0 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_1 5:3 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_2 8:6 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_3 11:9 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_4 14:12 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_5 17:15 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_6 20:18 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_7 23:21 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L0_LIST_ENTRY_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1(dev) (0x001c9ae0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1__SIZE_1 1 /* */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_0 2:0 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_1 5:3 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_2 8:6 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_3 11:9 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_4 14:12 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_5 17:15 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_6 20:18 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_7 23:21 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_LIST_MODIFICATION_L1_LIST_ENTRY_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET(dev) (0x001c9ae4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET__SIZE_1 1 /* */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_NUM 6:0 /* RWIUF */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_NUM_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_INTER_PREDICTION_FLAG 7:7 /* RWIUF */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_INTER_PREDICTION_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_DELTA_IDX_MINUS1 13:8 /* RWIUF */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_DELTA_IDX_MINUS1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_DELTA_RPS_SIGN 14:14 /* RWIUF */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_DELTA_RPS_SIGN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_ABS_DELTA_RPS_MINUS1 30:15 /* RWIUF */
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#define NV_PNVENC_H265_SHORT_TERM_REF_PIC_SET_ABS_DELTA_RPS_MINUS1_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_ENTRY_POINT(dev) (0x001c9ae8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_ENTRY_POINT__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_INTRA_COST(dev) (0x001c9af0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_INTRA_COST__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_INTRA_COST_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_STAT_TOTAL_INTRA_COST_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_STAT_TOTAL_INTER_COST(dev) (0x001c9af4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_INTER_COST__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_INTER_COST_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_STAT_TOTAL_INTER_COST_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_STAT_INTRA_CU32X32_NUM(dev) (0x001c9af8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTRA_CU32X32_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTRA_CU32X32_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTER_CU32X32_NUM(dev) (0x001c9afc+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTER_CU32X32_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTER_CU32X32_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_SKIP_CU32X32_NUM(dev) (0x001c9b00+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_SKIP_CU32X32_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_SKIP_CU32X32_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_IPCM_CU32X32_NUM(dev) (0x001c9b04+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_IPCM_CU32X32_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_IPCM_CU32X32_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTRA_CU16X16_NUM(dev) (0x001c9b08+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTRA_CU16X16_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTRA_CU16X16_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTER_CU16X16_NUM(dev) (0x001c9b0c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTER_CU16X16_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTER_CU16X16_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_SKIP_CU16X16_NUM(dev) (0x001c9b10+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_SKIP_CU16X16_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_SKIP_CU16X16_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_IPCM_CU16X16_NUM(dev) (0x001c9b14+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_IPCM_CU16X16_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_IPCM_CU16X16_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTRA_CU8X8_NUM(dev) (0x001c9b18+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTRA_CU8X8_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTRA_CU8X8_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_INTER_CU8X8_NUM(dev) (0x001c9b1c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_INTER_CU8X8_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_INTER_CU8X8_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_SKIP_CU8X8_NUM(dev) (0x001c9b20+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_SKIP_CU8X8_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_SKIP_CU8X8_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_STAT_IPCM_CU8X8_NUM(dev) (0x001c9b24+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_IPCM_CU8X8_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_IPCM_CU8X8_NUM_CNT 31:0 /* R--UF */
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#define NV_PNVENC_H265_STRPS_DELTA_POCS(dev) (0x001c9b28+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_STRPS_DELTA_POCS__SIZE_1 1 /* */
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#define NV_PNVENC_H265_STRPS_DELTA_POCS_USED_BY_CURR_PIC_FLAG 15:0 /* RWIUF */
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#define NV_PNVENC_H265_STRPS_DELTA_POCS_USED_BY_CURR_PIC_FLAG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_STRPS_DELTA_POCS_USE_DELTA_FLAG 31:16 /* RWIUF */
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#define NV_PNVENC_H265_STRPS_DELTA_POCS_USE_DELTA_FLAG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_STRPS_NUM(dev) (0x001c9b2c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_STRPS_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_H265_STRPS_NUM_NEGATIVE_PICS 15:0 /* RWIUF */
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#define NV_PNVENC_H265_STRPS_NUM_NEGATIVE_PICS_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_STRPS_NUM_POSITIVE_PICS 31:16 /* RWIUF */
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#define NV_PNVENC_H265_STRPS_NUM_POSITIVE_PICS_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_STRPS_USED_BY_CURR_PIC(dev) (0x001c9b30+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_STRPS_USED_BY_CURR_PIC__SIZE_1 1 /* */
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#define NV_PNVENC_H265_STRPS_USED_BY_CURR_PIC_S0_FLAG 15:0 /* RWIUF */
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#define NV_PNVENC_H265_STRPS_USED_BY_CURR_PIC_S0_FLAG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_STRPS_USED_BY_CURR_PIC_S1_FLAG 31:16 /* RWIUF */
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#define NV_PNVENC_H265_STRPS_USED_BY_CURR_PIC_S1_FLAG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_LTRPS_NUM(dev) (0x001c9b34+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_LTRPS_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_H265_LTRPS_NUM_LONG_TERM_REF_PIC_SET_NUM 4:0 /* RWIUF */
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#define NV_PNVENC_H265_LTRPS_NUM_LONG_TERM_REF_PIC_SET_NUM_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_LTRPS_NUM_LONG_TERM_SPS 9:5 /* RWIUF */
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#define NV_PNVENC_H265_LTRPS_NUM_LONG_TERM_SPS_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_LTRPS_NUM_LONG_TERM_PICS 14:10 /* RWIUF */
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#define NV_PNVENC_H265_LTRPS_NUM_LONG_TERM_PICS_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_H265_LTRPS_FLAG(dev) (0x001c9b38+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_LTRPS_FLAG__SIZE_1 1 /* */
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#define NV_PNVENC_H265_LTRPS_FLAG_USED_BY_CURR_PIC_LT_FLAG 15:0 /* RWIUF */
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#define NV_PNVENC_H265_LTRPS_FLAG_USED_BY_CURR_PIC_LT_FLAG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_LTRPS_FLAG_DELTA_POC_MSB_PRESENT_FLAG 31:16 /* RWIUF */
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#define NV_PNVENC_H265_LTRPS_FLAG_DELTA_POC_MSB_PRESENT_FLAG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_H265_REF_PIC_DATA(dev) (0x001c9b3c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_H265_REF_PIC_DATA__SIZE_1 1 /* */
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#define NV_PNVENC_H265_REF_PIC_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PNVENC_H265_REF_PIC_DATA_VALUE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_STAT_TOTAL_EMULATED_BITS(dev) (0x001c9b40+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_EMULATED_BITS__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_EMULATED_BITS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_MPEC_WP_PARAM(dev) (0x001c9b44+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WP_PARAM__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WP_PARAM_LUMA_LOG2_WEIGHT_DENOM 2:0 /* RWIUF */
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#define NV_PNVENC_MPEC_WP_PARAM_LUMA_LOG2_WEIGHT_DENOM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_WP_PARAM_CHROMA_LOG2_WEIGHT_DENOM 5:3 /* RWIUF */
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#define NV_PNVENC_MPEC_WP_PARAM_CHROMA_LOG2_WEIGHT_DENOM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_WP_DATA(dev) (0x001c9b48+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_WP_DATA__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_WP_DATA_WEIGHT_FLAG 0:0 /* RWIUF */
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#define NV_PNVENC_MPEC_WP_DATA_WEIGHT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_WP_DATA_WEIGHT 9:1 /* RWIUF */
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#define NV_PNVENC_MPEC_WP_DATA_WEIGHT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEC_WP_DATA_OFFSET 21:10 /* RWIUF */
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#define NV_PNVENC_MPEC_WP_DATA_OFFSET_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MPEC_WP_DATA_IDX 27:22 /* RWIUF */
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#define NV_PNVENC_MPEC_WP_DATA_IDX_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_DEBLK_DEBUG0(dev) (0x001c9b4c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_DEBLK_DEBUG0__SIZE_1 1 /* */
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#define NV_PNVENC_DEBLK_DEBUG0_DBF_DMA_RD_X 15:0 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG0_DBF_DMA_RD_Y 31:16 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG1(dev) (0x001c9b50+(dev)*16384) /* R--4A */
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#define NV_PNVENC_DEBLK_DEBUG1__SIZE_1 1 /* */
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#define NV_PNVENC_DEBLK_DEBUG1_DBF_DMA_WR_X 15:0 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG1_DBF_DMA_WR_Y 31:16 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG2(dev) (0x001c9b54+(dev)*16384) /* R--4A */
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#define NV_PNVENC_DEBLK_DEBUG2__SIZE_1 1 /* */
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#define NV_PNVENC_DEBLK_DEBUG2_DBF_PARAM_STATE 5:0 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG2_DBF_LUMA_STATE 8:6 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG2_DBF_CHRO_STATE 11:9 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG2_DBF_INPUT_STATE 14:12 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG2_DBFDMA_WSTATE 18:15 /* R-XUF */
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#define NV_PNVENC_DEBLK_DEBUG2_DBFDMA_RSTATE 20:19 /* R-XUF */
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#define NV_PNVENC_MPEB_SAO_MODE(dev) (0x001c9b58+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_SAO_MODE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_SAO_MODE_LUMA 4:0 /* RWIUF */
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#define NV_PNVENC_MPEB_SAO_MODE_LUMA_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEB_SAO_MODE_CHROMA 9:5 /* RWIUF */
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#define NV_PNVENC_MPEB_SAO_MODE_CHROMA_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_HW_PERF_CNT_MPEC_ACTIVE_STATUS(dev) (0x001c9b5c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HW_PERF_CNT_MPEC_ACTIVE_STATUS__SIZE_1 1 /* */
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#define NV_PNVENC_HW_PERF_CNT_MPEC_ACTIVE_STATUS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_MPEB_TU_BIAS_0(dev) (0x001c9b60+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_TU_BIAS_0__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_TU_BIAS_0_4X4 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_TU_BIAS_0_4X4_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_TU_BIAS_0_8X8 31:16 /* RWIUF */
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#define NV_PNVENC_MPEB_TU_BIAS_0_8X8_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_TU_BIAS_1(dev) (0x001c9b64+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_TU_BIAS_1__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_TU_BIAS_1_16X16 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_TU_BIAS_1_16X16_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_TU_BIAS_1_32X32 31:16 /* RWIUF */
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#define NV_PNVENC_MPEB_TU_BIAS_1_32X32_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEB_LAMBDA_DELTA(dev) (0x001c9b68+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_LAMBDA_DELTA__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_LAMBDA_DELTA_NUMBER_OF_1_DIV_8_LAMBDA_SSD 6:0 /* RWIUF */
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#define NV_PNVENC_MPEB_LAMBDA_DELTA_NUMBER_OF_1_DIV_8_LAMBDA_SSD_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_OFST_SLICE_IN_FRAME(dev) (0x001c9b6c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_OFST_SLICE_IN_FRAME__SIZE_1 1 /* */
|
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#define NV_PNVENC_MPEC_OFST_SLICE_IN_FRAME_CNT 31:0 /* RWIUF */
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#define NV_PNVENC_MPEC_OFST_SLICE_IN_FRAME_CNT_INIT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MPEC_PARTITION_FORMAT(dev) (0x001c9b70+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_PARTITION_FORMAT__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_PARTITION_FORMAT_STRIDE_IN256B 15:0 /* RWIUF */
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#define NV_PNVENC_MPEC_PARTITION_FORMAT_STRIDE_IN256B_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_HW_PERF_CNT_MPEB_ACTIVE_STATUS(dev) (0x001c9b74+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HW_PERF_CNT_MPEB_ACTIVE_STATUS__SIZE_1 1 /* */
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#define NV_PNVENC_HW_PERF_CNT_MPEB_ACTIVE_STATUS_CNT 31:0 /* R--UF */
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#define NV_PNVENC_MPEC_SLICE_STAT_1(dev) (0x001c9b78+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MPEC_SLICE_STAT_1__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_SLICE_STAT_1_SLICE_NUM 31:0 /* R-IUF */
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#define NV_PNVENC_MPEC_SLICE_STAT_1_SLICE_NUM_INIT 0x00000000 /* R-I-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1(dev) (0x001c9b7c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_POC_LSB_NOT_PRESENT_FLAG 0:0 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_POC_LSB_NOT_PRESENT_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_DEFAULT_REF_LAYERS_ACTIVE_FLAG 1:1 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_DEFAULT_REF_LAYERS_ACTIVE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_MAX_ONE_ACTIVE_REF_LAYER_FLAG 2:2 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_MAX_ONE_ACTIVE_REF_LAYER_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_NUM_DIRECT_REF_LAYERS 8:3 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_VPS_NUM_DIRECT_REF_LAYERS_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_DISCARDABLE_FLAG 9:9 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_DISCARDABLE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_CROSS_LAYER_BLA_FLAG 10:10 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_CROSS_LAYER_BLA_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_NUM_ACTIVE_REF_LAYER_PICS 16:11 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_NUM_ACTIVE_REF_LAYER_PICS_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_INTER_LAYER_PRED_ENABLE_FLAG 17:17 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_INTER_LAYER_PRED_ENABLE_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_NUM_INTER_LAYER_REF_PICS_MINUS1 23:18 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG1_SLH_NUM_INTER_LAYER_REF_PICS_MINUS1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2(dev) (0x001c9b80+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_0 2:0 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_1 5:3 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_2 8:6 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_3 11:9 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_4 14:12 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_5 17:15 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_6 20:18 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_7 23:21 /* RWIUF */
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#define NV_PNVENC_MPEC_MV_HEVC_CFG2_SLH_INTER_LAYER_PRED_LAYER_IDC_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MPEB_CFG(dev) (0x001c9b84+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_CFG__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_CFG_CHROMA_SKIP_THRESHOLD_4X4 15:0 /* RWIUF */
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#define NV_PNVENC_MPEB_CFG_CHROMA_SKIP_THRESHOLD_4X4_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MPEC_MVP_SCALE(dev) (0x001c9b88+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEC_MVP_SCALE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEC_MVP_SCALE_FACTOR0 12:0 /* RW-SF */
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#define NV_PNVENC_MPEC_MVP_SCALE_SAME_POC_0 15:15 /* RW-SF */
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#define NV_PNVENC_MPEC_MVP_SCALE_FACTOR1 28:16 /* RW-SF */
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#define NV_PNVENC_MPEC_MVP_SCALE_SAME_POC_1 31:31 /* RW-SF */
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#define NV_PNVENC_MPEB_LUMA_SCALE_BASE(dev) (0x001c9b8c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_LUMA_SCALE_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_LUMA_SCALE_BASE_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_MPEB_CHROMA_SCALE_BASE(dev) (0x001c9b90+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MPEB_CHROMA_SCALE_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MPEB_CHROMA_SCALE_BASE_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_LOW(dev) (0x001c9b94+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_LOW__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_LOW_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_LOW_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_HIGH(dev) (0x001c9b98+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_HIGH__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_HIGH_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSD_HIGH_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSIM(dev) (0x001c9b9c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSIM__SIZE_1 1 /* */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSIM_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_STAT_TOTAL_DIST_SSIM_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE(dev) (0x001c8400+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_ENABLE 0:0 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_SEARCH 1:1 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_SEARCH_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_SEARCH_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_SEARCH_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_REFINE 2:2 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_REFINE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_REFINE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_REFINE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_EXPLICIT 3:3 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_EXPLICIT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_EXPLICIT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_CONSTANT_MV_EXPLICIT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_ENABLE 4:4 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_SEARCH 5:5 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_SEARCH_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_SEARCH_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_SEARCH_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_REFINE 6:6 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_REFINE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_REFINE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_REFINE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_EXPLICIT 7:7 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_EXPLICIT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_EXPLICIT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_COLOC_EXPLICIT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_ENABLE 8:8 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_SEARCH 9:9 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_SEARCH_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_SEARCH_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_SEARCH_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_REFINE 10:10 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_REFINE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_REFINE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_REFINE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_EXPLICIT 11:11 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_EXPLICIT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_EXPLICIT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_SPATIAL_EXPLICIT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_ENABLE 12:12 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_SEARCH 13:13 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_SEARCH_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_SEARCH_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_SEARCH_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_REFINE 14:14 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_REFINE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_REFINE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_REFINE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_EXPLICIT 15:15 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_EXPLICIT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_EXPLICIT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_SELF_TEMPORAL_EXPLICIT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_ENABLE 16:16 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_SEARCH 17:17 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_SEARCH_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_SEARCH_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_SEARCH_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_REFINE 18:18 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_REFINE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_REFINE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_REFINE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_EXPLICIT 19:19 /* RWIUF */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_EXPLICIT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_EXPLICIT_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PREDICTOR_SOURCE_EXTERNAL_HINTS_EXPLICIT_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_GLOBAL_L0_MV(dev) (0x001c8404+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_GLOBAL_L0_MV__SIZE_1 1 /* */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVX_INT 29:18 /* RWISF */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVX_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVX_FRAC 17:16 /* RWIUF */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVX_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVY_INT 11:2 /* RWISF */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVY_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVY_FRAC 1:0 /* RWIUF */
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#define NV_PNVENC_ME_GLOBAL_L0_MV_MVY_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_GLOBAL_L1_MV(dev) (0x001c8408+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_GLOBAL_L1_MV__SIZE_1 1 /* */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVX_INT 29:18 /* RWISF */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVX_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVX_FRAC 17:16 /* RWIUF */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVX_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVY_INT 11:2 /* RWISF */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVY_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVY_FRAC 1:0 /* RWIUF */
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#define NV_PNVENC_ME_GLOBAL_L1_MV_MVY_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_SIZE(dev) (0x001c840c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_PIC_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_PIC_SIZE_WIDTH_IN_MB 28:16 /* RWIUF */
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#define NV_PNVENC_ME_PIC_SIZE_WIDTH_IN_MB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_PIC_SIZE_HEIGHT_IN_MB 12:0 /* RWIUF */
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#define NV_PNVENC_ME_PIC_SIZE_HEIGHT_IN_MB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_STATUS(dev) (0x001c8410+(dev)*16384) /* R--4A */
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#define NV_PNVENC_ME_STATUS__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STATUS_PG_BUSY 0:0 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_PG_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_PG_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_PG_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_SRF_BUSY 1:1 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_SRF_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_SRF_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_SRF_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_QS_BUSY 2:2 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_QS_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_QS_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_QS_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_FPS_BUSY 3:3 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_FPS_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_FPS_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_FPS_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_FBM_BUSY 4:4 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_FBM_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_FBM_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_FBM_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_MBC_BUSY 5:5 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_MBC_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_MBC_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_MBC_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_ICC_BUSY 6:6 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_ICC_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_ICC_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_ICC_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_CURMB_BUSY 7:7 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_CURMB_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_CURMB_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_CURMB_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_BUFADM_BUSY 8:8 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_BUFADM_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_BUFADM_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_BUFADM_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_SPS_BUSY 9:9 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_SPS_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_SPS_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_SPS_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPCTL_BUSY 10:10 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_HPCTL_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_HPCTL_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPCTL_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPF_BUSY 11:11 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_HPF_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_HPF_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPF_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_LBUF_BUSY 12:12 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_LBUF_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_LBUF_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_LBUF_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPSATD_BUSY 13:13 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_HPSATD_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_HPSATD_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPSATD_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPCOST_BUSY 14:14 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_HPCOST_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_HPCOST_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_HPCOST_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_QPCTL_BUSY 15:15 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_QPCTL_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_QPCTL_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_QPCTL_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_QPSATD_BUSY 16:16 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_QPSATD_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_QPSATD_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_QPSATD_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_QPCOST_BUSY 17:17 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_QPCOST_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_QPCOST_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_QPCOST_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_UVF_BUSY 18:18 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_UVF_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_UVF_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_UVF_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_BICTL_BUSY 19:19 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_BICTL_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_BICTL_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_BICTL_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_WPRED_BUSY 20:20 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_WPRED_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_WPRED_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_WPRED_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_BISATD_BUSY 21:21 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_BISATD_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_BISATD_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_BISATD_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_MVPACK_BUSY 22:22 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_MVPACK_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_MVPACK_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_MVPACK_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_STATUS_MCINTF_BUSY 23:23 /* R-IUF */
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#define NV_PNVENC_ME_STATUS_MCINTF_BUSY_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_STATUS_MCINTF_BUSY_IDLE 0x0 /* R---V */
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#define NV_PNVENC_ME_STATUS_MCINTF_BUSY_BUSY 0x1 /* R---V */
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#define NV_PNVENC_ME_SLICE_CONTROL(dev) (0x001c8414+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_SLICE_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SLICE_CONTROL_CURRENT_MB_X 27:16 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONTROL_CURRENT_MB_X_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONTROL_CURRENT_MB_Y 11:0 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONTROL_CURRENT_MB_Y_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL(dev) (0x001c8428+(dev)*16384) /* R--4A */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL_CURRENT_MB_X 31:24 /* R-IUF */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL_CURRENT_MB_X_DEFAULT 0x00 /* R-I-V */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL_CURRENT_MB_Y 23:16 /* R-IUF */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL_CURRENT_MB_Y_DEFAULT 0x00 /* R-I-V */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL_MB_CNT 15:0 /* R-IUF */
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#define NV_PNVENC_ME_SRF_SLICE_CONTROL_MB_CNT_DEFAULT 0x0000 /* R-I-V */
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#define NV_PNVENC_ME_PIC_CONTROL(dev) (0x001c842c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_PIC_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_EN 31:31 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_EN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_EN_OFF 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_EN_ON 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_BIT_DEPTH_MINUS8 30:27 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_BIT_DEPTH_MINUS8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_BIT_DEPTH_MINUS8_10BIT 0x2 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_BIT_DEPTH_MINUS8_12BIT 0x4 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_BIT_DEPTH_MINUS8_16BIT 0x8 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CTBSIZE 26:25 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_CTBSIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_CTBSIZE_16X16 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CTBSIZE_32X32 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CTBSIZE_64X64 0x2 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_YUV444 24:24 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_YUV444_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_YUV444_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_YUV444_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_VC1_MC_RND 23:23 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_VC1_MC_RND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_VC1_FASTUVMC 22:22 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_VC1_FASTUVMC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_VC1_FASTUVMC_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID 21:19 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_H264 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_MPEG4 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_VP8 0x2 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_MPEG2 0x3 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_VC1 0x4 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_H265 0x5 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_CODEC_ID_VP9 0x6 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_VP8_VERSION 18:16 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_VP8_VERSION_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER 15:13 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER_H264 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER_MPEG4 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER_VP8 0x2 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER_MPEG2 0x3 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER_VC1 0x4 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MC_FILTER_H265 0x5 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_FILTER 12:10 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_FILTER_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_FILTER_H264 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_FILTER_MPEG4 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_FILTER_VP8 0x2 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_FILTER_H265 0x5 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_COSTFUNC 9:9 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_COSTFUNC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_COSTFUNC_SATD 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_COSTFUNC_SAD 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_MVCOST 8:8 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_MVCOST_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_MVCOST_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_SPS_MVCOST_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_FPS_MVCOST 7:7 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_FPS_MVCOST_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_FPS_MVCOST_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_FPS_MVCOST_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_MODE 6:6 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_MODE_OPTICALFLOW 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_OFS_MODE_STEREO 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MEONLY 5:5 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_MEONLY_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_MEONLY_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MEONLY_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_WPRED_MODE 4:4 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_WPRED_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_WPRED_MODE_DFLT 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_WPRED_MODE_IMPLICIT 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MVY_LIMIT 3:2 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_MVY_LIMIT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_MVY_LIMIT_64 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MVY_LIMIT_128 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MVY_LIMIT_256 0x2 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_MVY_LIMIT_512 0x3 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_PIC_STRUCT 1:0 /* RWIUF */
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#define NV_PNVENC_ME_PIC_CONTROL_PIC_STRUCT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PIC_CONTROL_PIC_STRUCT_FRAME 0x0 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_PIC_STRUCT_TOP_FIELD 0x1 /* RW--V */
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#define NV_PNVENC_ME_PIC_CONTROL_PIC_STRUCT_BOTTOM_FIELD 0x2 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG(dev) (0x001c8440+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_SPS_CONFIG__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_MODE 1:0 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_MODE_MDP 0x0 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_MODE_SELF 0x1 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_MODE_CONSTANT 0x2 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_SEL 2:2 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_SEL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_SEL_HALF_PEL 0x0 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_SEL_QUARTER_PEL 0x1 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_FPS 3:3 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_FPS_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_FPS_OFF 0x0 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_REFINE_FPS_ON 0x1 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_WAIT_MOCOMP 4:4 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONFIG_WAIT_MOCOMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONFIG_WAIT_MOCOMP_OFF 0x0 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_WAIT_MOCOMP_ON 0x1 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_EVALUATE_MERGE_CAND_NUM 7:5 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONFIG_EVALUATE_MERGE_CAND_NUM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_FROM_FBM 8:8 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_FROM_FBM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_FROM_FBM_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONFIG_PREDICTOR_FROM_FBM_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR(dev) (0x001c8444+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR__SIZE_1 1 /* */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVX_INT 29:18 /* RWISF */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVX_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVX_FRAC 17:16 /* RWIUF */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVX_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVY_INT 11:2 /* RWISF */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVY_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVY_FRAC 1:0 /* RWIUF */
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#define NV_PNVENC_ME_CONSTANT_L0_PREDICTOR_MVY_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR(dev) (0x001c8448+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR__SIZE_1 1 /* */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVX_INT 29:18 /* RWISF */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVX_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVX_FRAC 17:16 /* RWIUF */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVX_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVY_INT 11:2 /* RWISF */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVY_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVY_FRAC 1:0 /* RWIUF */
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#define NV_PNVENC_ME_CONSTANT_L1_PREDICTOR_MVY_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_LAMBDA(dev) (0x001c844c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_LAMBDA__SIZE_1 1 /* */
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#define NV_PNVENC_ME_LAMBDA_FULLPEL 26:16 /* RWIUF */
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#define NV_PNVENC_ME_LAMBDA_FULLPEL_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_LAMBDA_SOURCE 15:15 /* RWIUF */
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#define NV_PNVENC_ME_LAMBDA_SOURCE_MDP 0x0 /* RW--V */
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#define NV_PNVENC_ME_LAMBDA_SOURCE_CSB 0x1 /* RW--V */
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#define NV_PNVENC_ME_LAMBDA_SOURCE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_LAMBDA_SUBPEL 10:0 /* RWIUF */
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#define NV_PNVENC_ME_LAMBDA_SUBPEL_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_LONGTERM(dev) (0x001c8450+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_LONGTERM__SIZE_1 1 /* */
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#define NV_PNVENC_ME_LONGTERM_L0 7:0 /* RWIUF */
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#define NV_PNVENC_ME_LONGTERM_L0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_LONGTERM_L1 23:16 /* RWIUF */
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#define NV_PNVENC_ME_LONGTERM_L1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_DBG_SEL(dev) (0x001c8454+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_DBG_SEL__SIZE_1 1 /* */
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#define NV_PNVENC_ME_DBG_SEL_IDX 5:0 /* RWIUF */
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#define NV_PNVENC_ME_DBG_SEL_IDX_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_DBG_STAT(dev) (0x001c8458+(dev)*16384) /* R--4A */
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#define NV_PNVENC_ME_DBG_STAT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_DBG_STAT_VAL 31:0 /* R-IUF */
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#define NV_PNVENC_ME_DBG_STAT_VAL_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_ME_SLICE_CONFIG(dev) (0x001c8464+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_SLICE_CONFIG__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SLICE_CONFIG_SLICE_TYPE 31:30 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_SLICE_TYPE_INTRA 0x2 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_SLICE_TYPE_B 0x1 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_SLICE_TYPE_P 0x0 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_SLICE_TYPE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_PSKIP 26:26 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_PSKIP_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_PSKIP_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_PSKIP_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_DIRECT 25:24 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_DIRECT_TEMPORAL 0x2 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_DIRECT_SPATIAL 0x1 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_DIRECT_NONE 0x0 /* RW--V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_DIRECT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_8X8 19:19 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_8X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_8X16 18:18 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_8X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_16X8 17:17 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_16X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_16X16 16:16 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_BI_16X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_8X8 11:11 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_8X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_8X16 10:10 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_8X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_16X8 9:9 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_16X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_16X16 8:8 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L1_16X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_8X8 3:3 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_8X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_8X16 2:2 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_8X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_16X8 1:1 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_16X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_16X16 0:0 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_CONFIG_EVAL_L0_16X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY0(dev) (0x001c8468+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MV_BOUNDARY0__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MV_BOUNDARY0_LEFT_ENABLE 31:31 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY0_LEFT_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY0_LEFT_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY0_LEFT_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY0_LEFT_MB 27:16 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY0_LEFT_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY0_RIGHT_ENABLE 15:15 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY0_RIGHT_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY0_RIGHT_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY0_RIGHT_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY0_RIGHT_MB 11:0 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY0_RIGHT_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY1(dev) (0x001c846c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MV_BOUNDARY1__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MV_BOUNDARY1_TOP_ENABLE 31:31 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY1_TOP_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY1_TOP_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY1_TOP_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY1_TOP_MB 27:16 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY1_TOP_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY1_BOTTOM_ENABLE 15:15 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY1_BOTTOM_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_BOUNDARY1_BOTTOM_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY1_BOTTOM_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_MV_BOUNDARY1_BOTTOM_MB 11:0 /* RWIUF */
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#define NV_PNVENC_ME_MV_BOUNDARY1_BOTTOM_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L0(dev,i) (0x001c8470+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_SELF_SCALE_L0__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SELF_SCALE_L0__SIZE_2 2 /* */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR0 7:0 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR1 15:8 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR2 23:16 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR3 31:24 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L0_SCALEFACTOR3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L1(dev,i) (0x001c8478+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_SELF_SCALE_L1__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SELF_SCALE_L1__SIZE_2 2 /* */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR0 7:0 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR1 15:8 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR2 23:16 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR3 31:24 /* RWISF */
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#define NV_PNVENC_ME_SELF_SCALE_L1_SCALEFACTOR3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_COLOC_DIST(dev,i) (0x001c8480+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_COLOC_DIST__SIZE_1 1 /* */
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#define NV_PNVENC_ME_COLOC_DIST__SIZE_2 32 /* */
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#define NV_PNVENC_ME_COLOC_DIST_SCALEFACTOR0 10:0 /* RW-SF */
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#define NV_PNVENC_ME_COLOC_DIST_SCALEFACTOR1 26:16 /* RW-SF */
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#define NV_PNVENC_ME_INTR_STATUS(dev) (0x001c8500+(dev)*16384) /* R--4A */
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#define NV_PNVENC_ME_INTR_STATUS__SIZE_1 1 /* */
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#define NV_PNVENC_ME_INTR_STATUS_CFGERR 0:0 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_CFGERR_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_CFGERR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_CFGERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_REFERR 1:1 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_REFERR_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_REFERR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_REFERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_PICERR 2:2 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_PICERR_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_PICERR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_PICERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_HINTOV 3:3 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_HINTOV_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_HINTOV_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_HINTOV_TRUE 0x1 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_INPERR 4:4 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_INPERR_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_INPERR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_INPERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_AFFERR 5:5 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_AFFERR_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_AFFERR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_AFFERR_TRUE 0x1 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_SSCERR 6:6 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_SSCERR_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_SSCERR_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_SSCERR_TRUE 0x1 /* R---V */
|
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#define NV_PNVENC_ME_INTR_STATUS_MCMISS 7:7 /* R-IUF */
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#define NV_PNVENC_ME_INTR_STATUS_MCMISS_DEFAULT 0x0 /* R-I-V */
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#define NV_PNVENC_ME_INTR_STATUS_MCMISS_FALSE 0x0 /* R---V */
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#define NV_PNVENC_ME_INTR_STATUS_MCMISS_TRUE 0x1 /* R---V */
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#define NV_PNVENC_ME_INTR_ENABLE(dev) (0x001c8504+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_ME_INTR_ENABLE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_CFGERR 0:0 /* RWIUF */
|
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#define NV_PNVENC_ME_INTR_ENABLE_CFGERR_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_CFGERR_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_CFGERR_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_REFERR 1:1 /* RWIUF */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_REFERR_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_REFERR_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_REFERR_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_PICERR 2:2 /* RWIUF */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_PICERR_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_PICERR_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_PICERR_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_HINTOV 3:3 /* RWIUF */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_HINTOV_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_HINTOV_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_HINTOV_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_INPERR 4:4 /* RWIUF */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_INPERR_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_INPERR_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_INPERR_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_AFFERR 5:5 /* RWIUF */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_AFFERR_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_AFFERR_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_AFFERR_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_SSCERR 6:6 /* RWIUF */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_SSCERR_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_SSCERR_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_SSCERR_ENABLE 0x1 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_MCMISS 7:7 /* RWIUF */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_MCMISS_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_MCMISS_DISABLE 0x0 /* RW--V */
|
|
#define NV_PNVENC_ME_INTR_ENABLE_MCMISS_ENABLE 0x1 /* RW--V */
|
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#define NV_PNVENC_ME_ICC_MODE(dev) (0x001c850c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_ICC_MODE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_ICC_MODE_16X16_VERT 0:0 /* RWIUF */
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#define NV_PNVENC_ME_ICC_MODE_16X16_VERT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_VERT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_VERT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_HORI 1:1 /* RWIUF */
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#define NV_PNVENC_ME_ICC_MODE_16X16_HORI_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_HORI_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_HORI_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_DC 2:2 /* RWIUF */
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#define NV_PNVENC_ME_ICC_MODE_16X16_DC_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_DC_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_16X16_DC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_ICC_MODE_MAD 3:3 /* RWIUF */
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#define NV_PNVENC_ME_ICC_MODE_MAD_DEFAULT 0x0 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_MAD_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_ICC_MODE_MAD_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_ME_DIFF_PIC_ORDER_CNT_ZERO(dev,i) (0x001c8510+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_DIFF_PIC_ORDER_CNT_ZERO__SIZE_1 1 /* */
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#define NV_PNVENC_ME_DIFF_PIC_ORDER_CNT_ZERO__SIZE_2 2 /* */
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#define NV_PNVENC_ME_DIFF_PIC_ORDER_CNT_ZERO_VALUE 31:0 /* RWISF */
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#define NV_PNVENC_ME_DIFF_PIC_ORDER_CNT_ZERO_VALUE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SHAPE_LO(dev,i) (0x001c8518+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_SHAPE_LO__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_SHAPE_LO__SIZE_2 8 /* */
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#define NV_PNVENC_ME_STAMP_SHAPE_LO_MASK_VALUE 31:0 /* RWISF */
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#define NV_PNVENC_ME_STAMP_SHAPE_LO_MASK_VALUE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SHAPE_HI(dev,i) (0x001c8538+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_SHAPE_HI__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_SHAPE_HI__SIZE_2 8 /* */
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#define NV_PNVENC_ME_STAMP_SHAPE_HI_MASK_VALUE 31:0 /* RWISF */
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#define NV_PNVENC_ME_STAMP_SHAPE_HI_MASK_VALUE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0(dev) (0x001c8558+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX0_STAMP 2:0 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX0_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX1_STAMP 6:4 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX1_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX2_STAMP 10:8 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX2_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX3_STAMP 14:12 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX3_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX4_STAMP 18:16 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX4_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX5_STAMP 22:20 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX5_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX6_STAMP 26:24 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX6_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX7_STAMP 30:28 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L0_REFIDX7_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1(dev) (0x001c855c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX0_STAMP 2:0 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX0_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX1_STAMP 6:4 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX1_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX2_STAMP 10:8 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX2_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX3_STAMP 14:12 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX3_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX4_STAMP 18:16 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX4_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX5_STAMP 22:20 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX5_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX6_STAMP 26:24 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX6_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX7_STAMP 30:28 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_EXT_L1_REFIDX7_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0(dev) (0x001c8560+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_CONSTANT_MV_STAMP 2:0 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_CONSTANT_MV_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_COLOC_STAMP 6:4 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_COLOC_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_SELF_SPATIAL_STAMP 10:8 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_SELF_SPATIAL_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_SELF_TEMPORAL_STAMP 14:12 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L0_SELF_TEMPORAL_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1(dev) (0x001c8564+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_CONSTANT_MV_STAMP 2:0 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_CONSTANT_MV_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_COLOC_STAMP 6:4 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_COLOC_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_SELF_SPATIAL_STAMP 10:8 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_SELF_SPATIAL_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_SELF_TEMPORAL_STAMP 14:12 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_INT_L1_SELF_TEMPORAL_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER(dev) (0x001c8568+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_CENTER__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_0 0:0 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_0 1:1 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_1 2:2 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_1 3:3 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_2 4:4 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_2 5:5 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_3 6:6 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_3 7:7 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_4 8:8 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_4 9:9 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_5 10:10 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_5 11:11 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_6 12:12 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_6 13:13 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_7 14:14 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_VERTICAL_ADJUST_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_7 15:15 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_CENTER_HORIZONTAL_ADJUST_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT0(dev) (0x001c856c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MV_LIMIT0__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MV_LIMIT0_ENABLE 31:31 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT0_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT0_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_ME_MV_LIMIT0_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_ME_MV_LIMIT0_LEFT_MVX_INT 29:18 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT0_LEFT_MVX_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT0_LEFT_MVX_FRAC 17:16 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT0_LEFT_MVX_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT0_TOP_MVY_INT 11:2 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT0_TOP_MVY_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT0_TOP_MVY_FRAC 1:0 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT0_TOP_MVY_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT1(dev) (0x001c8570+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MV_LIMIT1__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MV_LIMIT1_RIGHT_MVX_INT 29:18 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT1_RIGHT_MVX_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT1_RIGHT_MVX_FRAC 17:16 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT1_RIGHT_MVX_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT1_BOT_MVY_INT 11:2 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT1_BOT_MVY_INT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MV_LIMIT1_BOT_MVY_FRAC 1:0 /* RWIUF */
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#define NV_PNVENC_ME_MV_LIMIT1_BOT_MVY_FRAC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SLICE_MB_CNT(dev) (0x001c8574+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_SLICE_MB_CNT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SLICE_MB_CNT_BIT 24:0 /* RWIUF */
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#define NV_PNVENC_ME_SLICE_MB_CNT_BIT_DEFAULT 0x0000000 /* RWI-V */
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#define NV_PNVENC_ME_TEB_INFO(dev) (0x001c8578+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_TEB_INFO__SIZE_1 1 /* */
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#define NV_PNVENC_ME_TEB_INFO_S 27:24 /* RWIUF */
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#define NV_PNVENC_ME_TEB_INFO_S_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_TEB_INFO_P 23:16 /* RWIUF */
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#define NV_PNVENC_ME_TEB_INFO_P_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_TEB_INFO_N 15:8 /* RWIUF */
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#define NV_PNVENC_ME_TEB_INFO_N_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_TEB_INFO_K 7:0 /* RWIUF */
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#define NV_PNVENC_ME_TEB_INFO_K_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR(dev) (0x001c857c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_X_IDX 8:0 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_X_IDX_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_X_VALID 15:15 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_X_VALID_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_Y_IDX 24:16 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_Y_IDX_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_Y_VALID 31:31 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_ADDR_Y_VALID_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_DATA(dev) (0x001c8580+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_DATA__SIZE_1 1 /* */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_DATA_X 14:0 /* RW-UF */
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#define NV_PNVENC_ME_VP8_MVCOST_TABLE_DATA_Y 30:16 /* RW-UF */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_X(dev) (0x001c8584+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_X__SIZE_1 1 /* */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_X_POS 15:0 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_X_POS_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_X_NEG 31:16 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_X_NEG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_Y(dev) (0x001c8588+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_Y__SIZE_1 1 /* */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_Y_POS 15:0 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_Y_POS_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_Y_NEG 31:16 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_SIGNCOST_Y_NEG_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_X(dev) (0x001c858c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_X__SIZE_1 1 /* */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_X_LO 15:0 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_X_LO_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_X_HI 31:16 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_X_HI_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_Y(dev) (0x001c8590+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_Y__SIZE_1 1 /* */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_Y_LO 15:0 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_Y_LO_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_Y_HI 31:16 /* RWIUF */
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#define NV_PNVENC_ME_VP8_MV_OFFSET_Y_HI_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16(dev) (0x001c8594+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16__SIZE_1 1 /* */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NRX2N 23:23 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NLX2N 22:22 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NXND 21:21 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NXNU 20:20 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NXN 19:19 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NX2N 18:18 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NXN 17:17 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NX2N 16:16 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_BI_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NRX2N 15:15 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NLX2N 14:14 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NXND 13:13 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NXNU 12:12 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NXN 11:11 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NX2N 10:10 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NXN 9:9 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NX2N 8:8 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L1_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NRX2N 7:7 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NLX2N 6:6 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NXND 5:5 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NXNU 4:4 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NXN 3:3 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NX2N 2:2 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NXN 1:1 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NX2N 0:0 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_16X16_EVAL_L0_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32(dev) (0x001c8598+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32__SIZE_1 1 /* */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NRX2N 23:23 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NLX2N 22:22 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NXND 21:21 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NXNU 20:20 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NXN 19:19 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NX2N 18:18 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NXN 17:17 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NX2N 16:16 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_BI_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NRX2N 15:15 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NLX2N 14:14 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NXND 13:13 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NXNU 12:12 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NXN 11:11 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NX2N 10:10 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NXN 9:9 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NX2N 8:8 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L1_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NRX2N 7:7 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NLX2N 6:6 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NXND 5:5 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NXNU 4:4 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NXN 3:3 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NX2N 2:2 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NXN 1:1 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NX2N 0:0 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_32X32_EVAL_L0_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64(dev) (0x001c859c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64__SIZE_1 1 /* */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NRX2N 23:23 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NLX2N 22:22 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NXND 21:21 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NXNU 20:20 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NXN 19:19 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NX2N 18:18 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NXN 17:17 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NX2N 16:16 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_BI_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NRX2N 15:15 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NLX2N 14:14 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NXND 13:13 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NXNU 12:12 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NXN 11:11 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NX2N 10:10 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NXN 9:9 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NX2N 8:8 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L1_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NRX2N 7:7 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NRX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NLX2N 6:6 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NLX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NXND 5:5 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NXND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NXNU 4:4 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NXNU_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NXN 3:3 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NX2N 2:2 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NXN 1:1 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NXN_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NX2N 0:0 /* RWIUF */
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#define NV_PNVENC_ME_PART_MODE_CONFIG_CUSIZE_64X64_EVAL_L0_2NX2N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_DECISION_FPS(dev) (0x001c85a4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_PART_DECISION_FPS__SIZE_1 1 /* */
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#define NV_PNVENC_ME_PART_DECISION_FPS_CU16_ENABLE 16:16 /* RWIUF */
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#define NV_PNVENC_ME_PART_DECISION_FPS_CU16_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FBM_OUTPUT_WINNER_NUM_L1 15:13 /* RWIUF */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FBM_OUTPUT_WINNER_NUM_L1_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FBM_SELECT_BEST_CU32_PARTTYPE_NUM 12:10 /* RWIUF */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FBM_SELECT_BEST_CU32_PARTTYPE_NUM_DEFAULT 0x7 /* RWI-V */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FBM_OUTPUT_WINNER_NUM_L0 9:7 /* RWIUF */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FBM_OUTPUT_WINNER_NUM_L0_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FACTOR 6:1 /* RWIUF */
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#define NV_PNVENC_ME_PART_DECISION_FPS_FACTOR_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_PART_DECISION_FPS_ENABLE 0:0 /* RWIUF */
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#define NV_PNVENC_ME_PART_DECISION_FPS_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_WP_PARAM(dev) (0x001c85a8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_WP_PARAM__SIZE_1 1 /* */
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#define NV_PNVENC_ME_WP_PARAM_CHROMA_LOG2_DENOM 10:8 /* RWIUF */
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#define NV_PNVENC_ME_WP_PARAM_CHROMA_LOG2_DENOM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_WP_PARAM_LUMA_LOG2_DENOM 6:4 /* RWIUF */
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#define NV_PNVENC_ME_WP_PARAM_LUMA_LOG2_DENOM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_WP_PARAM_BIPRED_IDC 3:2 /* RWIUF */
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#define NV_PNVENC_ME_WP_PARAM_BIPRED_IDC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_WP_PARAM_PRED_FLAG 0:0 /* RWIUF */
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#define NV_PNVENC_ME_WP_PARAM_PRED_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_WP_DATA(dev) (0x001c85ac+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_WP_DATA__SIZE_1 1 /* */
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#define NV_PNVENC_ME_WP_DATA_IDX 27:22 /* RWIUF */
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#define NV_PNVENC_ME_WP_DATA_IDX_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_WP_DATA_OFFSET 21:10 /* RWIUF */
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#define NV_PNVENC_ME_WP_DATA_OFFSET_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_WP_DATA_WEIGHT 9:1 /* RWIUF */
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#define NV_PNVENC_ME_WP_DATA_WEIGHT_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_WP_DATA_FLAG 0:0 /* RWIUF */
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#define NV_PNVENC_ME_WP_DATA_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_FPS_HW_PERF_CNT(dev) (0x001c85b0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_ME_FPS_HW_PERF_CNT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_FPS_HW_PERF_CNT_VALUE 31:0 /* R--UF */
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#define NV_PNVENC_ME_FPS_HW_PERF_CNT_VALUE_DEFAULT 0x00000000 /* R---V */
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#define NV_PNVENC_ME_SPS_HW_PERF_CNT(dev) (0x001c85b4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_ME_SPS_HW_PERF_CNT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_SPS_HW_PERF_CNT_VALUE 31:0 /* R--UF */
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#define NV_PNVENC_ME_SPS_HW_PERF_CNT_VALUE_DEFAULT 0x00000000 /* R---V */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE(dev) (0x001c85b8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE_VAL 1:0 /* RWIUF */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE_VAL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE_VAL_EIGHTTAP_SMOOTH 0x0 /* RW--V */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE_VAL_EIGHTTAP 0x1 /* RW--V */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE_VAL_EIGHTTAP_SHARP 0x2 /* RW--V */
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#define NV_PNVENC_ME_VP9_MC_FILTER_TYPE_VAL_BILINEAR 0x3 /* RW--V */
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#define NV_PNVENC_ME_ACTIVE_REFPIC_NUM(dev) (0x001c85bc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_ACTIVE_REFPIC_NUM__SIZE_1 1 /* */
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#define NV_PNVENC_ME_ACTIVE_REFPIC_NUM_L0 4:0 /* RWIUF */
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#define NV_PNVENC_ME_ACTIVE_REFPIC_NUM_L0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_ACTIVE_REFPIC_NUM_L1 20:16 /* RWIUF */
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#define NV_PNVENC_ME_ACTIVE_REFPIC_NUM_L1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY(dev) (0x001c85c0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY__SIZE_1 1 /* */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_7 31:31 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA7 30:28 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_6 27:27 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA6 26:24 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_5 23:23 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA5 22:20 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_4 19:19 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA4 18:16 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_3 15:15 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA3 14:12 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_2 11:11 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA2 10:8 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_1 7:7 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA1 6:4 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_0 3:3 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_LONG_TERM_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA0 2:0 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST0_POCENTRY_DATA0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY(dev) (0x001c85c4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY__SIZE_1 1 /* */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_7 31:31 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA7 30:28 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_6 27:27 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA6 26:24 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_5 23:23 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA5 22:20 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_4 19:19 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA4 18:16 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_3 15:15 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA3 14:12 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_2 11:11 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA2 10:8 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_1 7:7 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA1 6:4 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_0 3:3 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_LONG_TERM_0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA0 2:0 /* RWIUF */
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#define NV_PNVENC_ME_REFLIST1_POCENTRY_DATA0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MVP_SCALE(dev) (0x001c85c8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MVP_SCALE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MVP_SCALE_FACTOR0 12:0 /* RW-SF */
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#define NV_PNVENC_ME_MVP_SCALE_SAME_POC_0 15:15 /* RW-SF */
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#define NV_PNVENC_ME_MVP_SCALE_FACTOR1 28:16 /* RW-SF */
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#define NV_PNVENC_ME_MVP_SCALE_SAME_POC_1 31:31 /* RW-SF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF(dev) (0x001c85cc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF__SIZE_1 1 /* */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX1_STAMP 2:0 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX1_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX2_STAMP 6:4 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX2_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX3_STAMP 10:8 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX3_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX4_STAMP 14:12 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX4_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX5_STAMP 18:16 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX5_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX6_STAMP 22:20 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX6_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX7_STAMP 26:24 /* RWIUF */
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#define NV_PNVENC_ME_STAMP_SELECT_MULTI_REF_REFIDX7_STAMP_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MULTI_REF_HINT_PATTERN(dev) (0x001c85d0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MULTI_REF_HINT_PATTERN__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MULTI_REF_HINT_PATTERN_SPATIAL_HINT 3:0 /* RWIUF */
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#define NV_PNVENC_ME_MULTI_REF_HINT_PATTERN_SPATIAL_HINT_DEFAULT 0xf /* RWI-V */
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#define NV_PNVENC_ME_MULTI_REF_HINT_PATTERN_TEMPORAL_HINT 9:4 /* RWIUF */
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#define NV_PNVENC_ME_MULTI_REF_HINT_PATTERN_TEMPORAL_HINT_DEFAULT 0x3f /* RWI-V */
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#define NV_PNVENC_ME_OFS_CT_THRESHOLD(dev) (0x001c85d4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_OFS_CT_THRESHOLD__SIZE_1 1 /* */
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#define NV_PNVENC_ME_OFS_CT_THRESHOLD_VAL 16:0 /* RWISF */
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#define NV_PNVENC_ME_OFS_CT_THRESHOLD_VAL_DEFAULT 0x00000 /* RWI-V */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN(dev) (0x001c85d8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN__SIZE_1 1 /* */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE0 2:0 /* RWIUF */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE1 5:3 /* RWIUF */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE1_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE2 8:6 /* RWIUF */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE2_DEFAULT 0x2 /* RWI-V */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE3 11:9 /* RWIUF */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE3_DEFAULT 0x3 /* RWI-V */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE4 14:12 /* RWIUF */
|
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_HINT_TYPE4_DEFAULT 0x4 /* RWI-V */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_EXTERNAL_HINT_ORDER 15:15 /* RWIUF */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_EXTERNAL_HINT_ORDER_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_COLOC_HINT_ORDER 16:16 /* RWIUF */
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#define NV_PNVENC_ME_HINT_TYPE_PATTERN_COLOC_HINT_ORDER_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_ME_HINT_CONTRL(dev) (0x001c85dc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_HINT_CONTRL__SIZE_1 1 /* */
|
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#define NV_PNVENC_ME_HINT_CONTRL_LEFT_HINT_DELAY_N 3:0 /* RWIUF */
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#define NV_PNVENC_ME_HINT_CONTRL_LEFT_HINT_DELAY_N_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_HINT_CONTRL_PYRAMIDAL_HINT_ORDER 4:4 /* RWIUF */
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#define NV_PNVENC_ME_HINT_CONTRL_PYRAMIDAL_HINT_ORDER_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONTROL(dev) (0x001c85e0+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_ME_SPS_CONTROL__SIZE_1 1 /* */
|
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#define NV_PNVENC_ME_SPS_CONTROL_H264_ACCURATE_SKIP_MV 0:0 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONTROL_H264_ACCURATE_SKIP_MV_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_SPS_CONTROL_H264_ACCURATE_SKIP_MV_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONTROL_H264_ACCURATE_SKIP_MV_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_SPS_CONTROL_H264_ACCURATE_NORMAL_ORDER 2:1 /* RWIUF */
|
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#define NV_PNVENC_ME_SPS_CONTROL_H264_ACCURATE_NORMAL_ORDER_DEFAULT 0x0 /* RWI-V */
|
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#define NV_PNVENC_ME_SPS_CONTROL_SEARCH_BEFORE_FINAL_STAGE 7:3 /* RWIUF */
|
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#define NV_PNVENC_ME_SPS_CONTROL_SEARCH_BEFORE_FINAL_STAGE_DEFAULT 0x00 /* RWI-V */
|
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#define NV_PNVENC_ME_SPS_CONTROL_SEARCH_BEFORE_EVAL_STAGE 9:8 /* RWIUF */
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#define NV_PNVENC_ME_SPS_CONTROL_SEARCH_BEFORE_EVAL_STAGE_DEFAULT 0x2 /* RWI-V */
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#define NV_PNVENC_RCOL_BASE(dev) (0x001c8d00+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_RCOL_BASE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_RCOL_BASE_ADDR 31:0 /* RW-UF */
|
|
#define NV_PNVENC_RCOL_MB_NUM(dev) (0x001c8d04+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_RCOL_MB_NUM__SIZE_1 1 /* */
|
|
#define NV_PNVENC_RCOL_MB_NUM_VAL 24:0 /* RW-UF */
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#define NV_PNVENC_RCOL_OFFS(dev) (0x001c8d08+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_RCOL_OFFS__SIZE_1 1 /* */
|
|
#define NV_PNVENC_RCOL_OFFS_OFFS 16:0 /* RW-UF */
|
|
#define NV_PNVENC_RCOL_CTL(dev) (0x001c8d0c+(dev)*16384) /* -W-4A */
|
|
#define NV_PNVENC_RCOL_CTL__SIZE_1 1 /* */
|
|
#define NV_PNVENC_RCOL_CTL_START 0:0 /* -WIUF */
|
|
#define NV_PNVENC_RCOL_CTL_START_INIT 0x0 /* -WI-V */
|
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#define NV_PNVENC_RCOL_CTL_START_ENABLE 0x1 /* -W--V */
|
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#define NV_PNVENC_RCOL_RESET(dev) (0x001c8d10+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_RCOL_RESET__SIZE_1 1 /* */
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#define NV_PNVENC_RCOL_RESET_EN 0:0 /* -WIUF */
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#define NV_PNVENC_RCOL_RESET_EN_INIT 0x0 /* -WI-V */
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#define NV_PNVENC_RCOL_DBG(dev) (0x001c8d14+(dev)*16384) /* R--4A */
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#define NV_PNVENC_RCOL_DBG__SIZE_1 1 /* */
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#define NV_PNVENC_RCOL_DBG_RDMA_RDVLD 0:0 /* R--VF */
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#define NV_PNVENC_RCOL_DBG_RDMA_WNUM 6:1 /* R--VF */
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#define NV_PNVENC_RCOL_DBG_ALLOC_CNT 9:7 /* R--VF */
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#define NV_PNVENC_RCOL_DBG_FULL_CNT 12:10 /* R--VF */
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#define NV_PNVENC_RCOL_DBG_OPKT_VLD 13:13 /* R-IVF */
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#define NV_PNVENC_RCOL_DBG_OPKT_VLD_TRUE 0x1 /* R---V */
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#define NV_PNVENC_RCOL_DBG_OPKT_VLD_FALSE 0x0 /* R-I-V */
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#define NV_PNVENC_RCOL_DBG_OPKT_RDY 14:14 /* R-IVF */
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#define NV_PNVENC_RCOL_DBG_OPKT_RDY_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_RCOL_DBG_OPKT_RDY_FALSE 0x0 /* R---V */
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#define NV_PNVENC_RCOL_DBG_IDLE 15:15 /* R-IVF */
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#define NV_PNVENC_RCOL_DBG_IDLE_RDY_TRUE 0x1 /* R-I-V */
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#define NV_PNVENC_RCOL_DBG_IDLE_RDY_FALSE 0x0 /* R---V */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL(dev) (0x001c8a00+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL_IDC_PROFILE 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL_IDC_PROFILE_DEFAULT 0x0042 /* RWI-V */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL_IDC_LEVEL 15:8 /* RWIUF */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL_IDC_LEVEL_DEFAULT 0x1e /* RWI-V */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL_MVNUM 7:0 /* RWIUF */
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#define NV_PNVENC_MDP_PROFILE_LEVEL_CONTROL_MVNUM_DEFAULT 0x20 /* RWI-V */
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#define NV_PNVENC_MDP_PIC_SIZE(dev) (0x001c8a04+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_PIC_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_PIC_SIZE_WIDTH_IN_MB 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_PIC_SIZE_WIDTH_IN_MB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_PIC_SIZE_HEIGHT_IN_MB 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_PIC_SIZE_HEIGHT_IN_MB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL(dev) (0x001c8a08+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MODE_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MODE_CONTROL_DISABLE_WMVP 31:31 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_DISABLE_WMVP_ON 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_DISABLE_WMVP_OFF 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_DISABLE_WMVP_DEFAULT 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_TU_SEARCH_BASEDON_PUSIZE 30:30 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_TU_SEARCH_BASEDON_PUSIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_TU_SEARCH_BASEDON_PUSIZE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_TU_SEARCH_BASEDON_PUSIZE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_64X64 29:29 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_64X64_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_64X64_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_64X64_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_32X32 28:28 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_32X32_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_32X32_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_32X32_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_16X16 27:27 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_16X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_16X16_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_16X16_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_8X8 26:26 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_8X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_8X8_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_8X8_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_4X4 25:25 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_4X4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_4X4_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H265_INTRA_MODE_4X4_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_IPRED_SEARCH 24:22 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_IPRED_SEARCH_DEFAULT 0x7 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_IPRED_SEARCH_IP1_NONE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_IPRED_SEARCH_IP1_16X16 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_IPRED_SEARCH_IP1_4X4 0x2 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_IPRED_SEARCH_IP1_8X8 0x4 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_SAD_COST_CONTROL 21:21 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_SAD_COST_CONTROL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_SAD_COST_CONTROL_SAD 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_SAD_COST_CONTROL_SATD 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_TRANSFORM_8X8 20:20 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_TRANSFORM_8X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_TRANSFORM_8X8_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_TRANSFORM_8X8_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_IP_MODE_DECISION_CONTROL 19:18 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_IP_MODE_DECISION_CONTROL_MPEB 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_IP_MODE_DECISION_CONTROL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_IP_MODE_DECISION_CONTROL_MDP 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_IP_MODE_DECISION_CONTROL_CUDA 0x2 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_IP_MODE_DECISION_CONTROL_INTER 0x3 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_FINAL_IP_MODE_DECISION 17:17 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_FINAL_IP_MODE_DECISION_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_FINAL_IP_MODE_DECISION_MPEB 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_FINAL_IP_MODE_DECISION_MDP 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_INTRA_DISABLE_MPEB_THRESHOLD 16:1 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_EARLY_INTRA_DISABLE_MPEB_THRESHOLD_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H264_ACCURATE_SKIP_MV 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_CONTROL_H264_ACCURATE_SKIP_MV_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H264_ACCURATE_SKIP_MV_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MODE_CONTROL_H264_ACCURATE_SKIP_MV_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL(dev) (0x001c8a0c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL_MV_COST 16:16 /* RWIUF */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL_MV_COST_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL_MV_COST_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL_MV_COST_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL_MV_BIAS 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_MOTION_VECTOR_COST_CONTROL_MV_BIAS_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_INTRA_BIAS_1(dev) (0x001c8a14+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_INTRA_BIAS_1__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_INTRA_BIAS_1_FAVOR_16X16 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_INTRA_BIAS_1_FAVOR_16X16_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_INTRA_BIAS_1_FAVOR_8X8 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_INTRA_BIAS_1_FAVOR_8X8_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_INTRA_BIAS_2(dev) (0x001c8a18+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_INTRA_BIAS_2__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_INTRA_BIAS_2_FAVOR_4X4 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_INTRA_BIAS_2_FAVOR_4X4_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_INTRA_BIAS_2_FAVOR_MOST_PROB 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_INTRA_BIAS_2_FAVOR_MOST_PROB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_BIAS_1(dev) (0x001c8a1c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MODE_BIAS_1__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MODE_BIAS_1_FAVOR_8X8 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_BIAS_1_FAVOR_8X8_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_BIAS_1_FAVOR_8X16 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_BIAS_1_FAVOR_8X16_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_BIAS_2(dev) (0x001c8a20+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MODE_BIAS_2__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MODE_BIAS_2_FAVOR_16X8 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_BIAS_2_FAVOR_16X8_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_BIAS_2_FAVOR_16X16 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_BIAS_2_FAVOR_16X16_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_BIAS_3(dev) (0x001c8a24+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MODE_BIAS_3__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MODE_BIAS_3_FAVOR_INTRA 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_BIAS_3_FAVOR_INTRA_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MODE_BIAS_3_FAVOR_INTRA_16X16_EARLY 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_MODE_BIAS_3_FAVOR_INTRA_16X16_EARLY_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL(dev) (0x001c8a28+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MB_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MB_CONTROL_FIVE_MINUS_MAX_NUM_MERGE_CAND 31:29 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_FIVE_MINUS_MAX_NUM_MERGE_CAND_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_MIN_CUSIZE 28:27 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_MIN_CUSIZE_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_MIN_CUSIZE_8X8 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_MIN_CUSIZE_16X16 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_MIN_CUSIZE_32X32 0x2 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_MIN_CUSIZE_64X64 0x3 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_CTBSIZE 26:25 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_CTBSIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_CTBSIZE_16X16 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_CTBSIZE_32X32 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_CTBSIZE_64X64 0x2 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_OWN_FIRST_MB_ROW_IN_PIC 24:24 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_OWN_FIRST_MB_ROW_IN_PIC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_OWN_FIRST_MB_ROW_IN_PIC_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_OWN_FIRST_MB_ROW_IN_PIC_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_IPCM 23:23 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_IPCM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_IPCM_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_IPCM_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_WMVPEN 22:22 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_WMVPEN_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_WMVPEN_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_WMVPEN_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_MEONLY 21:21 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_MEONLY_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_MEONLY_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_MEONLY_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE 20:18 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_H264 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_MPEG4 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_VP8 0x2 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_MPEG2 0x3 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_VC1 0x4 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_H265 0x5 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_PREDICTOR_MODE_VP9 0x6 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_ZERO 17:17 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_ZERO_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_ZERO_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_ZERO_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_MEIO_EN 16:16 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_MEIO_EN_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_MEIO_EN_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_MEIO_EN_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_OFS_MODE 10:9 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_OFS_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_OFS_MODE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_OFS_MODE_OPTICALFLOW 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_OFS_MODE_STEREO 0x2 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_INTRA 8:8 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_INTRA_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_INTRA_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_FORCE_INTRA_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_SLICE_TYPE 7:6 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_SLICE_TYPE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MB_CONTROL_SLICE_TYPE_P 0x0 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_SLICE_TYPE_B 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_SLICE_TYPE_I 0x2 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_SLICE_TYPE_IDR 0x3 /* RW--V */
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#define NV_PNVENC_MDP_MB_CONTROL_QP 5:0 /* RWIUF */
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#define NV_PNVENC_MDP_MB_CONTROL_QP_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_SLICE_CTRL(dev) (0x001c8a30+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_SLICE_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_SLICE_CTRL_MODE 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_SLICE_CTRL_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SLICE_CTRL_MODE_MBLK 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SLICE_CTRL_MODE_BYTE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SLICE_CTRL_DEPENDENT_SLICE_ENABLE 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_SLICE_CTRL_DEPENDENT_SLICE_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_PSKIP_BIAS(dev) (0x001c8a38+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_PSKIP_BIAS__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_PSKIP_BIAS_FAVOR_SKIP 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_PSKIP_BIAS_FAVOR_SKIP_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_PSKIP_BIAS_FAVOR_SKIP_ESC_IP 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_PSKIP_BIAS_FAVOR_SKIP_ESC_IP_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_BDIRECT_BIAS(dev) (0x001c8a3c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_BDIRECT_BIAS__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_BDIRECT_BIAS_FAVOR_BDIRECT_ESC_IP 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_BDIRECT_BIAS_FAVOR_BDIRECT_ESC_IP_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_BDIRECT_BIAS_FAVOR_BDIRECT_8X8 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_BDIRECT_BIAS_FAVOR_BDIRECT_8X8_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_LAMBDA_COEF(dev) (0x001c8a40+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_LAMBDA_COEF__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_LAMBDA_COEF_MODE 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_LAMBDA_COEF_MODE_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_LAMBDA_COEF_MV 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_LAMBDA_COEF_MV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA(dev) (0x001c8a48+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DC 2:2 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DC_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DC_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DL 3:3 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DL_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DL_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DR 4:4 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DR_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_DIAG_DR_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_R 5:5 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_R_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_R_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_R_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_D 6:6 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_D_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_D_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_D_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_L 7:7 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_L_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_L_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_VERT_L_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_U 8:8 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_U_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_U_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_HORI_U_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT 9:9 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI 10:10 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DC 11:11 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DC_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DC_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DL 12:12 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DL_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DL_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DR 13:13 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DR_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_DIAG_DR_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_R 14:14 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_R_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_R_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_R_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_D 15:15 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_D_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_D_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_D_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_L 16:16 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_L_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_L_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_VERT_L_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_U 17:17 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_U_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_U_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_8X8_HORI_U_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_VERT 18:18 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_VERT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_VERT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_VERT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_HORI 19:19 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_HORI_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_HORI_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_HORI_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_DC 20:20 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_DC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_DC_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_DC_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_PLANE 21:21 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_PLANE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_PLANE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_16X16_PLANE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DC 22:22 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DC_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DC_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_HORI 23:23 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_HORI_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_HORI_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_HORI_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_VERT 24:24 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_VERT_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_VERT_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_VERT_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_PLANE 25:25 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_PLANE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_PLANE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_PLANE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DECISION 26:26 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DECISION_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DECISION_UANDV 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_CHROMA_DECISION_UONLY 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_FORCE_MOST_PROB_MODE 27:27 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_FORCE_MOST_PROB_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_FORCE_MOST_PROB_MODE_OFF 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_FORCE_MOST_PROB_MODE_ON 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_TM 28:28 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_TM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_TM_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_MODE_4X4_TM_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MULTI_REF_CONFIG(dev) (0x001c8a4c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MULTI_REF_CONFIG__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MULTI_REF_CONFIG_L0_ACTIVE_MINUS1 31:28 /* RWIUF */
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#define NV_PNVENC_MDP_MULTI_REF_CONFIG_L0_ACTIVE_MINUS1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MULTI_REF_CONFIG_L1_ACTIVE_MINUS1 27:24 /* RWIUF */
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#define NV_PNVENC_MDP_MULTI_REF_CONFIG_L1_ACTIVE_MINUS1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_COMMAND_ENCODE(dev) (0x001c8a50+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_COMMAND_ENCODE__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_MB_START 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_MB_START_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_CTB_START 0:0 /* RW-UF */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_CTB_START_DEFAULT 0x0 /* RW--V */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_SLICE_START 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_SLICE_START_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_MB_COUNT 26:2 /* RWIUF */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_MB_COUNT_DEFAULT 0x0000001 /* RWI-V */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_CTB_COUNT 26:2 /* RW-UF */
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#define NV_PNVENC_MDP_COMMAND_ENCODE_CTB_COUNT_DEFAULT 0x0000001 /* RW--V */
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#define NV_PNVENC_MDP_INTEN(dev) (0x001c8a54+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_INTEN__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_INTEN_MB_DONE 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_INTEN_MB_DONE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_INTEN_MB_DONE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_INTEN_MB_DONE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_INTEN_ERR 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_INTEN_ERR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_INTEN_ERR_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_INTEN_ERR_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_INTEN_QPFIFO 2:2 /* RWIUF */
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#define NV_PNVENC_MDP_INTEN_QPFIFO_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_INTEN_QPFIFO_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_INTEN_QPFIFO_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_INTR(dev) (0x001c8a58+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_INTR__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_INTR_MB_DONE 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_INTR_MB_DONE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_INTR_MB_DONE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_INTR_MB_DONE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_INTR_ERR 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_INTR_ERR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_INTR_ERR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_INTR_ERR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_INTR_QPFIFO 2:2 /* RWIUF */
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#define NV_PNVENC_MDP_INTR_QPFIFO_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_INTR_QPFIFO_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_INTR_QPFIFO_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_MB_STATUS(dev) (0x001c8a5c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MDP_MB_STATUS__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_MB_STATUS_MB_POS_Y 25:17 /* R-IUF */
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#define NV_PNVENC_MDP_MB_STATUS_MB_POS_Y_DEFAULT 0x000 /* R-I-V */
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#define NV_PNVENC_MDP_MB_STATUS_MB_POS_X 16:8 /* R-IUF */
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#define NV_PNVENC_MDP_MB_STATUS_MB_POS_X_DEFAULT 0x000 /* R-I-V */
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#define NV_PNVENC_MDP_MB_STATUS_PIPELINE 7:5 /* R-IUF */
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#define NV_PNVENC_MDP_MB_STATUS_PIPELINE_DEFAULT 0x7 /* R-I-V */
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#define NV_PNVENC_MDP_MB_STATUS_PIPELINE_MDP_IDLE 0x1 /* R---V */
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#define NV_PNVENC_MDP_MB_STATUS_PIPELINE_EMD_IDLE 0x2 /* R---V */
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#define NV_PNVENC_MDP_MB_STATUS_PIPELINE_FMD_IDLE 0x4 /* R---V */
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#define NV_PNVENC_MDP_MB_STATUS_ERROR_CODE 4:0 /* R-IUF */
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#define NV_PNVENC_MDP_MB_STATUS_ERROR_CODE_DEFAULT 0x00 /* R-I-V */
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#define NV_PNVENC_MDP_MB_STATUS_ERROR_CODE_ERRVP8 0x01 /* R---V */
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#define NV_PNVENC_MDP_MB_STATUS_ERROR_CODE_H264_DCT_OVERFLOW 0x02 /* R---V */
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#define NV_PNVENC_MDP_SELF_SCALE_L0(dev,i) (0x001c8a64+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MDP_SELF_SCALE_L0__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_SELF_SCALE_L0__SIZE_2 2 /* */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR0 7:0 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR0_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR1 15:8 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR1_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR2 23:16 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR2_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR3 31:24 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L0_SCALEFACTOR3_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_SELF_SCALE_L1(dev,i) (0x001c8a6c+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_MDP_SELF_SCALE_L1__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_SELF_SCALE_L1__SIZE_2 2 /* */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR0 7:0 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR0_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR1 15:8 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR1_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR2 23:16 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR2_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR3 31:24 /* RWISF */
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#define NV_PNVENC_MDP_SELF_SCALE_L1_SCALEFACTOR3_DEFAULT 0x01 /* RWI-V */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL(dev) (0x001c8a74+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_SPATIAL_FLAG 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_SPATIAL_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_SPATIAL_FLAG_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_SPATIAL_FLAG_TRUE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_TEMPORAL_FLAG 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_TEMPORAL_FLAG_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_TEMPORAL_FLAG_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_BDIRECT_CONTROL_DIRECT_TEMPORAL_FLAG_TRUE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_PRED_GEN(dev) (0x001c8a78+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_PRED_GEN__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_PRED_GEN_SPREADTHR 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_PRED_GEN_SPREADTHR_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_PRED_GEN_DISTTHR 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_PRED_GEN_DISTTHR_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_DEBUG0(dev) (0x001c8a7c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_DEBUG0__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_DEBUG0_ENC_MBX 8:0 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG0_ENC_MBX_INIT 0x000 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG0_ENC_MBY 17:9 /* RWIUF */
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#define NV_PNVENC_MDP_DEBUG0_ENC_MBY_INIT 0x000 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG0_FMD_MBTYPE 19:18 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG0_FMD_MBTYPE_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG0_FMD_MVMODE 21:20 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG0_FMD_MVMODE_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART0_STATUS 23:22 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART0_STATUS_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART1_STATUS 25:24 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART1_STATUS_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART2_STATUS 27:26 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART2_STATUS_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART3_STATUS 29:28 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG0_FMD_PART3_STATUS_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1(dev) (0x001c8a80+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_DEBUG1__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_WINNER_PVLD 0:0 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_WINNER_PVLD_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_WINNER_PRDY 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_WINNER_PRDY_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_PRED_PVLD 2:2 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_PRED_PVLD_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_PRED_PRDY 3:3 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2ME_PRED_PRDY_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2MPEB_CMD_PVLD 4:4 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2MPEB_CMD_PVLD_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2MPEB_CMD_PRDY 5:5 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2MPEB_CMD_PRDY_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2HIST_PVLD 6:6 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2HIST_PVLD_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2HIST_PRDY 7:7 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2HIST_PRDY_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2WMVP_PVLD 8:8 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2WMVP_PVLD_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP2WMVP_PRDY 9:9 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP2WMVP_PRDY_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP_EMD_IDLE 10:10 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP_EMD_IDLE_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_MDP_FMD_IDLE 11:11 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_MDP_FMD_IDLE_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_INTRA_SATD_PENDING 12:12 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_INTRA_SATD_PENDING_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_DEBUG1_SCORE8X8_PENDING 13:13 /* R-IUF */
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#define NV_PNVENC_MDP_DEBUG1_SCORE8X8_PENDING_INIT 0x0 /* R-I-V */
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#define NV_PNVENC_MDP_VP8_NEARMV_NEARESTMV_BIAS(dev) (0x001c8a84+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_NEARMV_NEARESTMV_BIAS__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_VP8_NEARMV_NEARESTMV_BIAS_FAVOR_NEARESTMV 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_NEARMV_NEARESTMV_BIAS_FAVOR_NEARESTMV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_NEARMV_NEARESTMV_BIAS_FAVOR_NEARMV 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_NEARMV_NEARESTMV_BIAS_FAVOR_NEARMV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_NEWMV_ZEROMV_BIAS(dev) (0x001c8a88+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_NEWMV_ZEROMV_BIAS__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_VP8_NEWMV_ZEROMV_BIAS_FAVOR_ZEROMV 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_NEWMV_ZEROMV_BIAS_FAVOR_ZEROMV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_NEWMV_ZEROMV_BIAS_FAVOR_NEWMV 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_NEWMV_ZEROMV_BIAS_FAVOR_NEWMV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_LEFT4X4MV_ABOVE4X4MV_BIAS(dev) (0x001c8a8c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_LEFT4X4MV_ABOVE4X4MV_BIAS__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_VP8_LEFT4X4MV_ABOVE4X4MV_BIAS_FAVOR_ABOVE4X4MV 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_LEFT4X4MV_ABOVE4X4MV_BIAS_FAVOR_ABOVE4X4MV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_LEFT4X4MV_ABOVE4X4MV_BIAS_FAVOR_LEFT4X4MV 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_LEFT4X4MV_ABOVE4X4MV_BIAS_FAVOR_LEFT4X4MV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_NEW4X4MV_ZERO4X4MV_BIAS(dev) (0x001c8a90+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_NEW4X4MV_ZERO4X4MV_BIAS__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_VP8_NEW4X4MV_ZERO4X4MV_BIAS_FAVOR_ZERO4X4MV 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_NEW4X4MV_ZERO4X4MV_BIAS_FAVOR_ZERO4X4MV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_NEW4X4MV_ZERO4X4MV_BIAS_FAVOR_NEW4X4MV 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_NEW4X4MV_ZERO4X4MV_BIAS_FAVOR_NEW4X4MV_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG(dev) (0x001c8a94+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_PIC 18:17 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_PIC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_PIC_LAST 0x1 /* RW--V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_PIC_GOLDEN 0x2 /* RW--V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_PIC_ALTREF 0x3 /* RW--V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_SIGN_ARF 16:16 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_SIGN_ARF_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_SIGN_GF 15:15 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_REFFRAME_SIGN_GF_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_ZEROMV 14:14 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_ZEROMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_TOP_RIGHTMV 13:13 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_TOP_RIGHTMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_TOP_LEFTMV 12:12 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_TOP_LEFTMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_LEFT_BOTTOMMV 11:11 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_LEFT_BOTTOMMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_LEFT_TOPMV 10:10 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_LEFT_TOPMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_NEARMV 9:9 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_NEARMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_NEARESTMV 8:8 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EXPLICIT_EVAL_NEARESTMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEW4X4MV 7:7 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEW4X4MV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_ZERO4X4MV 6:6 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_ZERO4X4MV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_LEFT4X4MV 5:5 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_LEFT4X4MV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_ABOVE4X4MV 4:4 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_ABOVE4X4MV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEWMV 3:3 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEWMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_ZEROMV 2:2 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_ZEROMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEARMV 1:1 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEARMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEARESTMV 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_MODE_CONFIG_EVAL_NEARESTMV_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_LAMBDA(dev) (0x001c8a98+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_LAMBDA__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG3 31:24 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG2 23:16 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG1 15:8 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG0 7:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_LAMBDA_SEG0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_SEGMENTID(dev) (0x001c8a9c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_SEGMENTID__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_VP8_SEGMENTID_IDX 1:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_SEGMENTID_IDX_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_FRAME_CYCLE_CNT(dev) (0x001c8aa0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_FRAME_CYCLE_CNT__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_FRAME_CYCLE_CNT_CNT 31:0 /* RWIUF */
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#define NV_PNVENC_MDP_FRAME_CYCLE_CNT_CNT_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MDP_FRAME_CYCLE_CNT_CNT_START 0x00000000 /* RW--V */
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#define NV_PNVENC_MDP_FRAME_CYCLE_CNT_CNT_STOP 0x00000001 /* RW--V */
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#define NV_PNVENC_MDP_FRAME_CYCLE_CNT_CNT_RST 0x00000002 /* RW--V */
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#define NV_PNVENC_IP_VER(dev) (0x001c8aa4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_IP_VER__SIZE_1 1 /* */
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#define NV_PNVENC_IP_VER_DEV 7:0 /* RWIVF */
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#define NV_PNVENC_IP_VER_DEV_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_IP_VER_ECO 15:8 /* RWIVF */
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#define NV_PNVENC_IP_VER_ECO_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_IP_VER_MINOR 23:16 /* RWIVF */
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#define NV_PNVENC_IP_VER_MINOR_INIT 0x02 /* RWI-V */
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#define NV_PNVENC_IP_VER_MAJOR 31:24 /* RWIVF */
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#define NV_PNVENC_IP_VER_MAJOR_INIT 0x07 /* RWI-V */
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#define NV_PNVENC_CAP0(dev) (0x001c8aa8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_CAP0__SIZE_1 1 /* */
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#define NV_PNVENC_CAP0_H264 0:0 /* R-IVF */
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#define NV_PNVENC_CAP0_H264_ABSENT 0x0 /* R---V */
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#define NV_PNVENC_CAP0_H264_PRESENT 0x1 /* R-I-V */
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#define NV_PNVENC_CAP0_VP8 1:1 /* R-IVF */
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#define NV_PNVENC_CAP0_VP8_ABSENT 0x0 /* R---V */
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#define NV_PNVENC_CAP0_VP8_PRESENT 0x1 /* R-I-V */
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#define NV_PNVENC_CAP0_MPEG2 2:2 /* R-IVF */
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#define NV_PNVENC_CAP0_MPEG2_ABSENT 0x0 /* R---V */
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#define NV_PNVENC_CAP0_MPEG2_PRESENT 0x1 /* R-I-V */
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#define NV_PNVENC_CAP0_MPEG4 3:3 /* R-IVF */
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#define NV_PNVENC_CAP0_MPEG4_ABSENT 0x0 /* R---V */
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#define NV_PNVENC_CAP0_MPEG4_PRESENT 0x1 /* R-I-V */
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#define NV_PNVENC_CAP0_VC1 4:4 /* R-IVF */
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#define NV_PNVENC_CAP0_VC1_ABSENT 0x0 /* R---V */
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#define NV_PNVENC_CAP0_VC1_PRESENT 0x1 /* R-I-V */
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#define NV_PNVENC_CAP0_TEB 5:5 /* R-IVF */
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#define NV_PNVENC_CAP0_TEB_DISABLED 0x0 /* R-I-V */
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#define NV_PNVENC_CAP0_TEB_ENABLED 0x1 /* R---V */
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#define NV_PNVENC_CAP0_BL16X2 6:6 /* R-IVF */
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#define NV_PNVENC_CAP0_BL16X2_DISABLED 0x0 /* R-I-V */
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#define NV_PNVENC_CAP0_BL16X2_ENABLED 0x1 /* R---V */
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#define NV_PNVENC_CAP0_TILED 7:7 /* R-IVF */
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#define NV_PNVENC_CAP0_TILED_DISABLED 0x0 /* R-I-V */
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#define NV_PNVENC_CAP0_TILED_ENABLED 0x1 /* R---V */
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#define NV_PNVENC_CAP0_RESERVED 31:8 /* R-IVF */
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#define NV_PNVENC_CAP0_RESERVED_INIT 0x000000 /* R-I-V */
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#define NV_PNVENC_CAP1(dev) (0x001c8aac+(dev)*16384) /* R--4A */
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#define NV_PNVENC_CAP1__SIZE_1 1 /* */
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#define NV_PNVENC_CAP1_RESERVED 31:0 /* R-IVF */
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#define NV_PNVENC_CAP1_RESERVED_INIT 0x00000000 /* R-I-V */
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#define NV_PNVENC_CAP2(dev) (0x001c8ab0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_CAP2__SIZE_1 1 /* */
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#define NV_PNVENC_CAP2_RESERVED 31:0 /* R-IVF */
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#define NV_PNVENC_CAP2_RESERVED_INIT 0x00000000 /* R-I-V */
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#define NV_PNVENC_CAP3(dev) (0x001c8ab4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_CAP3__SIZE_1 1 /* */
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#define NV_PNVENC_CAP3_RESERVED 31:0 /* R-IVF */
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#define NV_PNVENC_CAP3_RESERVED_INIT 0x00000000 /* R-I-V */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_1(dev) (0x001c8ab8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_1__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_1_INTRA 10:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_1_INTRA_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_1_INTER_LAST 21:11 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_1_INTER_LAST_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_2(dev) (0x001c8abc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_2__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_2_INTER_GOLDEN 10:0 /* RWIUF */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_2_INTER_GOLDEN_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_2_INTER_ALTREF 21:11 /* RWIUF */
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|
#define NV_PNVENC_MDP_VP8_REF_FRAME_COST_2_INTER_ALTREF_DEFAULT 0x000 /* RWI-V */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_X(dev) (0x001c8ac0+(dev)*16384) /* R--4A */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_X__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_STAT_SUM_MV_X_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_MDP_STAT_SUM_MV_X_VALUE_DEFAULT 0x00000000 /* R-I-V */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_Y(dev) (0x001c8ac4+(dev)*16384) /* R--4A */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_Y__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_Y_VALUE 31:0 /* R-IUF */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_Y_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_MDP_STAT_SUM_MV_COUNT(dev) (0x001c8ac8+(dev)*16384) /* R--4A */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_COUNT__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_STAT_SUM_MV_COUNT_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_MDP_STAT_SUM_MV_COUNT_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_MDP_STAT_TOTAL_INTER_COST(dev) (0x001c8acc+(dev)*16384) /* R--4A */
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#define NV_PNVENC_MDP_STAT_TOTAL_INTER_COST__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_STAT_TOTAL_INTER_COST_VALUE 31:0 /* R-IUF */
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#define NV_PNVENC_MDP_STAT_TOTAL_INTER_COST_VALUE_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_MDP_INTRA_BIAS_3(dev) (0x001c8ad0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_INTRA_BIAS_3__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_INTRA_BIAS_3_FAVOR_32X32 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_INTRA_BIAS_3_FAVOR_32X32_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_INTRA_BIAS_3_FAVOR_64X64 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_INTRA_BIAS_3_FAVOR_64X64_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_0(dev) (0x001c8ad4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_0__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_0_FAVOR_2NX2N 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_0_FAVOR_2NX2N_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_0_FAVOR_2NXN 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_0_FAVOR_2NXN_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_1(dev) (0x001c8ad8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_1__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_1_FAVOR_NX2N 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_1_FAVOR_NX2N_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_1_FAVOR_NXN 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_1_FAVOR_NXN_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_2(dev) (0x001c8adc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_2__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_2_FAVOR_2NXNU 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_2_FAVOR_2NXNU_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_2_FAVOR_2NXND 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_2_FAVOR_2NXND_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_3(dev) (0x001c8ae0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_3__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_3_FAVOR_NLX2N 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_3_FAVOR_NLX2N_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_3_FAVOR_NRX2N 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_H265_INTER_MODE_BIAS_3_FAVOR_NRX2N_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_0(dev) (0x001c8ae4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_0__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_0_8X8 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_0_8X8_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_0_16X16 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_0_16X16_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_1(dev) (0x001c8ae8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_1__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_1_32X32 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_1_32X32_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_1_64X64 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_H265_CU_SIZE_BIAS_1_64X64_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION(dev) (0x001c8aec+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_ENABLE 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_FACTOR 6:1 /* RWIUF */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_FACTOR_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_TYPE 9:7 /* RWIUF */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_TYPE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_TYPE_NONE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_TYPE_16X16 0x1 /* RW--V */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_TYPE_4X4 0x2 /* RW--V */
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#define NV_PNVENC_MDP_IP1_EARLY_TERMINATION_TYPE_8X8 0x3 /* RW--V */
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#define NV_PNVENC_MDP_QPFIFO(dev) (0x001c8af0+(dev)*16384) /* RW-4A */
|
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#define NV_PNVENC_MDP_QPFIFO__SIZE_1 1 /* */
|
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#define NV_PNVENC_MDP_QPFIFO_INT_THRESHOLD 5:0 /* RWIUF */
|
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#define NV_PNVENC_MDP_QPFIFO_INT_THRESHOLD_DEFAULT 0x00 /* RWI-V */
|
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#define NV_PNVENC_MDP_QPFIFO_AVAILABLE_SIZE 11:6 /* R-IUF */
|
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#define NV_PNVENC_MDP_QPFIFO_AVAILABLE_SIZE_DEFAULT 0x3c /* R-I-V */
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#define NV_PNVENC_MDP_LAMBDA(dev) (0x001c8af4+(dev)*16384) /* RW-4A */
|
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#define NV_PNVENC_MDP_LAMBDA__SIZE_1 1 /* */
|
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#define NV_PNVENC_MDP_LAMBDA_SSD 15:0 /* RWIUF */
|
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#define NV_PNVENC_MDP_LAMBDA_SSD_DEFAULT 0x0000 /* RWI-V */
|
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#define NV_PNVENC_MDP_LAMBDA_SATD 31:16 /* RWIUF */
|
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#define NV_PNVENC_MDP_LAMBDA_SATD_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG(dev) (0x001c8af8+(dev)*16384) /* RW-4A */
|
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU4X4_ENABLE 0:0 /* RWIUF */
|
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU4X4_ENABLE_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU8X8_ENABLE 1:1 /* RWIUF */
|
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU8X8_ENABLE_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU16X16_ENABLE 2:2 /* RWIUF */
|
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU16X16_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU32X32_ENABLE 3:3 /* RWIUF */
|
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG_TU32X32_ENABLE_DEFAULT 0x0 /* RWI-V */
|
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG_CHROMA_MODE_ENABLE 8:4 /* RWIUF */
|
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#define NV_PNVENC_MDP_H265_INTRA_CONFIG_CHROMA_MODE_ENABLE_DEFAULT 0x00 /* RWI-V */
|
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#define NV_PNVENC_H265_INTRA_LUMA4X4_MODE_ENABLE(dev) (0x001c8afc+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_H265_INTRA_LUMA4X4_MODE_ENABLE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_H265_INTRA_LUMA4X4_MODE_ENABLE_VALUE 31:0 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA4X4_MODE_ENABLE_VALUE_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA8X8_MODE_ENABLE(dev) (0x001c8b00+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_H265_INTRA_LUMA8X8_MODE_ENABLE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_H265_INTRA_LUMA8X8_MODE_ENABLE_VALUE 31:0 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA8X8_MODE_ENABLE_VALUE_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA16X16_MODE_ENABLE(dev) (0x001c8b04+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_H265_INTRA_LUMA16X16_MODE_ENABLE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_H265_INTRA_LUMA16X16_MODE_ENABLE_VALUE 31:0 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA16X16_MODE_ENABLE_VALUE_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA32X32_MODE_ENABLE(dev) (0x001c8b08+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_H265_INTRA_LUMA32X32_MODE_ENABLE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_H265_INTRA_LUMA32X32_MODE_ENABLE_VALUE 31:0 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA32X32_MODE_ENABLE_VALUE_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA64X64_MODE_ENABLE(dev) (0x001c8b0c+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_H265_INTRA_LUMA64X64_MODE_ENABLE__SIZE_1 1 /* */
|
|
#define NV_PNVENC_H265_INTRA_LUMA64X64_MODE_ENABLE_VALUE 31:0 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA64X64_MODE_ENABLE_VALUE_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS(dev) (0x001c8b10+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS__SIZE_1 1 /* */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA4X4 2:0 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA4X4_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA8X8 5:3 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA8X8_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA16X16 8:6 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA16X16_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA32X32 11:9 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA32X32_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA64X64 14:12 /* RWIUF */
|
|
#define NV_PNVENC_H265_INTRA_LUMA_ENABLE_LEFTBITS_LUMA64X64_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_MDP_H265_TRANSFORM_SKIP_BIAS(dev) (0x001c8b14+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_MDP_H265_TRANSFORM_SKIP_BIAS__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_H265_TRANSFORM_SKIP_BIAS_VALUE 15:0 /* RWIUF */
|
|
#define NV_PNVENC_MDP_H265_TRANSFORM_SKIP_BIAS_VALUE_DEFAULT 0x0000 /* RWI-V */
|
|
#define NV_PNVENC_MDP_BIT_DEPTH_MINUS_8(dev) (0x001c8b18+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_MDP_BIT_DEPTH_MINUS_8__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_BIT_DEPTH_MINUS_8_VALUE 3:0 /* RWIUF */
|
|
#define NV_PNVENC_MDP_BIT_DEPTH_MINUS_8_VALUE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_BIT_DEPTH_MINUS_8_VALUE_MAIN10 0x2 /* RW--V */
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#define NV_PNVENC_MDP_AQ_QP_RANGE(dev) (0x001c8b1c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_AQ_QP_RANGE__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_AQ_QP_RANGE_MIN 6:0 /* RWIUF */
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#define NV_PNVENC_MDP_AQ_QP_RANGE_MIN_DEAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_AQ_QP_RANGE_MAX 13:7 /* RWIUF */
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#define NV_PNVENC_MDP_AQ_QP_RANGE_MAX_DEAULT 0x00 /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL(dev) (0x001c8b20+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_ENABLE 0:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_ENABLE_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP1 6:1 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP1_DEFAULT 0x23 /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP2 12:7 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP2_DEFAULT 0x20 /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP3 18:13 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP3_DEFAULT 0x1c /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP4 24:19 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP4_DEFAULT 0x1a /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP5 30:25 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_CONTROL_QP5_DEFAULT 0x17 /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP1(dev) (0x001c8b24+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP1__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP1_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP1_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP1_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP1_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP2(dev) (0x001c8b28+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP2__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP2_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP2_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP2_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP2_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP3(dev) (0x001c8b2c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP3__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP3_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP3_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP3_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP3_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP4(dev) (0x001c8b30+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP4__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP4_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP4_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP4_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP4_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP5(dev) (0x001c8b34+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP5__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP5_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP5_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP5_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_SOG_QP5_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP1(dev) (0x001c8b38+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP1__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP1_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP1_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP1_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP1_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP2(dev) (0x001c8b3c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP2__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP2_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP2_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP2_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP2_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP3(dev) (0x001c8b40+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP3__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP3_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP3_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP3_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP3_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP4(dev) (0x001c8b44+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP4__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP4_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP4_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP4_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP4_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP5(dev) (0x001c8b48+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP5__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP5_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP5_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP5_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_DOV_QP5_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP1(dev) (0x001c8b4c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP1__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP1_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP1_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP1_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP1_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP2(dev) (0x001c8b50+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP2__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP2_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP2_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP2_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP2_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP3(dev) (0x001c8b54+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP3__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP3_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP3_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP3_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP3_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP4(dev) (0x001c8b58+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP4__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP4_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP4_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP4_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP4_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP5(dev) (0x001c8b5c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP5__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP5_MIN 15:0 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP5_MIN_DEFAULT 0xffff /* RWI-V */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP5_MAX 31:16 /* RWIUF */
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#define NV_PNVENC_MDP_CUET_32X32_16X16_COSTDIFF_QP5_MAX_DEFAULT 0xfffe /* RWI-V */
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#define NV_PNVENC_MDP_CFG(dev) (0x001c8b60+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_CFG__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_CFG_RDO_LEVEL 2:0 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_RDO_LEVEL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU8 3:3 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU16 4:4 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU32 5:5 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU32_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU64 6:6 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_SKIP_EVALUATE_ENABLE_CU64_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_TU_SEARCH_NUM_CU16 9:7 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_TU_SEARCH_NUM_CU16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_TU_SEARCH_NUM_CU32 12:10 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_TU_SEARCH_NUM_CU32_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_TU_SEARCH_NUM_CU64 15:13 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_TU_SEARCH_NUM_CU64_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_LUMA_RESIDUAL_ZERO_EVAL 17:16 /* RWIUF */
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#define NV_PNVENC_MDP_CFG_LUMA_RESIDUAL_ZERO_EVAL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_INTRA_4X4_EARLY_TERMINATE 18:18 /* RWIVF */
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#define NV_PNVENC_MDP_CFG_INTRA_4X4_EARLY_TERMINATE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_CFG_INTRA_4X4_EARLY_TERMINATE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MDP_CFG_INTRA_4X4_EARLY_TERMINATE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT(dev) (0x001c8b64+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_4X4 3:0 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_4X4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_8X8 7:4 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_8X8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_16X16 11:8 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_16X16_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_32X32 15:12 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_32X32_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_64X64 19:16 /* RWIUF */
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#define NV_PNVENC_MDP_SET_MPEB_INTRA_SSD_CNT_64X64_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY(dev) (0x001c8b68+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY__SIZE_1 1 /* */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_7 31:31 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA7 30:28 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA7_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_6 27:27 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA6 26:24 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA6_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_5 23:23 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA5 22:20 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_4 19:19 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA4 18:16 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_3 15:15 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA3 14:12 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_2 11:11 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA2 10:8 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_1 7:7 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA1 6:4 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA1_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_0 3:3 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST0_POCENTRY_LONG_TERM_0_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA0 2:0 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST0_POCENTRY_DATA0_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY(dev) (0x001c8b6c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_7 31:31 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_7_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA7 30:28 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA7_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_6 27:27 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_6_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA6 26:24 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA6_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_5 23:23 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_5_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA5 22:20 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA5_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_4 19:19 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_4_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA4 18:16 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA4_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_3 15:15 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_3_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA3 14:12 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_2 11:11 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA2 10:8 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_1 7:7 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA1 6:4 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_0 3:3 /* RWIUF */
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#define NV_PNVENC_MDP_REFLIST1_POCENTRY_LONG_TERM_0_DEFAULT 0x0 /* RWI-V */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA0 2:0 /* RWIUF */
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|
#define NV_PNVENC_MDP_REFLIST1_POCENTRY_DATA0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_MVP_SCALE(dev) (0x001c8b70+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_MVP_SCALE__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_MVP_SCALE_FACTOR0 12:0 /* RW-SF */
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#define NV_PNVENC_MDP_MVP_SCALE_SAME_POC_0 15:15 /* RW-SF */
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#define NV_PNVENC_MDP_MVP_SCALE_FACTOR1 28:16 /* RW-SF */
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#define NV_PNVENC_MDP_MVP_SCALE_SAME_POC_1 31:31 /* RW-SF */
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#define NV_PNVENC_MDP_OFS_SEG_CONTRL(dev) (0x001c8b74+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_OFS_SEG_CONTRL__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_OFS_SEG_CONTRL_THR 7:0 /* RW-UF */
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#define NV_PNVENC_MDP_OFS_SEG_CONTRL_P2 15:8 /* RW-UF */
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#define NV_PNVENC_MDP_OFS_SEG_CONTRL_ENABLE 16:16 /* RWIUF */
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#define NV_PNVENC_MDP_OFS_SEG_CONTRL_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_OFS_SEG_CONTRL_BACKGROUND_SEG 21:17 /* RW-UF */
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#define NV_PNVENC_MDP_SKIP_BIAS(dev) (0x001c8b78+(dev)*16384) /* RW-4A */
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|
#define NV_PNVENC_MDP_SKIP_BIAS__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_SKIP_BIAS_VAL 15:0 /* RWIUF */
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|
#define NV_PNVENC_MDP_SKIP_BIAS_VAL_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MDP_OFS_MVX_RANGE_CONTRL(dev) (0x001c8b7c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MDP_OFS_MVX_RANGE_CONTRL__SIZE_1 1 /* */
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|
#define NV_PNVENC_MDP_OFS_MVX_RANGE_CONTRL_VAL 1:0 /* RWIUF */
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|
#define NV_PNVENC_MDP_OFS_MVX_RANGE_CONTRL_VAL_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SSIM_CONTROL(dev) (0x001c8b80+(dev)*16384) /* RW-4A */
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|
#define NV_PNVENC_MDP_SSIM_CONTROL__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_SSIM_CONTROL_LAMBDA 15:0 /* RWIUF */
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|
#define NV_PNVENC_MDP_SSIM_CONTROL_LAMBDA_DEFAULT 0x0000 /* RWI-V */
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|
#define NV_PNVENC_MDP_SSIM_CONTROL_SSIM_RDO 16:16 /* RWIUF */
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|
#define NV_PNVENC_MDP_SSIM_CONTROL_SSIM_RDO_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MDP_SSIM_CONTROL_CALC_SSIM 17:17 /* RWIUF */
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#define NV_PNVENC_MDP_SSIM_CONTROL_CALC_SSIM_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_BOOT_42(dev) (0x001c8b84+(dev)*16384) /* R--4A */
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|
#define NV_PNVENC_BOOT_42__SIZE_1 1 /* */
|
|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP 4:0 /* R-XVF */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_0 0x00 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_1 0x01 /* R---V */
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#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_2 0x02 /* R---V */
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#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_3 0x03 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_4 0x04 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_5 0x05 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_6 0x06 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_7 0x07 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_8 0x08 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_9 0x09 /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_A 0x0a /* R---V */
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#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_B 0x0b /* R---V */
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|
#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_C 0x0c /* R---V */
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#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_D 0x0d /* R---V */
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#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_E 0x0e /* R---V */
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#define NV_PNVENC_BOOT_42_DEVICE_ID_STRAP_F 0x0f /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_0 0x0 /* R---V */
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|
#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_1 0x1 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_2 0x2 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_3 0x3 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_4 0x4 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_5 0x5 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_6 0x6 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_7 0x7 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_8 0x8 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_9 0x9 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_A 0xa /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_B 0xb /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_C 0xc /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_D 0xd /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_E 0xe /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_EXTENDED_REVISION_F 0xf /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_1 0x1 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_2 0x2 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_3 0x3 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_4 0x4 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_5 0x5 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_6 0x6 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_7 0x7 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_8 0x8 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_9 0x9 /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_10 0xa /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_11 0xb /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_12 0xc /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_13 0xd /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_14 0xe /* R---V */
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#define NV_PNVENC_BOOT_42_MINOR_REVISION_15 0xf /* R---V */
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#define NV_PNVENC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
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#define NV_PNVENC_BOOT_42_MAJOR_REVISION_A 0xa /* R---V */
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#define NV_PNVENC_BOOT_42_MAJOR_REVISION_B 0xb /* R---V */
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#define NV_PNVENC_BOOT_42_MAJOR_REVISION_C 0xc /* R---V */
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#define NV_PNVENC_BOOT_42_MAJOR_REVISION_D 0xd /* R---V */
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#define NV_PNVENC_BOOT_42_MAJOR_REVISION_E 0xe /* R---V */
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#define NV_PNVENC_BOOT_42_MAJOR_REVISION_F 0xf /* R---V */
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#define NV_PNVENC_BOOT_42_IMPLEMENTATION 23:20 /* R-XVF */
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#define NV_PNVENC_BOOT_42_IMPLEMENTATION_0 0x0 /* R---V */
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#define NV_PNVENC_BOOT_42_IMPLEMENTATION_1 0x1 /* R---V */
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#define NV_PNVENC_BOOT_42_IMPLEMENTATION_2 0x2 /* R---V */
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#define NV_PNVENC_BOOT_42_IMPLEMENTATION_3 0x3 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_4 0x4 /* R---V */
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|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_5 0x5 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_6 0x6 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_7 0x7 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_8 0x8 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_9 0x9 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_A 0xa /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_B 0xb /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_C 0xc /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_D 0xd /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_E 0xe /* R---V */
|
|
#define NV_PNVENC_BOOT_42_IMPLEMENTATION_F 0xf /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE 28:24 /* R-XVF */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV10 0x01 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV20 0x02 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV30 0x03 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV40 0x04 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV50 0x05 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV60 0x06 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV70 0x07 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV80 0x08 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_G80 0x08 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV90 0x09 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_G90 0x09 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_NV100 0x0a /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_G100 0x0a /* R---V */
|
|
#define NV_PNVENC_BOOT_42_ARCHITECTURE_GF100 0x0c /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_TU102 0x162 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_TU104 0x164 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_TU105 0x165 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_TU106 0x166 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_TU107 0x167 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_TU117 0x167 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_TU116 0x168 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA100 0x170 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA000 0x171 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA102 0x172 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA102F 0x17f /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA103 0x173 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA104 0x174 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA106 0x176 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA107 0x177 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GA114 0x179 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GH100 0x180 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_GH100_SOC 0x181 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_G000_SOC 0x1e1 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_CHIP_ID_G000 0x1e0 /* R---V */
|
|
#define NV_PNVENC_BOOT_42_RSVD 31:29 /* R-XVF */
|
|
#define NV_PNVENC_OPT_FUSE_UCODE_NVENC_REV(dev) (0x001c8b88+(dev)*16384) /* R--4A */
|
|
#define NV_PNVENC_OPT_FUSE_UCODE_NVENC_REV__SIZE_1 1 /* */
|
|
#define NV_PNVENC_OPT_FUSE_UCODE_NVENC_REV_ID 3:0 /* R-XVF */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L0(dev) (0x001c8b8c+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L0__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L0_VAL 31:0 /* RWIUF */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L0_VAL_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L1(dev) (0x001c8b90+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L1__SIZE_1 1 /* */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L1_VAL 31:0 /* RWIUF */
|
|
#define NV_PNVENC_MDP_STAT_BEST_SATD_L1_VAL_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_PNVENC_HIST_CFG(dev) (0x001c8e00+(dev)*16384) /* RW-4A */
|
|
#define NV_PNVENC_HIST_CFG__SIZE_1 1 /* */
|
|
#define NV_PNVENC_HIST_CFG_MDPDEL 0:0 /* RWIVF */
|
|
#define NV_PNVENC_HIST_CFG_MDPDEL_FALSE 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HIST_CFG_MDPDEL_TRUE 0x1 /* RW--V */
|
|
#define NV_PNVENC_HIST_CFG_MEDEL 1:1 /* RWIVF */
|
|
#define NV_PNVENC_HIST_CFG_MEDEL_FALSE 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HIST_CFG_MEDEL_TRUE 0x1 /* RW--V */
|
|
#define NV_PNVENC_HIST_CFG_MPEBDEL 2:2 /* RWIVF */
|
|
#define NV_PNVENC_HIST_CFG_MPEBDEL_FALSE 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HIST_CFG_MPEBDEL_TRUE 0x1 /* RW--V */
|
|
#define NV_PNVENC_HIST_CFG_MPECDEL 3:3 /* RWIVF */
|
|
#define NV_PNVENC_HIST_CFG_MPECDEL_FALSE 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HIST_CFG_MPECDEL_TRUE 0x1 /* RW--V */
|
|
#define NV_PNVENC_HIST_CFG_CTBSIZE 5:4 /* RWIUF */
|
|
#define NV_PNVENC_HIST_CFG_CTBSIZE_DEFAULT 0x0 /* RWI-V */
|
|
#define NV_PNVENC_HIST_CFG_CTBSIZE_16X16 0x0 /* RW--V */
|
|
#define NV_PNVENC_HIST_CFG_CTBSIZE_32X32 0x1 /* RW--V */
|
|
#define NV_PNVENC_HIST_CFG_CTBSIZE_64X64 0x2 /* RW--V */
|
|
#define NV_PNVENC_HIST_CFG_PICWIDTHINMBS 18:6 /* RW-VF */
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#define NV_PNVENC_HIST_CFG_PICHEIGHTINMBS 31:19 /* RW-VF */
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#define NV_PNVENC_HIST_CTL(dev) (0x001c8e04+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_HIST_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_CTL_ENABLE 0:0 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_ENABLE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_RST_HISTW 1:1 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_RST_HISTW_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_RST_HISTW_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_RST_HISTW_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_RST_HISTR 2:2 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_RST_HISTR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_RST_HISTR_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_RST_HISTR_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_ME_IO_ENABLE 4:4 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_ME_IO_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_ME_IO_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_ME_IO_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_ICC_IO_ENABLE 5:5 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_ICC_IO_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_ICC_IO_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_ICC_IO_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_DBLK_IO_ENABLE 6:6 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_DBLK_IO_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_DBLK_IO_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_DBLK_IO_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_IPRED_IO_ENABLE 7:7 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_IPRED_IO_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_IPRED_IO_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_IPRED_IO_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_MPEC_IO_ENABLE 8:8 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_MPEC_IO_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_MPEC_IO_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_MPEC_IO_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_MDP_IO_ENABLE 9:9 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_MDP_IO_ENABLE_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_MDP_IO_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_MDP_IO_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_MEONLY 10:10 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_MEONLY_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_MEONLY_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_MEONLY_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_CODEC_ID_H265 11:11 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_CODEC_ID_H265_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_CODEC_ID_H265_DIS 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_CODEC_ID_H265_EN 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_OFS_MODE 16:15 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_OFS_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_OFS_MODE_DIS 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_OFS_MODE_OF 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_OFS_MODE_STEREO 0x2 /* RW--V */
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#define NV_PNVENC_HIST_CTL_OWN_FIRST_MB_ROW_IN_PIC 17:17 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_OWN_FIRST_MB_ROW_IN_PIC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_OWN_FIRST_MB_ROW_IN_PIC_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_OWN_FIRST_MB_ROW_IN_PIC_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_OWN_LAST_MB_ROW_IN_PIC 18:18 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_OWN_LAST_MB_ROW_IN_PIC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_HIST_CTL_OWN_LAST_MB_ROW_IN_PIC_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_HIST_CTL_OWN_LAST_MB_ROW_IN_PIC_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_HIST_CTL_START_ADDR_OFFSET 20:19 /* RWIVF */
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#define NV_PNVENC_HIST_CTL_START_ADDR_OFFSET_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_HIST_BUF_START(dev) (0x001c8e08+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_HIST_BUF_START__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_BUF_START_ADDR 31:0 /* RWXVF */
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#define NV_PNVENC_HIST_BUF_SIZE(dev) (0x001c8e0c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_HIST_BUF_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_BUF_SIZE_SIZE 24:0 /* RWXVF */
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#define NV_PNVENC_HIST_DBG0(dev) (0x001c8e10+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG0__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG0_MDP_RD_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG0_MDP_RD_HWVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG0_MDP_RD_HOVLD 5:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG0_MDP_RD_RDREQ 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG0_MDP_RD_LDREQ 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG0_MDP_RD_COLCNT 20:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG0_MDP_RD_ROWCNT 31:21 /* R-XVF */
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#define NV_PNVENC_HIST_DBG1(dev) (0x001c8e14+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG1__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG1_IPRED_RD_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG1_IPRED_RD_HWVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG1_IPRED_RD_HOVLD 5:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG1_IPRED_RD_RDREQ 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG1_IPRED_RD_LDREQ 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG1_IPRED_RD_COLCNT 18:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG1_IPRED_RD_ROWCNT 31:19 /* R-XVF */
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#define NV_PNVENC_HIST_DBG2(dev) (0x001c8e18+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG2__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG2_DBLK_RD_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG2_DBLK_RD_HWVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG2_DBLK_RD_HOVLD 5:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG2_DBLK_RD_RDREQ 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG2_DBLK_RD_LDREQ 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG2_DBLK_RD_COLCNT 20:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG2_DBLK_RD_ROWCNT 31:21 /* R-XVF */
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#define NV_PNVENC_HIST_DBG3(dev) (0x001c8e1c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG3__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG3_ME_RD_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG3_ME_RD_HWVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG3_ME_RD_HOVLD 5:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG3_ME_RD_RDREQ 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG3_ME_RD_LDREQ 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG3_ME_RD_COLCNT 20:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG3_ME_RD_ROWCNT 31:21 /* R-XVF */
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#define NV_PNVENC_HIST_DBG4(dev) (0x001c8e20+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG4__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG4_MPEC_RD_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG4_MPEC_RD_HWVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG4_MPEC_RD_HOVLD 5:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG4_MPEC_RD_RDREQ 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG4_MPEC_RD_LDREQ 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG4_MPEC_RD_COLCNT 20:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG4_MPEC_RD_ROWCNT 31:21 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5(dev) (0x001c8e24+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG5__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG5_IPRED_WR_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5_IPRED_WR_HIVLD 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5_IPRED_WR_HOVLD 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5_IPRED_WR_RECCNT 11:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5_MDP_WR_STATE 19:16 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5_MDP_WR_HIVLD 22:22 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5_MDP_WR_HOVLD 23:23 /* R-XVF */
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#define NV_PNVENC_HIST_DBG5_MDP_WR_RECCNT 27:24 /* R-XVF */
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#define NV_PNVENC_HIST_DBG6(dev) (0x001c8e28+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG6__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG6_RXFER_FBCNT 9:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG6_RXFER_PICDONE 10:10 /* R-XVF */
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#define NV_PNVENC_HIST_DBG6_RXFER_HISTR_IDLE 11:11 /* R-XVF */
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#define NV_PNVENC_HIST_DBG6_RXFER_COLCNT 24:12 /* R-XVF */
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#define NV_PNVENC_HIST_DBG6_RXFER_ROWCNT 31:25 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7(dev) (0x001c8e2c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG7__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG7_WXFER_STATE 1:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_HISTAV 2:2 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_MEMVLD 3:3 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_OVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_ACKCNT 7:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_HISTW_IDLE 8:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_FBREC 11:9 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_MEMOFFS 15:12 /* R-XVF */
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#define NV_PNVENC_HIST_DBG7_WXFER_FBOFFS 31:16 /* R-XVF */
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#define NV_PNVENC_HIST_DBG8(dev) (0x001c8e30+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG8__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG8_MPEC_STATE 4:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG8_MPEC_HIVLD 3:3 /* R-XVF */
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#define NV_PNVENC_HIST_DBG8_MPEC_HOVLD 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG8_MPEC_RCOUNT 11:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG9(dev) (0x001c8e34+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG9__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG9_ICC_RD_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG9_ICC_RD_HWVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG9_ICC_RD_HOVLD 5:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG9_ICC_RD_RDREQ 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG9_ICC_RD_LDREQ 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG9_ICC_RD_COLCNT 20:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG9_ICC_RD_ROWCNT 31:21 /* R-XVF */
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#define NV_PNVENC_HIST_DBG10(dev) (0x001c8e38+(dev)*16384) /* R--4A */
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#define NV_PNVENC_HIST_DBG10__SIZE_1 1 /* */
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#define NV_PNVENC_HIST_DBG10_ICC_RD_STATE 3:0 /* R-XVF */
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#define NV_PNVENC_HIST_DBG10_ICC_RD_HWVLD 4:4 /* R-XVF */
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#define NV_PNVENC_HIST_DBG10_ICC_RD_HOVLD 5:5 /* R-XVF */
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#define NV_PNVENC_HIST_DBG10_ICC_RD_RDREQ 6:6 /* R-XVF */
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#define NV_PNVENC_HIST_DBG10_ICC_RD_LDREQ 7:7 /* R-XVF */
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#define NV_PNVENC_HIST_DBG10_ICC_RD_COLCNT 20:8 /* R-XVF */
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#define NV_PNVENC_HIST_DBG10_ICC_RD_ROWCNT 31:21 /* R-XVF */
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#define NV_PNVENC_PDMA_LUMA_BASE_ADDR(dev) (0x001c8e80+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_LUMA_BASE_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_LUMA_BASE_ADDR_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_PDMA_CHROMA_BASE_ADDR(dev) (0x001c8e84+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_CHROMA_BASE_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_CHROMA_BASE_ADDR_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_PDMA_CHROMA_U_BASE_ADDR(dev) (0x001c8eb0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_CHROMA_U_BASE_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_CHROMA_U_BASE_ADDR_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_PDMA_CHROMA_V_BASE_ADDR(dev) (0x001c8eb4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_CHROMA_V_BASE_ADDR__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_CHROMA_V_BASE_ADDR_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_PDMA_PIC_INFO_1(dev) (0x001c8eb8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_PIC_INFO_1__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_PIC_INFO_1_LUMA_STRIDE 12:0 /* RW-UF */
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#define NV_PNVENC_PDMA_PIC_INFO_1_CHROMA_STRIDE 29:16 /* RW-UF */
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#define NV_PNVENC_PDMA_PIC_INFO(dev) (0x001c8e88+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_PIC_INFO__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_PIC_INFO_WIDTH 12:0 /* RWIVF */
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#define NV_PNVENC_PDMA_PIC_INFO_WIDTH_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_PIC_INFO_HEIGHT 25:13 /* RWIVF */
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#define NV_PNVENC_PDMA_PIC_INFO_HEIGHT_INIT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_PIC_INFO_YUV444 27:27 /* RWIUF */
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#define NV_PNVENC_PDMA_PIC_INFO_YUV444_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_PIC_INFO_YUV444_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_PIC_INFO_YUV444_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_PIC_INFO_OFS_MODE 29:28 /* RWIUF */
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#define NV_PNVENC_PDMA_PIC_INFO_OFS_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_PIC_INFO_OFS_MODE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_PIC_INFO_OFS_MODE_OPTICALFLOW 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_PIC_INFO_OFS_MODE_STEREO 0x2 /* RW--V */
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#define NV_PNVENC_PDMA_PIC_INFO_SSIM_MODE 31:31 /* RWIUF */
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#define NV_PNVENC_PDMA_PIC_INFO_SSIM_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_BLKLINEAR(dev) (0x001c8e8c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_BLKLINEAR__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_BLKLINEAR_GOB 2:0 /* RWIVF */
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#define NV_PNVENC_PDMA_BLKLINEAR_GOB_INIT 0x3 /* RWI-V */
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#define NV_PNVENC_PDMA_BLKLINEAR_GOB_2 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_BLKLINEAR_GOB_4 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_BLKLINEAR_GOB_8 0x2 /* RW--V */
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#define NV_PNVENC_PDMA_BLKLINEAR_GOB_16 0x3 /* RW--V */
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#define NV_PNVENC_PDMA_BLKLINEAR_GOB_32 0x4 /* RW--V */
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#define NV_PNVENC_PDMA_CTL(dev) (0x001c8e90+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_CTL_START 0:0 /* -WIVF */
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#define NV_PNVENC_PDMA_CTL_START_INIT 0x0 /* -WI-V */
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#define NV_PNVENC_PDMA_CTL_START_START 0x0 /* -W--V */
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#define NV_PNVENC_PDMA_CTL_MEIO_EN 1:1 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_MEIO_EN_INIT 0x1 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_MEIO_EN_ON 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_MEIO_EN_OFF 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_MEONLY 2:2 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_MEONLY_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_MEONLY_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_MEONLY_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_CTBSIZE 4:3 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_CTBSIZE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_CTBSIZE_16X16 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_CTBSIZE_32X32 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_CTBSIZE_64X64 0x2 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_BIT_DEPTH_MINUS8 8:5 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_BIT_DEPTH_MINUS8_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_BIT_DEPTH_MINUS8_MAIN10 0x2 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_BIT_DEPTH_MINUS8_MAIN12 0x4 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_BIT_DEPTH_MINUS8_MAIN16 0x8 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_OWN_FIRST_MB_ROW_IN_PIC 9:9 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_OWN_FIRST_MB_ROW_IN_PIC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_OWN_FIRST_MB_ROW_IN_PIC_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_OWN_FIRST_MB_ROW_IN_PIC_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_OWN_LAST_MB_ROW_IN_PIC 10:10 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_OWN_LAST_MB_ROW_IN_PIC_DEFAULT 0x1 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_OWN_LAST_MB_ROW_IN_PIC_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_OWN_LAST_MB_ROW_IN_PIC_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_GOB_START_Y_OFFSET 15:11 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_GOB_START_Y_OFFSET_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_INPUT_SUBSAMPLING 16:16 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_INPUT_SUBSAMPLING_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_INPUT_SUBSAMPLING_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_INPUT_SUBSAMPLING_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_INTRA_4X4_EARLY_TERMINATE 17:17 /* RWIVF */
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#define NV_PNVENC_PDMA_CTL_INTRA_4X4_EARLY_TERMINATE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_CTL_INTRA_4X4_EARLY_TERMINATE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_CTL_INTRA_4X4_EARLY_TERMINATE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_ACSET_EN(dev) (0x001c8e94+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_ACSET_EN__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_ACSET_EN_SET0 0:0 /* RWIVF */
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#define NV_PNVENC_PDMA_ACSET_EN_SET0_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_ACSET_EN_SET1 1:1 /* RWIVF */
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#define NV_PNVENC_PDMA_ACSET_EN_SET1_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_ACSET_EN_SET2 2:2 /* RWIVF */
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#define NV_PNVENC_PDMA_ACSET_EN_SET2_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_ACSET_EN_SET3 3:3 /* RWIVF */
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#define NV_PNVENC_PDMA_ACSET_EN_SET3_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_ACSET_EN_SET4 4:4 /* RWIVF */
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#define NV_PNVENC_PDMA_ACSET_EN_SET4_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_ACSET_POP(dev) (0x001c8e98+(dev)*16384) /* -W-4A */
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#define NV_PNVENC_PDMA_ACSET_POP__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_ACSET_POP_EN 0:0 /* -WIVF */
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#define NV_PNVENC_PDMA_ACSET_POP_EN_INIT 0x0 /* -WI-V */
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#define NV_PNVENC_PDMA_ACSET_CNT(dev) (0x001c8e9c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_PDMA_ACSET_CNT__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_ACSET_CNT_VAL 7:0 /* R-IVF */
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#define NV_PNVENC_PDMA_ACSET_CNT_VAL_INIT 0x00 /* R-I-V */
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#define NV_PNVENC_PDMA_ACSET_MAX(dev) (0x001c8ea0+(dev)*16384) /* R--4A */
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#define NV_PNVENC_PDMA_ACSET_MAX__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_ACSET_MAX_VAR 31:0 /* R-IVF */
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#define NV_PNVENC_PDMA_ACSET_MAX_VAR_INIT 0xdeadbeef /* R-I-V */
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#define NV_PNVENC_PDMA_ACSET_MIN(dev) (0x001c8ea4+(dev)*16384) /* R--4A */
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#define NV_PNVENC_PDMA_ACSET_MIN__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_ACSET_MIN_VAR 31:0 /* R-IVF */
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#define NV_PNVENC_PDMA_ACSET_MIN_VAR_INIT 0xdeadbeef /* R-I-V */
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#define NV_PNVENC_PDMA_ACSET_AVG(dev) (0x001c8ea8+(dev)*16384) /* R--4A */
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#define NV_PNVENC_PDMA_ACSET_AVG__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_ACSET_AVG_VAR 31:0 /* R-IVF */
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#define NV_PNVENC_PDMA_ACSET_AVG_VAR_INIT 0xdeadbeef /* R-I-V */
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#define NV_PNVENC_PDMA_SFC_TRANS(dev) (0x001c8eac+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_SFC_TRANS__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR 2:0 /* RWIVF */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_NORMAL 0x0 /* RW--V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_HFLIP 0x1 /* RW--V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_VFLIP 0x2 /* RW--V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_180DEG_ROTAT 0x3 /* RW--V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_315DEG_MIRROR 0x4 /* RW--V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_270DEG_ROTAT 0x5 /* RW--V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_90DEG_ROTAT 0x6 /* RW--V */
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#define NV_PNVENC_PDMA_SFC_TRANS_VAR_45DEG_MIRROR 0x7 /* RW--V */
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#define NV_PNVENC_PDMA_AQ_PARAMS(dev) (0x001c8ebc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_PARAMS__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_PARAMS_ENABLE 0:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_SET 3:1 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_SET_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L0 5:4 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L1 7:6 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L2 9:8 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L3 11:10 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L4 13:12 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L5 15:14 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_L5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H0 17:16 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H0_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H1 19:18 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H1_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H2 21:20 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H2_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H3 23:22 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H3_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H4 25:24 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H4_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H5 27:26 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_PARAMS_TYPE_H5_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT_CONFIG(dev) (0x001c8ec0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_LUT_CONFIG__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_LUT_CONFIG_LO_COUNT 2:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT_CONFIG_LO_COUNT_DEFAULT 0x6 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT_CONFIG_HI_COUNT 5:3 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT_CONFIG_HI_COUNT_DEFAULT 0x6 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT0(dev) (0x001c8ec4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_LUT0__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_LUT0_L0 15:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT0_L0_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT0_L1 31:16 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT0_L1_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT1(dev) (0x001c8ec8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_LUT1__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_LUT1_L2 15:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT1_L2_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT1_L3 31:16 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT1_L3_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT2(dev) (0x001c8ecc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_LUT2__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_LUT2_L4 15:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT2_L4_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT2_L5 31:16 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT2_L5_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT3(dev) (0x001c8ed0+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_LUT3__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_LUT3_H0 15:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT3_H0_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT3_H1 31:16 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT3_H1_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT4(dev) (0x001c8ed4+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_LUT4__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_LUT4_H2 15:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT4_H2_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT4_H3 31:16 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT4_H3_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT5(dev) (0x001c8ed8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_AQ_LUT5__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_AQ_LUT5_H4 15:0 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT5_H4_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_AQ_LUT5_H5 31:16 /* RWIVF */
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#define NV_PNVENC_PDMA_AQ_LUT5_H5_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_PDMA_THRESHOLD(dev) (0x001c8edc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PDMA_THRESHOLD__SIZE_1 1 /* */
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#define NV_PNVENC_PDMA_THRESHOLD_INTRA_4X4_EARLY_TERMINATE 31:0 /* RWIVF */
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#define NV_PNVENC_PDMA_THRESHOLD_INTRA_4X4_EARLY_TERMINATE_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_RHINT_BASE(dev) (0x001c8f80+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RHINT_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_RHINT_BASE_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_RHINT_INTR(dev) (0x001c8f84+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RHINT_INTR__SIZE_1 1 /* */
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#define NV_PNVENC_RHINT_INTR_ROW_DONE 0:0 /* RWIUF */
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#define NV_PNVENC_RHINT_INTR_ROW_DONE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_RHINT_INTR_ROW_DONE_CLR 0x1 /* RW--V */
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#define NV_PNVENC_RHINT_INTEN(dev) (0x001c8f88+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RHINT_INTEN__SIZE_1 1 /* */
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#define NV_PNVENC_RHINT_INTEN_ROW_DONE 0:0 /* RWIUF */
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#define NV_PNVENC_RHINT_INTEN_ROW_DONE_INIT 0x0 /* RWI-V */
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#define NV_PNVENC_RHINT_INTEN_ROW_DONE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_RHINT_INTEN_ROW_DONE_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_RHINT_INTERVAL_BYTENUM(dev) (0x001c8f8c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RHINT_INTERVAL_BYTENUM__SIZE_1 1 /* */
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#define NV_PNVENC_RHINT_INTERVAL_BYTENUM_VAL 31:0 /* RWXUF */
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#define NV_PNVENC_RHINT_CTL(dev) (0x001c8f90+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RHINT_CTL__SIZE_1 1 /* */
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#define NV_PNVENC_RHINT_CTL_START 0:0 /* -WXUF */
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#define NV_PNVENC_RHINT_CTL_RST 1:1 /* -WXUF */
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#define NV_PNVENC_RHINT_CTL_MODE 3:2 /* RWIUF */
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#define NV_PNVENC_RHINT_CTL_MODE_EXT 0x0 /* RWI-V */
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#define NV_PNVENC_RHINT_CTL_MODE_SEG 0x1 /* RW--V */
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#define NV_PNVENC_RHINT_CTL_MODE_EXT_SEG 0x2 /* RW--V */
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#define NV_PNVENC_RHINT_DBG(dev) (0x001c8f94+(dev)*16384) /* R--4A */
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#define NV_PNVENC_RHINT_DBG__SIZE_1 1 /* */
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#define NV_PNVENC_RHINT_DBG_RDMA_RDVLD 0:0 /* R--VF */
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#define NV_PNVENC_RHINT_DBG_RDMA_WNUM 6:1 /* R--VF */
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#define NV_PNVENC_RHINT_DBG_ALLOC_CNT 9:7 /* R--VF */
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#define NV_PNVENC_RHINT_DBG_FULL_CNT 12:10 /* R--VF */
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#define NV_PNVENC_RHINT_DBG_OPKT_VLD 13:13 /* R--VF */
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#define NV_PNVENC_RHINT_DBG_OPKT_VLD_TRUE 0x1 /* R---V */
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#define NV_PNVENC_RHINT_DBG_OPKT_VLD_FALSE 0x0 /* R---V */
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#define NV_PNVENC_RHINT_DBG_OPKT_RDY 14:14 /* R--VF */
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#define NV_PNVENC_RHINT_DBG_OPKT_RDY_TRUE 0x1 /* R---V */
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#define NV_PNVENC_RHINT_DBG_OPKT_RDY_FALSE 0x0 /* R---V */
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#define NV_PNVENC_RHINT_DBG_IDLE 15:15 /* R--VF */
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#define NV_PNVENC_RHINT_DBG_IDLE_RDY_TRUE 0x1 /* R---V */
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#define NV_PNVENC_RHINT_DBG_IDLE_RDY_FALSE 0x0 /* R---V */
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#define NV_PNVENC_RHINT_ADDR_OFFSET(dev) (0x001c8f98+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_RHINT_ADDR_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_RHINT_ADDR_OFFSET_128B_OFFSET 0:0 /* RW-UF */
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#define NV_PNVENC_RHINT_ADDR_OFFSET_4B_OFFSET 5:1 /* RW-UF */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_TOP(dev) (0x001c9000+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_TOP__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_TOP_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_TOP_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_BOT(dev) (0x001c9004+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_BOT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_BOT_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_OFFSET_BOT_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFPIC_SIZE(dev) (0x001c9008+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_SIZE_LUMA_STRIDE_IN_MB 12:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_SIZE_LUMA_STRIDE_IN_MB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFPIC_SIZE_CHROMA_STRIDE_IN_MB 29:16 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_SIZE_CHROMA_STRIDE_IN_MB_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY(dev) (0x001c900c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY_LEFT_MB 27:16 /* RWIUF */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY_LEFT_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY_RIGHT_MB 11:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY_RIGHT_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_MAX_REQ_NUM_PER_MB(dev) (0x001c9010+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_MAX_REQ_NUM_PER_MB__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_MAX_REQ_NUM_PER_MB_VAL 8:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_MAX_REQ_NUM_PER_MB_VAL_DEFAULT 0x140 /* RWI-V */
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#define NV_PNVENC_ME_MBC_MAX_REQ_NUM_PER_MB_VAL_YUV420 0x140 /* RW--V */
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#define NV_PNVENC_ME_MBC_MAX_REQ_NUM_PER_MB_VAL_YUV444 0x118 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL(dev) (0x001c9014+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_CTRL__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_CTRL_OFS_MODE 23:22 /* RWIUF */
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#define NV_PNVENC_ME_MBC_CTRL_OFS_MODE_DISABLE 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MBC_CTRL_OFS_MODE_OPTICALFLOW 0x1 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_OFS_MODE_STEREO 0x2 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_MAX_QUAD_PAIR_NUM_PER_CTB 21:12 /* RWIUF */
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#define NV_PNVENC_ME_MBC_CTRL_MAX_QUAD_PAIR_NUM_PER_CTB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_CTRL_BIT_DEPTH_MINUS8 11:8 /* RWIUF */
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#define NV_PNVENC_ME_MBC_CTRL_BIT_DEPTH_MINUS8_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MBC_CTRL_BIT_DEPTH_MINUS8_10BIT 0x2 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_BIT_DEPTH_MINUS8_12BIT 0x4 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_BIT_DEPTH_MINUS8_16BIT 0x8 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CTBSIZE 7:6 /* RWIUF */
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#define NV_PNVENC_ME_MBC_CTRL_CTBSIZE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MBC_CTRL_CTBSIZE_16X16 0x0 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CTBSIZE_32X32 0x1 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CTBSIZE_64X64 0x2 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID 5:3 /* RWIUF */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_H264 0x0 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_MPEG4 0x1 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_VP8 0x2 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_MPEG2 0x3 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_VC1 0x4 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_H265 0x5 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_CODEC_ID_VP9 0x6 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_YUV444 2:2 /* RWIUF */
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#define NV_PNVENC_ME_MBC_CTRL_YUV444_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MBC_CTRL_YUV444_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_YUV444_ENABLE 0x1 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_ARBITOR 1:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_CTRL_ARBITOR_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_ME_MBC_CTRL_ARBITOR_FPS 0x1 /* RW--V */
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#define NV_PNVENC_ME_MBC_CTRL_ARBITOR_SPS 0x2 /* RW--V */
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#define NV_PNVENC_ME_MBC_BLKLINEAR(dev) (0x001c901c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_BLKLINEAR__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_BLKLINEAR_GOB 2:0 /* RWIVF */
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#define NV_PNVENC_ME_MBC_BLKLINEAR_GOB_INIT 0x3 /* RWI-V */
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#define NV_PNVENC_ME_MBC_BLKLINEAR_GOB_2 0x0 /* RW--V */
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#define NV_PNVENC_ME_MBC_BLKLINEAR_GOB_4 0x1 /* RW--V */
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#define NV_PNVENC_ME_MBC_BLKLINEAR_GOB_8 0x2 /* RW--V */
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#define NV_PNVENC_ME_MBC_BLKLINEAR_GOB_16 0x3 /* RW--V */
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#define NV_PNVENC_ME_MBC_BLKLINEAR_GOB_32 0x4 /* RW--V */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT(dev,i) (0x001c9020+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT__SIZE_2 2 /* */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA3 29:24 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA2 21:16 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA1 13:8 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA0 5:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST0_DPBLUT_DATA0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT(dev,i) (0x001c9030+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT__SIZE_2 2 /* */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA3 29:24 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA3_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA2 21:16 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA2_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA1 13:8 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA1_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA0 5:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFLIST1_DPBLUT_DATA0_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_BASE(dev,i) (0x001c9040+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_BASE__SIZE_2 16 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_LUMA_BASE_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_TOP(dev) (0x001c9080+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_TOP__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_TOP_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_TOP_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_BOT(dev) (0x001c9084+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_BOT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_BOT_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_OFFSET_BOT_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_U_OFFSET(dev) (0x001c9088+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_U_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_U_OFFSET_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_U_OFFSET_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_V_OFFSET(dev) (0x001c908c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_V_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_V_OFFSET_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_V_OFFSET_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_DBG_SEL(dev) (0x001c9090+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_DBG_SEL__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_DBG_SEL_IDX 5:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_DBG_SEL_IDX_DEFAULT 0x00 /* RWI-V */
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#define NV_PNVENC_ME_MBC_DBG_STAT(dev) (0x001c9094+(dev)*16384) /* R--4A */
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#define NV_PNVENC_ME_MBC_DBG_STAT__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_DBG_STAT_VAL 31:0 /* R-IUF */
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#define NV_PNVENC_ME_MBC_DBG_STAT_VAL_DEFAULT 0x00000000 /* R-I-V */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_BASE(dev,i) (0x001c9098+(dev)*16384+(i)*4) /* RW-4A */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_BASE__SIZE_2 16 /* */
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#define NV_PNVENC_ME_MBC_REFPIC_CHROMA_BASE_ADDR 31:0 /* RW-UF */
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#define NV_PNVENC_ME_MBC_FRAME_SIZE(dev) (0x001c90d8+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_FRAME_SIZE__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_FRAME_SIZE_WIDTH 12:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_FRAME_SIZE_WIDTH_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_FRAME_SIZE_HEIGHT 28:16 /* RWIUF */
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#define NV_PNVENC_ME_MBC_FRAME_SIZE_HEIGHT_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY1(dev) (0x001c90dc+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY1__SIZE_1 1 /* */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY1_TOP_MB 27:16 /* RWIUF */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY1_TOP_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY1_BOTTOM_MB 11:0 /* RWIUF */
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#define NV_PNVENC_ME_MBC_MV_BOUNDARY1_BOTTOM_MB_DEFAULT 0x000 /* RWI-V */
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#define NV_PNVENC_PMM_MS(dev) (0x001c9100+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PMM_MS__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_MS_S0 7:0 /* RWIUF */
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#define NV_PNVENC_PMM_MS_S0_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS_S0_ANY_STARVING 0x01 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_I4X4_SEARCHING 0x02 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_I8X8_SEARCHING 0x03 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_I16X16_SEARCHING 0x04 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_CHROMA_PROCESSING 0x05 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_INTER_PROCESSING 0x06 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_HIST2IPRED_STARVING 0x07 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_HIST2DBLK_STARVING 0x08 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME2MPEB_STARVING 0x09 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2MPEB_STARVING 0x0a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_STARVING 0x0b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_IPRED2DBLK_STALLING 0x0c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_FBIF2DBFDMA_STARVING 0x0d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2HIST_STALLING 0x0e /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2MPEC_STALLING 0x0f /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_DBFDMA2FBIF_STALLING 0x10 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2MDP_STALLING 0x11 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2ME_STALLING 0x12 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2HIST_STALLING 0x13 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_STALLING 0x14 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_MPEB2MDP_ACK_STARVING 0x15 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_FALCON2MDP_STARVING 0x16 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_EMD_BUSY 0x17 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_FMD_BUSY 0x18 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_INTRA_MB_DONE 0x19 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_INTER_MB_DONE 0x1a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_I4X4_CMD_START 0x1b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_I8X8_CMD_START 0x1c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_I16X16_CMD_START 0x1d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2WMVP_STALLING 0x1e /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_RMVP2ME_STARVING 0x1f /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_RCOL2ME_STARVING 0x20 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_RHINT2ME_STARVING 0x21 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2ME_FPS_STARVING 0x22 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2ME_HPS_STARVING 0x23 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2MPEB_STARVING 0x24 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_MB_START 0x25 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_MB_DONE 0x26 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_IPCM_REWIND 0x27 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_SLICE_END_REWIND 0x28 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2MPEC_STARVING 0x29 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2MPEB_STALLING 0x2a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2MPEC_STALLING 0x2b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2MPEC_STARVING 0x2c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2HIST_STALLING 0x2d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2HIST_STARVING 0x2e /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_SPS_MB_START 0x2f /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_BICTL_MOCOMP_BUSY 0x30 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_BICTL_EVAL_BUSY 0x31 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_PG2SRF_STARVING 0x32 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SRF2QS_STALLING 0x33 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SRF2QS_STARVING 0x34 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_QS2MBC_STARVING 0x35 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC2FPS_STARVING 0x36 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FPS2FBM_STALLING 0x37 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FB2FPS_STARVING 0x38 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SRF2MBC_STALLING 0x39 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_QS2SPS_STARVING 0x3a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SPS2FBM_STARVING 0x3b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FPS2FBM_STARVING 0x3c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC2HPF_STARVING 0x3d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FB2HPF_STARVING 0x3e /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FBM2SPS_STARVING 0x3f /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_TL_BUSY 0x40 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FB_BUSY 0x41 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_LOCK_FULL 0x42 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_CACHE_FULL 0x43 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_REQ 0x44 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_DROP 0x45 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FPS_REQ 0x46 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FPS_DROP 0x47 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_SPS_REQ 0x48 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_SPS_DROP 0x49 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MDP2SPS_PRED_STARVING 0x4a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SPS2HPCOST_PRED_STARVING 0x4b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MDP2SPS_MOCOMP_STARVING 0x4c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPF2HPCOST_STALLING 0x4d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPF2UVRAM_STALLING 0x4e /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPF2HPRAM_STALLING 0x4f /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPCTL2HPF_STARVING 0x50 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_BICTL2WPRED_STALLING 0x51 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_QPF2BICTL_STARVING 0x52 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_WPRED2MCINTF_STALLING 0x53 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_WPRED2BISATD_STALLING 0x54 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPRAM2QPCTL_STARVING 0x55 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_ME2MDP_MV_STALLING 0x56 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2MDP_STARVING 0x57 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2ME_STARVING 0x58 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2ICC_STARVING 0x59 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2FALCON_ACTIVITY_STALLING 0x5a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_STATIC_PATTERN_1_1_GROUP 0x5b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_STATIC_PATTERN_0_1_GROUP 0x5c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_IS_WORKING 0x5d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ANY_STALLING_SC 0x80 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ANY_STARVING_SC 0x81 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_I4X4_SEARCHING_SC 0x82 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_I8X8_SEARCHING_SC 0x83 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_I16X16_SEARCHING_SC 0x84 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_CHROMA_PROCESSING_SC 0x85 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_INTER_PROCESSING_SC 0x86 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_HIST2IPRED_STARVING_SC 0x87 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_HIST2DBLK_STARVING_SC 0x88 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME2MPEB_STARVING_SC 0x89 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2MPEB_STARVING_SC 0x8a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_STARVING_SC 0x8b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_IPRED2DBLK_STALLING_SC 0x8c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_FBIF2DBFDMA_STARVING_SC 0x8d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2HIST_STALLING_SC 0x8e /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2MPEC_STALLING_SC 0x8f /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB_DBFDMA2FBIF_STALLING_SC 0x90 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2MDP_STALLING_SC 0x91 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2ME_STALLING_SC 0x92 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2HIST_STALLING_SC 0x93 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_STALLING_SC 0x94 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_MPEB2MDP_ACK_STARVING_SC 0x95 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_FALCON2MDP_STARVING_SC 0x96 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_EMD_BUSY_SC 0x97 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_FMD_BUSY_SC 0x98 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_INTRA_MB_DONE_SC 0x99 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP_INTER_MB_DONE_SC 0x9a /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_I4X4_CMD_START_SC 0x9b /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_I8X8_CMD_START_SC 0x9c /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2MPEB_I16X16_CMD_START_SC 0x9d /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MDP2WMVP_STALLING_SC 0x9e /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_RMVP2ME_STARVING_SC 0x9f /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_RCOL2ME_STARVING_SC 0xa0 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_RHINT2ME_STARVING_SC 0xa1 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2ME_FPS_STARVING_SC 0xa2 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2ME_HPS_STARVING_SC 0xa3 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2MPEB_STARVING_SC 0xa4 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_MB_START_SC 0xa5 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_MB_DONE_SC 0xa6 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_IPCM_REWIND_SC 0xa7 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_SLICE_END_REWIND_SC 0xa8 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEB2MPEC_STARVING_SC 0xa9 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2MPEB_STALLING_SC 0xaa /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2MPEC_STALLING_SC 0xab /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2MPEC_STARVING_SC 0xac /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2HIST_STALLING_SC 0xad /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC2HIST_STARVING_SC 0xae /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_SPS_MB_START_SC 0xaf /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_BICTL_MOCOMP_BUSY_SC 0xb0 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_BICTL_EVAL_BUSY_SC 0xb1 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_PG2SRF_STARVING_SC 0xb2 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SRF2QS_STALLING_SC 0xb3 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SRF2QS_STARVING_SC 0xb4 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_QS2MBC_STARVING_SC 0xb5 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC2FPS_STARVING_SC 0xb6 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FPS2FBM_STALLING_SC 0xb7 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FB2FPS_STARVING_SC 0xb8 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SRF2MBC_STALLING_SC 0xb9 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_QS2SPS_STARVING_SC 0xba /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SPS2FBM_STARVING_SC 0xbb /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FPS2FBM_STARVING_SC 0xbc /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC2HPF_STARVING_SC 0xbd /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FB2HPF_STARVING_SC 0xbe /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_FBM2SPS_STARVING_SC 0xbf /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_TL_BUSY_SC 0xc0 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FB_BUSY_SC 0xc1 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_LOCK_FULL_SC 0xc2 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_CACHE_FULL_SC 0xc3 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_REQ_SC 0xc4 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FETCH_DROP_SC 0xc5 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FPS_REQ_SC 0xc6 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_FPS_DROP_SC 0xc7 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_SPS_REQ_SC 0xc8 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MBC_SPS_DROP_SC 0xc9 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MDP2SPS_PRED_STARVING_SC 0xca /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_SPS2HPCOST_PRED_STARVING_SC 0xcb /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_MDP2SPS_MOCOMP_STARVING_SC 0xcc /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPF2HPCOST_STALLING_SC 0xcd /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPF2UVRAM_STALLING_SC 0xce /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPF2HPRAM_STALLING_SC 0xcf /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPCTL2HPF_STARVING_SC 0xd0 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_BICTL2WPRED_STALLING_SC 0xd1 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_QPF2BICTL_STARVING_SC 0xd2 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_WPRED2MCINTF_STALLING_SC 0xd3 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_WPRED2BISATD_STALLING_SC 0xd4 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_HPRAM2QPCTL_STARVING_SC 0xd5 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_ME_ME2MDP_MV_STALLING_SC 0xd6 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2MDP_STARVING_SC 0xd7 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2ME_STARVING_SC 0xd8 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_HIST2ICC_STARVING_SC 0xd9 /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_PDMA2FALCON_ACTIVITY_STALLING_SC 0xda /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_STATIC_PATTERN_1_1_GROUP_SC 0xdb /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_STATIC_PATTERN_0_1_GROUP_SC 0xdc /* RW--V */
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#define NV_PNVENC_PMM_MS_S0_MPEC_IS_WORKING_SC 0xdd /* RW--V */
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#define NV_PNVENC_PMM_MS_S1 15:8 /* RWIUF */
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#define NV_PNVENC_PMM_MS_S1_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS_S2 23:16 /* RWIUF */
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#define NV_PNVENC_PMM_MS_S2_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS_S3 31:24 /* RWIUF */
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#define NV_PNVENC_PMM_MS_S3_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS1(dev) (0x001c9120+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PMM_MS1__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_MS1_S0 7:0 /* RWIUF */
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#define NV_PNVENC_PMM_MS1_S0_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS1_S1 15:8 /* RWIUF */
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#define NV_PNVENC_PMM_MS1_S1_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS1_S2 23:16 /* RWIUF */
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#define NV_PNVENC_PMM_MS1_S2_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS1_S3 31:24 /* RWIUF */
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#define NV_PNVENC_PMM_MS1_S3_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS2(dev) (0x001c9124+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PMM_MS2__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_MS2_S0 7:0 /* RWIUF */
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#define NV_PNVENC_PMM_MS2_S0_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS2_S1 15:8 /* RWIUF */
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#define NV_PNVENC_PMM_MS2_S1_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS2_S2 23:16 /* RWIUF */
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#define NV_PNVENC_PMM_MS2_S2_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_MS2_S3 31:24 /* RWIUF */
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#define NV_PNVENC_PMM_MS2_S3_ANY_STALLING 0x00 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0(dev) (0x001c9104+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PMM_STALL_M0__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_STALL_M0_MPEB_IPRED2DBLK 0:0 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MPEB_IPRED2DBLK_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MPEB2HIST 1:1 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MPEB2HIST_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MPEB2MPEC 2:2 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MPEB2MPEC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MPEB_DBFDMA2FBIF 3:3 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MPEB_DBFDMA2FBIF_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MPEB2MDP 4:4 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MPEB2MDP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MDP2ME 5:5 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MDP2ME_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MDP2HIST 6:6 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MDP2HIST_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MDP2MPEB 7:7 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MDP2MPEB_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MDP2WMVP 8:8 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MDP2WMVP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MPEC2MPEB 9:9 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MPEC2MPEB_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_HIST2MPEC 10:10 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_HIST2MPEC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_MPEC2HIST 11:11 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_MPEC2HIST_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_SRF2QS 12:12 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_SRF2QS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_FPS2FBM 13:13 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_FPS2FBM_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_SRF2MBC 14:14 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_SRF2MBC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_HPF2HPCOST 15:15 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_HPF2HPCOST_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_HPF2UVRAM 16:16 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_HPF2UVRAM_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_HPF2HPRAM 17:17 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_HPF2HPRAM_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_BICTL2WPRED 18:18 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_BICTL2WPRED_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_WPRED2MCINTF 19:19 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_WPRED2MCINTF_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_WPRED2BISATD 20:20 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_WPRED2BISATD_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_ME_ME2MDP_MV 21:21 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_ME_ME2MDP_MV_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STALL_M0_PDMA2FALCON_ACTIVITY 22:22 /* RWIUF */
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#define NV_PNVENC_PMM_STALL_M0_PDMA2FALCON_ACTIVITY_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0(dev) (0x001c910c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PMM_STARVE_M0__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB_HIST2IPRED 0:0 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB_HIST2IPRED_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB_HIST2DBLK 1:1 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB_HIST2DBLK_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME2MPEB 2:2 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME2MPEB_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_MPEC2MPEB 3:3 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MPEC2MPEB_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_MDP2MPEB 4:4 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MDP2MPEB_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB_FBIF2DBFDMA 5:5 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB_FBIF2DBFDMA_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_MDP_MPEB2MDP_ACK 6:6 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MDP_MPEB2MDP_ACK_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_FALCON2MDP 7:7 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_FALCON2MDP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_RMVP2ME 8:8 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_RMVP2ME_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_RCOL2ME 9:9 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_RCOL2ME_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_RHINT2ME 10:10 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_RHINT2ME_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_PDMA2ME_FPS 11:11 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_PDMA2ME_FPS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_PDMA2ME_HPS 12:12 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_PDMA2ME_HPS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_PDMA2MPEB 13:13 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_PDMA2MPEB_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB2MPEC 14:14 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MPEB2MPEC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_HIST2MPEC 15:15 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_HIST2MPEC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_MPEC2HIST 16:16 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_MPEC2HIST_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_PG2SRF 17:17 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_PG2SRF_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_SRF2QS 18:18 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_SRF2QS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_QS2MBC 19:19 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_QS2MBC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MBC2FPS 20:20 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MBC2FPS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FB2FPS 21:21 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FB2FPS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_QS2SPS 22:22 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_QS2SPS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_SPS2FBM 23:23 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_SPS2FBM_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FPS2FBM 24:24 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FPS2FBM_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MBC2HPF 25:25 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MBC2HPF_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FB2HPF 26:26 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FB2HPF_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FBM2SPS 27:27 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_FBM2SPS_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MDP2SPS_PRED 28:28 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MDP2SPS_PRED_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_SPS2HPCOST_PRED 29:29 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_SPS2HPCOST_PRED_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MDP2SPS_MOCOMP 30:30 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_MDP2SPS_MOCOMP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M0_ME_HPCTL2HPF 31:31 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M0_ME_HPCTL2HPF_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M1(dev) (0x001c9110+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_PMM_STARVE_M1__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_STARVE_M1_ME_QPF2BICTL 0:0 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M1_ME_QPF2BICTL_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M1_ME_HPRAM2QPCTL 1:1 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M1_ME_HPRAM2QPCTL_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M1_HIST2MDP 2:2 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M1_HIST2MDP_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M1_HIST2ME 3:3 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M1_HIST2ME_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STARVE_M1_HIST2ICC 4:4 /* RWIUF */
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#define NV_PNVENC_PMM_STARVE_M1_HIST2ICC_ENABLE 0x1 /* RWI-V */
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#define NV_PNVENC_PMM_STAT0(dev) (0x001c9114+(dev)*16384) /* R--4A */
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#define NV_PNVENC_PMM_STAT0__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_STAT0_PM_ANY_STALLING 0:0 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_ANY_STARVING 1:1 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_I4X4_SEARCHING 2:2 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_I8X8_SEARCHING 3:3 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_I16X16_SEARCHING 4:4 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_CHROMA_PROCESSING 5:5 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_INTER_PROCESSING 6:6 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_HIST2IPRED_STARVING 7:7 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_HIST2DBLK_STARVING 8:8 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_ME2MPEB_STARVING 9:9 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEC2MPEB_STARVING 10:10 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2MPEB_STARVING 11:11 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_IPRED2DBLK_STALLING 12:12 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_FBIF2DBFDMA_STARVING 13:13 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB2HIST_STALLING 14:14 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB2MPEC_STALLING 15:15 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB_DBFDMA2FBIF_STALLING 16:16 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MPEB2MDP_STALLING 17:17 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2ME_STALLING 18:18 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2HIST_STALLING 19:19 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2MPEB_STALLING 20:20 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP_MPEB2MDP_ACK_STARVING 21:21 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_FALCON2MDP_STARVING 22:22 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP_EMD_BUSY 23:23 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP_FMD_BUSY 24:24 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP_INTRA_MB_DONE 25:25 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP_INTER_MB_DONE 26:26 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2MPEB_I4X4_CMD_START 27:27 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2MPEB_I8X8_CMD_START 28:28 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2MPEB_I16X16_CMD_START 29:29 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_MDP2WMVP_STALLING 30:30 /* R--UF */
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#define NV_PNVENC_PMM_STAT0_PM_RMVP2ME_STARVING 31:31 /* R--UF */
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#define NV_PNVENC_PMM_STAT1(dev) (0x001c9118+(dev)*16384) /* R--4A */
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#define NV_PNVENC_PMM_STAT1__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_STAT1_PM_RCOL2ME_STARVING 0:0 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_RHINT2ME_STARVING 1:1 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_PDMA2ME_FPS_STARVING 2:2 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_PDMA2ME_HPS_STARVING 3:3 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_PDMA2MPEB_STARVING 4:4 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEC_MB_START 5:5 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEC_MB_DONE 6:6 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEC_IPCM_REWIND 7:7 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEC_SLICE_END_REWIND 8:8 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEB2MPEC_STARVING 9:9 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEC2MPEB_STALLING 10:10 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_HIST2MPEC_STALLING 11:11 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_HIST2MPEC_STARVING 12:12 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEC2HIST_STALLING 13:13 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_MPEC2HIST_STARVING 14:14 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_SPS_MB_START 15:15 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_BICTL_MOCOMP_BUSY 16:16 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_BICTL_EVAL_BUSY 17:17 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_PG2SRF_STARVING 18:18 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_SRF2QS_STALLING 19:19 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_SRF2QS_STARVING 20:20 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_QS2MBC_STARVING 21:21 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_MBC2FPS_STARVING 22:22 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_FPS2FBM_STALLING 23:23 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_FB2FPS_STARVING 24:24 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_SRF2MBC_STALLING 25:25 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_QS2SPS_STARVING 26:26 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_SPS2FBM_STARVING 27:27 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_FPS2FBM_STARVING 28:28 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_MBC2HPF_STARVING 29:29 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_FB2HPF_STARVING 30:30 /* R--UF */
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#define NV_PNVENC_PMM_STAT1_PM_ME_FBM2SPS_STARVING 31:31 /* R--UF */
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#define NV_PNVENC_PMM_STAT2(dev) (0x001c911c+(dev)*16384) /* R--4A */
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#define NV_PNVENC_PMM_STAT2__SIZE_1 1 /* */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_TL_BUSY 0:0 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_FB_BUSY 1:1 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_FETCH_LOCK_FULL 2:2 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_FETCH_CACHE_FULL 3:3 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_FETCH_REQ 4:4 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_FETCH_DROP 5:5 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_FPS_REQ 6:6 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_FPS_DROP 7:7 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_SPS_REQ 8:8 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MBC_SPS_DROP 9:9 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MDP2SPS_PRED_STARVING 10:10 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_SPS2HPCOST_PRED_STARVING 11:11 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_MDP2SPS_MOCOMP_STARVING 12:12 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_HPF2HPCOST_STALLING 13:13 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_HPF2UVRAM_STALLING 14:14 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_HPF2HPRAM_STALLING 15:15 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_HPCTL2HPF_STARVING 16:16 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_BICTL2WPRED_STALLING 17:17 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_QPF2BICTL_STARVING 18:18 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_WPRED2MCINTF_STALLING 19:19 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_WPRED2BISATD_STALLING 20:20 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_HPRAM2QPCTL_STARVING 21:21 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_ME_ME2MDP_MV_STALLING 22:22 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_HIST2MDP_STARVING 23:23 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_HIST2ME_STARVING 24:24 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_HIST2ICC_STARVING 25:25 /* R--UF */
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#define NV_PNVENC_PMM_STAT2_PM_PDMA2FALCON_ACTIVITY_STALLING 26:26 /* R--UF */
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#define NV_PNVENC_MISC_BLCG(dev) (0x001c8f20+(dev)*16384) /* RWE4A */
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#define NV_PNVENC_MISC_BLCG__SIZE_1 1 /* */
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#define NV_PNVENC_MISC_BLCG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
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#define NV_PNVENC_MISC_BLCG_IDLE_CG_DLY_CNT_HWINIT 0x00 /* RWE-V */
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#define NV_PNVENC_MISC_BLCG_IDLE_CG_DLY_CNT__PROD 0x02 /* RW--V */
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#define NV_PNVENC_MISC_BLCG_IDLE_CG_EN 6:6 /* RWEVF */
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#define NV_PNVENC_MISC_BLCG_IDLE_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_MISC_BLCG_IDLE_CG_EN_DISABLED 0x0 /* RWE-V */
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#define NV_PNVENC_MISC_BLCG_IDLE_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PNVENC_MISC_BLCG_STATE_CG_EN 7:7 /* */
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#define NV_PNVENC_MISC_BLCG_STATE_CG_EN_ENABLED 0x1 /* */
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#define NV_PNVENC_MISC_BLCG_STATE_CG_EN_DISABLED 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_STATE_CG_EN__PROD 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PNVENC_MISC_BLCG_STALL_CG_DLY_CNT_HWINIT 0x00 /* */
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#define NV_PNVENC_MISC_BLCG_STALL_CG_DLY_CNT__PROD 0x00 /* */
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#define NV_PNVENC_MISC_BLCG_STALL_CG_EN 14:14 /* RWEVF */
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#define NV_PNVENC_MISC_BLCG_STALL_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_MISC_BLCG_STALL_CG_EN_DISABLED 0x0 /* RWE-V */
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#define NV_PNVENC_MISC_BLCG_STALL_CG_EN__PROD 0x1 /* RW--V */
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#define NV_PNVENC_MISC_BLCG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PNVENC_MISC_BLCG_QUIESCENT_CG_EN_ENABLED 0x1 /* */
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#define NV_PNVENC_MISC_BLCG_QUIESCENT_CG_EN_DISABLED 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_QUIESCENT_CG_EN__PROD 0x1 /* */
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#define NV_PNVENC_MISC_BLCG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
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#define NV_PNVENC_MISC_BLCG_WAKEUP_DLY_CNT_HWINIT 0x0 /* RWE-V */
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#define NV_PNVENC_MISC_BLCG_WAKEUP_DLY_CNT__PROD 0x3 /* RW--V */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_CNT 23:20 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_CNT_FULLSPEED 0xf /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_CNT__PROD 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PNVENC_MISC_BLCG_DI_DT_SKEW_VAL_HWINIT 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_DI_DT_SKEW_VAL__PROD 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_EN 28:28 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_EN_ENABLED 0x1 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_EN_DISABLED 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_EN__PROD 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_SW_OVER_EN 0x1 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_SW_OVER_DIS 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_THROT_CLK_SW_OVER__PROD 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_PAUSE_CG_EN 30:30 /* */
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#define NV_PNVENC_MISC_BLCG_PAUSE_CG_EN_ENABLED 0x1 /* */
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#define NV_PNVENC_MISC_BLCG_PAUSE_CG_EN_DISABLED 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_PAUSE_CG_EN__PROD 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_HALT_CG_EN 31:31 /* */
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#define NV_PNVENC_MISC_BLCG_HALT_CG_EN_ENABLED 0x1 /* */
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#define NV_PNVENC_MISC_BLCG_HALT_CG_EN_DISABLED 0x0 /* */
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#define NV_PNVENC_MISC_BLCG_HALT_CG_EN__PROD 0x0 /* */
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#define NV_PNVENC_MISC_BLCG1(dev) (0x001c8f24+(dev)*16384) /* RWE4A */
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#define NV_PNVENC_MISC_BLCG1__SIZE_1 1 /* */
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#define NV_PNVENC_MISC_BLCG1_MONITOR_CG_EN 0:0 /* RWEVF */
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#define NV_PNVENC_MISC_BLCG1_MONITOR_CG_EN_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_MISC_BLCG1_MONITOR_CG_EN_DISABLED 0x0 /* RWE-V */
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#define NV_PNVENC_MISC_BLCG1_MONITOR_CG_EN__PROD 0x0 /* RW--V */
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#define NV_PNVENC_MISC_BLCG1_SLCG 12:1 /* RWEVF */
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#define NV_PNVENC_MISC_BLCG1_SLCG_ENABLED 0x000 /* RW--V */
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#define NV_PNVENC_MISC_BLCG1_SLCG_DISABLED 0xfff /* RWE-V */
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#define NV_PNVENC_MISC_BLCG1_SLCG__PROD 0x000 /* RW--V */
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#define NV_PNVENC_MEDMA_BASE(dev) (0x001c9140+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MEDMA_BASE__SIZE_1 1 /* */
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#define NV_PNVENC_MEDMA_BASE_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MEDMA_BASE_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MEDMA_OFFSET(dev) (0x001c9144+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MEDMA_OFFSET__SIZE_1 1 /* */
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#define NV_PNVENC_MEDMA_OFFSET_ADDR 31:0 /* RWIUF */
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#define NV_PNVENC_MEDMA_OFFSET_ADDR_DEFAULT 0x00000000 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG(dev) (0x001c9148+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MEDMA_FRMCFG__SIZE_1 1 /* */
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#define NV_PNVENC_MEDMA_FRMCFG_MV_ONLY_ENABLE 0:0 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_MV_ONLY_ENABLE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG_MV_ONLY_ENABLE_FALSE 0x0 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_MV_ONLY_ENABLE_TRUE 0x1 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_START 1:1 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_START_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG_FRMTYPE 4:2 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_FRMTYPE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG_CODEC 7:5 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_CODEC_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG_OFS_MODE 9:8 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_OFS_MODE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG_OFS_MODE_DISABLE 0x0 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_OFS_MODE_OPTICALFLOW 0x1 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_OFS_MODE_STEREO 0x2 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_BLKLINEAR_GOB 12:10 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_BLKLINEAR_GOB_INIT 0x3 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG_BLKLINEAR_GOB_2 0x0 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_BLKLINEAR_GOB_4 0x1 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_BLKLINEAR_GOB_8 0x2 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_BLKLINEAR_GOB_16 0x3 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_BLKLINEAR_GOB_32 0x4 /* RW--V */
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#define NV_PNVENC_MEDMA_FRMCFG_STRIDE 25:13 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_STRIDE_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG_MBY_OFFSET 31:26 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG_MBY_OFFSET_INIT 0x00 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG1(dev) (0x001c914c+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MEDMA_FRMCFG1__SIZE_1 1 /* */
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#define NV_PNVENC_MEDMA_FRMCFG1_MBCNT 24:0 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG1_MBCNT_DEFAULT 0x0000000 /* RWI-V */
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#define NV_PNVENC_MEDMA_INTEN(dev) (0x001c9150+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MEDMA_INTEN__SIZE_1 1 /* */
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#define NV_PNVENC_MEDMA_INTEN_FRAME_DONE 0:0 /* RWISF */
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#define NV_PNVENC_MEDMA_INTEN_FRAME_DONE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MEDMA_INTS(dev) (0x001c9154+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MEDMA_INTS__SIZE_1 1 /* */
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#define NV_PNVENC_MEDMA_INTS_FRAME_DONE 0:0 /* RWISF */
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#define NV_PNVENC_MEDMA_INTS_FRAME_DONE_DEFAULT 0x0 /* RWI-V */
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#define NV_PNVENC_MEDMA_FRMCFG2(dev) (0x001c9158+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_MEDMA_FRMCFG2__SIZE_1 1 /* */
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#define NV_PNVENC_MEDMA_FRMCFG2_MB_WIDTH 12:0 /* RWIUF */
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#define NV_PNVENC_MEDMA_FRMCFG2_MB_WIDTH_DEFAULT 0x0000 /* RWI-V */
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#define NV_PNVENC_CG2(dev) (0x001c9200+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_CG2__SIZE_1 1 /* */
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#define NV_PNVENC_CG2_SLCG 31:0 /* RW-VF */
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#define NV_PNVENC_CG2_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_DISABLED 0xffffffff /* RW--V */
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#define NV_PNVENC_CG2_SLCG__PROD 0xffffffff /* RW--V */
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#define NV_PNVENC_CG2_SLCG_CSBMASTER_DIS 31:31 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_CSBMASTER_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_CSBMASTER_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_CSBMASTER_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCPLA_DIS 30:30 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_MBCPLA_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCPLA_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCPLA_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCTLS_DIS 29:29 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_MBCTLS_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCTLS_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCTLS_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCCFG_DIS 28:28 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_MBCCFG_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCCFG_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_MBCCFG_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RMVP_DIS 27:27 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_RMVP_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RMVP_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_RMVP_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RMVP_CSB_DIS 26:26 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_RMVP_CSB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RMVP_CSB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_RMVP_CSB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RCOL_DIS 25:25 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_RCOL_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RCOL_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_RCOL_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RCOL_CSB_DIS 24:24 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_RCOL_CSB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_RCOL_CSB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_RCOL_CSB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_IF_DIS 23:23 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_PDMA_IF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_IF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_PDMA_IF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_DIS 22:22 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_PDMA_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_PDMA_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_AC_DIS 21:21 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_PDMA_AC_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_AC_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_PDMA_AC_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_CSB_DIS 20:20 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_PDMA_CSB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_PDMA_CSB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_PDMA_CSB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_BISATD_DIS 19:19 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_BISATD_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_BISATD_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_BISATD_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPSATD_DIS 18:18 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_HPSATD_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPSATD_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_HPSATD_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_CURMB_DIS 17:17 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_CURMB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_CURMB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_CURMB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_FPS_DIS 16:16 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_FPS_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_FPS_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_FPS_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPF_DIS 15:15 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_HPF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_HPF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MVPACK_DIS 14:14 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_MVPACK_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MVPACK_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_MVPACK_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_QPCTL_DIS 13:13 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_QPCTL_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_QPCTL_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_QPCTL_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_FBM_DIS 12:12 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_FBM_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_FBM_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_FBM_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_UVF_DIS 11:11 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_UVF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_UVF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_UVF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_WPRED_DIS 10:10 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_WPRED_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_WPRED_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_WPRED_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_CFG_DIS 9:9 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_CFG_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_CFG_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_CFG_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_LBUF_DIS 8:8 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_LBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_LBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_LBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPCTL_DIS 7:7 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_HPCTL_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPCTL_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_HPCTL_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPCOST_DIS 6:6 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_HPCOST_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_HPCOST_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_HPCOST_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MCINTF_DIS 5:5 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_MCINTF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_MCINTF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_MCINTF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_SPS_DIS 4:4 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_SPS_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_SPS_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_SPS_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_OFS_DIS 3:3 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_OFS_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_OFS_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_OFS_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_QPSATD_DIS 2:2 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_QPSATD_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_QPSATD_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_QPSATD_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_ICC_DIS 1:1 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_ICC_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_ICC_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_ICC_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_QS_DIS 0:0 /* RWIVF */
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#define NV_PNVENC_CG2_SLCG_ME_QS_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG2_SLCG_ME_QS_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG2_SLCG_ME_QS_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3(dev) (0x001c9204+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_CG3__SIZE_1 1 /* */
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#define NV_PNVENC_CG3_SLCG 31:0 /* RW-VF */
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#define NV_PNVENC_CG3_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_DISABLED 0xffffffff /* RW--V */
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#define NV_PNVENC_CG3_SLCG__PROD 0xffffffff /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_BICTL_DIS 31:31 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_ME_BICTL_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_BICTL_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_ME_BICTL_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_BUFADM_DIS 30:30 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_ME_BUFADM_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_BUFADM_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_ME_BUFADM_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_SRF_DIS 29:29 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_ME_SRF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_SRF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_ME_SRF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_QPCOST_DIS 28:28 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_ME_QPCOST_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_QPCOST_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_ME_QPCOST_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_PG_DIS 27:27 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_ME_PG_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_ME_PG_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_ME_PG_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_RHINT_CSB_DIS 26:26 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_RHINT_CSB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_RHINT_CSB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_RHINT_CSB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_RHINT_DIS 25:25 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_RHINT_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_RHINT_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_RHINT_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MEDMA_DIS 24:24 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MEDMA_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MEDMA_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MEDMA_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_HHREG_DIS 23:23 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_HHREG_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_HHREG_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_HHREG_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_NBBUF_DIS 22:22 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_NBBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_NBBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_NBBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_Q_IQ_DIS 21:21 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_Q_IQ_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_Q_IQ_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_Q_IQ_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_IDCT_DIS 20:20 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_IDCT_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_IDCT_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_IDCT_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBF_DIS 19:19 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_SSD_DIS 18:18 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_SSD_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_SSD_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_SSD_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_QBUF_DIS 17:17 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_QBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_QBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_QBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_DCT_DIS 16:16 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_DCT_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_DCT_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_DCT_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECBUF_DIS 15:15 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECON_DIS 14:14 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECON_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECON_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_RECON_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_CMDBUF_DIS 13:13 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_CMDBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_CMDBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_CMDBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_SSD_DIS 12:12 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_SSD_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_SSD_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_SSD_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DEBLKPARAM_DIS 11:11 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_DEBLKPARAM_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DEBLKPARAM_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DEBLKPARAM_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_CBUF_DIS 10:10 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_CBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_CBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_CBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBFDMA_DIS 9:9 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBFDMA_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBFDMA_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_DBFDMA_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_IDCT_DIS 8:8 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_IDCT_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_IDCT_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_HEVC_IDCT_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_PBUF_DIS 7:7 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_PBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_PBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_PBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_QPPBUF_DIS 6:6 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_QPPBUF_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_QPPBUF_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_QPPBUF_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_SAOPARAM_DIS 5:5 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_SAOPARAM_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_SAOPARAM_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_SAOPARAM_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_IPRED_DIS 4:4 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_IPRED_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_IPRED_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_IPRED_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_DCT_DIS 3:3 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_DCT_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_DCT_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MPEB_H264_DCT_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MDP_DIS 2:2 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MDP_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MDP_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MDP_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MDP_FMD_DIS 1:1 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MDP_FMD_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MDP_FMD_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MDP_FMD_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MDP_EMD_DIS 0:0 /* RWIVF */
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#define NV_PNVENC_CG3_SLCG_MDP_EMD_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG3_SLCG_MDP_EMD_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG3_SLCG_MDP_EMD_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4(dev) (0x001c9208+(dev)*16384) /* RW-4A */
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#define NV_PNVENC_CG4__SIZE_1 1 /* */
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#define NV_PNVENC_CG4_SLCG 31:0 /* RW-VF */
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#define NV_PNVENC_CG4_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_DISABLED 0xffffffff /* RW--V */
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#define NV_PNVENC_CG4_SLCG__PROD 0xffffffff /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MDP_CSB_DIS 31:31 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MDP_CSB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MDP_CSB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MDP_CSB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTR_DIS 30:30 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTR_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTR_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTR_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_HIST_CSB_DIS 29:29 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_HIST_CSB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_HIST_CSB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_HIST_CSB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTW_DIS 28:28 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTW_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTW_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_HIST_HISTW_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_WMVP_DIS 27:27 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_WMVP_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_WMVP_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_WMVP_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_WMVP_CSB_DIS 26:26 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_WMVP_CSB_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_WMVP_CSB_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_WMVP_CSB_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_SM_DIS 25:25 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_SM_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_SM_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_SM_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_STAT_DIS 24:24 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_STAT_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_STAT_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_STAT_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CAVLC_DIS 23:23 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_CAVLC_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CAVLC_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CAVLC_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_DIS 22:22 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_RES_DIS 21:21 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_RES_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_RES_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_RES_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H265_DIS 20:20 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H265_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H265_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H265_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CABAC_DIS 19:19 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_CABAC_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CABAC_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CABAC_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_DIS 18:18 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_HDR_DIS 17:17 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_HDR_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_HDR_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_HDR_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CNT_DIS 16:16 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_CNT_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CNT_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CNT_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_RES_DIS 15:15 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_RES_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_RES_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_VP8_RES_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265MEONLY_DIS 14:14 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265MEONLY_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265MEONLY_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265MEONLY_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265_SM_DIS 13:13 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265_SM_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265_SM_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H265_SM_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H264_SM_DIS 12:12 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_H264_SM_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H264_SM_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_H264_SM_DIS__PROD 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H264_DIS 11:11 /* RWIVF */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H264_DIS_ENABLED 0x1 /* RW--V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H264_DIS_DISABLED 0x0 /* RWI-V */
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#define NV_PNVENC_CG4_SLCG_MPEC_CODEC_H264_DIS__PROD 0x1 /* RW--V */
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#endif // __ga102_dev_nvenc_pri_sw_h__
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