8345 lines
1.1 MiB
8345 lines
1.1 MiB
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
#ifndef __ga102_dev_gsp_prgnlcl_h__
|
|
#define __ga102_dev_gsp_prgnlcl_h__
|
|
/* This file is autogenerated. Do not edit */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_MMODE 0x00000000 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_RISCV_CTL 0x00000001 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_PIC 0x00000002 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_TIMER 0x00000003 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_HOSTIF 0x00000004 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_DMA 0x00000005 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_PMB 0x00000006 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_DIO 0x00000007 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_KEY 0x00000008 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_DEBUG 0x00000009 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_SHA 0x0000000a /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_KMEM 0x0000000b /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_BROM 0x0000000c /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_ROM_PATCH 0x0000000d /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_IOPMP 0x0000000e /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_NOACCESS 0x0000000f /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_SCP 0x00000010 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_FBIF 0x00000011 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_FALCON_ONLY 0x00000012 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_PRGN_CTL 0x00000013 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_SCRATCH_GROUP0 0x00000014 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_SCRATCH_GROUP1 0x00000015 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_SCRATCH_GROUP2 0x00000016 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_SCRATCH_GROUP3 0x00000017 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_PLM 0x00000018 /* */
|
|
#define NV_PRGNLCL_DEVICE_MAP_GROUP_HUB_DIO 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK 0x0128027c /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK 0x01280280 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK 0x01280284 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x01280288 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK 0x0128028c /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x01280290 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x01280294 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK 0x012800e8 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK 0x012800ec /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse2" /* */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK 0x012800f0 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse2" /* */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DIODTA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK 0x01280298 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0128029c /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x012803d0 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK 0x012803c4 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x012803f0 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000014 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x012803f4 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000015 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x012803f8 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000016 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x012803fc /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000017 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK(i) (0x012803d8+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0128018c+(i)*16) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x012802b0+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK 0x01280190 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x01280194 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK 0x01280198 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0128019c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK 0x012801a0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x012801a4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x012801a8 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x012801b0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK 0x012801b8 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK 0x012801bc /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x012801e0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x012801e4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK 0x012801e8 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK 0x012801ec /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x012801f0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK 0x012801f4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x012801f8 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK 0x012801fc /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK 0x01280220 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x01280224 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK 0x01280228 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0128022c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET 0x01280000 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ1_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ2_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ3_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ4_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ5_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ6_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ7_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_EXT_EXTIRQ8_SET 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_SHA 17:17 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_ICD 22:22 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_CORE_MISMATCH 24:24 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR 0x01280004 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_ICD 22:22 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_CORE_MISMATCH 24:24 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCLR_CORE_MISMATCH_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT 0x01280008 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_CORE_MISMATCH 24:24 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_CORE_MISMATCH_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSTAT_CORE_MISMATCH_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE 0x0128000c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SHA 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SHA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SHA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_SHA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MEMERR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MEMERR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_MEMERR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_ICD 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_ICD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_ICD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_ICD_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_IOPMP_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_IOPMP_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_IOPMP_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CORE_MISMATCH_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CORE_MISMATCH_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMODE_LVL_CORE_MISMATCH_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK 0x012800e0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x012801a4 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SHA 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SHA_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_SHA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_MEMERR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_MEMERR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_ICD 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_ICD_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_ICD_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_IOPMP_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_IOPMP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQSCMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL(i) (0x012803e0+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_VECTOR 11:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_GFID 25:20 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_GFID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_GSP 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_GSP_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_GSP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_CPU 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_CPU_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_INTR_CTRL_CPU_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_INTR_RETRIGGER(i) (0x012803e8+(i)*4) /* -W-4A */
|
|
#define NV_PRGNLCL_FALCON_INTR_RETRIGGER__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_RETRIGGER__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_RETRIGGER__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_INTR_CTRL_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
|
|
#define NV_PRGNLCL_FALCON_INTR_RETRIGGER_TRIGGER_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET 0x01280010 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_HALT 4:4 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_DMA 16:16 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_SHA 17:17 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_ICD 22:22 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_CORE_MISMATCH 24:24 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR 0x01280014 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_SHA 17:17 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_ICD 22:22 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_IRQMCLR_CORE_MISMATCH 24:24 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK 0x01280018 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SHA 17:17 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_MEMERR 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_MEMERR_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_MEMERR_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_ICD 22:22 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_ICD_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_ICD_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_IOPMP 23:23 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_IOPMP_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_IOPMP_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST 0x0128001c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2 0x0128003c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_SHA 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_SHA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_SHA_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_SHA_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_MEMERR 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_MEMERR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_MEMERR_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_MEMERR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_ICD 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_ICD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_ICD_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_ICD_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_IOPMP 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_IOPMP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_IOPMP_FALCON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_IOPMP_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_CORE_MISMATCH 8:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_CORE_MISMATCH_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_CORE_MISMATCH_FALCON 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_HOST_CORE_MISMATCH_HOST 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_SHA 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_SHA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_SHA_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_SHA_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_MEMERR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_MEMERR_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_MEMERR_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_MEMERR_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_MEMERR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_ICD 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_ICD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_ICD_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_ICD_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_ICD_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_ICD_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_IOPMP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_IOPMP_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_IOPMP_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_IOPMP_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_IOPMP_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_CORE_MISMATCH 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_FALCON_IRQ0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_FALCON_IRQ1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_HOST_NORMAL 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRINT 0x01280020 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_GPTMRINT__DEVICE_MAP 0x00000003 /* */
|
|
#define NV_PRGNLCL_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x012801a0 /* */
|
|
#define NV_PRGNLCL_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRVAL 0x01280024 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_GPTMRVAL__DEVICE_MAP 0x00000003 /* */
|
|
#define NV_PRGNLCL_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x012801a0 /* */
|
|
#define NV_PRGNLCL_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL 0x01280028 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL__DEVICE_MAP 0x00000003 /* */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x012801a0 /* */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PTIMER0 0x0128002c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_PTIMER0__DEVICE_MAP 0x00000003 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x012801bc /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER0_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_PTIMER1 0x01280030 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_PTIMER1__DEVICE_MAP 0x00000003 /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x012801bc /* */
|
|
#define NV_PRGNLCL_FALCON_PTIMER1_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_WDTMRVAL 0x01280034 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_WDTMRVAL__DEVICE_MAP 0x00000003 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0128029c /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL 0x01280038 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL__DEVICE_MAP 0x00000003 /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0128029c /* */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDDATA 0x01280064 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_MTHDDATA__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDID 0x01280068 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_MTHDID__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDID__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_ID 11:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_PRIV 15:15 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_WPEND 16:16 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_MTHDWDAT 0x0128006c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_MTHDWDAT__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCOUNT 0x01280070 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_MTHDCOUNT__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_MTHDPOP 0x01280074 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_MTHDPOP__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDPOP_POP 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_MTHDRAMSZ 0x01280078 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_MTHDRAMSZ__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX 0x01280050 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CURCTX__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_CURCTX__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX 0x01280054 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CTXACK 0x01280058 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_CTXACK__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_CTXACK__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CURCTX2 0x012803c8 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CURCTX2__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_CURCTX2__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_CURCTX2_CTXGFID 5:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CURCTX2_CTXGFID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX2 0x012803cc /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX2__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX2__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX2_CTXGFID 5:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_NXTCTX2_CTXGFID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MAILBOX0 0x01280040 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MAILBOX1 0x01280044 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN 0x01280048 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ITFEN__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_ITFEN__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE 0x0128004c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x012801e0 /* */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_RISCV_BUSY 20:20 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_RISCV_BUSY_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_RISCV_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_INT_BUSY_SHA 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_INT_BUSY_SHA_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IDLESTATE_INT_BUSY_SHA_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE 0x0128005c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x012801e4 /* */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_RISCV_HALTED 20:20 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_RISCV_HALTED_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_FHSTATE_RISCV_HALTED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE 0x01280060 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x012803d0 /* */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_VPR_FORCE_STICKY 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_VPR_FORCE_STICKY_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_VPR_FORCE_STICKY_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PRIVSTATE_VPR_FORCE_STICKY_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SFTRESET 0x0128007c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SFTRESET__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_SFTRESET_EXT 0:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL 0x012800a4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL__PRIV_LEVEL_MASK 0x0128027c /* */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLREQ_MODE 4:4 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLREQ_MODE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLREQ_MODE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ADDR 0x012800ac /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ADDR__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_ADDR__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_ADDR_LSB 5:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_ADDR_LSB_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_ADDR_MSB 11:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ADDR_EXT 11:0 /* */
|
|
#define NV_PRGNLCL_FALCON_PRICFG 0x012800f8 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_PRICFG__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_PRICFG_ALL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMACTL 0x0128010c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMACTL__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_DCACHE_INVALIDATING 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_DCACHE_INVALIDATING_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_DCACHE_INVALIDATING_DONE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_ICACHE_INVALIDATING 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_ICACHE_INVALIDATING_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_ICACHE_INVALIDATING_DONE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE 0x01280110 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFMOFFS 0x01280114 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMATRFMOFFS__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD 0x01280118 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFFBOFFS 0x0128011c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMATRFFBOFFS__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB 0x01280120 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP 0x01280124 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE1 0x01280128 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE1__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMATRFBASE1_BASE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x012802c0 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_LOW__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x012802c4 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_HIGH__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x012802c8 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_LOW__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x012802cc /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_HIGH__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x012802d0 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_LOW__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x012802d4 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_HIGH__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x012802d8 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_LOW__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x012802dc /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_HIGH__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL 0x012802e0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_HIGH 0x012802e4 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_HIGH__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_LOW 0x012802e8 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_LOW__DEVICE_MAP 0x00000005 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x01280190 /* */
|
|
#define NV_PRGNLCL_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC(i) (0x01280180+(i)*16) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_IMEMC__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMC__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_BLK 23:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IMEMD(i) (0x01280184+(i)*16) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_IMEMD__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMD__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMD_DATA 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_IMEMT(i) (0x01280188+(i)*16) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_IMEMT__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMT__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_IMEMT_TAG 15:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC(i) (0x012801c0+(i)*8) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DMEMC__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMC__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_OFFS 7:2 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_OFFS_INIT 0 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_BLK 23:8 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_BLK_INIT 0 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_VA 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_MISS 29:29 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMD(i) (0x012801c4+(i)*8) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DMEMD__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMD__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMD_DATA 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMT(i) (0x01280210+(i)*4) /* -W-4A */
|
|
#define NV_PRGNLCL_FALCON_DMEMT__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMT__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMT_TAG 15:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_DMEML(i) (0x012802a0+(i)*4) /* -W-4A */
|
|
#define NV_PRGNLCL_FALCON_DMEML__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEML__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEML__PRIV_LEVEL_MASK NV_PRGNLCL_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRGNLCL_FALCON_DMEML_LVL 2:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB 0x01280170 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_IMEM 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_IMEM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_IMEM_LOCK 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_IMEM_UNLOCK 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_DMEM 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_DMEM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_DMEM_LOCK 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_LOCKPMB_DMEM_UNLOCK 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_DUMMY 0x01280258 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DMEM_DUMMY__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x01280284 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_DUMMY 0x012801b4 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_IMEM_DUMMY__DEVICE_MAP 0x00000006 /* */
|
|
#define NV_PRGNLCL_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x01280280 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_RESET_DELAY 0x01280274 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DIO_RESET_DELAY__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_RESET_DELAY__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_RESET_DELAY_VALUE 15:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_RESET_DELAY_VALUE_INIT 0x00000100 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL 0x01280340 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_COUNT 7:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_RESET 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_STOP 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_STOP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_EMPTY 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_EMPTY_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_WR_FINISHED 19:19 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_WR_FINISHED_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_RD_FINISHED 20:20 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_RD_FINISHED_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_WR_ERROR 21:21 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_WR_ERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_RD_ERROR 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_RD_ERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_PROTOCOL_ERROR 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DOC_CTRL_PROTOCOL_ERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DOC_D0 0x01280344 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DOC_D0__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_D0__PRIV_LEVEL_MASK 0x012800ec /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_D0_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DOC_D1 0x01280348 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DOC_D1__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_D1__PRIV_LEVEL_MASK 0x012800ec /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_D1_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DOC_D2 0x0128034c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DOC_D2__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_D2__PRIV_LEVEL_MASK 0x012800ec /* */
|
|
#define NV_PRGNLCL_FALCON_DOC_D2_DATA 15:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL 0x01280350 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL_COUNT 7:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL_RESET 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL_VALID 19:19 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL_VALID_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DIC_CTRL_POP 20:20 /* -W-VF */
|
|
#define NV_PRGNLCL_FALCON_DIC_D0 0x01280354 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DIC_D0__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_D0__PRIV_LEVEL_MASK 0x012800ec /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_D0_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIC_D1 0x01280358 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DIC_D1__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_D1__PRIV_LEVEL_MASK 0x012800ec /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_D1_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIC_D2 0x0128035c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DIC_D2__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_D2__PRIV_LEVEL_MASK 0x012800ec /* */
|
|
#define NV_PRGNLCL_FALCON_DIC_D2_DATA 15:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_ERR 0x01280360 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_DIO_ERR__DEVICE_MAP 0x00000007 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_ERR__PRIV_LEVEL_MASK 0x012800ec /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_ERR_INFO 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL(i) (0x01280370+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_COUNT 7:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_RESET 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_STOP 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_STOP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_EMPTY 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_EMPTY_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_WR_FINISHED 19:19 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_WR_FINISHED_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_RD_FINISHED 20:20 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_RD_FINISHED_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_WR_ERROR 21:21 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_WR_ERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_RD_ERROR 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_RD_ERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_PROTOCOL_ERROR 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_CTRL_PROTOCOL_ERROR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D0(i) (0x01280374+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D0__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D0__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D0__PRIV_LEVEL_MASK 0x012800f0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D0_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D1(i) (0x01280378+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D1__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D1__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D1__PRIV_LEVEL_MASK 0x012800f0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D1_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D2(i) (0x0128037c+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D2__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D2__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D2__PRIV_LEVEL_MASK 0x012800f0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DOC_D2_DATA 15:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL(i) (0x01280380+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL_COUNT 7:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL_RESET 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL_VALID 19:19 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL_VALID_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_CTRL_POP 20:20 /* -W-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D0(i) (0x01280384+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D0__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D0__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D0__PRIV_LEVEL_MASK 0x012800f0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D0_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D1(i) (0x01280388+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D1__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D1__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D1__PRIV_LEVEL_MASK 0x012800f0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D1_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D2(i) (0x0128038c+(i)*36) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D2__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D2__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D2__PRIV_LEVEL_MASK 0x012800f0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIC_D2_DATA 15:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIO_ERR(i) (0x01280390+(i)*36) /* R--4A */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIO_ERR__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIO_ERR__DEVICE_MAP 0x00000019 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIO_ERR__PRIV_LEVEL_MASK 0x012800f0 /* */
|
|
#define NV_PRGNLCL_FALCON_DIO_DIO_ERR_INFO 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x01280300+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0__DEVICE_MAP 0x00000014 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x012803f0 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x01280310+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1__DEVICE_MAP 0x00000015 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x012803f4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x01280320+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x012803f8 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x01280330+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3__DEVICE_MAP 0x00000017 /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x012803fc /* */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PRGNVER 0x012803d4 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG 0x01280108 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */
|
|
#define NV_PRGNLCL_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */
|
|
#define NV_PRGNLCL_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1 0x0128012c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000003 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2 0x012800f4 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_SHA 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_BMEM 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_KMEM 4:4 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_VHR 7:7 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_HS 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_HWCFG3 0x01280278 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_CGCTL 0x012800a0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CGCTL__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2 0x01280134 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_CG2__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2__PRIV_LEVEL_MASK 0x012801e8 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG 17:1 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_ENABLED 0 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG__PROD 0x000A0 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_SHA__PROD 1 /* */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_ENGID 0x0128013c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_ENGID_INSTID 7:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_ENGID_INSTID_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID 15:8 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_SEC 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_DPU 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_NVDEC 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_PWR_PMU 0x00000004 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_FBFACLON 0x00000005 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_NVENC 0x00000006 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_GPCCS 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_FECS 0x00000008 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_MINION 0x00000009 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_XUSB 0x0000000a /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_GSP 0x0000000b /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_NVJPG 0x0000000c /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_OFA 0x0000000d /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_PSC 0x0000000e /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGID_FAMILYID_SOE 0x0000000f /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ENGINE 0x012803c0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ENGINE__PRIV_LEVEL_MASK 0x012803c4 /* */
|
|
#define NV_PRGNLCL_FALCON_ENGINE_RESET 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL 0x01280240 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SCTL__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL__PRIV_LEVEL_MASK 0x01280298 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_LSMODE 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_HSMODE 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_UCODE_LEVEL 5:4 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL1 0x01280250 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SCTL1__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL 0x012800e4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_HSCTL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL__PRIV_LEVEL_MASK 0x012800e8 /* */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL 0x012802f4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x012801b0 /* */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_FUSE_OPT_RISCV_DCLS_EN 17:17 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_FUSE_OPT_RISCV_DCLS_EN_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN 11:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN_FALSE 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS 7:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_FALSE 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY 0x012803b8 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY__PRIV_LEVEL_MASK 0x012801b0 /* */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH 31:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH_TRUE 0x000000a5 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH_FALSE 0x0000005a /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT 23:16 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT_ENABLED 0x000000a5 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT_DISABLED 0x0000005a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET 15:8 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET_ENABLED 0x000000a5 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET_DISABLED 0x0000005a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT 7:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT_ENABLED 0x000000a5 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT_DISABLED 0x0000005a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_OS 0x01280080 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_OS__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_OS_VERSION 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_RM 0x01280084 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_RM__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_RM_CONFIG 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM 0x01280088 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x012801ec /* */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SOFT_MODE 0x0128008c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SOFT_MODE__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x012801ec /* */
|
|
#define NV_PRGNLCL_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM 0x012800a8 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_PMM__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_PMM__PRIV_LEVEL_MASK 0x012801ec /* */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL 19:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_REQ32BYTE 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_REQ64BYTE 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_REQ128BYTE 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_REQ32BYTE_SC 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_REQ64BYTE_SC 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_DSTAT_SEL_REQ128BYTE_SC 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0x0000000e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1 0x01280090 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1__DEVICE_MAP 0x00000004 /* */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x01280294 /* */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DEBUGINFO 0x01280094 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DEBUGINFO__DEVICE_MAP 0x00000013 /* */
|
|
#define NV_PRGNLCL_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN 0x01280270 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x012801f0 /* */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI 0x012800d0 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_EXCI__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI__PRIV_LEVEL_MASK 0x012801f4 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXPC 19:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_BROM_CALL_INS 0x00000015 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_KMEM_VIOLATION_INS 0x00000016 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXCAUSE_BMEM_PERMISSION_INS 0x00000017 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI2 0x012800bc /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_EXCI2__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI2__PRIV_LEVEL_MASK 0x012801f4 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR 0x012800d4 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x012801f8 /* */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL 0x01280100 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x01280288 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS 0x01280130 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG 0x01280138 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC 0x01280104 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x01280194 /* */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL 0x01280254 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x012801a8 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_VAL 9:0 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_VAL_INIT 0 /* */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_CYA 31:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1 0x01280098 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x012801fc /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_PC 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_EN 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2 0x0128009c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x012801fc /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_PC 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_EN 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3 0x012800b0 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x012801fc /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_PC 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_EN 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4 0x012800b4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x012801fc /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_PC 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_EN 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5 0x012800b8 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x012801fc /* */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_PC 23:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_EN 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD 0x01280200 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x01280220 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_PARM 31:16 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK 31:16 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_ADDR 0x01280204 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ICD_ADDR__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x01280220 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_WDATA 0x01280208 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_ICD_WDATA__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x01280220 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA 0x0128020c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x01280220 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */
|
|
#define NV_PRGNLCL_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0 0x012800d8 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x01280224 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_VALID 28:28 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3 0x012800dc /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX 0x01280148 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0128019c /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_TRACEPC 0x0128014c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_TRACEPC__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0128019c /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEPC_PC 23:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_TRACEINFO 0x0128017c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_TRACEINFO__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0128019c /* */
|
|
#define NV_PRGNLCL_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_IMCTL 0x01280140 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IMCTL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_CMD 26:24 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_DEBUG 0x0128015c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_DEBUG__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_IMSTAT 0x01280144 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IMSTAT__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_IMSTAT_VAL 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG0 0x01280150 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG0__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG1 0x01280154 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG1__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_IMFILLCTL 0x01280158 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_IMFILLCTL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMCTL 0x01280260 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMCTL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD 26:24 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMSTAT 0x01280264 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMSTAT__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DMSTAT_VAL 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_DMVACTL 0x01280268 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMVACTL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x01280198 /* */
|
|
#define NV_PRGNLCL_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMVACTL_BOUND_INIT 0x00000100 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA 0x0128026c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMCYA__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_DMCYA__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_LDSTVA_DIS 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_LDSTVA_DIS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_LDSTVA_DIS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROB_DIS 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROB_DIS_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROB_DIS_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROBWB_DIS 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROBWB_DIS_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROBWB_DIS_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROBSPR_DIS 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROBSPR_DIS_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMCYA_ROBSPR_DIS_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CMEMBASE 0x01280160 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CMEMBASE__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_CMEMBASE__PRIV_LEVEL_MASK 0x01280198 /* */
|
|
#define NV_PRGNLCL_FALCON_CMEMBASE_VAL 31:18 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CMEMBASE_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT 0x01280164 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_TIME_OUT 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_TIME_OUT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_TIME_UNIT 11:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_TIME_UNIT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_ENABLE 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_ENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_DMEMAPERT_LDSTQ_NUM 19:17 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT 0x0128016c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT__PRIV_LEVEL_MASK 0x01280228 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_PC 23:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_STAT 27:24 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_STAT_ACK_POS 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_STAT_ACK_TOUT 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_VALID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_VALID_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERRSTAT_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXTERRADDR 0x01280168 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_EXTERRADDR__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERRADDR__PRIV_LEVEL_MASK 0x01280228 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERRADDR_ADDR 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_INFO 0x0128025c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_INFO__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_INFO__PRIV_LEVEL_MASK 0x01280228 /* */
|
|
#define NV_PRGNLCL_FALCON_EXTERR_INFO_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT 0x01280244 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0128022c /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_ADDR 0x0128024c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_ADDR__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0128022c /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_INFO 0x01280248 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_INFO__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0128022c /* */
|
|
#define NV_PRGNLCL_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK 0x01281250 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK 0x0128125c /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK 0x01281254 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK 0x01281128 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK__SETLVL_SIGNAL "setlvlm" /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK__CLRLVL_SIGNAL "clrlvlm" /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG 0x01281004 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE 31:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA1 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA224 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA256 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA384 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA512 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA512_224 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA512_256 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_ALG 15:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_ALG_SHA 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_ALG_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_DST 4:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_DST_HASH_REG 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG_DST_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CONFIG__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_TASK_CONFIG 0x01281008 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_TASK_CONFIG__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_TASK_CONFIG__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR 0x0128100c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR_VAL 31:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR_HI 0x01281010 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR_HI__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR_HI_MSB 31:24 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR_HI_SZ 23:0 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_ADDR_HI__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LENGTH(i) (0x0128101c+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LENGTH__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LENGTH__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LENGTH_VAL 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LENGTH__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LEFT(i) (0x0128102c+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LEFT__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LEFT__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LEFT_VAL 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_MSG_LEFT__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_HASH_RESULT(i) (0x0128103c+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_SHA_HASH_RESULT__SIZE_1 16 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_HASH_RESULT__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_HASH_RESULT_VAL 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_HASH_RESULT__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION 0x0128107c /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_LAST_BUF 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_LAST_BUF_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_LAST_BUF_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_SOFTRESET 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_SOFTRESET_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_SOFTRESET_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_HALT 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_HALT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_HALT_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_OP 2:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_OP_NOP 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_OP_START 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION_OP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_OPERATION__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS 0x01281080 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS_STATE 2:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS_STATE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS_STATE_IDLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS_STATE_BUSY 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_STATUS_STATE_HALTED 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR 0x01281084 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI 0x01281088 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN 0x0128108c /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_UNSET 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_UNSET 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR 0x01281090 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI 0x01281094 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS 0x01281130 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_LEVEL_ERR 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_LEVEL_ERR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_LEVEL_ERR_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_LEVEL_ERR_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MULTI_HIT 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MULTI_HIT_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MULTI_HIT_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MULTI_HIT_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MISS 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MISS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MISS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_MISS_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_PA_FAULT 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_PA_FAULT_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_PA_FAULT_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_PA_FAULT_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_FBIF_ERR 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_FBIF_ERR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_FBIF_ERR_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_FBIF_ERR_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_NS_ACCESS 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_NS_ACCESS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_NS_ACCESS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS_NS_ACCESS_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_STATUS__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR 0x01281120 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR_VAL 31:0 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR_HI 0x01281124 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR_HI__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR_HI_MSB 31:24 /* R-XVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS 0x01281134 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_ERR_STATUS 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_ERR_STATUS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_ERR_STATUS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_ERR_STATUS_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_OP_DONE 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_OP_DONE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_OP_DONE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS_OP_DONE_CLEAR 1 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_STATUS__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE 0x01281138 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE_ERR_STATUS 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE_ERR_STATUS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE_ERR_STATUS_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE_OP_DONE 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE_OP_DONE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE_OP_DONE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_INT_ENABLE__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX 0x01281100 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_VAL 7:0 /* -W-VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_RELEASE 0x01281104 /* -W-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_RELEASE__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_RELEASE_VAL 7:0 /* -W-VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_RELEASE__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS 0x01281108 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS_LOCKED 7:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS_LOCKED_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG 0x01281110 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_FB_BASE 24:16 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_CTXDMA 6:4 /* RWXVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC 1:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_DMEM 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_IMEM 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_FB 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_SRC_CONFIG__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_REQ_CTRL 0x01281114 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_REQ_CTRL__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_REQ_CTRL_WINDOW 31:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_REQ_CTRL_WINDOW_INIT 0x00001000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_REQ_CTRL_LIMIT 15:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_REQ_CTRL_LIMIT_INIT 0x00000800 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_REQ_CTRL__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_CTRL 0x01281098 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_CTRL__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_CTRL__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_CTRL_FB_DIS 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_CTRL_FB_DIS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CTRL_FB_DIS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CYA 0x01281118 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_CYA__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_CYA_BW_THROTTLE_DIS 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_CYA_BW_THROTTLE_DIS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CYA_BW_THROTTLE_DIS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_CYA__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO 0x0128111c /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_PW_HALTED 13:13 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_PW_HALTED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_PW_HALTED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_IDMA_HALTED 12:12 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_IDMA_HALTED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_IDMA_HALTED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_ALU_HALTED 11:11 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_ALU_HALTED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_ALU_HALTED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_PW_IDLE 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_PW_IDLE_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_PW_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_IDMA_IDLE 9:9 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_IDMA_IDLE_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_IDMA_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_ALU_IDLE 8:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_ALU_IDLE_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_ALU_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_CORE_STATUS 6:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_CORE_STATUS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_CORE_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_SECURE_LEVEL 1:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_INFO_SECURE_LEVEL_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_0 0x01281140 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_0__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_0__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_0_SHA_SHA_PREPROC_STATE 11:10 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_0_SHA_WD_NUMBER 9:6 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_0_SHA_SHA_HASH_STATE 5:3 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_0_SHA_BYTE_COUNTER 2:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1 0x01281144 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN 17:17 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS 14:14 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_2 0x01281148 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_2__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_2__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_SIZE 23:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_ADDR 31:24 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_3 0x0128114c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_3__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_3__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_3_SHA_IDMA_RESP_DMA_ADDR 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_4 0x01281150 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_4__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_4__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_4_SHA_IDMA_RESP_DMA_ADDR 8:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_4_SHA_IDMA_CORRECTED_RESP_DMA_SIZE 31:11 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_5 0x01281154 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_5__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_5__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_5_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6 0x01281158 /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 12:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_IDMA_FREE_COUNT 21:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE 25:25 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE 26:26 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA 27:27 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_LASTBUF 28:28 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0 29:29 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7 0x0128115c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7__DEVICE_MAP 0x0000000a /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7__PRIV_LEVEL_MASK 0x01281128 /* */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_PVLD 25:25 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_READ 24:24 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PRDY 23:23 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PVLD 22:22 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PRDY 21:21 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PVLD 20:20 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_VALID 15:15 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_STALL 14:14 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_PVLD 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_STALL 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PVLD 7:7 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PRDY 6:6 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PVLD 5:5 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PRDY 4:4 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_REQ 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_BUSY 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_VER 0x01281188 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_VER_MAJOR 3:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_VER_MAJOR_DEFT 0x00000002 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_VER_MINOR 17:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_VER_MINOR_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_VER_BUGFIX 31:18 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_VER_BUGFIX_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_MOD_SEL 0x01281180 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_MOD_SEL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_MOD_SEL_ALGO 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MOD_SEL_ALGO_AES 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MOD_SEL_ALGO_RSA3K 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN 0x01281184 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN_AES 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN_AES_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN_AES_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN_RSA3K 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN_RSA3K_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_MOD_EN_RSA3K_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_PKCBROM_VER 0x0128118c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_PKCBROM_VER__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_PKCBROM_VER_DEV 11:0 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_PKCBROM_VER_ECO 15:12 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_PKCBROM_VER_MINOR 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_PKCBROM_VER_MAJOR 31:24 /* R--VF */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE 0x01281190 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL_SEC 0x00008200 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL_PWR_PMU 0x000083f0 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL_NVDEC 0x00008490 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL_GSP 0x000087a0 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL_SOE 0x00008200 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL_PSC 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_BASE_VAL_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM 0x012811e8 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL_SEC 0x0000000a /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL_PWR_PMU 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL_NVDEC 0x00000010 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL_GSP 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL_SOE 0x0000000a /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL_PSC 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_VHRCFG_ENTNUM_VAL_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_BMEMBASE 0x01281194 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_BMEMBASE__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_BMEMBASE_VAL 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_BMEMBASE_VAL_DEFT 0x02100000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_CURR_UCODE_ID 0x01281198 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_BROM_CURR_UCODE_ID__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_CURR_UCODE_ID__PRIV_LEVEL_MASK 0x01281250 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_CURR_UCODE_ID_VAL 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_CURR_UCODE_ID_VAL_DEFT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_CURR_UCODE_ID_VAL_MAX 0x00000010 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_UCODE_VERSION(i) (0x012811a8+(i)*4) /* R-I4A */
|
|
#define NV_PRGNLCL_FALCON_UCODE_VERSION__SIZE_1 16 /* */
|
|
#define NV_PRGNLCL_FALCON_UCODE_VERSION__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_FALCON_UCODE_VERSION_VER 7:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_UCODE_VERSION_VER_DEF 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK 0x0128119c /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK__PRIV_LEVEL_MASK 0x01281250 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_SEC 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_SEC_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_SEC_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_DPU 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_DPU_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_DPU_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVDEC 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVDEC_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVDEC_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_PMU 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_PMU_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_PMU_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_FBFALCON 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_FBFALCON_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_FBFALCON_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVENC 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVENC_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVENC_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_GPCCS 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_GPCCS_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_GPCCS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_FECS 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_FECS_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_FECS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_MINION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_MINION_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_MINION_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_XUSB 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_XUSB_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_XUSB_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_GSP 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_GSP_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_GSP_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVJPG 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVJPG_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_NVJPG_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_OFA 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_OFA_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_OFA_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_PSC 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_PSC_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_PSC_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_SOE 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_SOE_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_ENGIDMASK_SOE_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL 0x012811ec /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL__PRIV_LEVEL_MASK 0x0128125c /* */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_VALID 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_VALID 8:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY 9:9 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_PR_CTKID 0x012811f0 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_PR_CTKID__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_FALCON_PR_CTKID_VAL 7:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_PR_CTKID_VAL_DEF 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID 0x012811a0 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID 7:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_DECFUSEKEY 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_GENTK 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_DECMPK 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_SIGBYMPK 0x00000004 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_CLRMPK 0x00000005 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_ECDSASIGN 0x00000006 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_ID_ECDSAVERIF 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_CALLER_LVL 9:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_CALLER_LVL_0 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_CALLER_LVL_1 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_CALLER_LVL_2 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_FUNID_CALLER_LVL_3 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_BROM_PARAADDR(i) (0x01281210+(i)*4) /* RWI4A */
|
|
#define NV_PRGNLCL_FALCON_BROM_PARAADDR__SIZE_1 1 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_PARAADDR__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_PARAADDR__PRIV_LEVEL_MASK 0x01281250 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_PARAADDR_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_PARAADDR_VAL_DEFT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE 0x012811a4 /* RW-4R */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_SUCCESS 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLFUNID 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_PA_FAULT 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NOT_IN_DMEM 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NO_ENOUGH_SPACE 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_VA_NOT_VALID 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_4BYTES 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_16BYTES 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_32BYTES 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_OUTPUT_NOT_ALLOWED 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_TK_PTR_IS_NS_READABLE 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_NOT_CALLED_BY_HS 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_CALL_FROM_LVL0 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLUCODEID 0x0000000d /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_DISPOSE_MPK_FAIL 0x0000000e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_CTKID_INVALID 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLTKID 0x00000010 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_INVLDPMUK 0x00000011 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_INVLDPDUK 0x00000012 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_INVLDMPK 0x00000013 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_SIGFAIL 0x00000014 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_PDI_INVALID 0x00000015 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_LOAD_KMEM2SCP_FAIL 0x00000016 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_WRONG_PROTECTINFO 0x00000017 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_KSLT_K3_IS_0 0x00000018 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF16B 0x00000019 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF32B 0x0000001a /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_RSVD_ZEROS 0x0000001b /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_MPK_IS_VALID 0x0000001c /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_SCP_ERR 0x0000001d /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_256BYTES 0x0000001e /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERRID 19:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERRID_DEFT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_FUNID 23:20 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_FUNID_DEFT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERRINFO 31:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_BROM_RETCODE_ERRINFO_DEFT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMBASE 0x012811f4 /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_KMEMBASE__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEMBASE_VAL 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMBASE_VAL_DEF 0x02000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC(i) (0x012811f8+(i)*4) /* RWI4A */
|
|
#define NV_PRGNLCL_FALCON_KMEMC__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEMC__DEVICE_MAP 0x0000000b /* */
|
|
#define NV_PRGNLCL_FALCON_KMEMC__PRIV_LEVEL_MASK 0x01281254 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_OFFS 15:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_OFFS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_OFFS_PROTINFO 0x00000400 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_OFFS_MAX 0x000005ff /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_AINCW 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_AINCW_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_AINCW_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_AINCR 25:25 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_AINCR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_AINCR_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR 28:26 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_SUCCESS 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_1 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_2 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_3 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_4 0x00000004 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_5 0x00000005 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_6 0x00000006 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMC_ERR_7 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMD(i) (0x01281200+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FALCON_KMEMD__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEMD__DEVICE_MAP 0x0000000b /* */
|
|
#define NV_PRGNLCL_FALCON_KMEMD__PRIV_LEVEL_MASK 0x01281254 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEMD_DATA 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL 0x01281208 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL__DEVICE_MAP 0x0000000b /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL__PRIV_LEVEL_MASK 0x01281254 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_IDX 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_IDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_CMD 19:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_CMD_NOP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_CMD_DISPOSE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_CMD_LOADTO63 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT 23:20 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_NOP 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_DISPOSE_DONE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_RECYCLABLE_IS_0 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_PRIVDISABLED 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_NOTWRITEABLE 0x00000004 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_LOADTO63_DONE 0x00000005 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_LOADABLE_IS_0 0x00000006 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_PRIVDISABLED 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_UCODIDMASK_IS_0 0x00000008 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_SLOT_MASK 0x00000009 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_SLOT_MASK 0x0000000a /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG 0x0128120c /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_NUMOFKSLT 15:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_NUMOFKSLT_DEFT 0x00000100 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_KSLT_LENGTH 21:16 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_KSLT_LENGTH_DEFT 0x00000010 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_PROTECTINFO_LENGTH 25:22 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_PROTECTINFO_LENGTH_DEFT 0x00000008 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_BROM_USED_SLOTS 31:26 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEMCFG_BROM_USED_SLOTS_DEFT 0x00000010 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VALID(i) (0x01281218+(i)*4) /* R-I4A */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VALID__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VALID__DEVICE_MAP 0x0000000b /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VALID__PRIV_LEVEL_MASK 0x01281254 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VALID_VAL 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VALID_VAL_DEFT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VIOLATION_CTL 0x01281238 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VIOLATION_CTL__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VIOLATION_CTL__PRIV_LEVEL_MASK 0x01281254 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VIOLATION_CTL_ACT 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VIOLATION_CTL_ACT_HALT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_VIOLATION_CTL_ACT_EXC 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF 0x0128123c /* R-I4R */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF__DEVICE_MAP 0x00000012 /* */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_READ 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_WRITE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL 5:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID 15:8 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX 23:16 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_KSLT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_PROTINFO 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KMEM_SLOT_MASK 0x01281240 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_KMEM_SLOT_MASK__DEVICE_MAP 0x00000008 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_SLOT_MASK__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_FALCON_KMEM_SLOT_MASK_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KMEM_SLOT_MASK_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL 0x01281248 /* RWI4R */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_INDEX 7:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_INDEX_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_VALID 16:16 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_BUSY 17:17 /* R-IVF */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_BUSY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_RELOAD 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_CTRL_STAT_RELOAD_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_DATA 0x0128124c /* R--4R */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_DATA__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_DATA__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_FALCON_KEYGLOB_DATA_VAL 31:0 /* R-XVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK 0x01281304 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK 0x01281308 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK 0x01281300 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK 0x01281314 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK 0x01281310 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK 0x01281664 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK 0x01281690 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK 0x0128130c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK 0x01281318 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK 0x0128131c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET 0x01281520 /* -W-4R */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_HALT 4:4 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT 15:8 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ1 8:8 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ1_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ2 9:9 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ2_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ3 10:10 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ3_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ4 11:11 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ4_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ5 12:12 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ5_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ6 13:13 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ6_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ7 14:14 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ7_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ8 15:15 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_EXT_EXTIRQ8_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_DMA 16:16 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_SHA 17:17 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_ICD 22:22 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_CORE_MISMATCH 24:24 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR 0x01281524 /* -W-4R */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_HALT 4:4 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT 15:8 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ1 8:8 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ1_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ2 9:9 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ2_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ3 10:10 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ3_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ4 11:11 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ4_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ5 12:12 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ5_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ6 13:13 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ6_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ7 14:14 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ7_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ8 15:15 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_EXT_EXTIRQ8_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_DMA 16:16 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_SHA 17:17 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_ICD 22:22 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMCLR_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK 0x01281528 /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_GPTMR 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_GPTMR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_GPTMR_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_WDTMR 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_WDTMR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_WDTMR_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_MTHD 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_MTHD_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_MTHD_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_CTXSW 3:3 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_CTXSW_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_CTXSW_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_HALT 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_HALT_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_HALT_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXTERR 5:5 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXTERR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXTERR_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SWGEN0 6:6 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SWGEN0_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SWGEN0_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SWGEN1 7:7 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SWGEN1_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SWGEN1_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ1_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ1_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ2_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ2_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ3_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ3_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ4_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ4_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ5_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ5_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ6_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ6_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ7_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ7_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ8_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_EXT_EXTIRQ8_SET 1 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_DMA 16:16 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_DMA_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_DMA_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SHA 17:17 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SHA_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_SHA_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_MEMERR 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_MEMERR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_MEMERR_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_ICD 22:22 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_ICD_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_ICD_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_IOPMP 23:23 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_IOPMP_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_IOPMP_SET 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST 0x0128152c /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_GPTMR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_GPTMR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_WDTMR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_WDTMR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_MTHD_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_MTHD_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_CTXSW_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_CTXSW_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_HALT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_HALT_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_HALT_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXTERR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXTERR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SWGEN0_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SWGEN0_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SWGEN1_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SWGEN1_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ1 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ1_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ2 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ2_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ3 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ3_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ4 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ4_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ5 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ5_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ6 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ6_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ7 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ7_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ8 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ8_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_DMA 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_DMA_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_DMA_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SHA 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SHA_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_SHA_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_MEMERR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_MEMERR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_ICD 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_ICD_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_ICD_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_IOPMP_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_IOPMP_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_CORE_MISMATCH_RISCV 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IRQDEST_CORE_MISMATCH_HOST 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE 0x01281530 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_GPTMR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_WDTMR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_MTHD_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_CTXSW_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_HALT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_HALT_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXTERR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SWGEN0_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SWGEN1_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ1 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ2 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ3 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ4 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ5 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ6 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ7 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ8 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_DMA 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_DMA_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_DMA_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SHA 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SHA_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_SHA_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_MEMERR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_MEMERR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_ICD 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_ICD_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_ICD_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_IOPMP_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_IOPMP_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_CORE_MISMATCH 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG 0x01281534 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG__PRIV_LEVEL_MASK 0x01280290 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_GPTMR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_GPTMR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_WDTMR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_WDTMR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_MTHD_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_MTHD_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_CTXSW_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_CTXSW_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_HALT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_HALT_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_HALT_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXTERR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXTERR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SWGEN0_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SWGEN0_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SWGEN1_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SWGEN1_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT 15:8 /* */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ1 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ1_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ1_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ2 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ2_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ2_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ3 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ3_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ3_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ4 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ4_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ4_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ5 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ5_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ5_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ6 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ6_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ6_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ7 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ7_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ7_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ8 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ8_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_EXT_EXTIRQ8_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_DMA 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_DMA_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_DMA_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SHA 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SHA_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_SHA_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_MEMERR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_MEMERR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_ICD 22:22 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_ICD_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_ICD_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_IOPMP_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_IOPMP_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_MEIP 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_SEIP 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_HI 0x01281384 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_HI__PRIV_LEVEL_MASK 0x01281310 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_HI_VECTOR 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_HI_VECTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_LO 0x01281380 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_LO__PRIV_LEVEL_MASK 0x01281310 /* */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_LO_VECTOR 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BOOT_VECTOR_LO_VECTOR_INIT 0x00080000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL 0x01281388 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL__PRIV_LEVEL_MASK 0x01281308 /* */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_HALTED_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG 0x01281390 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG__PRIV_LEVEL_MASK 0x0128130c /* */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_WR_ALLOC_EN 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_WR_ALLOC_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_LD_MERGE_EN 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_LD_MERGE_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_VB_FWD_EN 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_VB_FWD_EN_RST 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_WRITE_BACK_EN 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_WRITE_BACK_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_TLB_FIX_SIZE_EN 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_TLB_FIX_SIZE_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_SYSOP_CSR_EN 9:9 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_SYSOP_CSR_EN_RST 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_FENCE_FBFLUSH_EN 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_NVCONFIG_FENCE_FBFLUSH_EN_RST 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_CG 0x01281398 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_CG__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CG__PRIV_LEVEL_MASK 0x01281304 /* */
|
|
#define NV_PRGNLCL_RISCV_CG_SLCG 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CG_SLCG_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CG_SLCG_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CG_SLCG_DISABLED 0 /* */
|
|
#define NV_PRGNLCL_RISCV_CG_SLCG_ENABLED 1 /* */
|
|
#define NV_PRGNLCL_RISCV_CG_SLCG__PROD 1 /* */
|
|
#define NV_PRGNLCL_RISCV_CG_CORE_SLCG 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CG_CORE_SLCG_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_CG_CORE_SLCG_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_CG_RSVD 31:2 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_CG_RSVD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_CYA 0x0128139c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_CYA__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_CYA__PRIV_LEVEL_MASK 0x01281304 /* */
|
|
#define NV_PRGNLCL_RISCV_CYA_RSVD 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_CYA_RSVD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL 0x012813c8 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL__PRIV_LEVEL_MASK 0x01281314 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_RSVD1 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_J 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_J_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_J_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_EMASK 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RREG 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WREG 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RDM 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WDM 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WDM_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WDM_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RSTAT 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RCSR 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RCSR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RCSR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WCSR 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WCSR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WCSR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RPC 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RPC_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RPC_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RFREG 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RFREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_RFREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WFREG 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WFREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_ICD_CMDWL_WFREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_RSVD 29:17 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_RSVD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_START_IN_ICD 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_START_IN_ICD_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_START_IN_ICD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_SINGLE_STEP_MODE 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_SINGLE_STEP_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_SINGLE_STEP_MODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK 0x012813cc /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK__PRIV_LEVEL_MASK 0x01281314 /* */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_RSVD1 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_J 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG 6:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_RSVD 30:17 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_RSVD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD 0x012813d0 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC 4:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_STOP 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_J 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_RCSR 0x00000010 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_WCSR 0x00000011 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_RPC 0x00000012 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_RFREG 0x00000013 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_OPC_WFREG 0x00000014 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_SZ 7:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_SZ_B 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_SZ_HW 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_SZ_W 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_SZ_DW 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX 12:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG0 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG16 0x00000010 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG17 0x00000011 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG18 0x00000012 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG19 0x00000013 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG20 0x00000014 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG21 0x00000015 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG22 0x00000016 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG23 0x00000017 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG24 0x00000018 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG25 0x00000019 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG26 0x0000001a /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG27 0x0000001b /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG28 0x0000001c /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG29 0x0000001e /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG30 0x0000001e /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_REG31 0x0000001f /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_ERROR 14:14 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_ERROR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_BUSY 15:15 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_BUSY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_PARM 31:16 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_CMD_PARM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR0 0x012813d4 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR0__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR0_ADDR 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR0_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR1 0x012813d8 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR1__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR1_ADDR 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_ADDR1_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA0 0x012813dc /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA0__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA0_DATA 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA0_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA1 0x012813e0 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA1__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA1_DATA 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_ICD_WDATA1_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0 0x012813e4 /* R--4R */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_DATA 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_ROB_FULL 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_SSINT 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_SSINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_SSINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MSINT 3:3 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MSINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MSINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_STINT 5:5 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_STINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_STINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MTINT 7:7 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MTINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MTINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_SEINT 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_SEINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_SEINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MEINT 11:11 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MEINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT3_MEINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE 1:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ACTIVE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_INACTIVE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ICD 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_RS0 3:2 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_RS0_VALUE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_TRIGGER_HIT_INDEX 10:4 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_RS1 31:11 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA0_RSTAT4_RS1_VALUE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1 0x012813e8 /* R--4R */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_DATA 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IAMA 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IAMA_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IAMA_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IFAULT 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_ILL 2:2 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_ILL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_ILL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_BKPT 3:3 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_BKPT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_BKPT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LAMA 4:4 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LAMA_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LAMA_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LFAULT 5:5 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SAMA 6:6 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SAMA_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SAMA_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SFAULT 7:7 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_UCALL 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_UCALL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_UCALL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SCALL 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SCALL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SCALL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_MCALL 11:11 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_MCALL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_MCALL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IPFAULT 12:12 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LPFAULT 13:13 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SPFAULT 15:15 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP 28:28 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP 29:29 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT4_RS 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_ICD_RDATA1_RSTAT4_RS_VALUE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_RPC 0x012813ec /* R--4R */
|
|
#define NV_PRGNLCL_RISCV_RPC__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_RPC_PC_LO 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0 0x012813f0 /* R--4R */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_ROB_FULL 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL 0x01281400 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL__PRIV_LEVEL_MASK 0x01281318 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_LOW_THSHD 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_LOW_THSHD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_HIGH_THSHD 15:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_HIGH_THSHD_INIT 0x000000ff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_UMODE_ENABLE 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_UMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_UMODE_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_SMODE_ENABLE 21:21 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_SMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_SMODE_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_MMODE_ENABLE 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_MMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_MMODE_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_MODE 25:24 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_MODE_FULL 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_MODE_REDUCED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_MODE_STACK 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_BELOW_LO 27:27 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_BELOW_LO_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_ABOVE_HI 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_ABOVE_HI_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_INTR_ENABLE 29:29 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_INTR_ENABLE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_INTR_ENABLE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_FULL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_EMPTY 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACECTL_EMPTY_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX 0x01281404 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX__PRIV_LEVEL_MASK 0x01281318 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_RDIDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_RSVD0 15:8 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_RSVD0_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_MAXIDX_INIT 0x0000003f /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_RSVD1 31:24 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_TRACE_RDIDX_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_TRACE_WTIDX 0x01281408 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_TRACE_WTIDX__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACE_WTIDX__PRIV_LEVEL_MASK 0x01281318 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACE_WTIDX_WTIDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACE_WTIDX_RSVD1 23:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_TRACE_WTIDX_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_HI 0x01281410 /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_HI__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_HI__PRIV_LEVEL_MASK 0x01281318 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_HI_PC 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_HI_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_LO 0x0128140c /* RW-4R */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_LO__DEVICE_MAP 0x00000009 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_LO__PRIV_LEVEL_MASK 0x01281318 /* */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_LO_PC 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_TRACEPC_LO_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_HI 0x012813c4 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_HI__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_HI__PRIV_LEVEL_MASK 0x01281300 /* */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_HI_VALUE 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_HI_VALUE_INIT 0xffffffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_LO 0x012813c0 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_LO__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_LO__PRIV_LEVEL_MASK 0x01281300 /* */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_LO_VALUE 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MTIMECMP_LO_VALUE_INIT 0xffffffff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS 0x01281394 /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS__PRIV_LEVEL_MASK 0x01281300 /* */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_S_SOFTWARE_INTR 5:5 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_S_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_S_EXTERNAL_INTR 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_S_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_S_TIMER_INTR 3:3 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_S_TIMER_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_SOFTWARE_INTR 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_M_SOFTWARE_INTR 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_M_SOFTWARE_INTR_INIT 0 /* */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_EXTERNAL_INTR 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_M_EXTERNAL_INTR 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_M_EXTERNAL_INTR_INT 0 /* */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_TIMER_INTR 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_TIMER_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_M_TIMER_INTR 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_INTR_STATUS_M_TIMER_INTR_INIT 0 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP 0x0128138c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_MSIP__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP__PRIV_LEVEL_MASK 0x0128131c /* */
|
|
#define NV_PRGNLCL_RISCV_MSIP_VLD 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_MSIP_VLD_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_MSIP_VLD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT 0x01281500 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT_RESERVED 30:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_INFO 0x01281504 /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_INFO__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_INFO__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_INFO_ERROR_INFO 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_INFO_ERROR_INFO_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR 0x01281508 /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR_HI 0x0128150c /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR_HI__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_PRIV_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT 0x01281510 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT__DEVICE_MAP 0x00000002 /* */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT__PRIV_LEVEL_MASK 0x0128028c /* */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT_RESERVED 30:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_HUB_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_INDEX 0x01281590 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_INDEX__DEVICE_MAP 0x0000000d /* */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_INDEX_INDEX 4:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_INDEX_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_ADDR_VALID 0x01281594 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_ADDR_VALID__DEVICE_MAP 0x0000000d /* */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR 17:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_DATA 0x01281598 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_DATA__DEVICE_MAP 0x0000000d /* */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_DATA_DATA 15:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_CAM_DATA_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_SECURE 0x0128159c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_SECURE__DEVICE_MAP 0x0000000d /* */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_INDEX 0x012815b0 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_INDEX__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_INDEX__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_INDEX_VAL 4:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_INDEX_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG 0x012815b4 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_READ 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_READ_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_READ_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_WRITE 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_WRITE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_WRITE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER 15:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_ALL_MASTERS_ENABLED 0x00000ff7 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_FBDMA 4:4 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_FBDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_FBDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_CPDMA 5:5 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_CPDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_CPDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_SHA 6:6 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_SHA_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_SHA_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_PMB(i) (8+(i)):(8+(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_PMB__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_PMB_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_MASTER_PMB_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_LOCK 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_CFG_LOCK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_HI 0x012815bc /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_HI__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_HI__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_HI_VAL 28:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO 0x012815b8 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO_VAL 31:0 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO_ABOVE1K 31:7 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO_ABOVE1K_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO_1K 6:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ADDR_LO_1K_INIT 0x0000007f /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE(i) (0x012815c0+(i)*4) /* RWI4A */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE_VAL_ENTRY(i) (1+2*(i)):(2*(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE_VAL_ENTRY__SIZE_1 16 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE_VAL_ENTRY_OFF 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_MODE_VAL_ENTRY_NAPOT 0x00000003 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_STAT 0x012815e0 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_STAT__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_STAT__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_STAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_STAT_VALID_TURE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO 0x012815e4 /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER 3:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_FBDMA 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_CPDMA 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_SHA 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB0 0x00000004 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB1 0x00000005 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB2 0x00000006 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB3 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB4 0x00000008 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB5 0x00000009 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB6 0x0000000a /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_MASTER_PMB7 0x0000000b /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_READ 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_READ_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_READ_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_ENTRY 21:16 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_INFO_ENTRY_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_HI 0x012815ec /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_HI__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_LO 0x012815e8 /* R-I4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_LO__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_LO__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_LO_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_ADDR_LO_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN 0x012815f0 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN__DEVICE_MAP 0x0000000e /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER 11:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_ALL_MASTERS_ENABLED 0x00000fff /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA 0:0 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA 1:1 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA 2:2 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB(i) (4+(i)):(4+(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFMOFFS 0x01281570 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFMOFFS__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFMOFFS__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFMOFFS_OFFS 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD 0x01281574 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SUPPRESS 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SUPPRESS_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SUPPRESS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SHORTCUT 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SHORTCUT_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SHORTCUT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_IMEM 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_IMEM_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_WRITE 5:5 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_WRITE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_GPR 8:6 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_GPR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE 8:6 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_16B 2 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_32B 3 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_64B 4 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_128B 5 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_256B 6 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_CCI_EX 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_CCI_EX_SCPDMA 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_CCI_EX_CCI 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_CCI_CMD 31:16 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_CCI_CMD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_RY 19:16 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_RX_OR_IMM 25:20 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE 31:26 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_NOP 0 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_MOV 1 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_PUSH 2 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_FETCH 3 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_RAND 4 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE0 5 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE0 6 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE1 7 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_CHMOD 10 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_XOR 11 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_ADD 12 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_AND 13 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_BSWAP 14 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_CMAC_SK 15 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_SECRET 16 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_KEY 17 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_RKEY10 18 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_RKEY1 19 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT 20 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_DECRYPT 21 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_COMPARE_SIG 22 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT_SIG 23 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMATRFCMD_OPCODE_FORGET_SIG 24 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL 0x01281578 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_DMA_ACTIVE 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_DMA_ACTIVE_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_DMA_ACTIVE_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_ERROR_CLR 4:4 /* -WXVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_ERROR_CODE 9:8 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_ERROR_CODE_NO_ERROR 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_ERROR_CODE_NOT_SIZE_ALIGNED 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_ERROR_CODE_SECRET_NOT_ALLOWED 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_WCOUNT 19:16 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_WCOUNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_RCOUNT 23:20 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_RCOUNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_REQQ_NUM 27:24 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_REQQ_NUM_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_SCPDMAPOLL_REQQ_DEPTH 31:28 /* R-XVF */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK(i) (0x01281580+(i)*4) /* RWI4A */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK__DEVICE_MAP 0x00000008 /* */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_LOCK(i) (0x01281588+(i)*4) /* RWI4A */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_LOCK__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_LOCK__DEVICE_MAP 0x00000008 /* */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_LOCK__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_LOCK_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_SCP_SECRET_MASK_LOCK_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE 0x0128165c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_RESULT 1:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_RESULT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_RESULT_RUNNING 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_RESULT_FAIL 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_RESULT_PASS 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE 7:2 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_ENTRY 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_INIT_DEVICE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_LOAD_PUBLIC_KEY 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_LOAD_PKC_BOOT_PARAM 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_SHA_MANIFEST 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_VERIFY_MANIFEST_SIGNATURE 0x00000005 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_DECRYPT_MANIFEST 0x00000006 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_SANITIZE_MANIFEST 0x00000007 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_LOAD_FMC 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_VERIFY_FMC_DIGEST 0x00000009 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_DECRYPT_FMC 0x0000000a /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_DECRYPT_FUSEKEY 0x0000000b /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_REVOKE_RESOURCE 0x0000000c /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_PHASE_CONFIGURE_FMC_ENV 0x0000000d /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME 17:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_DMA_FB_ADDRESS_ERROR 0x00000020 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_DMA_NACK_ERROR 0x00000021 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SHA_ACQUIRE_MUTEX_ERROR 0x00000040 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SHA_EXECUTION_ERROR 0x00000041 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_DIO_READ_ERROR 0x00000060 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_DIO_WRITE_ERROR 0x00000061 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SE_PDI_INVALID_ERROR 0x00000080 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SE_PKEYHASH_INVALID_ERROR 0x00000081 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SW_PKEY_DIGEST_ERROR 0x00000082 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SE_PKA_RETURN_CODE_ERROR 0x00000083 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SCP_LOAD_SECRET_ERROR 0x000000a0 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_SCP_TRAPPED_DMA_NOT_ALIGNED_ERROR 0x000000a1 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CODE_SIZE_ERROR 0x000000c0 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CORE_PMP_RESERVATION_ERROR 0x000000c1 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DATA_SIZE_ERROR 0x000000c2 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DEVICEMAP_BR_UNLOCK_ERROR 0x000000c3 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_FAMILY_ID_ERROR 0x000000c4 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_MSPM_VALUE_ERROR 0x000000c5 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_PAD_INFO_MASK_ERROR 0x000000c6 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ADDRESS_ERROR 0x000000c7 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ENTRY_NUM_ERROR 0x000000c8 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_ERROR 0x000000c9 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_LOCK_ERROR 0x000000ca /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SIGNATURE_ERROR 0x000000cb /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_ID_ERROR 0x000000cc /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_VERSION_ERROR 0x000000cd /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_FMC_DIGEST_ERROR 0x000000e0 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_BAD_HEADER_ERROR 0x00000100 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_KEYGLOB_INVALID_ERROR 0x00000101 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_PROTECT_INFO_ERROR 0x00000102 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_SIGNATURE_ERROR 0x00000103 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_KMEM_DISPOSE_KSLOT_ERROR 0x00000120 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_KMEM_KEY_SLOT_K3_ERROR 0x00000121 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_KMEM_LOAD_KSLOT2SCP_ERROR 0x00000122 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_KMEM_READ_ERROR 0x00000123 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_KMEM_WRITE_ERROR 0x00000124 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_IOPMP_ERROR 0x00000141 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_MMIO_ERROR 0x00000142 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_SYNDROME_OK 0x000003ff /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO 31:18 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_DMA_WAIT_FOR_IDLE_HANG 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_SHA_HANG 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_DIO_READ_HANG 0x00000004 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_DIO_WAIT_FREE_ENTRY_HANG 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_DIO_WRITE_HANG 0x00000010 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_SE_ACQUIRE_MUTEX_HANG 0x00000020 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_SE_PDI_LOAD_HANG 0x00000040 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_SE_PKEYHASH_LOAD_HANG 0x00000080 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_PKA_POLL_RESULT_HANG 0x00000100 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_SCP_PIPELINE_RESET_HANG 0x00000200 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_TRAPPED_DMA_HANG 0x00000400 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_FUSEKEY_KEYGLOB_LOAD_HANG 0x00000800 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_RETCODE_INFO_KMEM_CMD_EXECUTE_HANG 0x00001000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN 0x01281660 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN__DEVICE_MAP 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN__PRIV_LEVEL_MASK 0x012801b8 /* */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN_LOCK 0:0 /* RW-VF */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN_LOCK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN_LOCK_UNLOCKED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_FALSE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_TRUE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_FALSE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_TRUE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL 0x01281668 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_CORE_SELECT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_CORE_SELECT_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_CORE_SELECT_RISCV 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_BRFETCH 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_BRFETCH_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_CTRL_BRFETCH_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG 0x0128166c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_TARGET 1:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_TARGET_LOCAL_FB 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_TARGET_COHERENT_SYSMEM 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_LOCK 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_LOCK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC 0x01281694 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC__PRIV_LEVEL_MASK 0x01281690 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_WPRID 1:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMACFG_SEC_WPRID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_LO 0x01281670 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_LO__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_LO__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_HI 0x01281674 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_HI__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_HI__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_LO 0x01281678 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_LO__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_LO__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_HI 0x0128167c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_HI__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_HI__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_LO 0x01281680 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_LO__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_LO__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_HI 0x01281684 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_HI__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_HI__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_LO 0x01281688 /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_LO__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_LO__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_HI 0x0128168c /* RWI4R */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_HI__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_HI__PRIV_LEVEL_MASK 0x01281664 /* */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE(i) (0x01281610+(i)*8) /* RWI4A */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_VAL_INIT 0x33333333 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_READ__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_READ_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_READ_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_WRITE__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_WRITE_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_WRITE_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_LOCK(i) (3+4*(i)):(3+4*(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_LOCK__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_LOCK_LOCKED 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVMMODE_LOCK_UNLOCKED 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE(i) (0x01281614+(i)*8) /* RWI4A */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE__SIZE_1 4 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL_INIT 0x33333333 /* RWI-V */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_READ__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_SCP_CTL0 0x01280400 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CTL0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CTL0_CTL_EN 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL0_CTL_EN_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL0_CTL_EN_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SEQ_EN 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL0_SEQ_EN_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SEQ_EN_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_CMD_IFACE_EN 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_CMD_IFACE_EN_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_CMD_IFACE_EN_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_PUSH_IFACE_EN 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_PUSH_IFACE_EN_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_PUSH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_FETCH_IFACE_EN 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_FETCH_IFACE_EN_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL0_SF_FETCH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL1 0x01280404 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CTL1__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_PUSH_BYPASS 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_PUSH_BYPASS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_PUSH_BYPASS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_FETCH_BYPASS 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_FETCH_BYPASS_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_FETCH_BYPASS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_FETCH_AS_ZERO 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_FETCH_AS_ZERO_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL1_SF_FETCH_AS_ZERO_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL1_RNG_EN 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL1_RNG_EN_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL1_RNG_EN_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL1_RNG_FAKE_MODE 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL1_RNG_FAKE_MODE_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL1_RNG_FAKE_MODE_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL1_PIPE_RESET 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL1_PIPE_RESET_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL1_PIPE_RESET_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL1_PIPE_RESET_TASK 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_CTL1_SEQ_CLEAR 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL1_SEQ_CLEAR_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL1_SEQ_CLEAR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL1_SEQ_CLEAR_TASK 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT 0x01280408 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_DEBUG_MODE_DISABLED 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_AES_SCC_DIS 2:2 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_AES_SCC_DIS_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_AES_SCC_DIS_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_HSMODE 1:1 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_HSMODE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_HSMODE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_SBOOT 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_SBOOT_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_STAT_SBOOT_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG 0x0128040c /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_PRE 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_PRE_ENABLED 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_PRE_DISABLED 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_SCP 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_SCP_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_SCP_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_SCP_PRE 6:6 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_ENABLED 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_DISABLED 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CFG0 0x01280410 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CFG0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CFG0_STALL_TIMEOUT 31:16 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_STALL_TIMEOUT_INIT 0x0000ffff /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CARRY_CHAIN 13:12 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_CARRY_CHAIN_32 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CARRY_CHAIN_64 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CARRY_CHAIN_96 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CARRY_CHAIN_128 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CMD_FLUSH 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_CMD_FLUSH_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CMD_FLUSH_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_AES_ENDIAN 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_AES_ENDIAN_BIG 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_AES_ENDIAN_LITTLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_PUSH_ENDIAN 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_PUSH_ENDIAN_BIG 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_PUSH_ENDIAN_LITTLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_FETCH_ENDIAN 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_FETCH_ENDIAN_BIG 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_FETCH_ENDIAN_LITTLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CMAC_ENDIAN 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_CMAC_ENDIAN_BIG 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_CMAC_ENDIAN_LITTLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CFG0_ADD_ENDIAN 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CFG0_ADD_ENDIAN_BIG 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CFG0_ADD_ENDIAN_LITTLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY 0x01280418 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY_REQUEST_RELOAD 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY_REQUEST_RELOAD_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY_REQUEST_RELOAD_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY_REQUEST_RELOAD_TASK 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY_LOADED 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY_LOADED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL_PKEY_LOADED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG 0x0128041c /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG_LOCKDOWN_CYA 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG_LOCKDOWN_CYA_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG_LOCKDOWN_CYA_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0 0x01280420 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_DEBUG0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_SECURE 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_SECURE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_SECURE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_VALID 30:30 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_CNT 26:25 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_PUSH_CNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_SECURE 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_SECURE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_SECURE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_VALID 23:23 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_CNT 22:19 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_FETCH_CNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_SECURE 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_SECURE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_SECURE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_VALID 17:17 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_PC 16:13 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_DEPTH 12:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_SEQ_DEPTH_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_TARGET 6:5 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_TARGET_NONE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_TARGET_PUSH 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_TARGET_FETCH 0x00000002 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_TARGET_SEQ 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_INDEX_AUTOINCREMENT 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_INDEX_AUTOINCREMENT_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_INDEX_AUTOINCREMENT_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_INDEX 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG0_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG1 0x01280424 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_DEBUG1__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_DEBUG1_DATA 31:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG1_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG2 0x01280428 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_DEBUG2__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_KU 15:12 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_KU_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_SEQ_CNT 9:4 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_SEQ_CNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_SEQ_STATE 1:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_SEQ_STATE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_SEQ_STATE_IDLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_SEQ_STATE_LOAD 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_DEBUG2_SEQ_STATE_LOOP 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD 0x01280430 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_SECURE 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_SECURE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_SECURE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_VALID 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_OP 24:20 /* RWXVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_RX_IMM 13:8 /* RWXVF */
|
|
#define NV_PRGNLCL_SCP_DEBUG_CMD_RY 3:0 /* RWXVF */
|
|
#define NV_PRGNLCL_SCP_ACL_FETCH 0x01280440 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_ACL_FETCH__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_ACL_FETCH_SECURE 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_ACL_FETCH_INSECURE 7:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_ACL_KEYABLE 0x01280444 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_ACL_KEYABLE__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_ACL_KEYABLE_SECURE 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_ACL_KEYABLE_INSECURE 7:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_ACL_WRITE 0x01280448 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_ACL_WRITE__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_ACL_WRITE_INSECURE 7:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_STATUS 0x01280450 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_STATUS__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCP_ACTIVE 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCP_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCP_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_CMD_ACTIVE 2:2 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_CMD_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_CMD_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_PUSH_ACTIVE 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_PUSH_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_PUSH_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SEQ_ACTIVE 6:6 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_SEQ_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SEQ_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_CTL_ACTIVE 8:8 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_CTL_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_CTL_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_FETCH_ACTIVE 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_FETCH_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_FETCH_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_AES_ACTIVE 14:14 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_AES_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_AES_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_RNG_ACTIVE 16:16 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_RNG_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_RNG_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_PKEY_LOADING_ACTIVE 18:18 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_PKEY_LOADING_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_PKEY_LOADING_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SFK_LOADING_ACTIVE 20:20 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_SFK_LOADING_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SFK_LOADING_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCC_TRNG_ACTIVE 26:26 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCC_TRNG_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCC_TRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCC_PRNG_ACTIVE 28:28 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCC_PRNG_ACTIVE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STATUS_SCC_PRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT0 0x01280454 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_STAT0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_CMD_VLD 14:14 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_CMD_VLD_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_CMD_VLD_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_CMD_SECURE 12:12 /* R-XVF */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_CMD_SECURE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_CMD_SECURE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_PUSH_VLD 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_PUSH_VLD_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_PUSH_VLD_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_PUSH_SECURE 8:8 /* R-XVF */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_PUSH_SECURE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_PUSH_SECURE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_FETCH_RDY 6:6 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_FETCH_RDY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_FETCH_RDY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_FETCH_SECURE 4:4 /* R-XVF */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_FETCH_SECURE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_SF_FETCH_SECURE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_CMP 1:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT0_CMP_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT0_CMP_PASS 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT0_CMP_FAIL 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1 0x01280458 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_STAT1__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_STAT1_SEQ_OP 4:0 /* R-XVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_SF_OP 9:5 /* R-XVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_DISPATCH_OP 14:10 /* R-XVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_OP 17:15 /* R-XVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_OP_ENCRYPT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_OP_DECRYPT 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_OP_RKEY 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_OP_RKEYI 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_HAZARD_STALL 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_HAZARD_STALL_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT1_HAZARD_STALL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_PUSH_STALL 25:25 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_PUSH_STALL_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT1_PUSH_STALL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_FETCH_STALL 26:26 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_FETCH_STALL_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT1_FETCH_STALL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_RNG_STALL 27:27 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_RNG_STALL_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT1_RNG_STALL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_WB_STALL 28:28 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_WB_STALL_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT1_WB_STALL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_STALL 29:29 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_STALL_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT1_AES_STALL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_STAT1_SECRET_STALL 30:30 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_STAT1_SECRET_STALL_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_STAT1_SECRET_STALL_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_SECRET63_CTL 0x01280460 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_SECRET63_CTL__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_SECRET63_CTL_SEL 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_SECRET63_CTL_SEL_PKEY 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_SECRET63_CTL_SEL_KMEM 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0 0x01280470 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RAW_RAND_READY 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RAW_RAND_READY_READY 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RAW_RAND_READY_PROCESSING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RAW_RAND_READY_RANDBUF_NOTFULL 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_AUTOCAL_TAP_A 7:4 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_AUTOCAL_TAP_A_INIT 0x0000000f /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_AUTOCAL_TAP_B 11:8 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_AUTOCAL_TAP_B_INIT 0x0000000f /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_LFSR_STAT_A 12:12 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_LFSR_STAT_A_LEGAL 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_LFSR_STAT_A_ILLEGAL 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_LFSR_STAT_B 13:13 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_LFSR_STAT_B_LEGAL 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_LFSR_STAT_B_ILLEGAL 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_A 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_A_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_A_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_A_CLEAR 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_B 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_B_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_B_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT0_RCTR_SATURATED_B_CLEAR 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT1 0x01280474 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT1__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A 15:0 /* R-IUF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B 31:16 /* R-IUF */
|
|
#define NV_PRGNLCL_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR 0x01280480 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_INTR__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_INTR_RAND_READY 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_RAND_READY_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR_RAND_READY_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_INTR_RAND_READY_RESET 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_INTR_ACL_VIO 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_ACL_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR_ACL_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_INTR_ACL_VIO_RESET 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_INTR_SECURITY_VIO 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_SECURITY_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR_SECURITY_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_INTR_SECURITY_VIO_RESET 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_INTR_CMD_ERROR 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_CMD_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR_CMD_ERROR_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_INTR_CMD_ERROR_RESET 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_INTR_STEP 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_STEP_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR_STEP_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_INTR_STEP_RESET 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_INTR_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_RNDHOLDOFF_REQUESTED_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR_RNDHOLDOFF_REQUESTED_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_INTR_RNDHOLDOFF_REQUESTED_RESET 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_INTR_STALL_TIMEOUT 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_STALL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_INTR_STALL_TIMEOUT_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_INTR_STALL_TIMEOUT_RESET 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_INTR_EN 0x01280484 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_INTR_EN__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_RAND_READY 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_RAND_READY_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_RAND_READY_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_ACL_VIO 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_ACL_VIO_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_ACL_VIO_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_SECURITY_VIO 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_SECURITY_VIO_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_SECURITY_VIO_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_CMD_ERROR 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_CMD_ERROR_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_CMD_ERROR_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_STEP 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_STEP_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_STEP_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_STALL_TIMEOUT 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_STALL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_INTR_EN_STALL_TIMEOUT_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO 0x01280490 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_VIOLATION 31:31 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_VIOLATION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_CHMOD_RELAX_VIO 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_CHMOD_RELAX_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_CHMOD_RELAX_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_CHMOD_RELAX_VIO_CLEAR 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_FETCH_VIO 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_FETCH_VIO_CLEAR 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_WR_VIO 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_WR_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_WR_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_ACL_VIO_WR_VIO_CLEAR 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO 0x01280494 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_VIOLATION 31:31 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_VIOLATION_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_VIO_SC 26:25 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_VIO_SC_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_VIO 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC 22:21 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_CHANGE_VIO 20:20 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_FETCH_VIO_SC 18:17 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_FETCH_VIO_SC_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_FETCH_VIO 16:16 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC 6:5 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOAD_TRACE_VIO 4:4 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOAD_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOAD_TRACE_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC 2:1 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOOP_TRACE_VIO 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOOP_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SECURITY_VIO_LOOP_TRACE_VIO_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR 0x01280498 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_UNDEFINED 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_UNDEFINED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_UNDEFINED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_UNDEFINED_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_EMPTY 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_EMPTY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_EMPTY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_EMPTY_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_OVERFLOW 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_OVERFLOW_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_OVERFLOW_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_OVERFLOW_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INSECURE 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INSECURE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INSECURE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INSECURE_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INVALID 20:20 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INVALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INVALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SIG_INVALID_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_CHMOD_INSECURE 24:24 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_CHMOD_INSECURE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_CHMOD_INSECURE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_CHMOD_INSECURE_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SECRET_INSECURE 28:28 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SECRET_INSECURE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SECRET_INSECURE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CMD_ERROR_SECRET_INSECURE_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_PRGNLCL_SCP_RNDCTL0 0x01280500 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL0_HOLDOFF_INIT_LOWER 31:0 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL0_HOLDOFF_INIT_LOWER_INIT 0x01c9c380 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL1 0x01280504 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL1__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL1_HOLDOFF_INIT_UPPER 15:0 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL1_HOLDOFF_INIT_UPPER_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL1_HOLDOFF_INTRA_MASK 31:16 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL1_HOLDOFF_INTRA_MASK_INIT 0x0000ffff /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL2 0x01280508 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL2__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL2_COMPRESS_CNT 15:0 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL2_COMPRESS_CNT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3 0x0128050c /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A 12:12 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B 16:16 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_TRIGGER 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_RNDCTL4 0x01280510 /* -W-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL4__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL4_POLYNOMIAL_A 31:0 /* -WIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL4_POLYNOMIAL_A_INIT 0x80200003 /* -WI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL5 0x01280514 /* -W-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL5__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL5_LFSR_INIT_A 31:0 /* -WIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL5_LFSR_INIT_A_INIT 0xdeadbeef /* -WI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL6 0x01280518 /* -W-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL6__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL6_POLYNOMIAL_B 31:0 /* -WIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL6_POLYNOMIAL_B_INIT 0x80200003 /* -WI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL7 0x0128051c /* -W-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL7__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL7_LFSR_INIT_B 31:0 /* -WIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL7_LFSR_INIT_B_INIT 0xbeefdead /* -WI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL8 0x01280520 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL8__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A 15:0 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B 31:16 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL9 0x01280524 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL9__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A 15:0 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B 31:16 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL10 0x01280528 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL10__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A 15:0 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A_INIT 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B 31:16 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B_INIT 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11 0x0128052c /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_ENABLE 0:0 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_ENABLE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE 1:1 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_A 2:2 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_A_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_A_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_A_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_B 3:3 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_B_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_B_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_SYNCH_RAND_B_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A 5:4 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_OSC 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_AUTOCAL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_LFSR 0x00000002 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_ZERO 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B 7:6 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_OSC 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_AUTOCAL 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_LFSR 0x00000002 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_ZERO 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A 11:8 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A_INIT 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B 15:12 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B_INIT 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_MIN_AUTO_TAP 19:16 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_MIN_AUTO_TAP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY 23:20 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY 30:24 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_SAFE_MODE 31:31 /* RWIUF */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX 0x01280530 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_FALLBACK_MODE 0:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_PENDING 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_TASK 0x00000001 /* -W--T */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_LOADED 3:3 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_LOADED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_CTL_P2PRX_SFK_LOADED_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG0 0x01280540 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT 15:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT_INIT 0x00000020 /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA 31:16 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA_INIT 0x0000000f /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG1 0x01280544 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG1__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX_INIT 0x00000fff /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG2 0x01280548 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG2__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD 31:0 /* R-IVF */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD_INIT 0x7fffffff /* R-I-V */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT0 0x0128054c /* R--4R */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT0__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT0_RSEED_TMOUT_CNT 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT1 0x01280550 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT1__DEVICE_MAP 0x00000010 /* */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT1_RSEED_BIT_CNT 5:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT1_RSEED_VALID 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_SCC_DEBUG_STAT1_RSEED_TMOUT 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC 0x01280560 /* RW-4R */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC__DEVICE_MAP 0x00000008 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_RSA1_N_OFFS 0x00000000 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_RSA1_N_SIZE 0x00000180 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_RSA1_E_OFFS 0x00000180 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_RSA1_E_SIZE 0x00000020 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_ECC1_X_OFFS 0x000001a0 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_ECC1_X_SIZE 0x00000020 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_ECC1_Y_OFFS 0x000001c0 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_ECC1_Y_SIZE 0x00000020 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_OFFS 9:2 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_OFFS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_AINCR 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_AINCR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_AINCR_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_PUBKEYC_AINCR_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_PUBKEYD 0x01280564 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_PUBKEYD__DEVICE_MAP 0x00000008 /* */
|
|
#define NV_PRGNLCL_SCP_PUBKEYD_DATA 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_SCP_PK_ADDR 0x01280570 /* RWI4R */
|
|
#define NV_PRGNLCL_SCP_PK_ADDR__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_SCP_PK_ADDR_OFFSET 11:0 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_PK_ADDR_OFFSET_DEFT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_PK_ADDR_AINCR 31:31 /* RWIVF */
|
|
#define NV_PRGNLCL_SCP_PK_ADDR_AINCR_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_SCP_PK_ADDR_AINCR_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_SCP_PK_DATA 0x01280574 /* R--4R */
|
|
#define NV_PRGNLCL_SCP_PK_DATA__DEVICE_MAP 0x0000000c /* */
|
|
#define NV_PRGNLCL_SCP_PK_DATA_VAL 31:0 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK 0x01283070 /* RWI4R */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK 0x01283088 /* RWI4R */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG(i) (0x01283000+(i)*4) /* RW-4A */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG__SIZE_1 8 /* */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_TARGET_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_MEM_TYPE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_WR_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_RD_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK0_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK0_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK1_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_WACHK1_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK0_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK0_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK1_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_RACHK1_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_ENGINE_ID_FLAG 16:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_TRANSCFG_ENGINE_ID_FLAG_OWN 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_INSTBLK 0x01283020 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_INSTBLK__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_INSTBLK_PTR 27:0 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_INSTBLK_TARGET 29:28 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_INSTBLK_TARGET_LOCAL_FB 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS 0x01283028 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS_STATUS 1:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS_STATUS_NOT_BIND 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS_STATUS_BOUND 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS_GFID 9:4 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS_GFID_INIT 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_BIND_STATUS_ENGINE_ID 23:16 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO 0x01283090 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_GPC 0:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_GPC_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB 1:1 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_TARGET 3:2 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_TARGET_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_ADR_LO 31:4 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_ADR_LO_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI 0x01283094 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_PDB_ADR_HI 6:0 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_PDB_ADR_HI_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_PAGE_TABLE_LEVEL 9:7 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_PAGE_TABLE_LEVEL_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_TARGET_AVA 10:10 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_TARGET_AVA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_MMU_REPLAY 13:11 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_MMU_REPLAY_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_CLIENT_UNIT_ID 20:14 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_CLIENT_UNIT_ID_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_GPC_ID 23:21 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_GPC_ID_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_SYS_MEMBAR 24:24 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_SYS_MEMBAR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_ACK_TYPE 26:25 /* R-IVF */
|
|
#define NV_PRGNLCL_FBIF_TLB_INVALIDATE_PARAM1_HI_ACK_TYPE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_CTL 0x01283024 /* RW-4R */
|
|
#define NV_PRGNLCL_FBIF_CTL__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_CTL_FLUSH 0:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_FLUSH_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_FLUSH_CLEAR 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_INVAL_CONTEXT_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_BWCOUNT_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_ENABLE 4:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL_ENABLE_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_ENABLE_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_IDLEWDERR_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_RESET 6:6 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_RESET_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_RESET_CLEAR 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_IDLE 8:8 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_IDLE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_CTL_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_IDLEWDERR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_CTL_IDLEWDERR_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_CTL_SRTOUT 10:10 /* R--VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_SRTOUT_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_CTL_SRTOUT_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_SRTOUT_SET 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_CLR_SRTOUT_CLEAR 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL_SRTOVAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2 0x01283084 /* RW-4R */
|
|
#define NV_PRGNLCL_FBIF_CTL2__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2__PRIV_LEVEL_MASK 0x01283088 /* */
|
|
#define NV_PRGNLCL_FBIF_CTL2_NACK_MODE 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CTL2_NACK_MODE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CTL2_NACK_MODE_NACK_AS_ACK 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE 0x0128302c /* RW-4R */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG 0x0128306c /* RW-4R */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T0 3:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T1 7:4 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T2 11:8 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T3 15:12 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T4 19:16 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T5 23:20 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T6 27:24 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T7 31:28 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_REGIONCFG_T7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CG1 0x01283074 /* RW-4R */
|
|
#define NV_PRGNLCL_FBIF_CG1__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG 3:0 /* */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_ENABLED 0 /* */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_DISABLED 0xF /* */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG__PROD 0x0 /* */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_MSD0_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_MSD0_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_MSD1_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_MSD1_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_FB0_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_FB0_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_FB1_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PRGNLCL_FBIF_CG1_SLCG_FB1_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_PRGNLCL_FBIF_ACHK_BLK(i) (0x01283030+(i)*8) /* RW-4A */
|
|
#define NV_PRGNLCL_FBIF_ACHK_BLK__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_FBIF_ACHK_BLK__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL(i) (0x01283034+(i)*8) /* RW-4A */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL__SIZE_1 2 /* */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_TYPE_INSIDE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_STATE_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_STATE_ENABLE 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0 0x01283040 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE 3:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_IDLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_CHECK 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_ALLOC 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_ISSUE 0x00000003 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_WDAT 0x00000004 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_FLT_FLUSH 0x00000005 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_HALT 0x00000006 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_INST 0x00000007 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_INST_ACK 0x00000008 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_OBJ 0x00000009 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DSP_STATE_FLUSH 0x0000000a /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_INST_VLD 4:4 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_INST_BOUND 5:5 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_RICF_HAS_DATA 6:6 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_ARQ_HAS_DATA 7:7 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_MRQ_HAS_DATA 8:8 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_FAULT_OR_HALT 9:9 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_ORQ_NOT_FULL 10:10 /* R-IUF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_ORQ_NOT_FULL_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_ORQ_NOT_FULL_FLASE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_FLUSH_OUTSTANDING 11:11 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DISPATCH_IDLE 12:12 /* R-IUF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DISPATCH_IDLE_TRUE 0x00000001 /* R-I-V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_DISPATCH_IDLE_FALSE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_MWF_FSM_STATE 17:16 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_MWF_FSM_STATE_IDLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_MWF_FSM_STATE_COMMIT 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_MWF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_MWF_HAS_DATA 18:18 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_MWF_COMMIT_COUNT 24:19 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_STALL_RQQ_FULL 25:25 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_STALL_WDF_FULL 26:26 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_STALL_FB_BUSY 27:27 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_STALL_ORQ_FULL 28:28 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_STALL_RDM_ALLOC 29:29 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_STALL_RDM_PORTQ 30:30 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT0_STALL_RDM_CLIENT 31:31 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1 0x01283044 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FLT_STATE 1:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FLT_FAULTED 2:2 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FLT_BUSY 3:3 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_ACKF_HAS_DATA 4:4 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_ORQ_HAS_DATA 5:5 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_ALL_READS_DONE 6:6 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FBR_IDLE 8:8 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FBR_FAULTED 9:9 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FBR_FB_BUSY 10:10 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FBR_PKT2FB_VLD 11:11 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FBR_RCV_DATA_VALID 12:12 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_FBR_RCV_DATA_TYPE 15:14 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_WDF_FSM_STATE 17:16 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_WDF_FSM_STATE_IDLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_WDF_FSM_STATE_COMMIT 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_WDF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_WDF_HAS_DATA 18:18 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_WDF_COMMIT_COUNT 23:19 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDM_STATE 25:24 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDM_STATE_IDLE 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDM_STATE_WAITBUF 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDM_STATE_SAVEBUF 0x00000002 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDM_ANY_READY 26:26 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDM_DAQ_HAS_DATA 27:27 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDM_DEALLOC_COUNT 30:28 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT1_RDATA_WAIT 31:31 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2 0x01283048 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2_FAULTED_PORTID 5:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2_FAULTED_SUBID 12:6 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2_FAULTED_SRCQ 13:13 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2_FAULTED_SRCQ_ARQ 0x00000001 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2_FAULTED_SRCQ_MRQ 0x00000000 /* R---V */
|
|
#define NV_PRGNLCL_FBIF_DBG_STAT2_FAULTED_VLD 14:14 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_LO 0x01283050 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_LO__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_LO_DATA 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_HI 0x01283054 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_HI__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_RDCOUNT_HI_DATA 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_LO 0x01283058 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_LO__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_LO_DATA 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_HI 0x0128305c /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_HI__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_WRCOUNT_HI_DATA 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_R32COUNT 0x01283060 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_R32COUNT__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_R32COUNT__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_R32COUNT_DATA 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_R64COUNT 0x01283064 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_R64COUNT__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_R64COUNT__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_R64COUNT_DATA 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_DBG_R128COUNT 0x01283068 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_DBG_R128COUNT__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_R128COUNT__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_DBG_R128COUNT_DATA 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG0 0x01283078 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG0__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG0__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG0_ADR_LO 31:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG1 0x0128307c /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG1__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG1__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG1_ADR_HI 16:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2 0x01283080 /* R--4R */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2__PRIV_LEVEL_MASK 0x01283070 /* */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2_OP 4:0 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2_RD 5:5 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2_SUBID 13:6 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2_WID 24:22 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2_SZ 29:25 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BLOCKER_DEBUG2_L2_CLASS 31:30 /* R--UF */
|
|
#define NV_PRGNLCL_FBIF_BW_ALLOC 0x0128304c /* RW-4R */
|
|
#define NV_PRGNLCL_FBIF_BW_ALLOC__DEVICE_MAP NV_PRGNLCL_FBIF_DEVICE_MAP_GROUP_FBIF /* */
|
|
#define NV_PRGNLCL_FBIF_BW_ALLOC_VAL 31:0 /* */
|
|
#define NV_PRGNLCL_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */
|
|
#define NV_PRGNLCL_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */
|
|
#endif // __ga102_dev_gsp_prgnlcl_h__
|