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gddr6/include/ampere/ga102/dev_nv_xve1.h
Ole Algoritme 698a8f7487 first commit
2022-09-05 21:52:22 +02:00

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/* _NVRM_COPYRIGHT_BEGIN_
*
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
* information contained herein is proprietary and confidential to NVIDIA
* Corporation. Any use, reproduction, or disclosure without the written
* permission of NVIDIA Corporation is prohibited.
*
* _NVRM_COPYRIGHT_END_
*/
#ifndef __ga102_dev_nv_xve1_h__
#define __ga102_dev_nv_xve1_h__
/* This file is autogenerated. Do not edit */
#define NV_PCFG1 0x0008AFFF:0x0008A000 /* RW--D */
#define NV_XVE1 0x00000FFF:0x00000000 /* RW--D */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK 0x000007F8 /* RW-4R */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK 0x000007FC /* RW-4R */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_protect_dropoff_cya_grp" /* */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_REGS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK 0x00000800 /* RW-4R */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_MISC_CYA_RESET_AZA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK 0x00000804 /* RW-4R */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
#define NV_XVE1_PROTECT_PRIV_XV_0_CYA_RESET_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK 0x00000808 /* RW-4R */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_LEVEL3_ENABLED 0x0000000C /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xve_cya_0" /* */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x0000000C /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
#define NV_XVE1_PROTECT_CYA_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */
#define NV_XVE1_ID 0x00000000 /* R--4R */
#define NV_XVE1_ID_VENDOR 15:0 /* C--VF */
#define NV_XVE1_ID_VENDOR_NVIDIA 0x000010DE /* C---V */
#define NV_XVE1_ID_DEVICE_CHIP 31:16 /* R-CVF */
#define NV_XVE1_ID_DEVICE_CHIP_NO_USE 0x00000000 /* R-C-V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GT212 0x00000BE0 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GT214 0x00000BE1 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GT215 0x00000BE4 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GT216 0x00000BE2 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GT218 0x00000BE3 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GF100 0x00000BE5 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GF102 0x00000BE6 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GF103 0x00000BE7 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GF104 0x00000BEB /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GF105 0x00000BE8 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GF106 0x00000BE9 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GF108 0x00000BEA /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GK104 0x00000E0A /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GK106 0x00000E0B /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GK107 0x00000E1B /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GK110 0x00000E1A /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GK208 0x00000E0F /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GM108 0x00000FBD /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GM107 0x00000FBC /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GM104 0x00000FB2 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GM204 0x00000FBB /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GM206 0x00000FBA /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GM200 0x00000FB0 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GP100 0x00000FB1 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GP102 0x000010EF /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GP104 0x000010F0 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GP106 0x000010F1 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GP107 0x00000FB9 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GP108 0x00000FB8 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GV100 0x000010F2 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_TU102 0x000010F7 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_TU104 0x000010F8 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_TU106 0x000010F9 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_TU107 0x000010FA /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_TU117 0x000010FA /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_TU108 0x000010FB /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_TU116 0x00001AEB /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA100 0x00001AE0 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA101 0x00002285 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA102 0x00001AEF /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA103 0x00002288 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA104 0x0000228B /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA106 0x0000228E /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA107 0x00002291 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GH202 0x000022B6 /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA114 0x00001AEF /* R---V */
#define NV_XVE1_ID_DEVICE_CHIP_AZALIA_GA10B 0x00001AEF /* R---V */
#define NV_XVE1_DEV_CTRL 0x00000004 /* RW-4R */
#define NV_XVE1_DEV_CTRL_CMD_IO_SPACE 0:0 /* R-IVF */
#define NV_XVE1_DEV_CTRL_CMD_IO_SPACE_DISABLED 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_CMD_MEMORY_SPACE 1:1 /* RWIVF */
#define NV_XVE1_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE1_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_DEV_CTRL_CMD_BUS_MASTER 2:2 /* RWIVF */
#define NV_XVE1_DEV_CTRL_CMD_BUS_MASTER_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE1_DEV_CTRL_CMD_BUS_MASTER_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_DEV_CTRL_CMD_SPECIAL_CYCLE 3:3 /* C--VF */
#define NV_XVE1_DEV_CTRL_CMD_SPECIAL_CYCLE_DISABLED 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE 4:4 /* C--VF */
#define NV_XVE1_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE_DISABLED 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_CMD_VGA_PALETTE_SNOOP 5:5 /* C--VF */
#define NV_XVE1_DEV_CTRL_CMD_VGA_PALETTE_SNOOP_DISABLED 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_CMD_PERR 6:6 /* RWIVF */
#define NV_XVE1_DEV_CTRL_CMD_PERR_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE1_DEV_CTRL_CMD_PERR_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_DEV_CTRL_CMD_IDSEL_STEP 7:7 /* C--VF */
#define NV_XVE1_DEV_CTRL_CMD_IDSEL_STEP_DISABLED 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_CMD_SERR 8:8 /* RWIVF */
#define NV_XVE1_DEV_CTRL_CMD_SERR_DISABLED 0x00000000 /* RWI-V */
#define NV_XVE1_DEV_CTRL_CMD_SERR_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_DEV_CTRL_CMD_FAST_BACK2BACK 9:9 /* C--VF */
#define NV_XVE1_DEV_CTRL_CMD_FAST_BACK2BACK_DISABLED 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_CMD_INTERRUPT_DISABLE 10:10 /* RWIVF */
#define NV_XVE1_DEV_CTRL_CMD_INTERRUPT_DISABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_DEV_CTRL_STAT_INTERRUPT 19:19 /* R-IVF */
#define NV_XVE1_DEV_CTRL_STAT_INTERRUPT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_STAT_INTERRUPT_PENDING 0x00000001 /* R---V */
#define NV_XVE1_DEV_CTRL_STAT_CAPLIST 20:20 /* C--VF */
#define NV_XVE1_DEV_CTRL_STAT_CAPLIST_PRESENT 0x00000001 /* C---V */
#define NV_XVE1_DEV_CTRL_STAT_66MHZ 21:21 /* C--VF */
#define NV_XVE1_DEV_CTRL_STAT_66MHZ_INCAPABLE 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_STAT_FAST_BACK2BACK 23:23 /* C--VF */
#define NV_XVE1_DEV_CTRL_STAT_FAST_BACK2BACK_INCAPABLE 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_STAT_MASTER_DATA_PERR 24:24 /* RWIVF */
#define NV_XVE1_DEV_CTRL_STAT_MASTER_DATA_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_DEV_CTRL_STAT_MASTER_DATA_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_STAT_MASTER_DATA_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEV_CTRL_STAT_DEVSEL_TIMING 26:25 /* C--VF */
#define NV_XVE1_DEV_CTRL_STAT_DEVSEL_TIMING_FAST 0x00000000 /* C---V */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT 27:27 /* RWIVF */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT 28:28 /* RWIVF */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT 29:29 /* RWIVF */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_NO 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_YES 0x00000001 /* R---V */
#define NV_XVE1_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_SERR 30:30 /* RWIVF */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_SERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_SERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_DEV_CTRL_STAT_SIGNALED_SERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEV_CTRL_STAT_DETECTED_PERR 31:31 /* RWIVF */
#define NV_XVE1_DEV_CTRL_STAT_DETECTED_PERR_NOT_ACTIVE 0x00000000 /* R-I-V */
#define NV_XVE1_DEV_CTRL_STAT_DETECTED_PERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_DEV_CTRL_STAT_DETECTED_PERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_REV_ID 0x00000008 /* R--4R */
#define NV_XVE1_REV_ID_FIB 3:0 /* R-CVF */
#define NV_XVE1_REV_ID_FIB_ONE 0x00000001 /* R-C-V */
#define NV_XVE1_REV_ID_FIB_TWO 0x00000002 /* R---V */
#define NV_XVE1_REV_ID_MASK 7:4 /* R-CVF */
#define NV_XVE1_REV_ID_MASK_A 0x0000000A /* R-C-V */
#define NV_XVE1_REV_ID_MASK_B 0x0000000B /* ----V */
#define NV_XVE1_REV_ID_CLASS_CODE 31:8 /* R-CVF */
#define NV_XVE1_REV_ID_CLASS_CODE_HDA 0x00040300 /* R-C-V */
#define NV_XVE1_MISC_1 0x0000000C /* RW-4R */
#define NV_XVE1_MISC_1_CACHE_LINE_SIZE 7:0 /* RWIVF */
#define NV_XVE1_MISC_1_CACHE_LINE_SIZE_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_MISC_1_MASTER_LATENCY_TIMER 15:8 /* C--VF */
#define NV_XVE1_MISC_1_MASTER_LATENCY_TIMER_0_CLOCKS 0x00000000 /* C---V */
#define NV_XVE1_MISC_1_HEADER_TYPE 23:16 /* R-IVF */
#define NV_XVE1_MISC_1_HEADER_TYPE_SINGLEFUNC 0x00000000 /* R---V */
#define NV_XVE1_MISC_1_HEADER_TYPE_MULTIFUNC 0x00000080 /* R-I-V */
#define NV_XVE1_MISC_1_BIST 31:24 /* C--VF */
#define NV_XVE1_MISC_1_BIST_NULL 0x00000000 /* C---V */
#define NV_XVE1_BAR0 0x00000010 /* RW-4R */
#define NV_XVE1_BAR0_SPACE_TYPE 0:0 /* C--VF */
#define NV_XVE1_BAR0_SPACE_TYPE_MEMORY 0x00000000 /* C---V */
#define NV_XVE1_BAR0_ADDRESS_TYPE 2:1 /* C--VF */
#define NV_XVE1_BAR0_ADDRESS_TYPE_32_BIT 0x00000000 /* C---V */
#define NV_XVE1_BAR0_PREFETCHABLE 3:3 /* C--VF */
#define NV_XVE1_BAR0_PREFETCHABLE_NOT 0x00000000 /* C---V */
#define NV_XVE1_BAR0_BASE_ADDRESS_RSVD 13:4 /* C--VF */
#define NV_XVE1_BAR0_BASE_ADDRESS_RSVD_NULL 0x00000000 /* C---V */
#define NV_XVE1_BAR0_BASE_ADDRESS 31:14 /* RWIVF */
#define NV_XVE1_BAR0_BASE_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_BAR_RSVD(i) (0x00000014+(i)*4) /* C--4A */
#define NV_XVE1_BAR_RSVD__SIZE_1 5 /* */
#define NV_XVE1_BAR_RSVD_BITS 31:0 /* C--VF */
#define NV_XVE1_BAR_RSVD_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_CARDBUS 0x00000028 /* C--4R */
#define NV_XVE1_CARDBUS_PTR 31:0 /* C--VF */
#define NV_XVE1_CARDBUS_PTR_0 0x00000000 /* C---V */
#define NV_XVE1_SUBSYSTEM 0x0000002C /* R--4R */
#define NV_XVE1_SUBSYSTEM_VENDOR_ID 15:0 /* R-CVF */
#define NV_XVE1_SUBSYSTEM_VENDOR_ID_NONE 0x00000000 /* R-C-V */
#define NV_XVE1_SUBSYSTEM_ID_USER 19:16 /* R-CVF */
#define NV_XVE1_SUBSYSTEM_ID_USER_NONE 0x00000000 /* R-C-V */
#define NV_XVE1_SUBSYSTEM_ID_NON_USER 31:20 /* R-CVF */
#define NV_XVE1_SUBSYSTEM_ID_NON_USER_NONE 0x00000000 /* R-C-V */
#define NV_XVE1_ROM_RSVD 0x00000030 /* C--4R */
#define NV_XVE1_ROM_RSVD_BITS 31:0 /* C--VF */
#define NV_XVE1_ROM_RSVD_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_CAP_LIST 0x00000034 /* C--4R */
#define NV_XVE1_CAP_LIST_CAP_PTR 7:0 /* C--VF */
#define NV_XVE1_CAP_LIST_CAP_PTR_POWER_MGMT 0x00000060 /* C---V */
#define NV_XVE1_RSVD_0 0x00000038 /* C--4R */
#define NV_XVE1_RSVD_0_BITS 31:0 /* C--VF */
#define NV_XVE1_RSVD_0_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_INTR_GNT 0x0000003C /* RW-4R */
#define NV_XVE1_INTR_GNT_INTR_LINE 7:0 /* RWIVF */
#define NV_XVE1_INTR_GNT_INTR_LINE_IRQ0 0x00000000 /* RWI-V */
#define NV_XVE1_INTR_GNT_INTR_LINE_IRQ1 0x00000001 /* RW--V */
#define NV_XVE1_INTR_GNT_INTR_LINE_IRQ15 0x0000000F /* RW--V */
#define NV_XVE1_INTR_GNT_INTR_LINE_UNKNOWN 0x000000FF /* RW--V */
#define NV_XVE1_INTR_GNT_INTR_PIN 15:8 /* C--VF */
#define NV_XVE1_INTR_GNT_INTR_PIN_INTB 0x00000002 /* C---V */
#define NV_XVE1_INTR_GNT_MIN_GNT 23:16 /* C--VF */
#define NV_XVE1_INTR_GNT_MIN_GNT_NO_REQUIREMENTS 0x00000000 /* C---V */
#define NV_XVE1_INTR_GNT_MAX_LAT 31:24 /* C--VF */
#define NV_XVE1_INTR_GNT_MAX_LAT_NO_REQUIREMENTS 0x00000000 /* C---V */
#define NV_XVE1_SUBSYSTEM_ALIAS 0x00000040 /* RW-4R */
#define NV_XVE1_SUBSYSTEM_ALIAS_VENDOR_ID 15:0 /* RWCVF */
#define NV_XVE1_SUBSYSTEM_ALIAS_VENDOR_ID_NONE 0x00000000 /* RWC-V */
#define NV_XVE1_SUBSYSTEM_ALIAS_ID 31:16 /* RWCVF */
#define NV_XVE1_SUBSYSTEM_ALIAS_ID_NONE 0x00000000 /* RWC-V */
#define NV_XVE1_MISC_3 0x00000058 /* RW-4R */
#define NV_XVE1_MISC_3_SCRATCH 23:0 /* RWCVF */
#define NV_XVE1_MISC_3_SCRATCH_DEFAULT 0x0023D6CE /* RWC-V */
#define NV_XVE1_OVERRIDE_ID 0x0000005C /* RW-4R */
#define NV_XVE1_OVERRIDE_ID__PRIV_LEVEL_MASK 0x000007F8 /* */
#define NV_XVE1_OVERRIDE_ID_UNUSED 3:0 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_UNUSED_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_DEV_WRITE 4:4 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_DEV_WRITE_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_DEV_WRITE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_DEV_READ 5:5 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_DEV_READ_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_DEV_READ_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_REV_WRITE 6:6 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_REV_WRITE_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_REV_WRITE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_OVERRIDE_ID_REV_READ 7:7 /* RWCVF */
#define NV_XVE1_OVERRIDE_ID_REV_READ_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_OVERRIDE_ID_REV_READ_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_PWR_MGMT_0 0x00000060 /* R--4R */
#define NV_XVE1_PWR_MGMT_0_PME_D3_COLD 31:31 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_PME_D3_COLD_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE1_PWR_MGMT_0_PME_D3_COLD_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_PME_D3_HOT 30:30 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_PME_D3_HOT_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE1_PWR_MGMT_0_PME_D3_HOT_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_PME_D2 29:29 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_PME_D2_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE1_PWR_MGMT_0_PME_D2_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_PME_D1 28:28 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_PME_D1_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE1_PWR_MGMT_0_PME_D1_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_PME_D0 27:27 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_PME_D0_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE1_PWR_MGMT_0_PME_D0_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_D2 26:26 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_D2_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE1_PWR_MGMT_0_D2_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_D1 25:25 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_D1_SUPPORTED 0x00000001 /* ----V */
#define NV_XVE1_PWR_MGMT_0_D1_NOT_SUPPORTED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_AUX_CURRENT 24:22 /* C--VF */
#define NV_XVE1_PWR_MGMT_0_AUX_CURRENT_SELF_POWERED 0x00000000 /* C---V */
#define NV_XVE1_PWR_MGMT_0_DSI 21:21 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_DSI_NOT_REQUIRED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_PME_CLOCK 19:19 /* R-IVF */
#define NV_XVE1_PWR_MGMT_0_PME_CLOCK_NOT_REQUIRED 0x00000000 /* R-I-V */
#define NV_XVE1_PWR_MGMT_0_VERSION 18:16 /* C--VF */
#define NV_XVE1_PWR_MGMT_0_VERSION_3 0x00000003 /* C---V */
#define NV_XVE1_PWR_MGMT_0_NEXT_PTR 15:8 /* C--VF */
#define NV_XVE1_PWR_MGMT_0_NEXT_PTR_MSI 0x00000068 /* C---V */
#define NV_XVE1_PWR_MGMT_0_CAP_ID 7:0 /* C--VF */
#define NV_XVE1_PWR_MGMT_0_CAP_ID_POWER_MGMT 0x00000001 /* C---V */
#define NV_XVE1_PWR_MGMT_1 0x00000064 /* RW-4R */
#define NV_XVE1_PWR_MGMT_1_PME_DATA 31:24 /* C--VF */
#define NV_XVE1_PWR_MGMT_1_PME_DATA_UNS 0x00000000 /* C---V */
#define NV_XVE1_PWR_MGMT_1_PME_BPCC 23:23 /* C--VF */
#define NV_XVE1_PWR_MGMT_1_PME_BPCC_UNS 0x00000000 /* C---V */
#define NV_XVE1_PWR_MGMT_1_PME_B2B3 22:22 /* C--VF */
#define NV_XVE1_PWR_MGMT_1_PME_B2B3_UNS 0x00000000 /* C---V */
#define NV_XVE1_PWR_MGMT_1_PME_STATUS 15:15 /* RWCVF */
#define NV_XVE1_PWR_MGMT_1_PME_STATUS_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_PWR_MGMT_1_PME_STATUS_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_PWR_MGMT_1_PME_STATUS_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_PWR_MGMT_1_PME_DATA_SCALE 14:13 /* C--VF */
#define NV_XVE1_PWR_MGMT_1_PME_DATA_SCALE_UNS 0x00000000 /* C---V */
#define NV_XVE1_PWR_MGMT_1_PME_DATA_SEL 12:9 /* C--VF */
#define NV_XVE1_PWR_MGMT_1_PME_DATA_SEL_UNS 0x00000000 /* C---V */
#define NV_XVE1_PWR_MGMT_1_PME 8:8 /* RWCVF */
#define NV_XVE1_PWR_MGMT_1_PME_DISABLE 0x00000000 /* RWC-V */
#define NV_XVE1_PWR_MGMT_1_PME_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_PWR_MGMT_1_NO_SOFT_RESET 3:3 /* R-IVF */
#define NV_XVE1_PWR_MGMT_1_NO_SOFT_RESET_ENABLE 0x00000001 /* R-I-V */
#define NV_XVE1_PWR_MGMT_1_NO_SOFT_RESET_DISABLE 0x00000000 /* R---V */
#define NV_XVE1_PWR_MGMT_1_PWR_STATE 1:0 /* RWIVF */
#define NV_XVE1_PWR_MGMT_1_PWR_STATE_D0 0x00000000 /* RWI-V */
#define NV_XVE1_PWR_MGMT_1_PWR_STATE_D1 0x00000001 /* RW--V */
#define NV_XVE1_PWR_MGMT_1_PWR_STATE_D2 0x00000002 /* RW--V */
#define NV_XVE1_PWR_MGMT_1_PWR_STATE_D3HOT 0x00000003 /* RW--V */
#define NV_XVE1_MSI_CTRL 0x00000068 /* RW-4R */
#define NV_XVE1_MSI_CTRL_RSVD 31:24 /* C--VF */
#define NV_XVE1_MSI_CTRL_RSVD_0 0x00000000 /* C---V */
#define NV_XVE1_MSI_CTRL_64BIT_CAP 23:23 /* R-IVF */
#define NV_XVE1_MSI_CTRL_64BIT_CAP_TRUE 0x00000001 /* R-I-V */
#define NV_XVE1_MSI_CTRL_64BIT_CAP_FALSE 0x00000000 /* R---V */
#define NV_XVE1_MSI_CTRL_MULT_EN 22:20 /* RWIVF */
#define NV_XVE1_MSI_CTRL_MULT_EN_CODE0 0x00000000 /* RWI-V */
#define NV_XVE1_MSI_CTRL_MULT_EN_CODE2 0x00000001 /* RW--V */
#define NV_XVE1_MSI_CTRL_MULT_EN_CODE4 0x00000002 /* RW--V */
#define NV_XVE1_MSI_CTRL_MULT_EN_CODE8 0x00000003 /* RW--V */
#define NV_XVE1_MSI_CTRL_MULT_CAP 19:17 /* R-IVF */
#define NV_XVE1_MSI_CTRL_MULT_CAP_CODE0 0x00000000 /* R-I-V */
#define NV_XVE1_MSI_CTRL_MSI 16:16 /* RWIVF */
#define NV_XVE1_MSI_CTRL_MSI_DISABLE 0x00000000 /* RWI-V */
#define NV_XVE1_MSI_CTRL_MSI_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_MSI_CTRL_NEXT_PTR 15:8 /* C--VF */
#define NV_XVE1_MSI_CTRL_NEXT_PTR_PCIEXP 0x00000078 /* C---V */
#define NV_XVE1_MSI_CTRL_CAP_ID 7:0 /* R-CVF */
#define NV_XVE1_MSI_CTRL_CAP_ID_MSI 0x00000005 /* R-C-V */
#define NV_XVE1_MSI_CTRL_CAP_ID_NULL 0x00000000 /* R---V */
#define NV_XVE1_MSI_LOW_ADDR 0x0000006C /* RW-4R */
#define NV_XVE1_MSI_LOW_ADDR_DWORD 31:2 /* RWIVF */
#define NV_XVE1_MSI_LOW_ADDR_DWORD_0 0x00000000 /* RWI-V */
#define NV_XVE1_MSI_LOW_ADDR_RSVD 1:0 /* C--VF */
#define NV_XVE1_MSI_LOW_ADDR_RSVD_0 0x00000000 /* C---V */
#define NV_XVE1_MSI_UPPER_ADDR 0x00000070 /* RW-4R */
#define NV_XVE1_MSI_UPPER_ADDR_DWORD 31:0 /* RWIVF */
#define NV_XVE1_MSI_UPPER_ADDR_DWORD_0 0x00000000 /* RWI-V */
#define NV_XVE1_MSI_DATA 0x00000074 /* RW-4R */
#define NV_XVE1_MSI_DATA_RSVD 31:16 /* R-IVF */
#define NV_XVE1_MSI_DATA_RSVD_0 0x00000000 /* R-I-V */
#define NV_XVE1_MSI_DATA_NON_RSVD 15:0 /* RWIVF */
#define NV_XVE1_MSI_DATA_NON_RSVD_0 0x00000000 /* RWI-V */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY 0x00000078 /* R--4R */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID 7:0 /* C--VF */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID_INIT 0x00000010 /* C---V */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR 15:8 /* C--VF */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_INIT 0x00000000 /* C---V */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_VERSION 19:16 /* R-IVF */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_VERSION_GEN1 0x00000001 /* R---V */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_VERSION_GEN2 0x00000002 /* R-I-V */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE 23:20 /* C--VF */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_INIT 0x00000000 /* C---V */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED 24:24 /* R-EVF */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED_INIT 0x00000000 /* R-E-V */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER 29:25 /* C--VF */
#define NV_XVE1_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITY 0x0000007C /* R--4R */
#define NV_XVE1_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE 2:0 /* R-IVF */
#define NV_XVE1_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_INIT 0x00000001 /* R-I-V */
#define NV_XVE1_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_128 0x00000000 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_256 0x00000001 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED 4:3 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE 5:5 /* R-IVF */
#define NV_XVE1_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE_INIT 0x00000001 /* R-I-V */
#define NV_XVE1_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY 8:6 /* R-XVF */
#define NV_XVE1_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY 11:9 /* R-XVF */
#define NV_XVE1_DEVICE_CAPABILITY_RSVD 14:12 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITY_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING 15:15 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING_INIT 0x00000001 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE 25:18 /* R-EVF */
#define NV_XVE1_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* R-E-V */
#define NV_XVE1_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE 27:26 /* R-EVF */
#define NV_XVE1_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* R-E-V */
#define NV_XVE1_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET 28:28 /* R-XVF */
#define NV_XVE1_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS 0x00000080 /* RW-4R */
#define NV_XVE1_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE 0:0 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE 1:1 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE 2:2 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE 3:3 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT 0x00000001 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE 7:5 /* RWEVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT 0x00000000 /* RWE-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT 0x00000001 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE 9:9 /* R-IVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE 10:10 /* R-CVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT 0x00000000 /* R-C-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT 0x00000001 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE 14:12 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT 0x00000002 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST 15:15 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_INITIATE_FN_LVL_RST_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED 16:16 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED 19:19 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED 20:20 /* R-IVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING 21:21 /* R-IVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_LINK_CAPABILITIES 0x00000084 /* R--4R */
#define NV_XVE1_LINK_CAPABILITIES_MAX_LINK_SPEED 3:0 /* R-XVF */
#define NV_XVE1_LINK_CAPABILITIES_MAX_LINK_WIDTH 9:4 /* R-XVF */
#define NV_XVE1_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT 11:10 /* R-IVF */
#define NV_XVE1_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT_INIT 0x00000003 /* R-I-V */
#define NV_XVE1_LINK_CAPABILITIES_L0S_EXIT_LATENCY 14:12 /* R-XVF */
#define NV_XVE1_LINK_CAPABILITIES_L1_EXIT_LATENCY 17:15 /* R-XVF */
#define NV_XVE1_LINK_CAPABILITIES_CLOCK_PM 18:18 /* R-IVF */
#define NV_XVE1_LINK_CAPABILITIES_CLOCK_PM_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_LINK_CAPABILITIES_CLOCK_PM_DISABLE 0x00000000 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_CLOCK_PM_ENABLE 0x00000001 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING 19:19 /* C--VF */
#define NV_XVE1_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING 20:20 /* C--VF */
#define NV_XVE1_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION 21:21 /* C--VF */
#define NV_XVE1_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE 22:22 /* R-EVF */
#define NV_XVE1_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_SUPPORTED 0x00000001 /* R-E-V */
#define NV_XVE1_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_PORT_NUMBER 31:24 /* R-XVF */
#define NV_XVE1_LINK_CONTROL_STATUS 0x00000088 /* RW-4R */
#define NV_XVE1_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL 1:0 /* RWEVF */
#define NV_XVE1_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_INIT 0x00000000 /* RWE-V */
#define NV_XVE1_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_DISABLE 0x00000002 /* RW--V */
#define NV_XVE1_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_ENABLE 0x00000003 /* RW--V */
#define NV_XVE1_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY 3:3 /* RWEVF */
#define NV_XVE1_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_INIT 0x00000000 /* RWE-V */
#define NV_XVE1_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_64B 0x00000000 /* RW--V */
#define NV_XVE1_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_128B 0x00000001 /* RW--V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_DISABLE 4:4 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_RETRAIN_LINK 5:5 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_RETRAIN_LINK_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION 6:6 /* RWEVF */
#define NV_XVE1_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION_INIT 0x00000000 /* RWE-V */
#define NV_XVE1_LINK_CONTROL_STATUS_EXTENDED_SYNCH 7:7 /* RWEVF */
#define NV_XVE1_LINK_CONTROL_STATUS_EXTENDED_SYNCH_INIT 0x00000000 /* RWE-V */
#define NV_XVE1_LINK_CONTROL_STATUS_CLOCK_PM 8:8 /* RWEVF */
#define NV_XVE1_LINK_CONTROL_STATUS_CLOCK_PM_INIT 0x00000000 /* RWE-V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN 10:10 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN 11:11 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_SPEED 19:16 /* R--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_SPEED_2P5 0x00000001 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_SPEED_5P0 0x00000002 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_SPEED_8P0 0x00000003 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH 25:20 /* R--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X1 0x00000001 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X2 0x00000002 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X4 0x00000004 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X8 0x00000008 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X16 0x00000010 /* R---V */
#define NV_XVE1_LINK_CONTROL_STATUS_RSVD 26:26 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_TRAINING 27:27 /* R-IVF */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_TRAINING_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON 28:28 /* R-EVF */
#define NV_XVE1_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON_INIT 0x00000001 /* R-E-V */
#define NV_XVE1_LINK_CONTROL_STATUS_DLL_ACTIVE 29:29 /* R-IVF */
#define NV_XVE1_LINK_CONTROL_STATUS_DLL_ACTIVE_INIT 0x00000000 /* R-I-V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT 30:30 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH 31:31 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES 0x0000008C /* C--4R */
#define NV_XVE1_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT 0:0 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT 1:1 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT 2:2 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT 3:3 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT 4:4 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE 5:5 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE 6:6 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE 14:7 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE 16:15 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT 17:17 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT 18:18 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_NO_COMMAND_COMPLETED_SUPPORT_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER 31:19 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS 0x00000090 /* C--4R */
#define NV_XVE1_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE 0:0 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE 1:1 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE 2:2 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE 3:3 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE 4:4 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE 5:5 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL 7:6 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL 9:8 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL 10:10 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL 11:11 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE 12:12 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED 16:16 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED 17:17 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED 18:18 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED 19:19 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_COMMAND_COMPLETED 20:20 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE 21:21 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE 22:22 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS 23:23 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATUS_INIT 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED 24:24 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_DATA_LINK_LAYER_STATE_CHANGED_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2 0x0000009C /* R--4R */
#define NV_XVE1_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES 3:0 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGES_A_AND_B 0x00000003 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE 4:4 /* R-IVF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_SUPPORTED 0x00000001 /* R-I-V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ARI_FORWARDING 5:5 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ARI_FORWARDING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING 6:6 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ATOMIC_OP_ROUTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT 7:7 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_32BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT 8:8 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_ATOMIC_COMPLETER_64BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT 9:9 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_CAS_COMPLETER_128BIT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING 11:11 /* R--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_LATENCY_TOLERANCE_REPORTING_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_TPH_COMPLETER 13:12 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_TPH_COMPLETER_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER 16:16 /* R--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED 0x00000001 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER 17:17 /* R-EVF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED 0x00000001 /* R-E-V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_OBFF 19:18 /* R--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_OBFF_NOT_SUPPORTED 0x00000000 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_SGNL 0x00000001 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_WAKE_SGNL 0x00000002 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_MSG_WAKE_SGNL 0x00000003 /* R---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_EXTENDED_FMT 20:20 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_EXTENDED_FMT_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX 21:21 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX 23:22 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIX_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CAPABILITIES_2_BITS 31:24 /* C--VF */
#define NV_XVE1_DEVICE_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2 0x000000A0 /* RWI4R */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES 3:0 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_LO 0x00000001 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_HI 0x00000002 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_LO 0x00000005 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_HI 0x00000006 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_DEFAULT 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE 4:4 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_ENABLED 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_DISABLED 0x00000001 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE 5:5 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE 6:6 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING 7:7 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE 8:8 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE 9:9 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_LTR_ENABLE 10:10 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE 12:12 /* RWIVF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_INIT 0x00000000 /* RWI-V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_10_BIT_TAG_REQ_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE 14:13 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_BITS 31:15 /* C--VF */
#define NV_XVE1_DEVICE_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_LINK_CAPABILITIES_2 0x000000A4 /* R--4R */
#define NV_XVE1_LINK_CAPABILITIES_2_RSVD 0:0 /* C--VF */
#define NV_XVE1_LINK_CAPABILITIES_2_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED 7:1 /* R-EVF */
#define NV_XVE1_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN 0x00000000 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1 0x00000001 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2 0x00000003 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3 0x00000007 /* R-E-V */
#define NV_XVE1_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT 8:8 /* C--VF */
#define NV_XVE1_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED 0x00000000 /* C---V */
#define NV_XVE1_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP 23:23 /* R--VF */
#define NV_XVE1_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_2_RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP 24:24 /* R--VF */
#define NV_XVE1_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_2_2RET_PRESENCE_DET_SUPP_UNSET 0x00000000 /* R---V */
#define NV_XVE1_LINK_CAPABILITIES_2_BITS 31:25 /* C--VF */
#define NV_XVE1_LINK_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2 0x000000A8 /* R--4R */
#define NV_XVE1_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED 3:0 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_GEN2_PROTO_DISABLED 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE 4:4 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE 5:5 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_RVSD 6:6 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_RVSD_0 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN 9:7 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE 10:10 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS 11:11 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS 15:12 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_CUR_DEEMPHASIS_LEVEL 16:16 /* R--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE 17:17 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL 18:18 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL 19:19 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL 20:20 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST 21:21 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_INIT 0x00000000 /* C---V */
#define NV_XVE1_LINK_CONTROL_STATUS_2_BITS 31:22 /* C--VF */
#define NV_XVE1_LINK_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CAPABILITIES_2 0x000000AC /* C--4R */
#define NV_XVE1_SLOT_CAPABILITIES_2_BITS 31:0 /* C--VF */
#define NV_XVE1_SLOT_CAPABILITIES_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_SLOT_CONTROL_STATUS_2 0x000000B0 /* C--4R */
#define NV_XVE1_SLOT_CONTROL_STATUS_2_BITS 31:0 /* C--VF */
#define NV_XVE1_SLOT_CONTROL_STATUS_2_BITS_0 0x00000000 /* C---V */
#define NV_XVE1_AER_CAP_HDR 0x00000100 /* R--4R */
#define NV_XVE1_AER_CAP_HDR_ID 15:0 /* R-IVF */
#define NV_XVE1_AER_CAP_HDR_ID_LINK_DEC 0x00000001 /* R---V */
#define NV_XVE1_AER_CAP_HDR_ID_AER_DISABLED 0x00000000 /* R-I-V */
#define NV_XVE1_AER_CAP_HDR_ID_VERSION 19:16 /* R-IVF */
#define NV_XVE1_AER_CAP_HDR_ID_VERSION_1 0x00000001 /* R---V */
#define NV_XVE1_AER_CAP_HDR_ID_VERSION_2 0x00000002 /* R-I-V */
#define NV_XVE1_AER_CAP_HDR_ID_VERSION_AER_DISABLED 0x00000000 /* R---V */
#define NV_XVE1_AER_CAP_HDR_ID_NEXT_PTR 31:20 /* R-IVF */
#define NV_XVE1_AER_CAP_HDR_ID_NEXT_PTR_ARI 0x0000012C /* R-I-V */
#define NV_XVE1_AER_CAP_HDR_ID_NEXT_PTR_GEN4 0x00000160 /* R---V */
#define NV_XVE1_AER_CAP_HDR_ID_NEXT_PTR_NONE 0x00000000 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR 0x00000104 /* RW-4R */
#define NV_XVE1_AER_UNCORR_ERR_RSVD 0:0 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_DLINK_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_DLINK_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_DLINK_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SURPRISE_DOWN_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_POISONED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_POISONED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_POISONED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_FC_PROTO_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_FC_PROTO_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_FC_PROTO_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_CPL_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_CPL_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_CPL_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_CPL_ABORT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_CPL_ABORT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_CPL_ABORT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_UNEXP_CPL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_UNEXP_CPL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_UNEXP_CPL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_RCVR_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_RCVR_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_RCVR_OVERFLOW_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MALFORMED_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_MALFORMED_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_MALFORMED_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_ECRC_ERROR 19:19 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_ECRC_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_UNSUPPORTED_REQ_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_UNCORR_ERR_UNSUPPORTED_REQ_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_UNCORR_ERR_UNSUPPORTED_REQ_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_UNCORR_ERR_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_INTERNAL_ERROR 22:22 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK 0x00000108 /* RW-4R */
#define NV_XVE1_AER_UNCORR_ERR_MASK_RSVD 0:0 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_SURPRISE_DOWN_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_POISONED_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_POISONED_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_CPL_ABORT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_CPL_ABORT_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_UNEXP_CPL_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_UNEXP_CPL_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_MALFORMED_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_MALFORMED_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_ECRC_ERR 19:19 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_ECRC_ERR_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_INTERNAL_ERROR 22:22 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_MASK_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR 0x0000010C /* RW-4R */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_RSVD 0:0 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR 4:4 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_FATAL 0x00000001 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN 5:5 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN_INIT 0x00000001 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_POISONED_TLP 12:12 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_POISONED_TLP_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_POISONED_TLP_FATAL 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR 13:13 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_FATAL 0x00000001 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT 14:14 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_FATAL 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_CPL_ABORT 15:15 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_CPL_ABORT_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_CPL_ABORT_FATAL 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_UNEXP_CPL 16:16 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_UNEXP_CPL_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_UNEXP_CPL_FATAL 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW 17:17 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_FATAL 0x00000001 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_MALFORMED_TLP 18:18 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_NON_FATAL 0x00000000 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_FATAL 0x00000001 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_ECRC_ERR 19:19 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_ECRC_ERR_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ 20:20 /* RWCVF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_NON_FATAL 0x00000000 /* RWC-V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_FATAL 0x00000001 /* RW--V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_ACS_VIOLATION 21:21 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_ACS_VIOLATION_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR 22:22 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR_INIT 0x00000001 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP 23:23 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED 24:24 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED 25:25 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED 26:26 /* C--VF */
#define NV_XVE1_AER_UNCORR_ERR_SEVR_POISONED_TLP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_CORR_ERR 0x00000110 /* RW-4R */
#define NV_XVE1_AER_CORR_ERR_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_RCV_ERR_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_CORR_ERR_RCV_ERR_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_CORR_ERR_RCV_ERR_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_CORR_ERR_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_BAD_TLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_CORR_ERR_BAD_TLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_CORR_ERR_BAD_TLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_CORR_ERR_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_BAD_DLLP_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_CORR_ERR_BAD_DLLP_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_CORR_ERR_BAD_DLLP_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_CORR_ERR_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_RPLY_ROLLOVER_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_CORR_ERR_RPLY_ROLLOVER_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_CORR_ERR_RPLY_ROLLOVER_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_CORR_ERR_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_RPLY_TIMEOUT_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_CORR_ERR_RPLY_TIMEOUT_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_CORR_ERR_RPLY_TIMEOUT_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_CORR_ERR_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_CORR_ERR_INTERNAL_ERROR 14:14 /* C--VF */
#define NV_XVE1_AER_CORR_ERR_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_CORR_ERR_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_HEADER_LOG_OVERFLOW_NOT_ACTIVE 0x00000000 /* R-C-V */
#define NV_XVE1_AER_CORR_ERR_HEADER_LOG_OVERFLOW_ACTIVE 0x00000001 /* R---V */
#define NV_XVE1_AER_CORR_ERR_HEADER_LOG_OVERFLOW_CLEAR 0x00000001 /* -W--C */
#define NV_XVE1_AER_CORR_ERR_MASK 0x00000114 /* RW-4R */
#define NV_XVE1_AER_CORR_ERR_MASK_RCV_ERR 0:0 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_MASK_RCV_ERR_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_CORR_ERR_MASK_RCV_ERR_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_CORR_ERR_MASK_BAD_TLP 6:6 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_MASK_BAD_TLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_CORR_ERR_MASK_BAD_TLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_CORR_ERR_MASK_BAD_DLLP 7:7 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_MASK_BAD_DLLP_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_CORR_ERR_MASK_BAD_DLLP_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_CORR_ERR_MASK_RPLY_ROLLOVER 8:8 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_MASK_RPLY_ROLLOVER_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_CORR_ERR_MASK_RPLY_ROLLOVER_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_CORR_ERR_MASK_RPLY_TIMEOUT 12:12 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_MASK_RPLY_TIMEOUT_NOT_MASKED 0x00000000 /* RWC-V */
#define NV_XVE1_AER_CORR_ERR_MASK_RPLY_TIMEOUT_MASKED 0x00000001 /* RW--V */
#define NV_XVE1_AER_CORR_ERR_MASK_ADVISORY_NONFATAL 13:13 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_NOT_MASKED 0x00000000 /* RW--V */
#define NV_XVE1_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_MASKED 0x00000001 /* RWC-V */
#define NV_XVE1_AER_CORR_ERR_MASK_INTERNAL_ERROR 14:14 /* C--VF */
#define NV_XVE1_AER_CORR_ERR_MASK_INTERNAL_ERROR_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW 15:15 /* RWCVF */
#define NV_XVE1_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_NOT_MASKED 0x00000000 /* RW--V */
#define NV_XVE1_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_MASKED 0x00000001 /* RWC-V */
#define NV_XVE1_AER_CAP_CNTL 0x00000118 /* RW-4R */
#define NV_XVE1_AER_CAP_CNTL_ERR_PTR 4:0 /* R--VF */
#define NV_XVE1_AER_CAP_CNTL_ECRC_GEN_CAP 5:5 /* C--VF */
#define NV_XVE1_AER_CAP_CNTL_ECRC_GEN_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE1_AER_CAP_CNTL_ECRC_GEN_EN 6:6 /* RWCVF */
#define NV_XVE1_AER_CAP_CNTL_ECRC_GEN_EN_FALSE 0x00000000 /* RWC-V */
#define NV_XVE1_AER_CAP_CNTL_ECRC_GEN_EN_TRUE 0x00000001 /* RW--V */
#define NV_XVE1_AER_CAP_CNTL_ECRC_CHK_CAP 7:7 /* C--VF */
#define NV_XVE1_AER_CAP_CNTL_ECRC_CHK_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE1_AER_CAP_CNTL_ECRC_CHK_EN 8:8 /* RWCVF */
#define NV_XVE1_AER_CAP_CNTL_ECRC_CHK_EN_FALSE 0x00000000 /* RWC-V */
#define NV_XVE1_AER_CAP_CNTL_ECRC_CHK_EN_TRUE 0x00000001 /* RW--V */
#define NV_XVE1_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP 9:9 /* C--VF */
#define NV_XVE1_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_CAP_FALSE 0x00000000 /* C---V */
#define NV_XVE1_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN 10:10 /* C--VF */
#define NV_XVE1_AER_CAP_CNTL_MULTIPLE_HDR_RECORDING_EN_FALSE 0x00000000 /* C---V */
#define NV_XVE1_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT 11:11 /* C--VF */
#define NV_XVE1_AER_CAP_CNTL_TLP_PREFIX_LOG_PRESENT_INIT 0x00000000 /* C---V */
#define NV_XVE1_AER_HDR_LOG_DW0 0x0000011C /* R--4R */
#define NV_XVE1_AER_HDR_LOG_DW0_0 31:0 /* R-CVF */
#define NV_XVE1_AER_HDR_LOG_DW0_0_INIT 0x00000000 /* R-C-V */
#define NV_XVE1_AER_HDR_LOG_DW1 0x00000120 /* R--4R */
#define NV_XVE1_AER_HDR_LOG_DW1_1 31:0 /* R-CVF */
#define NV_XVE1_AER_HDR_LOG_DW1_1_INIT 0x00000000 /* R-C-V */
#define NV_XVE1_AER_HDR_LOG_DW2 0x00000124 /* R--4R */
#define NV_XVE1_AER_HDR_LOG_DW2_2 31:0 /* R-CVF */
#define NV_XVE1_AER_HDR_LOG_DW2_2_INIT 0x00000000 /* R-C-V */
#define NV_XVE1_AER_HDR_LOG_DW3 0x00000128 /* R--4R */
#define NV_XVE1_AER_HDR_LOG_DW3_3 31:0 /* R-CVF */
#define NV_XVE1_AER_HDR_LOG_DW3_3_INIT 0x00000000 /* R-C-V */
#define NV_XVE1_ARI_CAP0 0x0000012C /* R--4R */
#define NV_XVE1_ARI_CAP0_CAPID 15:0 /* C--VF */
#define NV_XVE1_ARI_CAP0_CAPID_EXT_CAP 0x0000000E /* C---V */
#define NV_XVE1_ARI_CAP0_HDR0_ID_VERSION 19:16 /* C--VF */
#define NV_XVE1_ARI_CAP0_HDR0_ID_VERSION_1 0x00000001 /* C---V */
#define NV_XVE1_ARI_CAP0_HDR0_ID_NEXT_PTR 31:20 /* R-IVF */
#define NV_XVE1_ARI_CAP0_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* R---V */
#define NV_XVE1_ARI_CAP0_HDR0_ID_NEXT_PTR_GEN4 0x00000160 /* R-I-V */
#define NV_XVE1_ARI_CAP1 0x00000130 /* R--4R */
#define NV_XVE1_ARI_CAP1_MFVC_FN_GRPS_CAP 0:0 /* C--VF */
#define NV_XVE1_ARI_CAP1_MFVC_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE1_ARI_CAP1_ACS_FN_GRPS_CAP 1:1 /* C--VF */
#define NV_XVE1_ARI_CAP1_ACS_FN_GRPS_CAP_UNSUPP 0x00000000 /* C---V */
#define NV_XVE1_ARI_CAP1_NXT_FN_NUM 15:8 /* R--VF */
#define NV_XVE1_ARI_CAP1_NXT_FN_NUM_VAL 0x00000002 /* R---V */
#define NV_XVE1_ARI_CAP1_MFVC_FN_GRPS_EN 16:16 /* C--VF */
#define NV_XVE1_ARI_CAP1_MFVC_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE1_ARI_CAP1_ACS_FN_GRPS_EN 17:17 /* C--VF */
#define NV_XVE1_ARI_CAP1_ACS_FN_GRPS_EN_UNSET 0x00000000 /* C---V */
#define NV_XVE1_ARI_CAP1_FN_GRP 22:20 /* C--VF */
#define NV_XVE1_ARI_CAP1_FN_GRP_ZERO 0x00000000 /* C---V */
#define NV_XVE1_DL_FEATURE_EXT_CAP_HDR 0x00000160 /* C--4R */
#define NV_XVE1_DL_FEATURE_EXT_CAP_HDR_CAPID 15:0 /* C--VF */
#define NV_XVE1_DL_FEATURE_EXT_CAP_HDR_CAPID_EXT_CAP 0x00000025 /* C---V */
#define NV_XVE1_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION 19:16 /* C--VF */
#define NV_XVE1_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_VERSION_1 0x00000001 /* C---V */
#define NV_XVE1_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR 31:20 /* C--VF */
#define NV_XVE1_DL_FEATURE_EXT_CAP_HDR_HDR0_ID_NEXT_PTR_NONE 0x00000000 /* C---V */
#define NV_XVE1_DL_FEATURE_CAP 0x00000164 /* R--4R */
#define NV_XVE1_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP 0:0 /* R-EVF */
#define NV_XVE1_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */
#define NV_XVE1_DL_FEATURE_CAP_LOCAL_SCALED_FC_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE1_DL_FEATURE_CAP_RSVDP 22:1 /* C--VF */
#define NV_XVE1_DL_FEATURE_CAP_RSVDP_NULL 0x00000000 /* C---V */
#define NV_XVE1_DL_FEATURE_CAP_EXCH_EN 31:31 /* R-EVF */
#define NV_XVE1_DL_FEATURE_CAP_EXCH_EN_SET 0x00000001 /* R---V */
#define NV_XVE1_DL_FEATURE_CAP_EXCH_EN_UNSET 0x00000000 /* R-E-V */
#define NV_XVE1_DL_FEATURE_STATUS 0x00000168 /* R--4R */
#define NV_XVE1_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP 0:0 /* R-EVF */
#define NV_XVE1_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_UNSET 0x00000000 /* R-E-V */
#define NV_XVE1_DL_FEATURE_STATUS_REMOTE_SCALED_FC_SUPP_SET 0x00000001 /* R---V */
#define NV_XVE1_DL_FEATURE_STATUS_RSVDP 22:1 /* C--VF */
#define NV_XVE1_DL_FEATURE_STATUS_RSVDP_NULL 0x00000000 /* C---V */
#define NV_XVE1_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD 31:31 /* R-EVF */
#define NV_XVE1_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_UNSET 0x00000000 /* R-E-V */
#define NV_XVE1_DL_FEATURE_STATUS_REMOTE_DL_SUPP_VLD_SET 0x00000001 /* R---V */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA 0x0000016C /* RW-4R */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA__PRIV_LEVEL_MASK 0x00000800 /* */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_DL_UP 0:0 /* RWCVF */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_DL_UP_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_DL_UP_RESET 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_DL_UP_NORESET 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_HOT_RESET 8:8 /* RWCVF */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_HOT_RESET_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_HOT_RESET_RESET 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_CYA_RESET_AZA_HOT_RESET_NORESET 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG 0x00000170 /* RW-4R */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG__PRIV_LEVEL_MASK 0x00000804 /* */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_DL_UP 0:0 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_DL_UP_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_DL_UP_RESET 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_DL_UP_NORESET 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET 8:8 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET_RESET 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_XV_0_CYA_RESET_CFG_HOT_RESET_NORESET 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_XV_TIMEOUT 0x00000148 /* RW-4R */
#define NV_XVE1_PRIV_XV_TIMEOUT_MILLISECOND 7:0 /* RWCVF */
#define NV_XVE1_PRIV_XV_TIMEOUT_MILLISECOND_16 0x00000010 /* RWC-V */
#define NV_XVE1_PRIV_XV_TIMEOUT_DISABLE 8:8 /* RWCVF */
#define NV_XVE1_PRIV_XV_TIMEOUT_DISABLE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_TIMEOUT_OVERRIDE 16:16 /* RWCVF */
#define NV_XVE1_PRIV_XV_TIMEOUT_OVERRIDE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_TIMEOUT_OVERRIDE_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_XV_TIMEOUT_OVERRIDE_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC 0x0000014C /* RW-4R */
#define NV_XVE1_PRIV_MISC_CYA_IGNORE_POISONED_WDATA 23:23 /* RWCVF */
#define NV_XVE1_PRIV_MISC_CYA_IGNORE_POISONED_WDATA_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_AZA_COHERENT_RELAXED_ORDERING 24:24 /* RWCVF */
#define NV_XVE1_PRIV_MISC_AZA_COHERENT_RELAXED_ORDERING_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_MISC_AZA_NON_COHERENT_RELAXED_ORDERING 25:25 /* RWCVF */
#define NV_XVE1_PRIV_MISC_AZA_NON_COHERENT_RELAXED_ORDERING_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_MISC_CYA_GPIO_D3HOT_POLARITY 28:28 /* RWCVF */
#define NV_XVE1_PRIV_MISC_CYA_GPIO_D3HOT_POLARITY_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_CYA_GPIO_D3HOT_IGNORE 29:29 /* RWCVF */
#define NV_XVE1_PRIV_MISC_CYA_GPIO_D3HOT_IGNORE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_CYA_PMCSR_POWER_STATE_D3HOT_IGNORE 31:31 /* RWCVF */
#define NV_XVE1_PRIV_MISC_CYA_PMCSR_POWER_STATE_D3HOT_IGNORE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_0 0x00000150 /* RW-4R */
#define NV_XVE1_PRIV_XV_0_UNUSED 3:0 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_UNUSED_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_USE_SERR_ENABLE_FOR_ERROR_REPORTING 6:6 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_USE_SERR_ENABLE_FOR_ERROR_REPORTING_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_L0S_ENABLE 7:7 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_L0S_ENABLE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_L1_ENABLE 8:8 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_L1_ENABLE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_FORCE_SNOOP_WRITES_VC0 25:25 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_FORCE_SNOOP_WRITES_VC0_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_FORCE_SNOOP_READS_VC0 26:26 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_FORCE_SNOOP_READS_VC0_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_XV_0_CYA_D3HOT_NO_SOFT_RESET 31:31 /* RWCVF */
#define NV_XVE1_PRIV_XV_0_CYA_D3HOT_NO_SOFT_RESET_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_XV_0_CYA_D3HOT_NO_SOFT_RESET_ENABLE 0x00000001 /* RWC-V */
#define NV_XVE1_CYA_0 0x00000154 /* RW-4R */
#define NV_XVE1_CYA_0__PRIV_LEVEL_MASK 0x00000808 /* */
#define NV_XVE1_CYA_0_RSVD1 3:0 /* RWCVF */
#define NV_XVE1_CYA_0_RSVD1_VAL 0x00000000 /* RWC-V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1 6:4 /* RWCVF */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_LESS_THAN_1US 0x00000000 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_1US_TO_2US 0x00000001 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_2US_TO_4US 0x00000002 /* RWC-V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_4US_TO_8US 0x00000003 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_8US_TO_16US 0x00000004 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_16US_TO_32US 0x00000005 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_32US_TO_64US 0x00000006 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN1_MORE_THAN_64US 0x00000007 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2 9:7 /* RWCVF */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_LESS_THAN_1US 0x00000000 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_1US_TO_2US 0x00000001 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_2US_TO_4US 0x00000002 /* RWC-V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_4US_TO_8US 0x00000003 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_8US_TO_16US 0x00000004 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_16US_TO_32US 0x00000005 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_32US_TO_64US 0x00000006 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN2_MORE_THAN_64US 0x00000007 /* R---V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY 14:12 /* RWCVF */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_LESS_THAN_64NS 0x00000000 /* R---V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_64NS_TO_128NS 0x00000001 /* R---V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_128NS_TO_256NS 0x00000002 /* R---V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_256NS_TO_512NS 0x00000003 /* R---V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_512NS_TO_1US 0x00000004 /* R---V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_1US_TO_2US 0x00000005 /* R---V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_2US_TO_4US 0x00000006 /* RW--V */
#define NV_XVE1_CYA_0_L0S_ACCEPTABLE_LATENCY_MORE_THAN_4US 0x00000007 /* R-C-V */
#define NV_XVE1_CYA_0_RSVD_0 18:15 /* RWCVF */
#define NV_XVE1_CYA_0_RSVD_0_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3 21:19 /* RWCVF */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_LESS_THAN_1US 0x00000000 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_1US_TO_2US 0x00000001 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_2US_TO_4US 0x00000002 /* RWC-V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_4US_TO_8US 0x00000003 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_8US_TO_16US 0x00000004 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_16US_TO_32US 0x00000005 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_32US_TO_64US 0x00000006 /* R---V */
#define NV_XVE1_CYA_0_L1_EXIT_LATENCY_GEN3_MORE_THAN_64US 0x00000007 /* R---V */
#define NV_XVE1_CYA_1 0x00000158 /* RW-4R */
#define NV_XVE1_CYA_1_SKIP_UR_INCR_CE_CNT 0:0 /* RWCVF */
#define NV_XVE1_CYA_1_SKIP_UR_INCR_CE_CNT_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_CYA_1_UNUSED 31:1 /* RWCVF */
#define NV_XVE1_CYA_1_UNUSED_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_SOR_EXPOSED 0x0000015C /* RW-4R */
#define NV_XVE1_SOR_EXPOSED__PRIV_LEVEL_MASK 0x000007FC /* */
#define NV_XVE1_SOR_EXPOSED_SOR0 0:0 /* RWCVF */
#define NV_XVE1_SOR_EXPOSED_SOR0_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_SOR_EXPOSED_SOR0_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SOR0_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SOR1 1:1 /* RWCVF */
#define NV_XVE1_SOR_EXPOSED_SOR1_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_SOR_EXPOSED_SOR1_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SOR1_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SOR2 2:2 /* RWCVF */
#define NV_XVE1_SOR_EXPOSED_SOR2_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_SOR_EXPOSED_SOR2_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SOR2_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SOR3 3:3 /* RWCVF */
#define NV_XVE1_SOR_EXPOSED_SOR3_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_SOR_EXPOSED_SOR3_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SOR3_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_OVERRIDE 30:30 /* RWCVF */
#define NV_XVE1_SOR_EXPOSED_OVERRIDE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_SOR_EXPOSED_OVERRIDE_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_OVERRIDE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SCRATCH 31:31 /* RWCVF */
#define NV_XVE1_SOR_EXPOSED_SCRATCH_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_SOR_EXPOSED_SCRATCH_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_SOR_EXPOSED_SCRATCH_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_1 0x0000041C /* RW-4R */
#define NV_XVE1_PRIV_MISC_1__PRIV_LEVEL_MASK 0x000007FC /* */
#define NV_XVE1_PRIV_MISC_1_CYA_AER 8:8 /* RWCVF */
#define NV_XVE1_PRIV_MISC_1_CYA_AER_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_AER_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_AER_INIT 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_MISC_1_CYA_RSVD_NO_CPL_BUBBLE 15:15 /* RWCVF */
#define NV_XVE1_PRIV_MISC_1_CYA_RSVD_NO_CPL_BUBBLE_ENABLE 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_MISC_1_CYA_RSVD_NO_CPL_BUBBLE_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY 21:19 /* RWCVF */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_INIT 0x00000006 /* RWC-V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_LESS_THAN_1US 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_1US_TO_2US 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_2US_TO_4US 0x00000002 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_4US_TO_8US 0x00000003 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_8US_TO_16US 0x00000004 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_16US_TO_32US 0x00000005 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_32US_TO_64US 0x00000006 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_MORE_THAN_64US 0x00000006 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_SIDEBAND_INTERRUPT_MODE 27:27 /* RWCVF */
#define NV_XVE1_PRIV_MISC_1_CYA_SIDEBAND_INTERRUPT_MODE_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_SIDEBAND_INTERRUPT_MODE_DISABLED 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_SIDEBAND_INTERRUPT_MODE_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING 28:28 /* RWCVF */
#define NV_XVE1_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_ENABLE 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_DISABLE 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_2 0x0000048C /* RW-4R */
#define NV_XVE1_PRIV_MISC_2__PRIV_LEVEL_MASK 0x000007FC /* */
#define NV_XVE1_PRIV_MISC_2_DS_FN2VC_MAP_ENABLE 6:6 /* RWCVF */
#define NV_XVE1_PRIV_MISC_2_DS_FN2VC_MAP_ENABLE_SET 0x00000001 /* RWC-V */
#define NV_XVE1_PRIV_MISC_2_DS_FN2VC_MAP_ENABLE_CLEAR 0x00000000 /* RW--V */
#define NV_XVE1_PRIV_MISC_2_DS_FN2VC_MAP 9:7 /* RWCVF */
#define NV_XVE1_PRIV_MISC_2_DS_FN2VC_MAP_VC0 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_2_US_FN2VC_MAP 12:10 /* RWCVF */
#define NV_XVE1_PRIV_MISC_2_US_FN2VC_MAP_VC1 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_2_SUBSYSTEM_ID_LOCK 13:13 /* RWCVF */
#define NV_XVE1_PRIV_MISC_2_SUBSYSTEM_ID_LOCK_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_PRIV_MISC_2_SUBSYSTEM_ID_LOCK_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_PRIV_MISC_2_UNUSED 31:14 /* RWCVF */
#define NV_XVE1_PRIV_MISC_2_UNUSED_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER 0x000004AC /* R--4R */
#define NV_XVE1_ERROR_COUNTER_RSVD 7:0 /* C--VF */
#define NV_XVE1_ERROR_COUNTER_RSVD_INIT 0x00000000 /* C---V */
#define NV_XVE1_ERROR_COUNTER_NON_FATAL_ERROR_COUNT_VALUE 15:8 /* R-XVF */
#define NV_XVE1_ERROR_COUNTER_FATAL_ERROR_COUNT_VALUE 23:16 /* R-XVF */
#define NV_XVE1_ERROR_COUNTER_UNSUPP_REQ_COUNT_VALUE 31:24 /* R-XVF */
#define NV_XVE1_ERROR_COUNTER1 0x000004B0 /* R--4R */
#define NV_XVE1_ERROR_COUNTER1_CORR_ERROR_COUNT_VALUE 15:0 /* R-XVF */
#define NV_XVE1_ERROR_COUNTER_FREEZE 0x000004B4 /* RW-4R */
#define NV_XVE1_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT 0:0 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT 1:1 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT 2:2 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT 3:3 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT_DISABLED 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT_ENABLED 0x00000001 /* RW--V */
#define NV_XVE1_ERROR_COUNTER_RESET 0x000004B8 /* RW-4R */
#define NV_XVE1_ERROR_COUNTER_RESET_RSVD1 4:0 /* C--VF */
#define NV_XVE1_ERROR_COUNTER_RESET_RSVD1_INIT 0x00000000 /* C---V */
#define NV_XVE1_ERROR_COUNTER_RESET_CORR_ERROR_COUNT 5:5 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_DONE 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XVE1_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT 6:6 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_DONE 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XVE1_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT 7:7 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_DONE 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XVE1_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT 8:8 /* RWCVF */
#define NV_XVE1_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_DONE 0x00000000 /* RWC-V */
#define NV_XVE1_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_PENDING 0x00000001 /* -W--T */
#define NV_XVE1_ERROR_COUNTER_RESET_RSVD2 14:9 /* C--VF */
#define NV_XVE1_ERROR_COUNTER_RESET_RSVD2_INIT 0x00000000 /* C---V */
#define NV_XVE1_CYA_2 0x00000704 /* RW-4R */
#define NV_XVE1_CYA_2_RSVD 31:0 /* RWCVF */
#define NV_XVE1_CYA_2_RSVD_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_CYA_3 0x00000708 /* RW-4R */
#define NV_XVE1_CYA_3_RSVD 31:0 /* RWCVF */
#define NV_XVE1_CYA_3_RSVD_INIT 0x00000000 /* RWC-V */
#define NV_XVE1_DBG0 0x0000070C /* RW-4R */
#define NV_XVE1_DBG0_OUTSTANDING_UPSTREAM_READ 8:0 /* R--VF */
#define NV_XVE1_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET 9:9 /* RWCVF */
#define NV_XVE1_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_TRIGGER 0x00000001 /* -W--T */
#define NV_XVE1_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_DONE 0x00000000 /* R-C-V */
#define NV_XVE1_DBG0_OUTSTANDING_DOWNSTREAM_READ_CNTR_RESET_PENDING 0x00000001 /* R---V */
#define NV_XVE1_DBG0_OUTSTANDING_DOWNSTREAM_READ 19:12 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_POS_DW0 0x00000710 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_POS_DW0_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_POS_DW1 0x00000714 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_POS_DW1_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_POS_DW2 0x00000718 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_POS_DW2_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_POS_DW3 0x0000071C /* R--4R */
#define NV_XVE1_DBG_HDRLOG_POS_DW3_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_UR_DW0 0x00000720 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_UR_DW0_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_UR_DW1 0x00000724 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_UR_DW1_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_UR_DW2 0x00000728 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_UR_DW2_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_UR_DW3 0x0000072C /* R--4R */
#define NV_XVE1_DBG_HDRLOG_UR_DW3_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW0 0x00000730 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW0_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW1 0x00000734 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW1_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW2 0x00000738 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW2_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW3 0x0000073C /* R--4R */
#define NV_XVE1_DBG_HDRLOG_MALFORMED_DW3_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_UNEXP_CPL_DW0 0x00000740 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_UNEXP_CPL_DW0_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_UNEXP_CPL_DW1 0x00000744 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_UNEXP_CPL_DW1_0 31:0 /* R--VF */
#define NV_XVE1_DBG_HDRLOG_UNEXP_CPL_DW2 0x00000748 /* R--4R */
#define NV_XVE1_DBG_HDRLOG_UNEXP_CPL_DW2_0 31:0 /* R--VF */
#define NV_XVE1_CYA_FLR_RESET 0x000074C /* RW-4R */
#define NV_XVE1_CYA_FLR_RESET__PRIV_LEVEL_MASK 0x000007FC /* */
#define NV_XVE1_CYA_FLR_RESET_BUSY_OVERRIDE 0:0 /* RWCVF */
#define NV_XVE1_CYA_FLR_RESET_BUSY_OVERRIDE_VAL 0x0000000 /* RWC-V */
#define NV_XVE1_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH 8:1 /* RWCVF */
#define NV_XVE1_CYA_FLR_RESET_BUSY_STRETCH_COUNTER_WIDTH_VAL 0x0000010 /* RWC-V */
#endif // __ga102_dev_nv_xve1_h__
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