873 lines
71 KiB
C
873 lines
71 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_esched_pbdma_h__
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#define __ga102_dev_esched_pbdma_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PBDMA 0x000007ff:0x00000000 /* RW--D */
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#define NV_GPENTRY 0x00000007:0x00000000 /* ----M */
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#define NV_GPENTRY_ENTRY_SIZE 8 /* */
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#define NV_GPENTRY_OPERAND 31:0 /* RW-UF */
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#define NV_GPENTRY_FETCH 0:0 /* RW-UF */
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#define NV_GPENTRY_FETCH_UNCONDITIONAL 0x00000000 /* RW--V */
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#define NV_GPENTRY_FETCH_CONDITIONAL 0x00000001 /* RW--V */
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#define NV_GPENTRY_GET 31:2 /* RW-UF */
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#define NV_GPENTRY_GET_HI 39:32 /* RW-UF */
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#define NV_GPENTRY_LEVEL 41:41 /* RW-UF */
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#define NV_GPENTRY_LEVEL_MAIN 0x00000000 /* RW--V */
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#define NV_GPENTRY_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_GPENTRY_LENGTH 62:42 /* RW-UF */
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#define NV_GPENTRY_LENGTH_CONTROL 0x00000000 /* RW--V */
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#define NV_GPENTRY_SYNC 63:63 /* RW-UF */
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#define NV_GPENTRY_SYNC_PROCEED 0x00000000 /* RW--V */
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#define NV_GPENTRY_SYNC_WAIT 0x00000001 /* RW--V */
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#define NV_GPENTRY_OPCODE 39:32 /* RW-UF */
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#define NV_GPENTRY_OPCODE_NOP 0x00000000 /* RW--V */
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#define NV_GPENTRY_OPCODE_ILLEGAL 0x00000001 /* RW--V */
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#define NV_GPENTRY_OPCODE_GP_CRC 0x00000002 /* RW--V */
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#define NV_GPENTRY_OPCODE_PB_CRC 0x00000003 /* RW--V */
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#define NV_PBDMA_GP_BASE 0x048 /* RW-4R */
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#define NV_PBDMA_GP_BASE_OFFSET 31:3 /* RWXUF */
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#define NV_PBDMA_GP_BASE_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_BASE_RSVD 2:0 /* RWXUF */
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#define NV_PBDMA_GP_BASE_RSVD_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_BASE_HI 0x04c /* RW-4R */
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#define NV_PBDMA_GP_BASE_HI_OFFSET 7:0 /* RWXUF */
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#define NV_PBDMA_GP_BASE_HI_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_BASE_HI_LIMIT2 20:16 /* RWXUF */
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#define NV_PBDMA_GP_BASE_HI_LIMIT2_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_BASE_HI_RSVDA 15:8 /* RWXUF */
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#define NV_PBDMA_GP_BASE_HI_RSVDA_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_BASE_HI_RSVDB 31:21 /* RWXUF */
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#define NV_PBDMA_GP_BASE_HI_RSVDB_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_FETCH 0x050 /* RW-4R */
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#define NV_PBDMA_GP_FETCH_ENTRY 31:0 /* RWXUF */
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#define NV_PBDMA_GP_FETCH_ENTRY_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_GET 0x014 /* RW-4R */
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#define NV_PBDMA_GP_GET_ENTRY 31:0 /* RWXUF */
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#define NV_PBDMA_GP_GET_ENTRY_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_PUT 0x000 /* RW-4R */
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#define NV_PBDMA_GP_PUT_ENTRY 31:0 /* RWXUF */
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#define NV_PBDMA_GP_PUT_ENTRY_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_FETCH 0x054 /* RW-4R */
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#define NV_PBDMA_PB_FETCH_CONDITIONAL 0:0 /* RWXUF */
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#define NV_PBDMA_PB_FETCH_CONDITIONAL_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_FETCH_CONDITIONAL_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_FETCH_ADDR 31:2 /* RWXUF */
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#define NV_PBDMA_PB_FETCH_ADDR_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_FETCH_HI 0x058 /* RW-4R */
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#define NV_PBDMA_PB_FETCH_HI_ADDR 7:0 /* RWXUF */
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#define NV_PBDMA_PB_FETCH_HI_ADDR_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_FETCH_HI_LEVEL 9:9 /* RWXUF */
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#define NV_PBDMA_PB_FETCH_HI_LEVEL_MAIN 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_FETCH_HI_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_FETCH_HI_SYNC 10:10 /* RWXUF */
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#define NV_PBDMA_PB_FETCH_HI_SYNC_PROCEED 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_FETCH_HI_SYNC_WAIT 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_FETCH_HI_LENGTH 31:11 /* RWXUF */
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#define NV_PBDMA_PB_FETCH_HI_LENGTH_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GET 0x018 /* RW-4R */
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#define NV_PBDMA_GET_OFFSET 31:2 /* RWXUF */
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#define NV_PBDMA_GET_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GET_HI 0x01c /* RW-4R */
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#define NV_PBDMA_GET_HI_OFFSET 7:0 /* RWXUF */
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#define NV_PBDMA_GET_HI_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PUT 0x05c /* RW-4R */
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#define NV_PBDMA_PUT_OFFSET 31:2 /* RWXUF */
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#define NV_PBDMA_PUT_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PUT_RSVD 1:0 /* R-IUF */
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#define NV_PBDMA_PUT_RSVD_ZERO 0x00000000 /* R-I-V */
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#define NV_PBDMA_PUT_HI 0x060 /* RW-4R */
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#define NV_PBDMA_PUT_HI_OFFSET 7:0 /* RWXUF */
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#define NV_PBDMA_PUT_HI_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_TOP_LEVEL_GET 0x020 /* RW-4R */
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#define NV_PBDMA_TOP_LEVEL_GET_OFFSET 31:2 /* RWXUF */
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#define NV_PBDMA_TOP_LEVEL_GET_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_TOP_LEVEL_GET_RSVD 1:0 /* R-IUF */
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#define NV_PBDMA_TOP_LEVEL_GET_RSVD_ZERO 0x00000000 /* R-I-V */
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#define NV_PBDMA_TOP_LEVEL_GET_HI 0x024 /* RW-4R */
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#define NV_PBDMA_TOP_LEVEL_GET_HI_OFFSET 7:0 /* RWXUF */
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#define NV_PBDMA_TOP_LEVEL_GET_HI_OFFSET_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_TOP_LEVEL_GET_HI_VALID 31:31 /* RWIUF */
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#define NV_PBDMA_TOP_LEVEL_GET_HI_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PBDMA_TOP_LEVEL_GET_HI_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_GP_CRC 0x074 /* RW-4R */
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#define NV_PBDMA_GP_CRC_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_GP_CRC_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_HEADER 0x084 /* RW-4R */
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#define NV_PBDMA_PB_HEADER_METHOD_OR_SDMASK 15:2 /* RWXUF */
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#define NV_PBDMA_PB_HEADER_METHOD 13:2 /* */
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#define NV_PBDMA_PB_HEADER_METHOD_ZERO 0x00000000 /* */
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#define NV_PBDMA_PB_HEADER_SDMASK 15:4 /* */
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#define NV_PBDMA_PB_HEADER_SUBCHANNEL 18:16 /* RWXUF */
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#define NV_PBDMA_PB_HEADER_SUBCHANNEL_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_HEADER_LEVEL 20:20 /* RWXVF */
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#define NV_PBDMA_PB_HEADER_LEVEL_MAIN 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_HEADER_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_HEADER_FIRST 22:22 /* RWXVF */
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#define NV_PBDMA_PB_HEADER_FIRST_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_HEADER_FIRST_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_HEADER_CONDITIONAL 23:23 /* RWXVF */
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#define NV_PBDMA_PB_HEADER_CONDITIONAL_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_HEADER_CONDITIONAL_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_HEADER_FINAL 24:24 /* RWXVF */
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#define NV_PBDMA_PB_HEADER_FINAL_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_HEADER_FINAL_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE 31:29 /* RWXUF */
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#define NV_PBDMA_PB_HEADER_TYPE_SSDM 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE_INC 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE_STORE_SDM 0x00000002 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE_NON_INC 0x00000003 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE_IMMD 0x00000004 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE_INC_ONCE 0x00000005 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE_USE_SDM 0x00000006 /* RW--V */
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#define NV_PBDMA_PB_HEADER_TYPE_END_SEG 0x00000007 /* RW--V */
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#define NV_PBDMA_PB_COUNT 0x088 /* RW-4R */
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#define NV_PBDMA_PB_COUNT_VALUE 12:0 /* RWXUF */
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#define NV_PBDMA_PB_COUNT_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL0 16:16 /* RWXUF */
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#define NV_PBDMA_PB_COUNT_DATAVAL0_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL0_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL0 17:17 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_LEVEL0_MAIN 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL0_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL0 18:18 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL0_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL0_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL0 19:19 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_FINAL0_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL0_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL1 20:20 /* RWXUF */
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#define NV_PBDMA_PB_COUNT_DATAVAL1_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL1_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL1 21:21 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_LEVEL1_MAIN 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL1_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL1 22:22 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL1_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL1_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL1 23:23 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_FINAL1_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL1_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL2 24:24 /* RWXUF */
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#define NV_PBDMA_PB_COUNT_DATAVAL2_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL2_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL2 25:25 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_LEVEL2_MAIN 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL2_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL2 26:26 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL2_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL2_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL2 27:27 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_FINAL2_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL2_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL3 28:28 /* RWXUF */
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#define NV_PBDMA_PB_COUNT_DATAVAL3_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_DATAVAL3_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL3 29:29 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_LEVEL3_MAIN 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_LEVEL3_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL3 30:30 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL3_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_CONDITIONAL3_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL3 31:31 /* RWXVF */
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#define NV_PBDMA_PB_COUNT_FINAL3_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_COUNT_FINAL3_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_PB_DATA0 0x08c /* RW-4R */
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#define NV_PBDMA_PB_DATA0_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_PB_DATA0_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_DATA1 0x090 /* RW-4R */
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#define NV_PBDMA_PB_DATA1_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_PB_DATA1_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_DATA2 0x0f0 /* RW-4R */
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#define NV_PBDMA_PB_DATA2_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_PB_DATA2_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_DATA3 0x068 /* RW-4R */
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#define NV_PBDMA_PB_DATA3_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_PB_DATA3_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_PB_CRC 0x098 /* RW-4R */
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#define NV_PBDMA_PB_CRC_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_PB_CRC_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SUBDEVICE 0x094 /* RW-4R */
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#define NV_PBDMA_SUBDEVICE_ID 11:0 /* RWXUF */
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#define NV_PBDMA_SUBDEVICE_ID_ENABLE 0x00000FFF /* RW--V */
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#define NV_PBDMA_SUBDEVICE_STORED_MASK 27:16 /* RWXUF */
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#define NV_PBDMA_SUBDEVICE_STORED_MASK_ENABLE 0x00000FFF /* RW--V */
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#define NV_PBDMA_SUBDEVICE_STATUS 28:28 /* RWXUF */
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#define NV_PBDMA_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* RW--V */
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#define NV_PBDMA_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* RW--V */
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#define NV_PBDMA_SUBDEVICE_CHANNEL_DMA 29:29 /* RWXUF */
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#define NV_PBDMA_SUBDEVICE_CHANNEL_DMA_DISABLE 0x00000000 /* RW--V */
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#define NV_PBDMA_SUBDEVICE_CHANNEL_DMA_ENABLE 0x00000001 /* RW--V */
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#define NV_PBDMA_METHOD(i) (0x0c0+(i)*8) /* RW-4A */
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#define NV_PBDMA_METHOD__SIZE_1 4 /* */
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#define NV_PBDMA_METHOD_ADDR 13:2 /* RWXUF */
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#define NV_PBDMA_METHOD_ADDR_NULL 0x00000000 /* RW--V */
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#define NV_PBDMA_METHOD_SUBCH 18:16 /* RWXUF */
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#define NV_PBDMA_METHOD_SUBCH_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_METHOD_FIRST 22:22 /* RWXUF */
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#define NV_PBDMA_METHOD_FIRST_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_METHOD_FIRST_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_METHOD_VALID 31:31 /* RWXUF */
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#define NV_PBDMA_METHOD_VALID_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_METHOD_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_DATA(i) (0x0c4+(i)*8) /* RW-4A */
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#define NV_PBDMA_DATA__SIZE_1 4 /* */
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#define NV_PBDMA_DATA_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_DATA_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS 0x0e8 /* R--4R */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_VALID 31:31 /* R-XVF */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_VALID_TRUE 1 /* R---V */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_VALID_FALSE 0 /* R---V */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_0_INDEX 30:16 /* R-XVF */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_VALID 15:15 /* R-XVF */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_VALID_TRUE 1 /* R---V */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_VALID_FALSE 0 /* R---V */
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#define NV_PBDMA_ALLOWED_SYNCPOINTS_1_INDEX 14:0 /* R-XVF */
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#define NV_PBDMA_TARGET 0x0ac /* RW-4R */
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#define NV_PBDMA_TARGET_ENGINE 1:0 /* RWXUF */
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#define NV_PBDMA_TARGET_ENGINE_SW_LOCAL 3 /* RW--V */
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#define NV_PBDMA_TARGET_ENG_CTX_VALID 16:16 /* RWXUF */
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#define NV_PBDMA_TARGET_ENG_CTX_VALID_TRUE 1 /* RW--V */
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#define NV_PBDMA_TARGET_ENG_CTX_VALID_FALSE 0 /* RW--V */
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#define NV_PBDMA_TARGET_CE_CTX_VALID 17:17 /* RWXUF */
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#define NV_PBDMA_TARGET_CE_CTX_VALID_TRUE 1 /* RW--V */
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#define NV_PBDMA_TARGET_CE_CTX_VALID_FALSE 0 /* RW--V */
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#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON 25:24 /* RWXUF */
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#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_PBDMA_IDLE 0x0 /* RW--V */
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#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_SEMAPHORE_ACQUIRE_FAILURE 0x1 /* RW--V */
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#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_TSG_YIELD 0x2 /* RW--V */
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#define NV_PBDMA_TARGET_HOST_TSG_EVENT_REASON_HOST_SUBCHANNEL_SWITCH 0x3 /* RW--V */
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#define NV_PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT 29:29 /* RWXUF */
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#define NV_PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT_TRUE 1 /* RW--V */
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#define NV_PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT_FALSE 0 /* RW--V */
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#define NV_PBDMA_TARGET_NEEDS_HOST_TSG_EVENT 31:31 /* RWXUF */
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#define NV_PBDMA_TARGET_NEEDS_HOST_TSG_EVENT_TRUE 1 /* RW--V */
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#define NV_PBDMA_TARGET_NEEDS_HOST_TSG_EVENT_FALSE 0 /* RW--V */
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#define NV_PBDMA_TARGET_ENGINE_SW 31 /* */
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#define NV_PBDMA_REF 0x028 /* RW-4R */
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#define NV_PBDMA_REF_CNT 31:0 /* RWXUF */
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#define NV_PBDMA_REF_CNT_ZERO 0x00000000 /* RW--V */
|
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#define NV_PBDMA_RUNTIME 0x02c /* RW-4R */
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#define NV_PBDMA_RUNTIME_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_RUNTIME_VALUE_ZERO 0x00000000 /* RW--V */
|
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#define NV_PBDMA_SEM_ADDR_LO 0x03c /* RW-4R */
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#define NV_PBDMA_SEM_ADDR_LO_ADDR 31:2 /* RWXUF */
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#define NV_PBDMA_SEM_ADDR_LO_ADDR_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_ADDR_HI 0x038 /* RW-4R */
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#define NV_PBDMA_SEM_ADDR_HI_ADDR 7:0 /* RWXUF */
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#define NV_PBDMA_SEM_ADDR_HI_ADDR_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_PAYLOAD_LO 0x040 /* RW-4R */
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#define NV_PBDMA_SEM_PAYLOAD_LO_DATA 31:0 /* RWXVF */
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#define NV_PBDMA_SEM_PAYLOAD_LO_DATA_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_PAYLOAD_HI 0x09c /* RW-4R */
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#define NV_PBDMA_SEM_PAYLOAD_HI_DATA 31:0 /* RWXVF */
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#define NV_PBDMA_SEM_PAYLOAD_HI_DATA_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE 0x044 /* RW-4R */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION 2:0 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_OPERATION_INVALID 0x00000007 /* -W--V */
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#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_FAIL 19:19 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_FAIL_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_RELEASE_WFI 20:20 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_PAYLOAD_SIZE 24:24 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION 30:27 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IAND 0x00000003 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IOR 0x00000004 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_IADD 0x00000005 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_INC 0x00000006 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_DEC 0x00000007 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_INVALID 0x0000000f /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_FORMAT 31:31 /* RWXVF */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 /* RW--V */
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#define NV_PBDMA_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 /* RW--V */
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#define NV_PBDMA_ACQUIRE_DEADLINE 0x034 /* RW-4R */
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#define NV_PBDMA_ACQUIRE_DEADLINE_TIMESTAMP 31:0 /* RWXUF */
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#define NV_PBDMA_ACQUIRE_DEADLINE_TIMESTAMP_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_ACQUIRE 0x030 /* RW-4R */
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#define NV_PBDMA_ACQUIRE_RETRY_MAN 6:0 /* RWXUF */
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|
#define NV_PBDMA_ACQUIRE_RETRY_MAN_2 0x00000002 /* RW--V */
|
|
#define NV_PBDMA_ACQUIRE_RETRY_EXP 10:7 /* RWXUF */
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|
#define NV_PBDMA_ACQUIRE_RETRY_EXP_2 0x00000002 /* RW--V */
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|
#define NV_PBDMA_ACQUIRE_TIMEOUT_EXP 14:11 /* RWXUF */
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|
#define NV_PBDMA_ACQUIRE_TIMEOUT_EXP_MAX 0x0000000F /* RW--V */
|
|
#define NV_PBDMA_ACQUIRE_TIMEOUT_MAN 30:15 /* RWXUF */
|
|
#define NV_PBDMA_ACQUIRE_TIMEOUT_MAN_MAX 0x0000FFFF /* RW--V */
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#define NV_PBDMA_ACQUIRE_TIMEOUT_EN 31:31 /* RWXUF */
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|
#define NV_PBDMA_ACQUIRE_TIMEOUT_EN_DISABLE 0x00000000 /* RW--V */
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|
#define NV_PBDMA_ACQUIRE_TIMEOUT_EN_ENABLE 0x00000001 /* RW--V */
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|
#define NV_PBDMA_CFG0 0x104 /* R--4R */
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#define NV_PBDMA_CFG0_PBDMA_FAULT_ID 9:0 /* R-XUF */
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#define NV_PBDMA_STATUS 0x100 /* R--4R */
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#define NV_PBDMA_STATUS_GPF 3:0 /* R-IUF */
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#define NV_PBDMA_STATUS_GPF_EMPTY 0x00000000 /* R-I-V */
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#define NV_PBDMA_STATUS_GPF_SUSPENDED 0x00000001 /* R---V */
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#define NV_PBDMA_STATUS_GPF_BLOCKED 0x00000002 /* R---V */
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#define NV_PBDMA_STATUS_GPF_BUSY 0x00000008 /* R---V */
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#define NV_PBDMA_STATUS_GPP 7:4 /* R-IUF */
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#define NV_PBDMA_STATUS_GPP_EMPTY 0x00000000 /* R-I-V */
|
|
#define NV_PBDMA_STATUS_GPP_SUSPENDED 0x00000001 /* R---V */
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#define NV_PBDMA_STATUS_GPP_BLOCKED 0x00000002 /* R---V */
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#define NV_PBDMA_STATUS_GPP_BUSY 0x00000008 /* R---V */
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|
#define NV_PBDMA_STATUS_PBP 11:8 /* R-IUF */
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|
#define NV_PBDMA_STATUS_PBP_EMPTY 0x00000000 /* R-I-V */
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|
#define NV_PBDMA_STATUS_PBP_SUSPENDED 0x00000001 /* R---V */
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|
#define NV_PBDMA_STATUS_PBP_BLOCKED 0x00000002 /* R---V */
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#define NV_PBDMA_STATUS_PBP_BUSY 0x00000008 /* R---V */
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|
#define NV_PBDMA_STATUS_MP 15:12 /* R-IUF */
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|
#define NV_PBDMA_STATUS_MP_EMPTY 0x00000000 /* R-I-V */
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#define NV_PBDMA_STATUS_MP_SUSPENDED 0x00000001 /* R---V */
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|
#define NV_PBDMA_STATUS_MP_BLOCKED 0x00000002 /* R---V */
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|
#define NV_PBDMA_STATUS_MP_BUSY 0x00000008 /* R---V */
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#define NV_PBDMA_STATUS_SEM 19:16 /* R-IUF */
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#define NV_PBDMA_STATUS_SEM_EMPTY 0x00000000 /* R-I-V */
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|
#define NV_PBDMA_STATUS_SEM_SUSPENDED 0x00000001 /* R---V */
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|
#define NV_PBDMA_STATUS_SEM_BLOCKED 0x00000002 /* R---V */
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#define NV_PBDMA_STATUS_SEM_BUSY 0x00000008 /* R---V */
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#define NV_PBDMA_STATUS_PBDMA 31:28 /* R-IUF */
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#define NV_PBDMA_STATUS_PBDMA_EMPTY 0x00000000 /* R-I-V */
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|
#define NV_PBDMA_STATUS_PBDMA_SUSPENDED 0x00000001 /* R---V */
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#define NV_PBDMA_STATUS_PBDMA_BLOCKED 0x00000002 /* R---V */
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#define NV_PBDMA_STATUS_PBDMA_BUSY 0x00000008 /* R---V */
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#define NV_PBDMA_STATUS_SCHED 0x15C /* R--4R */
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#define NV_PBDMA_STATUS_SCHED_TSGID 11:0 /* */
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#define NV_PBDMA_STATUS_SCHED_TSGID_HW 10:0 /* R-XUF */
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#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS 15:13 /* R-EVF */
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#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_INVALID 0x00000000 /* R-E-V */
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#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_VALID 0x00000001 /* R---V */
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#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_CHSW_SAVE 0x00000005 /* R---V */
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#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_CHSW_LOAD 0x00000006 /* R---V */
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#define NV_PBDMA_STATUS_SCHED_CHAN_STATUS_CHSW_SWITCH 0x00000007 /* R---V */
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#define NV_PBDMA_STATUS_SCHED_NEXT_TSGID 27:16 /* */
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#define NV_PBDMA_STATUS_SCHED_NEXT_TSGID_HW 26:16 /* R-XUF */
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#define NV_PBDMA_STATUS_SCHED_CHAN 13:13 /* */
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#define NV_PBDMA_STATUS_SCHED_CHAN_INVALID 0x00000000 /* */
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#define NV_PBDMA_STATUS_SCHED_CHAN_VALID 0x00000001 /* */
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#define NV_PBDMA_STATUS_SCHED_CHANLOAD 14:14 /* */
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#define NV_PBDMA_STATUS_SCHED_CHANLOAD_NOT_IN_PROGRESS 0x00000000 /* */
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#define NV_PBDMA_STATUS_SCHED_CHANLOAD_IN_PROGRESS 0x00000001 /* */
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#define NV_PBDMA_STATUS_SCHED_CHSW 15:15 /* */
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#define NV_PBDMA_STATUS_SCHED_CHSW_NOT_IN_PROGRESS 0x00000000 /* */
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#define NV_PBDMA_STATUS_SCHED_CHSW_IN_PROGRESS 0x00000001 /* */
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#define NV_PBDMA_STATUS_INST 0x160 /* R--4R */
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#define NV_PBDMA_STATUS_INST_TARGET 1:0 /* R-XUF */
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#define NV_PBDMA_STATUS_INST_TARGET_VID_MEM 0x00000000 /* R---V */
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#define NV_PBDMA_STATUS_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
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#define NV_PBDMA_STATUS_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
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#define NV_PBDMA_STATUS_INST_VALID 11:11 /* R-EVF */
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#define NV_PBDMA_STATUS_INST_VALID_FALSE 0x00000000 /* R-E-V */
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#define NV_PBDMA_STATUS_INST_VALID_TRUE 0x00000001 /* R---V */
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#define NV_PBDMA_STATUS_INST_PTR_LO 31:12 /* R-XUF */
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#define NV_PBDMA_STATUS_INST_HI 0x164 /* R--4R */
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#define NV_PBDMA_STATUS_INST_HI_PTR_HI 31:0 /* R-XUF */
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#define NV_PBDMA_STATUS_NEXT_INST 0x138 /* R--4R */
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#define NV_PBDMA_STATUS_NEXT_INST_TARGET 1:0 /* R-XUF */
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#define NV_PBDMA_STATUS_NEXT_INST_TARGET_VID_MEM 0x00000000 /* R---V */
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#define NV_PBDMA_STATUS_NEXT_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
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#define NV_PBDMA_STATUS_NEXT_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
|
|
#define NV_PBDMA_STATUS_NEXT_INST_VALID 11:11 /* R-EVF */
|
|
#define NV_PBDMA_STATUS_NEXT_INST_VALID_FALSE 0x00000000 /* R-E-V */
|
|
#define NV_PBDMA_STATUS_NEXT_INST_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PBDMA_STATUS_NEXT_INST_PTR_LO 31:12 /* R-XUF */
|
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#define NV_PBDMA_STATUS_NEXT_INST_HI 0x13C /* R--4R */
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|
#define NV_PBDMA_STATUS_NEXT_INST_HI_PTR_HI 31:0 /* R-XUF */
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|
#define NV_PBDMA_STATUS_USERD 0x168 /* R--4R */
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|
#define NV_PBDMA_STATUS_USERD_TARGET 1:0 /* R--UF */
|
|
#define NV_PBDMA_STATUS_USERD_TARGET_VID_MEM 0x00000000 /* R---V */
|
|
#define NV_PBDMA_STATUS_USERD_TARGET_VID_MEM_NVLINK_COHERENT 0x00000001 /* R---V */
|
|
#define NV_PBDMA_STATUS_USERD_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
|
|
#define NV_PBDMA_STATUS_USERD_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
|
|
#define NV_PBDMA_STATUS_USERD_VALID 7:7 /* R-EVF */
|
|
#define NV_PBDMA_STATUS_USERD_VALID_FALSE 0x00000000 /* R-E-V */
|
|
#define NV_PBDMA_STATUS_USERD_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PBDMA_STATUS_USERD_PTR_LO 31:8 /* R--UF */
|
|
#define NV_PBDMA_STATUS_USERD_HI 0x16C /* R--4R */
|
|
#define NV_PBDMA_STATUS_USERD_HI_PTR_HI 31:0 /* R--UF */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD 0x140 /* R--4R */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET 1:0 /* R--UF */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_VID_MEM 0x00000000 /* R---V */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_VID_MEM_NVLINK_COHERENT 0x00000001 /* R---V */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_VALID 7:7 /* R-EVF */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_VALID_FALSE 0x00000000 /* R-E-V */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_PTR_LO 31:8 /* R--UF */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_HI 0x144 /* R--4R */
|
|
#define NV_PBDMA_STATUS_NEXT_USERD_HI_PTR_HI 31:0 /* R--UF */
|
|
#define NV_PBDMA_CHANNEL 0x120 /* R--4R */
|
|
#define NV_PBDMA_CHANNEL_CHID 11:0 /* */
|
|
#define NV_PBDMA_CHANNEL_CHID_HW 10:0 /* R-XUF */
|
|
#define NV_PBDMA_CHANNEL_VALID 13:13 /* R-IVF */
|
|
#define NV_PBDMA_CHANNEL_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PBDMA_CHANNEL_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PBDMA_CHANNEL_GFID 21:16 /* R-XVF */
|
|
#define NV_PBDMA_NEXT_CHANNEL 0x124 /* R--4R */
|
|
#define NV_PBDMA_NEXT_CHANNEL_CHID 11:0 /* */
|
|
#define NV_PBDMA_NEXT_CHANNEL_CHID_HW 10:0 /* R-XUF */
|
|
#define NV_PBDMA_NEXT_CHANNEL_VALID 13:13 /* R-IVF */
|
|
#define NV_PBDMA_NEXT_CHANNEL_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PBDMA_NEXT_CHANNEL_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PBDMA_NEXT_CHANNEL_GFID 21:16 /* R-XVF */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK 0x130 /* RW-4R */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PBDMA_SECURE_CONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PBDMA_SECURE_CONFIG 0x134 /* RW-4R */
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#define NV_PBDMA_SECURE_CONFIG__PRIV_LEVEL_MASK 0x130 /* */
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#define NV_PBDMA_SECURE_CONFIG_FORCE_CE_SPLIT 0:0 /* RWIUF */
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#define NV_PBDMA_SECURE_CONFIG_FORCE_CE_SPLIT_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_SECURE_CONFIG_FORCE_CE_SPLIT_TRUE 0x00000001 /* RWI-V */
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#define NV_PBDMA_GP_SHADOW(i) (0x110+(i)*4) /* R--4A */
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#define NV_PBDMA_GP_SHADOW__SIZE_1 2 /* */
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#define NV_PBDMA_GP_SHADOW_VALUE 31:0 /* R-XUF */
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#define NV_PBDMA_HDR_SHADOW 0x06c /* RW-4R */
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#define NV_PBDMA_HDR_SHADOW_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_INTR_PRI_DEBUG 0x11c /* RW-4R */
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#define NV_PBDMA_INTR_PRI_DEBUG_ADDRESS 31:0 /* RWXUF */
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#define NV_PBDMA_MEM_OP_A 0x004 /* RW-4R */
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#define NV_PBDMA_MEM_OP_A_DATA 31:0 /* RWXUF */
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#define NV_PBDMA_MEM_OP_B 0x064 /* RW-4R */
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#define NV_PBDMA_MEM_OP_B_DATA 31:0 /* RWXUF */
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#define NV_PBDMA_MEM_OP_C 0x0a0 /* RW-4R */
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#define NV_PBDMA_MEM_OP_C_DATA 31:0 /* RWXUF */
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#define NV_PBDMA_SIGNATURE 0x010 /* RW-4R */
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#define NV_PBDMA_SIGNATURE_HW 15:0 /* RWXUF */
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#define NV_PBDMA_SIGNATURE_HW_VALID 0x0000face /* RW--V */
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#define NV_PBDMA_SIGNATURE_HW_HOST_CLASS_ID 51055 /* RW--V */
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#define NV_PBDMA_SIGNATURE_SW 31:16 /* RWXUF */
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#define NV_PBDMA_SIGNATURE_SW_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_CONFIG 0x0f4 /* R--4R */
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#define NV_PBDMA_CONFIG_L2_EVICT 0:0 /* R--VF */
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#define NV_PBDMA_CONFIG_L2_EVICT_FIRST 0x00000000 /* R---V */
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#define NV_PBDMA_CONFIG_L2_EVICT_NORMAL 0x00000001 /* R---V */
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#define NV_PBDMA_CONFIG_CE_SPLIT 4:4 /* R--VF */
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#define NV_PBDMA_CONFIG_CE_SPLIT_ENABLE 0x00000000 /* R---V */
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#define NV_PBDMA_CONFIG_CE_SPLIT_DISABLE 0x00000001 /* R---V */
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#define NV_PBDMA_CONFIG_CE_THROTTLE_MODE 5:5 /* R--VF */
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#define NV_PBDMA_CONFIG_CE_THROTTLE_MODE_THROTTLE 0x00000000 /* R---V */
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#define NV_PBDMA_CONFIG_CE_THROTTLE_MODE_NO_THROTTLE 0x00000001 /* R---V */
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#define NV_PBDMA_CONFIG_AUTH_LEVEL 8:8 /* R--VF */
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#define NV_PBDMA_CONFIG_AUTH_LEVEL_NON_PRIVILEGED 0x00000000 /* R---V */
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#define NV_PBDMA_CONFIG_AUTH_LEVEL_PRIVILEGED 0x00000001 /* R---V */
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#define NV_PBDMA_CONFIG_USERD_WRITEBACK 12:12 /* R--VF */
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#define NV_PBDMA_CONFIG_USERD_WRITEBACK_DISABLE 0x00000000 /* R---V */
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#define NV_PBDMA_CONFIG_USERD_WRITEBACK_ENABLE 0x00000001 /* R---V */
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#define NV_PBDMA_CONFIG_PM_TRIGGER 31:31 /* R--VF */
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#define NV_PBDMA_CONFIG_PM_TRIGGER_ASSERTED 0x00000001 /* R---V */
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#define NV_PBDMA_CONFIG_PM_TRIGGER_DEASSERTED 0x00000000 /* R---V */
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#define NV_PBDMA_INTR_NOTIFY 0x0f8 /* RW-4R */
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#define NV_PBDMA_INTR_NOTIFY_VECTOR 11:0 /* RWXUF */
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#define NV_PBDMA_INTR_NOTIFY_CTRL_GSP 30:30 /* RWXUF */
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#define NV_PBDMA_INTR_NOTIFY_CTRL_GSP_DISABLE 0 /* R---V */
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#define NV_PBDMA_INTR_NOTIFY_CTRL_GSP_ENABLE 1 /* R---V */
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#define NV_PBDMA_INTR_NOTIFY_CTRL_CPU 31:31 /* RWXUF */
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#define NV_PBDMA_INTR_NOTIFY_CTRL_CPU_DISABLE 0 /* R---V */
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#define NV_PBDMA_INTR_NOTIFY_CTRL_CPU_ENABLE 1 /* R---V */
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#define NV_PBDMA_SET_CHANNEL_INFO 0x0fc /* RW-4R */
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#define NV_PBDMA_SET_CHANNEL_INFO_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_SET_CHANNEL_INFO_SCG_TYPE 0:0 /* */
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#define NV_PBDMA_SET_CHANNEL_INFO_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 /* */
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#define NV_PBDMA_SET_CHANNEL_INFO_SCG_TYPE_COMPUTE1 0x00000001 /* */
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#define NV_PBDMA_SET_CHANNEL_INFO_VEID ((6-1)+8):8 /* */
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#define NV_PBDMA_SET_CHANNEL_INFO_CHID 27:16 /* */
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#define NV_PBDMA_SET_CHANNEL_INFO_RESERVED 31:27 /* */
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#define NV_PBDMA_SET_CHANNEL_INFO_CHID_HW 26:16 /* */
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#define NV_PBDMA_SPARE56 0x0e0 /* RW-4R */
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#define NV_PBDMA_SPARE56_PB_GET_CONDITIONAL 0:0 /* RWXUF */
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#define NV_PBDMA_SPARE56_PB_GET_CONDITIONAL_FALSE 0x00000000 /* RW--V */
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#define NV_PBDMA_SPARE56_PB_GET_CONDITIONAL_TRUE 0x00000001 /* RW--V */
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#define NV_PBDMA_SPARE56_PB_GET_LEVEL 3:3 /* RWXUF */
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#define NV_PBDMA_SPARE56_PB_GET_LEVEL_MAIN 0x00000000 /* RW--V */
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#define NV_PBDMA_SPARE56_PB_GET_LEVEL_SUBROUTINE 0x00000001 /* RW--V */
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#define NV_PBDMA_SPARE56_PB_GET_SYNC 4:4 /* RWXUF */
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#define NV_PBDMA_SPARE56_PB_GET_SYNC_PROCEED 0x00000000 /* RW--V */
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#define NV_PBDMA_SPARE56_PB_GET_SYNC_WAIT 0x00000001 /* RW--V */
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#define NV_PBDMA_SPARE56_PB_GET_FIRST 7:7 /* */
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#define NV_PBDMA_SPARE56_PB_GET_FIRST_FALSE 0x00000000 /* */
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#define NV_PBDMA_SPARE56_PB_GET_FIRST_TRUE 0x00000001 /* */
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#define NV_PBDMA_HCE_CTRL 0x0e4 /* RW-4R */
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#define NV_PBDMA_HCE_CTRL_SP_AWAITS_HCEH 0:0 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_SP_AWAITS_HCEH_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_SP_AWAITS_HCEH_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_HCE_RENDER_DISABLED 2:2 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_HCE_RENDER_DISABLED_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_HCE_RENDER_DISABLED_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_HCE_SUBCHSW 4:4 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_HCE_SUBCHSW_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_HCE_SUBCHSW_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_HCE_PRIV_MODE 5:5 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_HCE_PRIV_MODE_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_HCE_PRIV_MODE_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_LAUNCH_DMA_RCVD 16:16 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_LAUNCH_DMA_RCVD_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_LAUNCH_DMA_RCVD_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_NOP_RCVD 17:17 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_NOP_RCVD_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_NOP_RCVD_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_RCVD 18:18 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_RCVD_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_RCVD_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_END_RCVD 19:19 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_END_RCVD_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_PM_TRIGGER_END_RCVD_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD 20:20 /* RWXUF */
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#define NV_PBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD_NO 0x00000000 /* RW--V */
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#define NV_PBDMA_HCE_CTRL_SET_RENDER_ENABLE_C_RCVD_YES 0x00000001 /* RW--V */
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#define NV_PBDMA_SPLITTER_REM_LINES 0x078 /* RW-4R */
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#define NV_PBDMA_SPLITTER_REM_LINES_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_SPLITTER_REM_LINES_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SPLITTER_OFFSET_IN_LOWER 0x07c /* RW-4R */
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#define NV_PBDMA_SPLITTER_OFFSET_IN_LOWER_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_SPLITTER_OFFSET_IN_LOWER_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SPLITTER_OFFSET_IN_UPPER 0x080 /* RW-4R */
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#define NV_PBDMA_SPLITTER_OFFSET_IN_UPPER_VALUE 16:0 /* RWXUF */
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#define NV_PBDMA_SPLITTER_OFFSET_IN_UPPER_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SPLITTER_REM_PIXELS 0x0b4 /* RW-4R */
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#define NV_PBDMA_SPLITTER_REM_PIXELS_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_SPLITTER_REM_PIXELS_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SPLITTER_OFFSET_OUT_LOWER 0x0b8 /* RW-4R */
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#define NV_PBDMA_SPLITTER_OFFSET_OUT_LOWER_VALUE 31:0 /* RWXUF */
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#define NV_PBDMA_SPLITTER_OFFSET_OUT_LOWER_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_SPLITTER_OFFSET_OUT_UPPER 0x0bc /* RW-4R */
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#define NV_PBDMA_SPLITTER_OFFSET_OUT_UPPER_VALUE 16:0 /* RWXUF */
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#define NV_PBDMA_SPLITTER_OFFSET_OUT_UPPER_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_GP_PEEK 0x0ec /* RW-4R */
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#define NV_PBDMA_GP_PEEK_ENTRY 31:0 /* RWXUF */
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#define NV_PBDMA_GP_PEEK_ENTRY_ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_CE_METHOD_STATE(i) (0x200+(i)*4) /* RW-4A */
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#define NV_PBDMA_CE_METHOD_STATE__SIZE_1 42 /* */
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#define NV_PBDMA_CE_METHOD_STATE_ENTRY 31:0 /* RWXUF */
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#define NV_PBDMA_CE_METHOD_STATE_ENTRY__ZERO 0x00000000 /* RW--V */
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#define NV_PBDMA_INTR_0 0x108 /* RW-4R */
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#define NV_PBDMA_INTR_0_GPFIFO 13:13 /* RWIUF */
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#define NV_PBDMA_INTR_0_GPFIFO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_GPFIFO_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_GPFIFO_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_GPPTR 14:14 /* RWIUF */
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#define NV_PBDMA_INTR_0_GPPTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_GPPTR_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_GPPTR_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_GPENTRY 15:15 /* RWIUF */
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#define NV_PBDMA_INTR_0_GPENTRY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_GPENTRY_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_GPENTRY_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_GPCRC 16:16 /* RWIUF */
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#define NV_PBDMA_INTR_0_GPCRC_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_GPCRC_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_GPCRC_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_PBPTR 17:17 /* RWIUF */
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#define NV_PBDMA_INTR_0_PBPTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_PBPTR_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_PBPTR_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_PBENTRY 18:18 /* RWIUF */
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#define NV_PBDMA_INTR_0_PBENTRY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_PBENTRY_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_PBENTRY_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_PBCRC 19:19 /* RWIUF */
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#define NV_PBDMA_INTR_0_PBCRC_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_PBCRC_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_PBCRC_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_METHOD 21:21 /* RWIUF */
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#define NV_PBDMA_INTR_0_METHOD_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_METHOD_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_METHOD_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_DEVICE 23:23 /* RWIUF */
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#define NV_PBDMA_INTR_0_DEVICE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_DEVICE_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_DEVICE_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_ENG_RESET 24:24 /* RWIUF */
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#define NV_PBDMA_INTR_0_ENG_RESET_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_ENG_RESET_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_ENG_RESET_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_SEMAPHORE 25:25 /* RWIUF */
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#define NV_PBDMA_INTR_0_SEMAPHORE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_SEMAPHORE_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_SEMAPHORE_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_ACQUIRE 26:26 /* RWIUF */
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#define NV_PBDMA_INTR_0_ACQUIRE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_ACQUIRE_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_ACQUIRE_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_PRI 27:27 /* RWIUF */
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#define NV_PBDMA_INTR_0_PRI_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_PRI_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_PRI_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_PBSEG 30:30 /* RWIUF */
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#define NV_PBDMA_INTR_0_PBSEG_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_PBSEG_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_PBSEG_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_0_SIGNATURE 31:31 /* RWIUF */
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#define NV_PBDMA_INTR_0_SIGNATURE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_0_SIGNATURE_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_0_SIGNATURE_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_1 0x148 /* RW-4R */
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#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP 0:0 /* RWIUF */
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#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_1_HCE_RE_ILLEGAL_OP_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB 1:1 /* RWIUF */
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#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_1_HCE_RE_ALIGNB_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_1_HCE_PRIV 2:2 /* RWIUF */
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#define NV_PBDMA_INTR_1_HCE_PRIV_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_1_HCE_PRIV_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_1_HCE_PRIV_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD 3:3 /* RWIUF */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_MTHD_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS 4:4 /* RWIUF */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_1_HCE_ILLEGAL_CLASS_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_INTR_1_CTXNOTVALID 31:31 /* RWIUF */
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#define NV_PBDMA_INTR_1_CTXNOTVALID_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PBDMA_INTR_1_CTXNOTVALID_PENDING 0x00000001 /* R---V */
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#define NV_PBDMA_INTR_1_CTXNOTVALID_RESET 0x00000001 /* -W--C */
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#define NV_PBDMA_HCE_DBG0 0x150 /* R--4R */
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#define NV_PBDMA_HCE_DBG0_MTHD_ADDR 13:2 /* R-EUF */
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#define NV_PBDMA_HCE_DBG0_MTHD_ADDR_VAL0 0x00000000 /* R-E-V */
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#define NV_PBDMA_HCE_DBG1 0x154 /* R--4R */
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#define NV_PBDMA_HCE_DBG1_MTHD_DATA 31:0 /* R-EUF */
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#define NV_PBDMA_HCE_DBG1_MTHD_DATA_VAL0 0x00000000 /* R-E-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE(i) (0x170+(i)*4) /* RW-4A */
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|
#define NV_PBDMA_INTR_0_EN_SET_TREE__SIZE_1 2 /* */
|
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPFIFO 13:13 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPFIFO_DISABLED 0x00000000 /* RWE-V */
|
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPFIFO_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPPTR 14:14 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPPTR_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPPTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPENTRY 15:15 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPENTRY_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPENTRY_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPCRC 16:16 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPCRC_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_GPCRC_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBPTR 17:17 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBPTR_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBPTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBENTRY 18:18 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBENTRY_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBENTRY_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBCRC 19:19 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBCRC_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBCRC_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_METHOD 21:21 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_METHOD_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_METHOD_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_DEVICE 23:23 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_DEVICE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_DEVICE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_ENG_RESET 24:24 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_ENG_RESET_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_ENG_RESET_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_SEMAPHORE 25:25 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_SEMAPHORE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_SEMAPHORE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_ACQUIRE 26:26 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_ACQUIRE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_ACQUIRE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PRI 27:27 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PRI_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PRI_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBSEG 30:30 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBSEG_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_PBSEG_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_SIGNATURE 31:31 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_SIGNATURE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_SET_TREE_SIGNATURE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE(i) (0x180+(i)*4) /* RW-4A */
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#define NV_PBDMA_INTR_1_EN_SET_TREE__SIZE_1 2 /* */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ILLEGAL_OP 0:0 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ILLEGAL_OP_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ILLEGAL_OP_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ALIGNB 1:1 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ALIGNB_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_RE_ALIGNB_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_PRIV 2:2 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_PRIV_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_PRIV_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_MTHD 3:3 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_MTHD_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_MTHD_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_CLASS 4:4 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_CLASS_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_HCE_ILLEGAL_CLASS_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_CTXNOTVALID 31:31 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_CTXNOTVALID_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_SET_TREE_CTXNOTVALID_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE(i) (0x190+(i)*4) /* RW-4A */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE__SIZE_1 2 /* */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPFIFO 13:13 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPFIFO_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPFIFO_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPPTR 14:14 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPPTR_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPPTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPENTRY 15:15 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPENTRY_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPENTRY_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPCRC 16:16 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPCRC_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_GPCRC_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBPTR 17:17 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBPTR_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBPTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBENTRY 18:18 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBENTRY_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBENTRY_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBCRC 19:19 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBCRC_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBCRC_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_METHOD 21:21 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_METHOD_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_METHOD_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_DEVICE 23:23 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_DEVICE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_DEVICE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ENG_RESET 24:24 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ENG_RESET_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ENG_RESET_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SEMAPHORE 25:25 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SEMAPHORE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SEMAPHORE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ACQUIRE 26:26 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ACQUIRE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_ACQUIRE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PRI 27:27 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PRI_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PRI_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBSEG 30:30 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBSEG_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_PBSEG_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SIGNATURE 31:31 /* RWEUF */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SIGNATURE_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_0_EN_CLEAR_TREE_SIGNATURE_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE(i) (0x1a0+(i)*4) /* RW-4A */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE__SIZE_1 2 /* */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ILLEGAL_OP 0:0 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ILLEGAL_OP_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ILLEGAL_OP_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ALIGNB 1:1 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ALIGNB_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_RE_ALIGNB_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_PRIV 2:2 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_PRIV_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_PRIV_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_MTHD 3:3 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_MTHD_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_MTHD_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_CLASS 4:4 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_CLASS_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_HCE_ILLEGAL_CLASS_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_CTXNOTVALID 31:31 /* RWEUF */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_CTXNOTVALID_DISABLED 0x00000000 /* RWE-V */
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#define NV_PBDMA_INTR_1_EN_CLEAR_TREE_CTXNOTVALID_ENABLED 0x00000001 /* RW--V */
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#define NV_PBDMA_LB_ENTRY_SIZE 128 /* */
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#define NV_PBDMA_LB_GPBUF_CONTROL 0x1b0 /* R--4R */
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#define NV_PBDMA_LB_GPBUF_CONTROL_SIZE 31:24 /* R-XUF */
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#define NV_PBDMA_LB_GPBUF_CONTROL_SIZE_128B 0x00000001 /* R---V */
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#define NV_PBDMA_LB_PBBUF_CONTROL 0x1c0 /* R--4R */
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#define NV_PBDMA_LB_PBBUF_CONTROL_SIZE 31:23 /* R-XUF */
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#define NV_PBDMA_LB_PBBUF_CONTROL_SIZE_128B 0x00000001 /* R---V */
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#define NV_PBDMA_LB_GPBUF_STATUS 0x1d0 /* R--4R */
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#define NV_PBDMA_LB_GPBUF_STATUS_STATE 3:0 /* R-EVF */
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#define NV_PBDMA_LB_GPBUF_STATUS_STATE_EMPTY 0x00000000 /* R-E-V */
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#define NV_PBDMA_LB_GPBUF_STATUS_STATE_BLOCKED 0x00000002 /* R---V */
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#define NV_PBDMA_LB_GPBUF_STATUS_STATE_BUSY 0x00000003 /* R---V */
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#define NV_PBDMA_LB_GPBUF_STATUS_PBDMA_REQ_COUNT 14:4 /* R-EUF */
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#define NV_PBDMA_LB_GPBUF_STATUS_PBDMA_REQ_COUNT_0 0x00000000 /* R-E-V */
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#define NV_PBDMA_LB_GPBUF_STATUS_MEM_REQ_COUNT 25:15 /* R-EUF */
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#define NV_PBDMA_LB_GPBUF_STATUS_MEM_REQ_COUNT_0 0x00000000 /* R-E-V */
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#define NV_PBDMA_LB_PBBUF_STATUS 0x1e0 /* R--4R */
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#define NV_PBDMA_LB_PBBUF_STATUS_STATE 3:0 /* R-EVF */
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#define NV_PBDMA_LB_PBBUF_STATUS_STATE_EMPTY 0x00000000 /* R-E-V */
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#define NV_PBDMA_LB_PBBUF_STATUS_STATE_BLOCKED 0x00000002 /* R---V */
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#define NV_PBDMA_LB_PBBUF_STATUS_STATE_BUSY 0x00000003 /* R---V */
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#define NV_PBDMA_LB_PBBUF_STATUS_PBDMA_REQ_COUNT 14:4 /* R-EUF */
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#define NV_PBDMA_LB_PBBUF_STATUS_PBDMA_REQ_COUNT_0 0x00000000 /* R-E-V */
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#define NV_PBDMA_LB_PBBUF_STATUS_MEM_REQ_COUNT 25:15 /* R-EUF */
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#define NV_PBDMA_LB_PBBUF_STATUS_MEM_REQ_COUNT_0 0x00000000 /* R-E-V */
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#define NV_PBDMA_LB_PBBUF_THROTTLE 0x1f0 /* RW-4R */
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#define NV_PBDMA_LB_PBBUF_THROTTLE_ROWS 15:0 /* RWIUF */
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#define NV_PBDMA_LB_PBBUF_THROTTLE_ROWS_131KB 0x00001000 /* RW--V */
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#define NV_PBDMA_LB_PBBUF_THROTTLE_ROWS_INVALID 0x0000FFFF /* RWI-V */
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#define NV_PBDMA_LB_GPBUF_THROTTLE 0x300 /* RW-4R */
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#define NV_PBDMA_LB_GPBUF_THROTTLE_ROWS 15:0 /* RWIUF */
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#define NV_PBDMA_LB_GPBUF_THROTTLE_ROWS_131KB 0x00001000 /* RW--V */
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#define NV_PBDMA_LB_GPBUF_THROTTLE_ROWS_INVALID 0x0000FFFF /* RWI-V */
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#define NV_PBDMA_GLOBAL_PRI_RANGE_0 0x44fff:0x40000 /* ----M */
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#endif // __ga102_dev_esched_pbdma_h__
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