665 lines
60 KiB
C
665 lines
60 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_nvlpllctl_ip_h__
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#define __ga102_dev_nvlpllctl_ip_h__
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/* This file is autogenerated. Do not edit */
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#define NV_NVLPLLCTL 0x000007FF:0x00000000 /* RW--D */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0 0x00000500 /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1 0x00000504 /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2 0x00000508 /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3 0x0000050c /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4 0x00000510 /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5 0x00000514 /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6 0x00000518 /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask6" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7 0x0000051c /* RW-4R */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLPLLCTL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1 0x00000000 /* RW-4R */
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#define NV_NVLPLLCTL_PLL_CTL_1__PRIV_LEVEL_MASK 0x00000500 /* */
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#define NV_NVLPLLCTL_PLL_CTL_1_IDDQ 0:0 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_IDDQ_PWR_DOWN 0x00000001 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_IDDQ_PWR_UP 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_SLEEP 2:1 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_SLEEP_PWR_DOWN 0x00000003 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_SLEEP_PWR_UP 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_ENABLE 3:3 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_ENABLE_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_ENABLE_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_PWR_OVRD 4:4 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_PWR_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_PWR_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_CFG_SEL 6:6 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_CFG_SEL_EXTERNAL 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_CFG_SEL_INTERNAL 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_BYPASS_EN 7:7 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_BYPASS_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_BYPASS_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID 10:8 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_SYM16 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_OVRD 11:11 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_RATE_ID_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_LOCKDET_STATUS 15:15 /* R--VF */
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#define NV_NVLPLLCTL_PLL_CTL_1_LOCKDET_STATUS_UNLOCK 0x00000000 /* R---V */
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#define NV_NVLPLLCTL_PLL_CTL_1_LOCKDET_STATUS_LOCK 0x00000001 /* R---V */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLKBUF_EN 16:16 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLKBUF_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLKBUF_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_CFG_BUSY 17:17 /* R--VF */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_DRV_EN 18:18 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_REFCLK_DRV_EN_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_TCLKOUT_EN 20:20 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_TCLKOUT_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_TCLKOUT_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_PLL_CFG_RESET 30:30 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_PLL_CFG_RESET_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_1_PLL_CFG_RESET_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_PLL_RESET 31:31 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_1_PLL_RESET_OFF 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_1_PLL_RESET_ON 0x00000001 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_2 0x00000004 /* RW-4R */
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#define NV_NVLPLLCTL_PLL_CTL_2__PRIV_LEVEL_MASK 0x00000500 /* */
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#define NV_NVLPLLCTL_PLL_CTL_2_CAL_EN 0:0 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_2_CAL_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_2_CAL_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_2_CAL_DONE 1:1 /* R--VF */
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#define NV_NVLPLLCTL_PLL_CTL_2_CAL_OVRD 2:2 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_2_CAL_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_2_CAL_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_EN 12:12 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_OVRD 15:15 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_OVRD_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_OVRD_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE 20:16 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE_MINIMUM 0x00000000 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE_NOMINAL 0x00000007 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_CODE_MAXIMUM 0x0000000f /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_EN 23:23 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_EN_OFF 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_BYP_EN_ON 0x00000001 /* RW--V */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_VAL 28:24 /* R--VF */
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#define NV_NVLPLLCTL_PLL_CTL_2_RCAL_DONE 31:31 /* R--VF */
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#define NV_NVLPLLCTL_PLL_CTL_3 0x00000008 /* RW-4R */
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#define NV_NVLPLLCTL_PLL_CTL_3__PRIV_LEVEL_MASK 0x00000500 /* */
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#define NV_NVLPLLCTL_PLL_CTL_3_MISC_OUT 15:0 /* R-XVF */
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#define NV_NVLPLLCTL_PLL_CTL_3_MISC_CTRL 31:16 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_3_MISC_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_4 0x0000000c /* RW-4R */
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#define NV_NVLPLLCTL_PLL_CTL_4__PRIV_LEVEL_MASK 0x00000500 /* */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDATA 15:0 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDATA_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_ADDR 25:16 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_ADDR_INIT 0x00000000 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_SECURE 29:29 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_SECURE_INIT 0x00000001 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDS 30:30 /* -WEVF */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDS_OFF 0x00000000 /* -WE-V */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_WDS_ON 0x00000001 /* -W--V */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_RDS 31:31 /* -WEVF */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_RDS_OFF 0x00000000 /* -WE-V */
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#define NV_NVLPLLCTL_PLL_CTL_4_CFG_RDS_ON 0x00000001 /* -W--V */
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#define NV_NVLPLLCTL_PLL_CTL_5 0x00000010 /* R--4R */
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#define NV_NVLPLLCTL_PLL_CTL_5__PRIV_LEVEL_MASK 0x00000504 /* */
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#define NV_NVLPLLCTL_PLL_CTL_5_CFG_RDATA 15:0 /* R--VF */
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#define NV_NVLPLLCTL_PLL_CTL_6 0x00000014 /* RW-4R */
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#define NV_NVLPLLCTL_PLL_CTL_6__PRIV_LEVEL_MASK 0x00000508 /* */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_SETUP 7:0 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_SETUP_INIT 0x00000005 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_HOLD 15:8 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_HOLD_INIT 0x00000005 /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_STROBE_PULSE 23:16 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_STROBE_PULSE_INIT 0x0000000d /* RWE-V */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_READ_DELAY 31:24 /* RWEVF */
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#define NV_NVLPLLCTL_PLL_CTL_6_CFG_READ_DELAY_INIT 0x00000005 /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_WARM 0x000007c0 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_COLD 0x000007c4 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_NVLPLLCTL_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0 0x000007d0 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00000500 /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1 0x000007d4 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00000504 /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2 0x000007d8 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00000508 /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3 0x000007dc /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000050c /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4 0x000007e0 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00000510 /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5 0x000007e4 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00000514 /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6 0x000007e8 /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00000518 /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7 0x000007ec /* RW-4R */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000051c /* */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
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#define NV_NVLPLLCTL_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
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#endif // __ga102_dev_nvlpllctl_ip_h__
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