309 lines
30 KiB
C
309 lines
30 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_ist_seq_slv_h__
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#define __ga102_dev_ist_seq_slv_h__
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/* This file is autogenerated. Do not edit */
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#define NV_IST_SEQ_SLV 0x1C53FF:0x1C5000 /* RW--D */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK 0x1C5000 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ist_disable_debug_features" /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCK 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWER 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCK 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWER 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK 0x1C5064 /* RW-4R */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCK 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWER 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCK 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWER 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWD-V */
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#define NV_IST_SEQ_SLV_SRAM_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK 0x1C5100 /* RW-4R */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCK 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWER 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCK 0x00000001 /* RWD-V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWER 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWD-V */
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#define NV_IST_SEQ_SLV_START_ADR_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0 0x1C5004 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0_PRE_IST_MODE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_IST_TRIGGER_0_PRE_IST_MODE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0 0x1C5008 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0_MASK_0 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_ALWAYS_0_0_MASK_0_INIT 0x00000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0 0x1C500C /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0_VAL 5:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_PLATFORM_INTR_INV_0_VAL_INIT 0x00000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0 0x1C5010 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0_MASK_2 15:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_INTERRUPT_MASK_COND_0_0_MASK_2_INIT 0x00000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0 0x1C5014 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_JTAGCTRL_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0 0x1C5018 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_LBISTTOP_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0 0x1C502c /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0_IST_LINK_CTRL_SEL 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_LINK_CONTROLS_0_IST_LINK_CTRL_SEL_INIT 0x00000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0 0x1C5030 /* R--4R */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_IST_MODE 0:0 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_IST_MODE_INIT 0x0 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_EXP_PATT_RD_SUCCESS 1:1 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_EXP_PATT_RD_SUCCESS_INIT 0x0 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_WR_READ_SUCCESS 2:2 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_DEBUG_CAPTURE_0_EMMC_WR_READ_SUCCESS_INIT 0x0 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0 0x1C5034 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_TRAIN_TIMEOUT_0_COUNTER_VAL_INIT 0x6146580 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0 0x1C5038 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_DGPULINK_POSTTRAIN_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0 0x1C503c /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0__PRIV_LEVEL_MASK 0x1C5064 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0_START_DWORD_NO 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_START_DWORD_0_START_DWORD_NO_INIT 0x00000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0 0x1C5040 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0__PRIV_LEVEL_MASK 0x1C5064 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_WRITE_ENABLE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_WRITE_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_READ_ENABLE 1:1 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_EN_0_READ_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0 0x1C5044 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0__PRIV_LEVEL_MASK 0x1C5064 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0_WRITE_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_RAM_LOAD_DATA_0_WRITE_VAL_INIT 0x00000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0 0x1C5048 /* R--4R */
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#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0__PRIV_LEVEL_MASK 0x1C5064 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0_READ_VAL 31:0 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_RAM_READ_DATA_0_READ_VAL_INIT 0x00000000 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0 0x1C504c /* R--4R */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0__PRIV_LEVEL_MASK 0x1C5064 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_DONE 0:0 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_DONE_INIT 0x0 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_READ_DONE 1:1 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_READ_DONE_INIT 0x0 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_READ_OVERFLOW 2:2 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_RAM_STATUS_0_WRITE_READ_OVERFLOW_INIT 0x0 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0 0x1C5050 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0__PRIV_LEVEL_MASK 0x1C5064 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0_NO_OF_DWORDS 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_RAM_CTRL_NO_DWORDS_0_NO_OF_DWORDS_INIT 0x0000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0 0x1C5054 /* R--4R */
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#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0__PRIV_LEVEL_MASK 0x1C5064 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0_DWORD_NO 31:0 /* R-DUF */
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#define NV_IST_SEQ_SLV_IST_RAM_TARGET_DWORD_0_DWORD_NO_INIT 0x0000000 /* R-D-V */
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#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0 0x1C5058 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0_ENABLE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_JTAG_FILLER_0_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0 0x1C5060 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0_ENABLE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_RAM_WRITE_LOCK_0_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0 0x1C5068 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_EMMCCTRL_TIMEOUT_0_COUNTER_VAL_INIT 0x1312D00 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0 0x1C506c /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0_FORCE_PRGM 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_EMMC_CARD_SETTINGS_0_FORCE_PRGM_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0 0x1C5070 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0__PRIV_LEVEL_MASK 0x1C5100 /* */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0_START_ADDRESS 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_0_START_ADDRESS_INIT 0x0000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0 0x1C5074 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0_COUNTER_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_TIMEOUT_0_COUNTER_VAL_INIT 0x608F3D00 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0 0x1C5078 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL 15:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_GPU_CLK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL_INIT 0x1770 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0 0x1C507c /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL 15:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_LINK_SHUTDOWN_TIMEOUT_0_COUNTER_VAL_INIT 0x1770 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_DGPU_IST_0 0x1C5080 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_DGPU_IST_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_DGPU_IST_0_DGPU_IST_ENABLED 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_DGPU_IST_0_DGPU_IST_ENABLED_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0 0x1C5084 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0_RAND_LFSR_ENABLE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_RAND_LFSR_0_RAND_LFSR_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0 0x1C5088 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0_SEED_VAL 15:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_SEED_LFSR_0_SEED_VAL_INIT 0x6f41 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0 0x1C508c /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_ENABLE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_TRIGGER 1:1 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_GLOBAL_SHUTDOWN_COUNTER_0_TRIGGER_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0 0x1C5090 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0__PRIV_LEVEL_MASK 0x1C5100 /* */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0_START_ADDRESS 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_EMMC_START_ADDRESS_MSB_0_START_ADDRESS_INIT 0x0000000 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0 0x1C5094 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_ENABLE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_SPARE 1:1 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_FGC6_CLAMP_0_SPARE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0 0x1C5098 /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0_COUNTER_VAL 31:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_MODE_DELAY_0_COUNTER_VAL_INIT 0x00000032 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0 0x1C509c /* RW-4R */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0__PRIV_LEVEL_MASK 0x1C5000 /* */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_ENABLE 0:0 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_MATHS_MODE_GATING_ENABLE 1:1 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_MATHS_MODE_GATING_ENABLE_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_0 2:2 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_0_INIT 0x0 /* RWD-V */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_1 3:3 /* RWDUF */
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#define NV_IST_SEQ_SLV_IST_ABSOLUTE_ADDRESS_0_SPARE_1_INIT 0x0 /* RWD-V */
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#endif // __ga102_dev_ist_seq_slv_h__
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