Patch cuda.cpp with cloudy's fix

For XCDs, we dont show them if the GPU is made of a single
XCD, as it adds little value

For matrix cores, we assume it can be computed as
compute_units * simds_per_cu, it seems to work for the GPUs
I checked from CDNA3 and RDNA3. Not sure what would happen for
older GPUs that do not have matrix cores though.

src/common/gpu.cpp

@@ -101,6 +101,17 @@ char* get_str_bus_width(struct gpu_info* gpu) {
   return string;
 }
 
+char* get_str_lds_size(struct gpu_info* gpu) {
+  // TODO: Show XX KB (XX MB Total) like in cpufetch
+  uint32_t size = 3+1+3+1;
+  assert(strlen(STRING_UNKNOWN)+1 <= size);
+  char* string = (char *) ecalloc(size, sizeof(char));
+
+  sprintf(string, "%d KB", gpu->mem->lds_size / 1024);
+
+  return string;
+}
+
 char* get_str_memory_clock(struct gpu_info* gpu) {
   return get_freq_as_str_mhz(gpu->mem->freq);
 }

src/common/gpu.hpp

@@ -46,6 +46,10 @@ struct topology_c {
 // HSA topology
 struct topology_h {
   int32_t compute_units;
+  int32_t num_shader_engines;
+  int32_t simds_per_cu;
+  int32_t num_xcc;
+  int32_t matrix_cores;
 };
 
 // Intel topology
@@ -61,6 +65,7 @@ struct memory {
   int32_t bus_width;
   int32_t freq;
   int32_t clk_mul; // clock multiplier
+  int32_t lds_size; // HSA specific for now
 };
 
 struct gpu_info {
@@ -88,6 +93,7 @@ char* get_str_freq(struct gpu_info* gpu);
 char* get_str_memory_size(struct gpu_info* gpu);
 char* get_str_memory_type(struct gpu_info* gpu);
 char* get_str_bus_width(struct gpu_info* gpu);
+char* get_str_lds_size(struct gpu_info* gpu);
 char* get_str_memory_clock(struct gpu_info* gpu);
 char* get_str_l2(struct gpu_info* gpu);
 char* get_str_peak_performance(struct gpu_info* gpu);

src/common/printer.cpp

@@ -48,14 +48,17 @@ enum {
   ATTRIBUTE_FREQUENCY,     // ALL
   ATTRIBUTE_PEAK,          // ALL
   ATTRIBUTE_COMPUTE_UNITS, // HSA
+  ATTRIBUTE_MATRIX_CORES,  // HSA
+  ATTRIBUTE_XCDS,          // HSA
+  ATTRIBUTE_LDS_SIZE,      // HSA
   ATTRIBUTE_STREAMINGMP,   // CUDA
   ATTRIBUTE_CORESPERMP,    // CUDA
   ATTRIBUTE_CUDA_CORES,    // CUDA
   ATTRIBUTE_TENSOR_CORES,  // CUDA
   ATTRIBUTE_L2,            // CUDA
-  ATTRIBUTE_MEMORY,        // CUDA
+  ATTRIBUTE_MEMORY,        // CUDA,HSA
   ATTRIBUTE_MEMORY_FREQ,   // CUDA
-  ATTRIBUTE_BUS_WIDTH,     // CUDA
+  ATTRIBUTE_BUS_WIDTH,     // CUDA,HSA
   ATTRIBUTE_PEAK_TENSOR,   // CUDA
   ATTRIBUTE_EUS,           // Intel
   ATTRIBUTE_GT,            // Intel
@@ -69,6 +72,9 @@ static const AttributeField ATTRIBUTE_INFO[] = {
   { ATTRIBUTE_FREQUENCY,     "Max Frequency:",          "Max Freq.:" },
   { ATTRIBUTE_PEAK,          "Peak Performance:",       "Peak Perf.:" },
   { ATTRIBUTE_COMPUTE_UNITS, "Compute Units (CUs):",    "CUs" },
+  { ATTRIBUTE_MATRIX_CORES,  "Matrix Cores:",           "Matrix Cores:" },
+  { ATTRIBUTE_XCDS,          "XCDs:",                   "XCDs" },
+  { ATTRIBUTE_LDS_SIZE,      "LDS size:",               "LDS:" },
   { ATTRIBUTE_STREAMINGMP,   "SMs:",                    "SMs:" },
   { ATTRIBUTE_CORESPERMP,    "Cores/SM:",               "Cores/SM:" },
   { ATTRIBUTE_CUDA_CORES,    "CUDA Cores:",             "CUDA Cores:" },
@@ -486,7 +492,12 @@ bool print_gpufetch_amd(struct gpu_info* gpu, STYLE s, struct color** cs, struct
   char* uarch = get_str_uarch_hsa(gpu->arch);
   char* manufacturing_process = get_str_process(gpu->arch);
   char* cus = get_str_cu(gpu);
+  char* matrix_cores = get_str_matrix_cores(gpu);
+  char* xcds = get_str_xcds(gpu);
   char* max_frequency = get_str_freq(gpu);
+  char* bus_width = get_str_bus_width(gpu);
+  char* mem_size = get_str_memory_size(gpu);
+  char* lds_size = get_str_lds_size(gpu);
 
   setAttribute(art, ATTRIBUTE_NAME, gpu_name);
   if (gpu_chip != NULL) {
@@ -496,6 +507,13 @@ bool print_gpufetch_amd(struct gpu_info* gpu, STYLE s, struct color** cs, struct
   setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
   setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
   setAttribute(art, ATTRIBUTE_COMPUTE_UNITS, cus);
+  setAttribute(art, ATTRIBUTE_MATRIX_CORES, matrix_cores);
+  if (xcds != NULL) {
+    setAttribute(art, ATTRIBUTE_XCDS, xcds);
+  }
+  setAttribute(art, ATTRIBUTE_LDS_SIZE, lds_size);
+  setAttribute(art, ATTRIBUTE_MEMORY, mem_size);
+  setAttribute(art, ATTRIBUTE_BUS_WIDTH, bus_width);
 
   bool use_short = false;
   uint32_t longest_attribute = longest_attribute_length(art, use_short);

src/cuda/cuda.cpp

@@ -1,3 +1,6 @@
+
+// patched cuda.cpp for cuda13 by cloudy
+
 #include <cuda_runtime.h>
 #include <cstring>
 #include <cstdlib>
@@ -14,25 +17,20 @@ bool print_gpu_cuda(struct gpu_info* gpu) {
   char* cc = get_str_cc(gpu->arch);
   printf("%s (Compute Capability %s)\n", gpu->name, cc);
   free(cc);
-
   return true;
 }
 
 struct cache* get_cache_info(cudaDeviceProp prop) {
   struct cache* cach = (struct cache*) emalloc(sizeof(struct cache));
-
   cach->L2 = (struct cach*) emalloc(sizeof(struct cach));
   cach->L2->size = prop.l2CacheSize;
   cach->L2->num_caches = 1;
   cach->L2->exists = true;
-
   return cach;
 }
 
 int get_tensor_cores(struct uarch* arch, int sm, int major) {
   if(major == 7) {
-    // TU116 does not have tensor cores!
-    // https://www.anandtech.com/show/13973/nvidia-gtx-1660-ti-review-feat-evga-xc-gaming/2
     if (is_chip_TU116(arch))
       return 0;
     return sm * 8;
@@ -43,57 +41,57 @@ int get_tensor_cores(struct uarch* arch, int sm, int major) {
 
 struct topology_c* get_topology_info(struct uarch* arch, cudaDeviceProp prop) {
   struct topology_c* topo = (struct topology_c*) emalloc(sizeof(struct topology_c));
-
   topo->streaming_mp = prop.multiProcessorCount;
   topo->cores_per_mp = _ConvertSMVer2Cores(prop.major, prop.minor);
   topo->cuda_cores = topo->streaming_mp * topo->cores_per_mp;
   topo->tensor_cores = get_tensor_cores(arch, topo->streaming_mp, prop.major);
-
   return topo;
 }
 
 int32_t guess_clock_multipilier(struct gpu_info* gpu, struct memory* mem) {
-  // Guess clock multiplier
   int32_t clk_mul = 1;
-
   int32_t clk8 = abs((mem->freq/8) - gpu->freq);
   int32_t clk4 = abs((mem->freq/4) - gpu->freq);
   int32_t clk2 = abs((mem->freq/2) - gpu->freq);
   int32_t clk1 = abs((mem->freq/1) - gpu->freq);
-
   int32_t min = mem->freq;
   if(clkm_possible_for_uarch(8, gpu->arch) && min > clk8) { clk_mul = 8; min = clk8; }
   if(clkm_possible_for_uarch(4, gpu->arch) && min > clk4) { clk_mul = 4; min = clk4; }
   if(clkm_possible_for_uarch(2, gpu->arch) && min > clk2) { clk_mul = 2; min = clk2; }
   if(clkm_possible_for_uarch(1, gpu->arch) && min > clk1) { clk_mul = 1; min = clk1; }
-
   return clk_mul;
 }
 
 struct memory* get_memory_info(struct gpu_info* gpu, cudaDeviceProp prop) {
   struct memory* mem = (struct memory*) emalloc(sizeof(struct memory));
+  int val = 0;
 
   mem->size_bytes = (unsigned long long) prop.totalGlobalMem;
-  mem->freq = prop.memoryClockRate * 0.001f;
+
+  if (cudaDeviceGetAttribute(&val, cudaDevAttrMemoryClockRate, gpu->idx) == cudaSuccess) {
+      if (val > 1000000)
+          mem->freq = (float)val / 1000000.0f;
+      else
+          mem->freq = (float)val * 0.001f;
+  } else {
+      mem->freq = 0.0f;
+  }
+
   mem->bus_width = prop.memoryBusWidth;
   mem->clk_mul = guess_clock_multipilier(gpu, mem);
   mem->type = guess_memtype_from_cmul_and_uarch(mem->clk_mul, gpu->arch);
 
-  // Fix frequency returned from CUDA to show real frequency
-  mem->freq = mem->freq  / mem->clk_mul;
+  if (mem->clk_mul > 0)
+      mem->freq = mem->freq / mem->clk_mul;
 
   return mem;
 }
 
-// Compute peak performance when using CUDA cores
 int64_t get_peak_performance_cuda(struct gpu_info* gpu) {
   return gpu->freq * 1000000 * gpu->topo_c->cuda_cores * 2;
 }
 
-// Compute peak performance when using tensor cores
 int64_t get_peak_performance_tcu(cudaDeviceProp prop, struct gpu_info* gpu) {
-  // Volta / Turing tensor cores performs 4x4x4 FP16 matrix multiplication
-  // Ampere tensor cores performs 8x4x8 FP16 matrix multiplicacion
   if(prop.major == 7) return gpu->freq * 1000000 * 4 * 4 * 4  * 2 * gpu->topo_c->tensor_cores;
   else if(prop.major == 8) return gpu->freq * 1000000 * 8 * 4 * 8 * 2 * gpu->topo_c->tensor_cores;
   else return 0;
@@ -115,8 +113,7 @@ struct gpu_info* get_gpu_info_cuda(struct pci_dev *devices, int gpu_idx) {
   }
 
   int num_gpus = -1;
-  cudaError_t err = cudaSuccess;
-  err = cudaGetDeviceCount(&num_gpus);
+  cudaError_t err = cudaGetDeviceCount(&num_gpus);
 
   if(gpu_idx == 0) {
     printf("\r%*c\r", (int) strlen(CUDA_DRIVER_START_WARNING), ' ');
@@ -134,7 +131,6 @@ struct gpu_info* get_gpu_info_cuda(struct pci_dev *devices, int gpu_idx) {
   }
 
   if(gpu->idx+1 > num_gpus) {
-    // Master is trying to query an invalid GPU
     return NULL;
   }
 
@@ -144,15 +140,25 @@ struct gpu_info* get_gpu_info_cuda(struct pci_dev *devices, int gpu_idx) {
     return NULL;
   }
 
-  gpu->freq = deviceProp.clockRate * 1e-3f;
+  int core_clk = 0;
+  if (cudaDeviceGetAttribute(&core_clk, cudaDevAttrClockRate, gpu->idx) == cudaSuccess) {
+      if (core_clk > 1000000)
+          gpu->freq = core_clk / 1000000.0f;
+      else
+          gpu->freq = core_clk * 0.001f;
+  } else {
+      gpu->freq = 0.0f;
+  }
+
   gpu->vendor = GPU_VENDOR_NVIDIA;
-  gpu->name = (char *) emalloc(sizeof(char) * (strlen(deviceProp.name) + 1));
+  gpu->name = (char *) emalloc(strlen(deviceProp.name) + 1);
   strcpy(gpu->name, deviceProp.name);
 
   if((gpu->pci = get_pci_from_pciutils(devices, PCI_VENDOR_ID_NVIDIA, gpu_idx)) == NULL) {
     printErr("Unable to find a valid device for vendor id 0x%.4X using pciutils", PCI_VENDOR_ID_NVIDIA);
     return NULL;
   }
+
   gpu->arch = get_uarch_from_cuda(gpu);
   gpu->cach = get_cache_info(deviceProp);
   gpu->mem = get_memory_info(gpu, deviceProp);
@@ -163,19 +169,7 @@ struct gpu_info* get_gpu_info_cuda(struct pci_dev *devices, int gpu_idx) {
   return gpu;
 }
 
-char* get_str_sm(struct gpu_info* gpu) {
-  return get_str_generic(gpu->topo_c->streaming_mp);
-}
-
-char* get_str_cores_sm(struct gpu_info* gpu) {
-  return get_str_generic(gpu->topo_c->cores_per_mp);
-}
-
-char* get_str_cuda_cores(struct gpu_info* gpu) {
-  return get_str_generic(gpu->topo_c->cuda_cores);
-}
-
-char* get_str_tensor_cores(struct gpu_info* gpu) {
-  return get_str_generic(gpu->topo_c->tensor_cores);
-}
-
+char* get_str_sm(struct gpu_info* gpu) { return get_str_generic(gpu->topo_c->streaming_mp); }
+char* get_str_cores_sm(struct gpu_info* gpu) { return get_str_generic(gpu->topo_c->cores_per_mp); }
+char* get_str_cuda_cores(struct gpu_info* gpu) { return get_str_generic(gpu->topo_c->cuda_cores); }
+char* get_str_tensor_cores(struct gpu_info* gpu) { return get_str_generic(gpu->topo_c->tensor_cores); }

src/hsa/hsa.cpp

@@ -22,7 +22,16 @@ struct agent_info {
   char vendor_name[64];
   char device_mkt_name[64];
   uint32_t max_clock_freq;
+  // Memory
+  uint32_t bus_width;
+  uint32_t lds_size;
+  uint64_t global_size;
+  // Topology
   uint32_t compute_unit;
+  uint32_t num_shader_engines;
+  uint32_t simds_per_cu;
+  uint32_t num_xcc;            // Acccelerator Complex Dies (XCDs)
+  uint32_t matrix_cores;       // Cores with WMMA/MFMA capabilities
 };
 
 #define RET_IF_HSA_ERR(err) { \
@@ -40,6 +49,51 @@ struct agent_info {
   }                                                                           \
 }
 
+hsa_status_t memory_pool_callback(hsa_amd_memory_pool_t pool, void* data) {
+  struct agent_info* info = reinterpret_cast<struct agent_info *>(data);
+
+  hsa_amd_segment_t segment;
+  hsa_status_t err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SEGMENT, &segment);
+  RET_IF_HSA_ERR(err);
+
+  if (segment == HSA_AMD_SEGMENT_GROUP) {
+    // LDS memory
+    // We want to make sure that this memory pool is not repeated.
+    if (info->lds_size != 0) {
+      printErr("Found HSA_AMD_SEGMENT_GROUP twice!");
+      return HSA_STATUS_ERROR;
+    }
+    uint32_t size = 0;
+
+    err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SIZE, &size);
+    RET_IF_HSA_ERR(err);
+
+    info->lds_size = size;    
+  }
+  else if (segment == HSA_AMD_SEGMENT_GLOBAL) {
+    // Global memory
+    uint32_t global_flags = 0;
+    
+    err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS, &global_flags);
+    RET_IF_HSA_ERR(err);
+
+    if (global_flags & HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED) {
+      if (info->global_size != 0) {
+        printErr("Found HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED twice!");
+        return HSA_STATUS_ERROR;
+      }
+
+      uint64_t size = 0;
+
+      err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SIZE, &size);
+      RET_IF_HSA_ERR(err);
+
+      info->global_size = size;
+    }    
+  }
+  return HSA_STATUS_SUCCESS;
+}
+
 hsa_status_t agent_callback(hsa_agent_t agent, void *data) {
   struct agent_info* info = reinterpret_cast<struct agent_info *>(data);
 
@@ -62,6 +116,26 @@ hsa_status_t agent_callback(hsa_agent_t agent, void *data) {
 
     err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT, &info->compute_unit);
     RET_IF_HSA_ERR(err);
+
+    // According to the documentation, this is deprecated. But what should I be using then?
+    err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_MEMORY_WIDTH, &info->bus_width);
+    RET_IF_HSA_ERR(err);
+
+    err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES, &info->num_shader_engines);
+    RET_IF_HSA_ERR(err);
+
+    err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU, &info->simds_per_cu);
+    RET_IF_HSA_ERR(err);
+
+    err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_NUM_XCC, &info->num_xcc);
+    RET_IF_HSA_ERR(err);
+
+    // We will check against zero to see if it was set beforehand.
+    info->global_size = 0;
+    info->lds_size = 0;
+    // This will fill global_size and lds_size.
+    err = hsa_amd_agent_iterate_memory_pools(agent, memory_pool_callback, data);
+    RET_IF_HSA_ERR(err);
   }
 
   return HSA_STATUS_SUCCESS;
@@ -71,10 +145,26 @@ struct topology_h* get_topology_info(struct agent_info info) {
   struct topology_h* topo = (struct topology_h*) emalloc(sizeof(struct topology_h));
 
   topo->compute_units = info.compute_unit;
+  topo->num_shader_engines = info.num_shader_engines; // not printed at the moment
+  topo->simds_per_cu = info.simds_per_cu;             // not printed at the moment
+  topo->num_xcc = info.num_xcc;
+  // Old GPUs (GCN I guess) might not have matrix cores.
+  // Not sure what would happen here?
+  topo->matrix_cores = topo->compute_units * topo->simds_per_cu;
 
   return topo;
 }
 
+struct memory* get_memory_info(struct gpu_info* gpu, struct agent_info info) {
+  struct memory* mem = (struct memory*) emalloc(sizeof(struct memory));
+  
+  mem->bus_width = info.bus_width;
+  mem->lds_size = info.lds_size;
+  mem->size_bytes = info.global_size;
+
+  return mem;
+}
+
 struct gpu_info* get_gpu_info_hsa(int gpu_idx) {
   struct gpu_info* gpu = (struct gpu_info*) emalloc(sizeof(struct gpu_info));
   gpu->pci = NULL;
@@ -118,6 +208,7 @@ struct gpu_info* get_gpu_info_hsa(int gpu_idx) {
   gpu->name = (char *) emalloc(sizeof(char) * (strlen(info.device_mkt_name) + 1));
   strcpy(gpu->name, info.device_mkt_name);
   gpu->arch = get_uarch_from_hsa(gpu, info.gpu_name);
+  gpu->mem = get_memory_info(gpu, info);
 
   if (gpu->arch == NULL) {
     return NULL;
@@ -135,3 +226,17 @@ struct gpu_info* get_gpu_info_hsa(int gpu_idx) {
 char* get_str_cu(struct gpu_info* gpu) {
   return get_str_generic(gpu->topo_h->compute_units);
 }
+
+char* get_str_xcds(struct gpu_info* gpu) {
+  // If there is a single XCD, then we dont want to
+  // print it.
+  if (gpu->topo_h->num_xcc == 1) {
+    return NULL;
+  }
+  return get_str_generic(gpu->topo_h->num_xcc);
+}
+
+char* get_str_matrix_cores(struct gpu_info* gpu) {
+  // TODO: Show XX (WMMA/MFMA)
+  return get_str_generic(gpu->topo_h->matrix_cores);
+}

src/hsa/hsa.hpp

@@ -5,5 +5,7 @@
 
 struct gpu_info* get_gpu_info_hsa(int gpu_idx);
 char* get_str_cu(struct gpu_info* gpu);
+char* get_str_xcds(struct gpu_info* gpu);
+char* get_str_matrix_cores(struct gpu_info* gpu);
 
 #endif