5f619dc95a
For XCDs, we dont show them if the GPU is made of a single XCD, as it adds little value For matrix cores, we assume it can be computed as compute_units * simds_per_cu, it seems to work for the GPUs I checked from CDNA3 and RDNA3. Not sure what would happen for older GPUs that do not have matrix cores though.
242 lines
7.7 KiB
C++
242 lines
7.7 KiB
C++
#include <iostream>
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#include <hsa/hsa.h>
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#include <hsa/hsa_ext_amd.h>
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#include <cstring>
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#include <cstdlib>
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#include <cstdio>
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#include <iostream>
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#include <iomanip>
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#include <hsa/hsa.h>
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#include <hsa/hsa_ext_amd.h>
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#include "hsa.hpp"
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#include "uarch.hpp"
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#include "../common/global.hpp"
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#include "../common/uarch.hpp"
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struct agent_info {
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unsigned deviceId; // ID of the target GPU device
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char gpu_name[64];
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char vendor_name[64];
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char device_mkt_name[64];
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uint32_t max_clock_freq;
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// Memory
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uint32_t bus_width;
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uint32_t lds_size;
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uint64_t global_size;
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// Topology
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uint32_t compute_unit;
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uint32_t num_shader_engines;
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uint32_t simds_per_cu;
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uint32_t num_xcc; // Acccelerator Complex Dies (XCDs)
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uint32_t matrix_cores; // Cores with WMMA/MFMA capabilities
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};
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#define RET_IF_HSA_ERR(err) { \
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if ((err) != HSA_STATUS_SUCCESS) { \
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char err_val[12]; \
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char* err_str = NULL; \
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if (hsa_status_string(err, \
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(const char**)&err_str) != HSA_STATUS_SUCCESS) { \
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snprintf(&(err_val[0]), sizeof(err_val), "%#x", (uint32_t)err); \
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err_str = &(err_val[0]); \
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} \
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printErr("HSA failure at: %s:%d\n", __FILE__, __LINE__); \
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printErr("Call returned %s\n", err_str); \
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return (err); \
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} \
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}
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hsa_status_t memory_pool_callback(hsa_amd_memory_pool_t pool, void* data) {
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struct agent_info* info = reinterpret_cast<struct agent_info *>(data);
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hsa_amd_segment_t segment;
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hsa_status_t err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SEGMENT, &segment);
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RET_IF_HSA_ERR(err);
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if (segment == HSA_AMD_SEGMENT_GROUP) {
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// LDS memory
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// We want to make sure that this memory pool is not repeated.
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if (info->lds_size != 0) {
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printErr("Found HSA_AMD_SEGMENT_GROUP twice!");
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return HSA_STATUS_ERROR;
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}
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uint32_t size = 0;
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err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SIZE, &size);
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RET_IF_HSA_ERR(err);
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info->lds_size = size;
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}
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else if (segment == HSA_AMD_SEGMENT_GLOBAL) {
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// Global memory
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uint32_t global_flags = 0;
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err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS, &global_flags);
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RET_IF_HSA_ERR(err);
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if (global_flags & HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED) {
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if (info->global_size != 0) {
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printErr("Found HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED twice!");
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return HSA_STATUS_ERROR;
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}
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uint64_t size = 0;
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err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SIZE, &size);
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RET_IF_HSA_ERR(err);
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info->global_size = size;
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}
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}
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return HSA_STATUS_SUCCESS;
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}
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hsa_status_t agent_callback(hsa_agent_t agent, void *data) {
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struct agent_info* info = reinterpret_cast<struct agent_info *>(data);
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hsa_device_type_t type;
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hsa_status_t err = hsa_agent_get_info(agent, HSA_AGENT_INFO_DEVICE, &type);
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RET_IF_HSA_ERR(err);
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if (type == HSA_DEVICE_TYPE_GPU) {
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err = hsa_agent_get_info(agent, HSA_AGENT_INFO_NAME, info->gpu_name);
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RET_IF_HSA_ERR(err);
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err = hsa_agent_get_info(agent, HSA_AGENT_INFO_VENDOR_NAME, info->vendor_name);
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RET_IF_HSA_ERR(err);
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_PRODUCT_NAME, &info->device_mkt_name);
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RET_IF_HSA_ERR(err);
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_MAX_CLOCK_FREQUENCY, &info->max_clock_freq);
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RET_IF_HSA_ERR(err);
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT, &info->compute_unit);
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RET_IF_HSA_ERR(err);
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// According to the documentation, this is deprecated. But what should I be using then?
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_MEMORY_WIDTH, &info->bus_width);
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RET_IF_HSA_ERR(err);
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_NUM_SHADER_ENGINES, &info->num_shader_engines);
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RET_IF_HSA_ERR(err);
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_NUM_SIMDS_PER_CU, &info->simds_per_cu);
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RET_IF_HSA_ERR(err);
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_NUM_XCC, &info->num_xcc);
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RET_IF_HSA_ERR(err);
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// We will check against zero to see if it was set beforehand.
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info->global_size = 0;
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info->lds_size = 0;
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// This will fill global_size and lds_size.
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err = hsa_amd_agent_iterate_memory_pools(agent, memory_pool_callback, data);
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RET_IF_HSA_ERR(err);
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}
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return HSA_STATUS_SUCCESS;
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}
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struct topology_h* get_topology_info(struct agent_info info) {
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struct topology_h* topo = (struct topology_h*) emalloc(sizeof(struct topology_h));
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topo->compute_units = info.compute_unit;
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topo->num_shader_engines = info.num_shader_engines; // not printed at the moment
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topo->simds_per_cu = info.simds_per_cu; // not printed at the moment
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topo->num_xcc = info.num_xcc;
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// Old GPUs (GCN I guess) might not have matrix cores.
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// Not sure what would happen here?
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topo->matrix_cores = topo->compute_units * topo->simds_per_cu;
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return topo;
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}
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struct memory* get_memory_info(struct gpu_info* gpu, struct agent_info info) {
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struct memory* mem = (struct memory*) emalloc(sizeof(struct memory));
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mem->bus_width = info.bus_width;
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mem->lds_size = info.lds_size;
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mem->size_bytes = info.global_size;
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return mem;
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}
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struct gpu_info* get_gpu_info_hsa(int gpu_idx) {
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struct gpu_info* gpu = (struct gpu_info*) emalloc(sizeof(struct gpu_info));
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gpu->pci = NULL;
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gpu->idx = gpu_idx;
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if(gpu->idx < 0) {
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printErr("GPU index must be equal or greater than zero");
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return NULL;
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}
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if(gpu->idx > 0) {
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// Currently we only support fetching GPU 0.
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return NULL;
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}
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hsa_status_t err = hsa_init();
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if (err != HSA_STATUS_SUCCESS) {
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printErr("Failed to initialize HSA runtime");
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return NULL;
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}
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struct agent_info info;
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info.deviceId = gpu_idx;
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// Iterate over all agents in the system
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err = hsa_iterate_agents(agent_callback, &info);
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if (err != HSA_STATUS_SUCCESS) {
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printErr("Failed to iterate HSA agents");
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hsa_shut_down();
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return NULL;
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}
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if (strcmp(info.vendor_name, "AMD") != 0) {
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printErr("HSA vendor name is: '%s'. Only AMD is supported!", info.vendor_name);
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return NULL;
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}
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gpu->vendor = GPU_VENDOR_AMD;
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gpu->freq = info.max_clock_freq;
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gpu->topo_h = get_topology_info(info);
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gpu->name = (char *) emalloc(sizeof(char) * (strlen(info.device_mkt_name) + 1));
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strcpy(gpu->name, info.device_mkt_name);
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gpu->arch = get_uarch_from_hsa(gpu, info.gpu_name);
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gpu->mem = get_memory_info(gpu, info);
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if (gpu->arch == NULL) {
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return NULL;
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}
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// Shut down the HSA runtime
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err = hsa_shut_down();
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if (err != HSA_STATUS_SUCCESS) {
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printErr("Failed to shutdown HSA runtime");
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return NULL;
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}
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return gpu;
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}
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char* get_str_cu(struct gpu_info* gpu) {
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return get_str_generic(gpu->topo_h->compute_units);
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}
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char* get_str_xcds(struct gpu_info* gpu) {
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// If there is a single XCD, then we dont want to
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// print it.
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if (gpu->topo_h->num_xcc == 1) {
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return NULL;
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}
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return get_str_generic(gpu->topo_h->num_xcc);
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}
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char* get_str_matrix_cores(struct gpu_info* gpu) {
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// TODO: Show XX (WMMA/MFMA)
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return get_str_generic(gpu->topo_h->matrix_cores);
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} |