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amd-suppor
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e0c843274c | ||
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b543b23f60 | ||
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9b519828f4 | ||
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3b567b9381 | ||
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e1f03c4e04 | ||
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046f8c1299 | ||
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b434fc6fd0 | ||
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5beccaebb0 |
@@ -101,6 +101,17 @@ char* get_str_bus_width(struct gpu_info* gpu) {
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return string;
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}
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char* get_str_lds_size(struct gpu_info* gpu) {
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// TODO: Show XX KB (XX MB Total) like in cpufetch
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uint32_t size = 3+1+3+1;
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assert(strlen(STRING_UNKNOWN)+1 <= size);
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char* string = (char *) ecalloc(size, sizeof(char));
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sprintf(string, "%d KB", gpu->mem->lds_size / 1024);
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return string;
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}
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char* get_str_memory_clock(struct gpu_info* gpu) {
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return get_freq_as_str_mhz(gpu->mem->freq);
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}
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@@ -61,6 +61,7 @@ struct memory {
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int32_t bus_width;
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int32_t freq;
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int32_t clk_mul; // clock multiplier
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int32_t lds_size; // HSA specific for now
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};
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struct gpu_info {
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@@ -88,6 +89,7 @@ char* get_str_freq(struct gpu_info* gpu);
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char* get_str_memory_size(struct gpu_info* gpu);
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char* get_str_memory_type(struct gpu_info* gpu);
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char* get_str_bus_width(struct gpu_info* gpu);
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char* get_str_lds_size(struct gpu_info* gpu);
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char* get_str_memory_clock(struct gpu_info* gpu);
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char* get_str_l2(struct gpu_info* gpu);
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char* get_str_peak_performance(struct gpu_info* gpu);
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@@ -48,14 +48,15 @@ enum {
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ATTRIBUTE_FREQUENCY, // ALL
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ATTRIBUTE_PEAK, // ALL
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ATTRIBUTE_COMPUTE_UNITS, // HSA
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ATTRIBUTE_LDS_SIZE, // HSA
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ATTRIBUTE_STREAMINGMP, // CUDA
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ATTRIBUTE_CORESPERMP, // CUDA
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ATTRIBUTE_CUDA_CORES, // CUDA
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ATTRIBUTE_TENSOR_CORES, // CUDA
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ATTRIBUTE_L2, // CUDA
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ATTRIBUTE_MEMORY, // CUDA
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ATTRIBUTE_MEMORY, // CUDA,HSA
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ATTRIBUTE_MEMORY_FREQ, // CUDA
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ATTRIBUTE_BUS_WIDTH, // CUDA
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ATTRIBUTE_BUS_WIDTH, // CUDA,HSA
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ATTRIBUTE_PEAK_TENSOR, // CUDA
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ATTRIBUTE_EUS, // Intel
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ATTRIBUTE_GT, // Intel
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@@ -69,6 +70,7 @@ static const AttributeField ATTRIBUTE_INFO[] = {
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{ ATTRIBUTE_FREQUENCY, "Max Frequency:", "Max Freq.:" },
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{ ATTRIBUTE_PEAK, "Peak Performance:", "Peak Perf.:" },
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{ ATTRIBUTE_COMPUTE_UNITS, "Compute Units (CUs):", "CUs" },
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{ ATTRIBUTE_LDS_SIZE, "LDS size:", "LDS:" },
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{ ATTRIBUTE_STREAMINGMP, "SMs:", "SMs:" },
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{ ATTRIBUTE_CORESPERMP, "Cores/SM:", "Cores/SM:" },
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{ ATTRIBUTE_CUDA_CORES, "CUDA Cores:", "CUDA Cores:" },
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@@ -487,6 +489,9 @@ bool print_gpufetch_amd(struct gpu_info* gpu, STYLE s, struct color** cs, struct
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char* manufacturing_process = get_str_process(gpu->arch);
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char* cus = get_str_cu(gpu);
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char* max_frequency = get_str_freq(gpu);
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char* bus_width = get_str_bus_width(gpu);
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char* mem_size = get_str_memory_size(gpu);
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char* lds_size = get_str_lds_size(gpu);
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setAttribute(art, ATTRIBUTE_NAME, gpu_name);
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if (gpu_chip != NULL) {
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@@ -496,6 +501,9 @@ bool print_gpufetch_amd(struct gpu_info* gpu, STYLE s, struct color** cs, struct
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setAttribute(art, ATTRIBUTE_TECHNOLOGY, manufacturing_process);
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setAttribute(art, ATTRIBUTE_FREQUENCY, max_frequency);
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setAttribute(art, ATTRIBUTE_COMPUTE_UNITS, cus);
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setAttribute(art, ATTRIBUTE_LDS_SIZE, lds_size);
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setAttribute(art, ATTRIBUTE_MEMORY, mem_size);
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setAttribute(art, ATTRIBUTE_BUS_WIDTH, bus_width);
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bool use_short = false;
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uint32_t longest_attribute = longest_attribute_length(art, use_short);
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@@ -23,6 +23,9 @@ struct agent_info {
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char device_mkt_name[64];
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uint32_t max_clock_freq;
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uint32_t compute_unit;
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uint32_t bus_width;
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uint32_t lds_size;
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uint64_t global_size;
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};
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#define RET_IF_HSA_ERR(err) { \
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@@ -40,6 +43,46 @@ struct agent_info {
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} \
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}
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hsa_status_t memory_pool_callback(hsa_amd_memory_pool_t pool, void* data) {
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struct agent_info* info = reinterpret_cast<struct agent_info *>(data);
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hsa_amd_segment_t segment;
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hsa_status_t err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SEGMENT, &segment);
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RET_IF_HSA_ERR(err);
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if (segment == HSA_AMD_SEGMENT_GROUP) {
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// LDS memory
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uint32_t size = 0;
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err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SIZE, &size);
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RET_IF_HSA_ERR(err);
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info->lds_size = size;
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}
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else if (segment == HSA_AMD_SEGMENT_GLOBAL) {
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// Global memory
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uint32_t global_flags = 0;
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err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_GLOBAL_FLAGS, &global_flags);
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RET_IF_HSA_ERR(err);
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if (global_flags & HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED) {
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if (info->global_size != 0) {
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printErr("Found HSA_AMD_MEMORY_POOL_GLOBAL_FLAG_EXTENDED_SCOPE_FINE_GRAINED twice!");
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return HSA_STATUS_ERROR;
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}
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uint64_t size = 0;
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err = hsa_amd_memory_pool_get_info(pool, HSA_AMD_MEMORY_POOL_INFO_SIZE, &size);
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RET_IF_HSA_ERR(err);
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info->global_size = size;
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}
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}
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return HSA_STATUS_SUCCESS;
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}
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hsa_status_t agent_callback(hsa_agent_t agent, void *data) {
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struct agent_info* info = reinterpret_cast<struct agent_info *>(data);
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@@ -62,6 +105,14 @@ hsa_status_t agent_callback(hsa_agent_t agent, void *data) {
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_COMPUTE_UNIT_COUNT, &info->compute_unit);
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RET_IF_HSA_ERR(err);
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// According to the documentation, this is deprecated. But what should I be using then?
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err = hsa_agent_get_info(agent, (hsa_agent_info_t) HSA_AMD_AGENT_INFO_MEMORY_WIDTH, &info->bus_width);
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RET_IF_HSA_ERR(err);
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info->global_size = 0;
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err = hsa_amd_agent_iterate_memory_pools(agent, memory_pool_callback, data);
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RET_IF_HSA_ERR(err);
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}
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return HSA_STATUS_SUCCESS;
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@@ -75,6 +126,16 @@ struct topology_h* get_topology_info(struct agent_info info) {
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return topo;
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}
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struct memory* get_memory_info(struct gpu_info* gpu, struct agent_info info) {
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struct memory* mem = (struct memory*) emalloc(sizeof(struct memory));
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mem->bus_width = info.bus_width;
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mem->lds_size = info.lds_size;
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mem->size_bytes = info.global_size;
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return mem;
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}
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struct gpu_info* get_gpu_info_hsa(int gpu_idx) {
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struct gpu_info* gpu = (struct gpu_info*) emalloc(sizeof(struct gpu_info));
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gpu->pci = NULL;
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@@ -118,6 +179,7 @@ struct gpu_info* get_gpu_info_hsa(int gpu_idx) {
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gpu->name = (char *) emalloc(sizeof(char) * (strlen(info.device_mkt_name) + 1));
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strcpy(gpu->name, info.device_mkt_name);
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gpu->arch = get_uarch_from_hsa(gpu, info.gpu_name);
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gpu->mem = get_memory_info(gpu, info);
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if (gpu->arch == NULL) {
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return NULL;
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