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[v0.11] Completed most of Intel iGPU topologies

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Dr-Noob
2021-12-10 15:32:29 +01:00
parent e5deeb1309
commit 5f52f73fe0
1 changed files with 26 additions and 13 deletions
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39
src/intel/uarch.cpp
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@@ -14,7 +14,16 @@
// Unknown manufacturing process // Unknown manufacturing process
#define UNK -1 #define UNK -1
// MICROARCH values /*
* Mapping between iGPU and CPU uarchs
* -----------------------------------
* Gen6: Sandy Bridge (2th Gen)
* Gen7: Ivy Brdige (3th Gen)
* Gen7.5: Haswell (4th Gen)
* Gen8: Broadwell (5th Gen)
* Gen9: Skylake (6th Gen)
* Gen9.5: Kaby Lake
*/
enum { enum {
UARCH_UNKNOWN, UARCH_UNKNOWN,
UARCH_GEN6, UARCH_GEN6,
@@ -152,13 +161,14 @@ char* get_name_from_uarch(struct uarch* arch) {
/* /*
* Refs: * Refs:
* Gen7.5: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen7 * Gen6: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen6
"The Compute Architecture of Intel Processor Graphics Gen7.5, v1.0" * Gen7/7.5: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen7
* Gen8: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen8 "The Compute Architecture of Intel Processor Graphics Gen7.5, v1.0"
"The Compute Architecture of Intel Processor Graphics Gen8, v1.1" * Gen8: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen8
* Gen9: https://en.wikichip.org/wiki/intel/microarchitectures/gen9#Configuration "The Compute Architecture of Intel Processor Graphics Gen8, v1.1"
"The Compute Architecture of Intel Processor Graphics Gen9, v1.0" * Gen9: https://en.wikichip.org/wiki/intel/microarchitectures/gen9#Configuration
* Gen9.5: https://en.wikichip.org/wiki/intel/microarchitectures/gen9.5#Configuration "The Compute Architecture of Intel Processor Graphics Gen9, v1.0"
* Gen9.5: https://en.wikichip.org/wiki/intel/microarchitectures/gen9.5#Configuration
*/ */
struct topology_i* get_topology_info(struct uarch* arch) { struct topology_i* get_topology_info(struct uarch* arch) {
struct topology_i* topo = (struct topology_i*) emalloc(sizeof(struct topology_i)); struct topology_i* topo = (struct topology_i*) emalloc(sizeof(struct topology_i));
@@ -166,13 +176,16 @@ struct topology_i* get_topology_info(struct uarch* arch) {
// Syntax: (EU per subslice, Subslices, Slices) // Syntax: (EU per subslice, Subslices, Slices)
CHECK_TOPO_START CHECK_TOPO_START
// Gen6 // Gen6
// CHECK_TOPO(topo, arch, UARCH_GEN6, GT1, 6, 1, 1) CHECK_TOPO(topo, arch, UARCH_GEN6, GT1, 6, 1, 1)
CHECK_TOPO(topo, arch, UARCH_GEN6, GT2, 6, 2, 1)
// Gen7 // Gen7
// CHECK_TOPO(topo, arch, UARCH_GEN7, GT1, 6, 2, 1) CHECK_TOPO(topo, arch, UARCH_GEN7, GT1, 6, 1, 1)
CHECK_TOPO(topo, arch, UARCH_GEN7, GT2, 8, 2, 1)
CHECK_TOPO(topo, arch, UARCH_GEN7, GT3, 6, 1, 1)
// Gen7.5 // Gen7.5
CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT1, 6, 1, 1) CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT1, 10, 1, 1)
CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT2, 8, 2, 1) CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT2, 10, 2, 1)
CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT3, 6, 1, 1) CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT3, 10, 4, 1)
// Gen8 // Gen8
CHECK_TOPO(topo, arch, UARCH_GEN8, GT1, 6, 2, 1) CHECK_TOPO(topo, arch, UARCH_GEN8, GT1, 6, 2, 1)
CHECK_TOPO(topo, arch, UARCH_GEN8, GT2, 8, 3, 1) CHECK_TOPO(topo, arch, UARCH_GEN8, GT2, 8, 3, 1)