1404 lines
180 KiB
C
1404 lines
180 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
#ifndef __ga102_dev_se_seb_h__
|
|
#define __ga102_dev_se_seb_h__
|
|
/* This file is autogenerated. Do not edit */
|
|
#define NV_SSE 0xffff:0x0000 /* RW--D */
|
|
#define NV_SSE_SE_PKA_ADDR_OFFSET 0x4000
|
|
#define NV_SSE_SE_PKA_BANK_START_A_OFFSET 0x400;
|
|
#define NV_SSE_SE_PKA_BANK_START_B_OFFSET 0x800;
|
|
#define NV_SSE_SE_PKA_BANK_START_C_OFFSET 0xC00;
|
|
#define NV_SSE_SE_PKA_BANK_START_D_OFFSET 0x1000;
|
|
#define NV_SSE_SE_SWITCH_KFUSE_ADDR_START 0x00003000
|
|
#define NV_SSE_SE_SWITCH_KFUSE_ADDR_END 0x000030fc
|
|
#define NV_SSE_SE_SWITCH_BSI_ADDR_START 0x00008100
|
|
#define NV_SSE_SE_SWITCH_BSI_ADDR_END 0x000088fc
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ADDR_START 0x00008e00
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ADDR_END 0x00008ffc
|
|
#define NV_SSE_SE_SWITCH_DISP_ADDR_START 0x00009000
|
|
#define NV_SSE_SE_SWITCH_DISP_ADDR_END 0x0000d1fc
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK 0x00000000 /* RWE4R */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 2:0 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "opt_secure_se_control_secure" /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x00000007 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 3:3 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 6:4 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_se_control_secure" /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x00000007 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 7:7 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK 0x00000004 /* RWE4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION 2:0 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "opt_secure_se_control_secure" /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x00000007 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION 3:3 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION 6:4 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_se_control_secure" /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x00000007 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION 7:7 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK 0x00000008 /* RWE4R */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION 2:0 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DEFAULT 0x00000006 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION 3:3 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION 6:4 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DEFAULT 0x00000006 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION 7:7 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK(i) (0x0000000c+(4*i)) /* RWE4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION 2:0 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "opt_secure_se_control_secure" /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x00000007 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION 3:3 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION 6:4 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_se_control_secure" /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x00000007 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION 7:7 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK 0x000031a0 /* RWE4R */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK__PROT_PLVL /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION 2:0 /* RWEVF */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RWE-V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION 3:3 /* RWEVF */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 6:4 /* RWEVF */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RWE-V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 7:7 /* RWEVF */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET 0x00000100 /* RW-4R */
|
|
#define NV_SSE_SE_CTRL_RESET__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_RESET__PROT_PMTX /* */
|
|
#define NV_SSE_SE_CTRL_RESET_SE_SOFT_RESET 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_RESET_SE_SOFT_RESET_TRIGGER 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_SE_SOFT_RESET_DONE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_RESET_TRNG_RESET 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_RESET_TRNG_RESET_TRIGGER 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_TRNG_RESET_DONE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_RESET_ZEROIZE_TRNG 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_RESET_ZEROIZE_TRNG_TRIGGER 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_RESET_ZEROIZE_TRNG_DONE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_RESET__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_CTRL_CONTROL 0x00000104 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_CONTROL__PROT_PMTX /* */
|
|
#define NV_SSE_SE_CTRL_CONTROL_AUTORESEED 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_AUTORESEED_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_AUTORESEED_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_LOAD_KEY 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_LOAD_KEY_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_LOAD_KEY_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_SCRUB_PKA_MEM 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_SCRUB_PKA_MEM_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_SCRUB_PKA_MEM_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_KEYSLOT 19:16 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_KEYSLOT_0 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_KEYSLOT_1 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_KEYSLOT_2 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_KEYSLOT_3 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL 0x00000108 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL__PROT_PMTX /* */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_PARTIAL_RADIX 7:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_PARTIAL_RADIX_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_BASE_RADIX 10:8 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_BASE_RADIX_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_BASE_RADIX_256 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_BASE_RADIX_512 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_BASE_RADIX_1024 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_BASE_RADIX_2048 0x00000005 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_BASE_RADIX_4096 0x00000006 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_M521_MODE 20:16 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_M521_MODE_ENABLE 0x00000009 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_M521_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_STOP_RQST 27:27 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_STOP_RQST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_STOP_RQST_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_GO 31:31 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_GO_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_CTRL_GO_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_STATUS 0x0000010c /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_STATUS_SE_STATUS 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_STATUS_SE_STATUS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SE_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_PKA_STATUS 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_STATUS_PKA_STATUS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_STATUS_PKA_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_TRNG_STATUS 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_STATUS_TRNG_STATUS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_STATUS_TRNG_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_CTRL_STATUS 5:4 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_STATUS_CTRL_STATUS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_STATUS_CTRL_STATUS_LOAD 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_CTRL_STATUS_WAIT 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_CTRL_STATUS_SCRUB 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS 11:8 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS_KEY_ATUO_LOAD_SCRUB 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS_MUTEX_RELEASE_SCRUB 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS_REG_TRIGGER_SCRUB 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS_PKA_MUTEX_TIMEOUT_SCRUB 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS_KEYSLOT_MUTEX_TIMEOUT_SCRUB 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_SCRUB_STATUS_CLP300_RESET_SCRUB 0x00000006 /* R---V */
|
|
#define NV_SSE_SE_CTRL_STATUS_CG_STATUS 31:31 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_STATUS_CG_STATUS_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_STATUS_CG_STATUS_BUSY 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_WDTMR 0x00000110 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_WDTMR__PROT_PMTX /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_WDTMR_VAL 31:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_WDTMR_VAL_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX 0x00000114 /* RW-4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_SE_LOCK 0:0 /* RWXVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_SE_LOCK_RELEASE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_VAL 0:0 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_VAL_SUCCESS 1 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_VAL_FAIL 0 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON 31:24 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_SCRUBBING 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER 27:24 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_PMU 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_TZSECURE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_NVDEC 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_NVSECURE 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_SEC 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_NVTZSECURE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_OEMSECURE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_DPU 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_NONSECURE 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_MASTER_PRIV 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL 29:28 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_0 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_NONSECURE 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_1 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_TZSECURE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_2 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_NVSECURE 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_3 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_NVTZSECURE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_REASON_LEVEL_OEMSECURE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_SUCCESS 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_SCRUBBING 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_PMU 0x01000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_TZSECURE 0x11000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_NVDEC 0x02000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_NVSECURE 0x22000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_SEC 0x03000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_NVTZSECURE 0x33000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_OEMSECURE 0x33000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_DPU 0x04000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_NONSECURE 0x04000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RC_FAIL_PRIV 0x05000000 /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RELEASE 0x00000118 /* RW-4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RELEASE__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RELEASE_SE_LOCK 0:0 /* RWXVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RELEASE_SE_LOCK_RELEASE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RELEASE__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS 0x0000011c /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED 7:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_PMU 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_TZSECURE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_NVDEC 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_NVSECURE 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_SEC 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_NVTZSECURE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_OEMSECURE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_DPU 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_NONSECURE 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_LOCKED_PRIV 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_TMOUT 8:8 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_TMOUT_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_STATUS_TMOUT_TRUE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_TMOUT 0x00000120 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_TMOUT__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_TMOUT_VAL 31:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_TMOUT_VAL_INIT 0x00000100 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_TMOUT__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_RESET_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS 0x00000124 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_COUNTER 19:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_COUNTER_TIMEOUT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER 27:20 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_NONE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_PMU 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_TZSECURE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_NVDEC 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_NVSECURE 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_SEC 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_NVTZSECURE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_DPU 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_NONSECURE 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_CUR_MASTER_PRIV 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_PND_NUM 31:28 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_RR_STATUS_PND_NUM_NONE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION 0x00000128 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION__PROT_PMTX /* */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_INTERRUPT 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_INTERRUPT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_INTERRUPT_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_RELEASE_MUTEX 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_RELEASE_MUTEX_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_RELEASE_MUTEX_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_RESET_PKA 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_RESET_PKA_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_RESET_PKA_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_STATUS 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_STATUS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_PKA_MUTEX_TMOUT_ACTION_STATUS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL 0x0000012c /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL__PROT_PMTX /* */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL_DPA_DISABLE 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL_DPA_DISABLE_SET 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL_DPA_DISABLE_UNSET 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_INTERNAL_STATUS 0x00000130 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_INTERNAL_STATUS_TRNG_IRQ 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_INTERNAL_STATUS_TRNG_IRQ_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_INTERNAL_STATUS_TRNG_IRQ_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_INTERNAL_STATUS_TRNG_SECURE 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_INTERNAL_STATUS_TRNG_SECURE_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_INTERNAL_STATUS_TRNG_SECURE_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE 0x00000134 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO 7:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_SUCCESS 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_MB_MUTEX_VIOLATION 0x00000081 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_MB_MASTER_VIOLATION 0x00000082 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_MB_LEVEL_VIOLATION 0x00000083 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_OPERAND_MEM_VIOLATION 0x00000084 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_KS_MASTER_VIOLATION 0x00000085 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_KS_PRIVILEGE_VIOLATION 0x00000086 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_KS_MODE_VIOLATION 0x00000087 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_KSLT_READ_LOCK 0x00000088 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_KSLT_WRITE_LOCK 0x00000089 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_KSLT_OWNER_MIS 0x0000008a /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_TZSEC_MODE_VIO 0x0000008b /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_OTHER_SPEC_VIO 0x0000008c /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_ENG_DIS_VIO 0x0000008d /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_KSLT_USE_VIO 0x0000008e /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_DMA_LOAD_VIO 0x0000008f /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_SEC_BUS_SWCH_READ_VIOLATION 0x000000f0 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_SEC_BUS_SWCH_WRITE_VIOLATION 0x000000f1 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_SEC_BUS_SWCH_ADDRESS_HOLE 0x000000f2 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_INFO_SEC_BUS_SWCH_TIMEOUT 0x000000f3 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_BIT 16:16 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_BIT_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ERROR_BIT_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_PKA_MUTEX_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_CTRL_CG 0x00000138 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_ENABLE_SLCG 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_DISABLE_SLCG 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PMU 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PMU__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PMU_ENABLE_SLCG 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PMU_DISABLE_SLCG 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_NVDEC 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_NVDEC__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_NVDEC_ENABLE_SLCG 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_NVDEC_DISABLE_SLCG 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_SEC 3:3 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_SEC__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_SEC_ENABLE_SLCG 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_SEC_DISABLE_SLCG 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_DPU 4:4 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_DPU__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_DPU_ENABLE_SLCG 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_DPU_DISABLE_SLCG 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PRIV 5:5 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PRIV__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PRIV_ENABLE_SLCG 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_ON_PRIV_DISABLE_SLCG 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_DELAY_CNT 15:6 /* R--VF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF 16:16 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_ENABLE_CND 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_DISABLE_CND 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PMU 17:17 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PMU__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PMU_ENABLE_CND 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PMU_DISABLE_CND 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_NVDEC 18:18 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_NVDEC__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_NVDEC_ENABLE_CND 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_NVDEC_DISABLE_CND 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_SEC 19:19 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_SEC__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_SEC_ENABLE_CND 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_SEC_DISABLE_CND 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_DPU 20:20 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_DPU__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_DPU_ENABLE_CND 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_DPU_DISABLE_CND 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PRIV 21:21 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PRIV__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PRIV_ENABLE_CND 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_OVR_OFF_PRIV_DISABLE_CND 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CG_ITF_OVR_ON 22:22 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CG_ITF_OVR_ON__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_ITF_OVR_ON_ENABLE_SLCG 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_ITF_OVR_ON_DISABLE_SLCG 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_DELAY_INIT 31:23 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_CG_SE_DELAY_INIT__PROD 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_CG_SE_DELAY_INIT_DEFAULT 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS 0x0000013c /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_EIP0 8:8 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_EIP0_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_EIP0_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_EIP1 9:9 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_EIP1_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_EIP1_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_ERROR 16:16 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_ERROR_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_ERROR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_MUTEX_TMOUT 17:17 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_MUTEX_TMOUT_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_STATUS_MUTEX_TMOUT_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK 0x00000140 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK__PROT_PMTX /* */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_EIP0 8:8 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_EIP0_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_EIP0_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_EIP1 9:9 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_EIP1_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_EIP1_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ERROR 16:16 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ERROR_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ERROR_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_MUTEX_TMOUT 17:17 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_MUTEX_TMOUT_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_MUTEX_TMOUT_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SE_MUTEX_TMOUT_DFTVAL 0x00000144 /* RWI4R */
|
|
#define NV_SSE_SE_CTRL_SE_MUTEX_TMOUT_DFTVAL__PROT_SPEC /* */
|
|
#define NV_SSE_SE_CTRL_SE_MUTEX_TMOUT_DFTVAL_TMOUT 31:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_SE_MUTEX_TMOUT_DFTVAL_TMOUT_MAX 0xffffffff /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_SE_VERSION 0x00000148 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_SE_VERSION_MAJOR 7:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_VERSION_MAJOR_1 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_VERSION_MINOR 15:8 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_VERSION_MINOR_0 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS 0x00000600 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_AUTORESEED 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_AUTORESEED_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_AUTORESEED_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_LOAD_KEY 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_LOAD_KEY_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_LOAD_KEY_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_SCRUB_PKA_MEM 3:3 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_SCRUB_PKA_MEM_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_SCRUB_PKA_MEM_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_KEYSLOT 19:16 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_KEYSLOT_0 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_KEYSLOT_1 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_KEYSLOT_2 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_CONTROL_ALIAS_KEYSLOT_3 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS 0x00000604 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_PARTIAL_RADIX 7:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_PARTIAL_RADIX_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_BASE_RADIX 10:8 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_BASE_RADIX_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_BASE_RADIX_256 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_BASE_RADIX_512 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_BASE_RADIX_1024 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_BASE_RADIX_2048 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_BASE_RADIX_4096 0x00000006 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_M521_MODE 20:16 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_M521_MODE_ENABLE 0x00000009 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_M521_MODE_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_STOP_RQST 27:27 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_STOP_RQST_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_STOP_RQST_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_GO 31:31 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_GO_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_PKA_CONTROL_ALIAS_CTRL_GO_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS 0x00000608 /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_NONCE_MODE 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_NONCE_MODE_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_NONCE_MODE_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_SECURE_EN 8:8 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_SECURE_EN_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_SECURE_EN_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_MAX_REJECTS 23:16 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_SMODE_ALIAS_MAX_REJECTS_10 0x0000000a /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS 0x0000060c /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_RAND_RDY_EN 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_RAND_RDY_EN_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_RAND_RDY_EN_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_SEED_DONE_EN 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_SEED_DONE_EN_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_SEED_DONE_EN_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_AGE_ALARM_EN 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_AGE_ALARM_EN_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_AGE_ALARM_EN_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_RQST_ALARM_EN 3:3 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_RQST_ALARM_EN_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_RQST_ALARM_EN_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_GLBL_EN 31:31 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_GLBL_EN_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_IE_ALIAS_GLBL_EN_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS 0x00000610 /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_RAND_RDY 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_RAND_RDY_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_RAND_RDY_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_SEED_DONE 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_SEED_DONE_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_SEED_DONE_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_AGE_ALARM 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_AGE_ALARM_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_AGE_ALARM_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_RQST_ALARM 3:3 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_RQST_ALARM_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_ALIAS_RQST_ALARM_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST_ALIAS 0x00000614 /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST_ALIAS_RQSTS 15:0 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST_ALIAS_RQSTS_MAX 0x0000ffff /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST_ALIAS_RQSTS_DISABLE 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE_ALIAS 0x00000618 /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE_ALIAS_AGE 15:0 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE_ALIAS_AGE_MAX 0x0000ffff /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE_ALIAS_AGE_DISABLE 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS 0x0000061c /* R-I4R */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR 11:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_CLEAR 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_BIT_SERIAL_MOD 0x00000018 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_BIT_SERIAL_MOD_DP 0x00000017 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_CALC_MP 0x00000010 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_CALC_R_INV 0x00000011 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_CALC_R_SQR 0x00000012 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_CRT 0x00000016 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_CRT_KEY_SETUP 0x00000015 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_ERR_CHKS 0x00000013 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_IS_A_M3 0x00000022 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_IS_P_EQUAL_Q 0x00000020 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_IS_P_REFLECT_Q 0x00000021 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_MODADD 0x0000000b /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_MODDIV 0x0000000d /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_MODEXP 0x00000014 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_MODINV 0x0000000e /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_MODMULT 0x0000000a /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_MODSUB 0x0000000c /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_PADD 0x0000001c /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_PADD_STD_PRJ 0x0000001d /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_PDBL 0x0000001a /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_PDBL_STD_PRJ 0x0000001b /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_PMULT 0x00000019 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_PVER 0x0000001e /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_REDUCE 0x0000000f /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_SHAMIR 0x00000023 /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_STD_PRJ_TO_AFFINE 0x0000001f /* R---V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_ALIAS_PROG_ADDR_TESTOP 0x00000024 /* R---V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_ALIAS 0x00000620 /* R-I4R */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_ALIAS_CFG_DPA_ALT_ACCESS 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_ALIAS_CFG_DPA_ALT_ACCESS_NORMAL_C_MEMORY_ACCESS 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_ALIAS_CFG_DPA_ALT_ACCESS_SWITCH_C_MEMORY_ACCESS 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_ALIAS_CFG_ENDIAN_BYTE_SWAP 26:26 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_ALIAS_CFG_ENDIAN_BYTE_SWAP_LITTEL_ENDIAN 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_ALIAS_CFG_ENDIAN_BYTE_SWAP_BIG_ENDIAN 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_STATUS_ALIAS 0x00000624 /* R-I4R */
|
|
#define NV_SSE_SE_PKA_STATUS_ALIAS_STAT_IRQ 30:30 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_STATUS_ALIAS_STAT_IRQ_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_STATUS_ALIAS_STAT_IRQ_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_WATCHDOG_ALIAS 0x00000628 /* R-I4R */
|
|
#define NV_SSE_SE_PKA_WATCHDOG_ALIAS_INSTRUCTIONS_UNTIL_HALT 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_WATCHDOG_ALIAS_INSTRUCTIONS_UNTIL_HALT_MAX 0xffffffff /* R-I-V */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE_ALIAS 0x0000062c /* R-I4R */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE_ALIAS_IE_IRQ_EN 30:30 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE_ALIAS_IE_IRQ_EN_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE_ALIAS_IE_IRQ_EN_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL_ALIAS 0x00000630 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL_ALIAS_DPA_DISABLE 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL_ALIAS_DPA_DISABLE_SET 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SCC_CONTROL_ALIAS_DPA_DISABLE_UNSET 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS 0x00000634 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO 7:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_SUCCESS 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_MB_MUTEX_VIOLATION 0x00000081 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_MB_MASTER_VIOLATION 0x00000082 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_MB_LEVEL_VIOLATION 0x00000083 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_OPERAND_MEM_VIOLATION 0x00000084 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_KS_MASTER_VIOLATION 0x00000085 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_KS_PRIVILEGE_VIOLATION 0x00000086 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_KS_MODE_VIOLATION 0x00000087 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_KSLT_READ_LOCK 0x00000088 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_KSLT_WRITE_LOCK 0x00000089 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_KSLT_OWNER_MIS 0x0000008a /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_TZSEC_MODE_VIO 0x0000008b /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_OTHER_SPEC_VIO 0x0000008c /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_ENG_DIS_VIO 0x0000008d /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_KSLT_USE_VIO 0x0000008e /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_INFO_DMA_LOAD_VIO 0x0000008f /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_BIT 16:16 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_BIT_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_ERROR_CAPTURE_ALIAS_ERROR_BIT_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS 0x00000638 /* R-I4R */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_EIP0 8:8 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_EIP0_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_EIP0_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_EIP1 9:9 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_EIP1_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_EIP1_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_ERROR 16:16 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_ERROR_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_ERROR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_MUTEX_TMOUT 17:17 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_MUTEX_TMOUT_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_SE_INTR_MASK_ALIAS_MUTEX_TMOUT_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR(i) (0x00000800+(i)*4) /* RWI4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR__PROT_KMTX /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_WORD_ADDR 6:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_WORD_ADDR_ZERO 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD 11:8 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_RSA_EXPONENT 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_RSA_MODULUS 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_RSA_M_SPECIAL 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_RSA_R_SQUARE 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_A 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_B 0x00000005 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_P 0x00000006 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_N 0x00000007 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_XP 0x00000008 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_YP 0x00000009 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_XQ 0x0000000a /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_YQ 0x0000000b /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_K 0x0000000c /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_P_SPECIAL 0x0000000d /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_FIELD_ECC_R_SQUARE 0x0000000e /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_AINC 31:31 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_AINC_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_ADDR_AINC_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_DATA(i) (0x00000810+(i)*4) /* RW-4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_DATA__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_DATA__PROT_KMTX /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_DATA_DATA 31:0 /* RWXVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX(i) (0x00000820+(i)*4) /* RW-4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX__PROT_PLVL /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_MUTEX 0:0 /* RW-VF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_MUTEX_RELEASE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_VAL 0:0 /* RW-VF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_VAL_SUCCESS 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_VAL_FAIL 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON 31:24 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_SCRUBBING 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_MASTER 27:24 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_MASTER_PMU 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_MASTER_NVDEC 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_MASTER_SEC 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_MASTER_DPU 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_MASTER_PRIV 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_LEVEL 29:28 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_LEVEL_0 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_LEVEL_1 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_LEVEL_2 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_REASON_LEVEL_3 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_SUCCESS 0x00000001 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_FAIL_SCRUBBING 0x00000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_FAIL_PMU 0x01000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_FAIL_NVDEC 0x02000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_FAIL_SEC 0x03000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_FAIL_DPU 0x04000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_RC_FAIL_PRIV 0x05000000 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_KSLT_MUTEX_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS(i) (0x00000830+(i)*4) /* RWI4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_LOCKED 7:0 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_LOCKED_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_LOCKED_PMU 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_LOCKED_NVDEC 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_LOCKED_SEC 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_LOCKED_DPU 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_LOCKED_PRIV 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_TMOUT 8:8 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_TMOUT_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_STATUS_TMOUT_TRUE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_WDTMR(i) (0x00000840+(i)*4) /* RWI4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_WDTMR__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_WDTMR__PROT_KMTX /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_WDTMR_VAL 31:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_WDTMR_VAL_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION(i) (0x00000850+(i)*4) /* RWI4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION__PROT_KMTX /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_INTERRUPT 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_INTERRUPT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_INTERRUPT_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_RELEASE_MUTEX 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_RELEASE_MUTEX_ENABLE 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_STATUS 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_STATUS_TRUE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MUTEX_TMOUT_ACTION_STATUS_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER(i) (0x00000860+(i)*4) /* RWE4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER__PROT_KMTX /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_PMU 0:0 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_PMU_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_PMU_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_NVDEC 1:1 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_NVDEC_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_NVDEC_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_SEC 2:2 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_SEC_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_SEC_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_DPU 3:3 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_DPU_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_DPU_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_PRIV 4:4 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_PRIV_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MASTER_PRIV_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE(i) (0x00000870+(i)*4) /* RWE4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE__PROT_KMTX /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL0 0:0 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL0_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL0_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL1 1:1 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL1_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL1_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL2 2:2 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL2_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_PRIVILEGE_LEVEL2_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MODE(i) (0x00000880+(i)*4) /* RWE4A */
|
|
#define NV_SSE_SE_CTRL_KSLT_MODE__SIZE_1 4 /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MODE__PROT_KMTX /* */
|
|
#define NV_SSE_SE_CTRL_KSLT_MODE_DEBUG_MODE 0:0 /* RWEVF */
|
|
#define NV_SSE_SE_CTRL_KSLT_MODE_DEBUG_MODE_ENABLED 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_CTRL_KSLT_MODE_DEBUG_MODE_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_CTRL 0x00003f00 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_CTRL__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_CTRL_CMD 2:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_CTRL_CMD_NOP 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_CTRL_CMD_GEN_RAN_NUM 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_CTRL_CMD_RAN_RESEED 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_CTRL_CMD_NONCE_RESEED 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_STATUS 0x00003f04 /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_STATUS_NONCE_MODE 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_NONCE_MODE_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_NONCE_MODE_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_STATUS_R256 3:3 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_R256_ENABLE 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_STATUS_R256_DISABLE 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_SECURE 8:8 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_SECURE_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_SECURE_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_STATUS_SEEDED 9:9 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_SEEDED_ENABLE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_SEEDED_DISABLE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_STATUS_LAST_RESEED 18:16 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_LAST_RESEED_BY_HOST 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_LAST_RESEED_BY_NONCE 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_LAST_RESEED_BY_I_RESEED 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_LAST_RESEED_UNSEEDED 0x00000007 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_STATUS_SRVC_RQST 27:27 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_SRVC_RQST_HAVE_REQUEST 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_SRVC_RQST_NO_REQUEST 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_STATUS_RAND_GENERATING 30:30 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_RAND_GENERATING_IN_PROGRESS 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_RAND_GENERATING_NO_PROGRESS 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_STATUS_RAND_RESEEDING 31:31 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_STATUS_RAND_RESEEDING_IN_PROGRESS 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_STATUS_RAND_RESEEDING_NO_PROGRESS 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_MODE 0x00003f08 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_MODE__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_MODE_R256 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_MODE_R256_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_MODE_R256_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_SMODE 0x00003f0c /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_SMODE__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_SMODE_NONCE_MODE 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_SMODE_NONCE_MODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_SMODE_NONCE_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_SMODE_SECURE_EN 8:8 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_SMODE_SECURE_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_SMODE_SECURE_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_SMODE_MAX_REJECTS 23:16 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_SMODE_MAX_REJECTS_10 0x0000000a /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IE 0x00003f10 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_IE__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_IE_RAND_RDY_EN 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IE_RAND_RDY_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IE_RAND_RDY_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IE_SEED_DONE_EN 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IE_SEED_DONE_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IE_SEED_DONE_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IE_AGE_ALARM_EN 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IE_AGE_ALARM_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IE_AGE_ALARM_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IE_RQST_ALARM_EN 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IE_RQST_ALARM_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IE_RQST_ALARM_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IE_GLBL_EN 31:31 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IE_GLBL_EN_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IE_GLBL_EN_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT 0x00003f14 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_ISTAT__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_ISTAT_RAND_RDY 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_RAND_RDY_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_RAND_RDY_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_SEED_DONE 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_SEED_DONE_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_SEED_DONE_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_AGE_ALARM 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_AGE_ALARM_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_AGE_ALARM_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_RQST_ALARM 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_ISTAT_RQST_ALARM_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_ISTAT_RQST_ALARM_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_COREKIT_REL 0x00003f18 /* R--4R */
|
|
#define NV_SSE_SE_TRNG_COREKIT_REL_REL_NUM 15:0 /* R--VF */
|
|
#define NV_SSE_SE_TRNG_COREKIT_REL_REL_NUM_VAL 0x0000200a /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_COREKIT_REL_EXT_VER 23:16 /* R--VF */
|
|
#define NV_SSE_SE_TRNG_COREKIT_REL_EXT_VER_VAL 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_COREKIT_REL_EXT_ENUM 31:28 /* R--VF */
|
|
#define NV_SSE_SE_TRNG_COREKIT_REL_EXT_ENUM_VAL 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_FEATURES 0x00003f1c /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_FEATURES_MAX_RAND_LENGTH 1:0 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_FEATURES_MAX_RAND_LENGTH_128 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_TRNG_FEATURES_MAX_RAND_LENGTH_256 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_FEATURES_RAND_SEED_AVAIL 2:2 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_FEATURES_RAND_SEED_AVAIL_PRNG_ONLY 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_TRNG_FEATURES_RAND_SEED_AVAIL_FULL_TRNG 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_FEATURES_SECURE_RST_STATE 3:3 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_FEATURES_SECURE_RST_STATE_PROMISCUOUS 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_FEATURES_SECURE_RST_STATE_SECURE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_TRNG_FEATURES_DIAG_LEVEL 6:4 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_FEATURES_DIAG_LEVEL_0 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_FEATURES_RESERVED 31:7 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_FEATURES_RESERVED_CLEAR 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_RAND(i) (0x00003f20+(i)*4) /* R-I4A */
|
|
#define NV_SSE_SE_TRNG_RAND__SIZE_1 8 /* */
|
|
#define NV_SSE_SE_TRNG_RAND__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_RAND_RAND 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_RAND_RAND_CLEAR 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_SEED(i) (0x00003f40+(i)*4) /* RWI4A */
|
|
#define NV_SSE_SE_TRNG_SEED__SIZE_1 8 /* */
|
|
#define NV_SSE_SE_TRNG_SEED__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_SEED_SEED 31:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_SEED_SEED_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST 0x00003f60 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST_RQSTS 15:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST_RQSTS_MAX 0x0000ffff /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_AUTO_RQST_RQSTS_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE 0x00003f64 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE_AGE 15:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE_AGE_MAX 0x0000ffff /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_AUTO_AGE_AGE_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IA_RDATA 0x00003f70 /* R-I4R */
|
|
#define NV_SSE_SE_TRNG_IA_RDATA__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_IA_RDATA_RDATA 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_TRNG_IA_RDATA_RDATA_CLEAR 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_TRNG_IA_WDATA 0x00003f74 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_IA_WDATA__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_IA_WDATA_WDATA 31:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IA_WDATA_WDATA_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IA_ADDR 0x00003f78 /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_IA_ADDR__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_IA_ADDR_ADDR 8:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IA_ADDR_ADDR_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IA_CMD 0x00003f7c /* RWI4R */
|
|
#define NV_SSE_SE_TRNG_IA_CMD__PROT_PMTX /* */
|
|
#define NV_SSE_SE_TRNG_IA_CMD_W_NR 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IA_CMD_W_NR_READ 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_TRNG_IA_CMD_W_NR_WRITE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IA_CMD_GO 31:31 /* RWIVF */
|
|
#define NV_SSE_SE_TRNG_IA_CMD_GO_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_TRNG_IA_CMD_GO_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONTROL 0x00004000 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_CONTROL__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_PARTIAL_RADIX 7:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_PARTIAL_RADIX_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_BASE_RADIX 10:8 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_BASE_RADIX_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_BASE_RADIX_256 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_BASE_RADIX_512 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_BASE_RADIX_1024 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_BASE_RADIX_2048 0x00000005 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_BASE_RADIX_4096 0x00000006 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_M521_MODE 20:16 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_M521_MODE_ENABLE 0x00000009 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_M521_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_STOP_RQST 27:27 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_STOP_RQST_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_STOP_RQST_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_GO 31:31 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_GO_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONTROL_CTRL_GO_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS 0x00004004 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR 11:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_BIT_SERIAL_MOD 0x00000018 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_BIT_SERIAL_MOD_DP 0x00000017 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_CALC_MP 0x00000010 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_CALC_R_INV 0x00000011 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_CALC_R_SQR 0x00000012 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_CRT 0x00000016 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_CRT_KEY_SETUP 0x00000015 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_ERR_CHKS 0x00000013 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_IS_A_M3 0x00000022 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_IS_P_EQUAL_Q 0x00000020 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_IS_P_REFLECT_Q 0x00000021 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_MODADD 0x0000000b /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_MODDIV 0x0000000d /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_MODEXP 0x00000014 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_MODINV 0x0000000e /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_MODMULT 0x0000000a /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_MODSUB 0x0000000c /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_PADD 0x0000001c /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_PADD_STD_PRJ 0x0000001d /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_PDBL 0x0000001a /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_PDBL_STD_PRJ 0x0000001b /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_PMULT 0x00000019 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_PVER 0x0000001e /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_REDUCE 0x0000000f /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_SHAMIR 0x00000023 /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_STD_PRJ_TO_AFFINE 0x0000001f /* RW--V */
|
|
#define NV_SSE_SE_PKA_PROGRAM_ENTRY_ADDRESS_PROG_ADDR_TESTOP 0x00000024 /* RW--V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE 0x00004008 /* R-I4R */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON 23:16 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_NORMAL 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_INVALID_OPCODE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_F_STACK_UNDERFLOW 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_F_STACK_OVERFLOW 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_WATCHDOG 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_HOST_REQUEST 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_P_STACK_UNDERFLOW 0x00000006 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_P_STACK_OVERFLOW 0x00000007 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_MEM_PORT_COLLISION 0x00000008 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_STOP_REASON_OPERATION_SIZE_EXCEED_CFG 0x00000009 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_ZERO 28:28 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_ZERO_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_ZERO_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_WR_PENDING 29:29 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_WR_PENDING_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_WR_PENDING_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_IRQ 30:30 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_IRQ_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_IRQ_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_BUSY 31:31 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_BUSY_SET 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_RETURN_CODE_RC_BUSY_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION 0x0000400c /* R-I4R */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_A 1:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_A_1 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_A_2 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_A_4 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_B 3:2 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_B_1 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_B_2 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_B_4 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_C 5:4 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_C_1 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_C_2 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_C_4 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_D 7:6 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_D_1 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_D_2 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_BANK_SW_D_4 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_RAM 10:8 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_RAM_256_WORDS 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_RAM_512_WORDS 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_RAM_1024_WORDS 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_RAM_4096_WORDS 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_RAM_0_WORDS 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_RAM_2048_WORDS 0x00000004 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_ROM 13:11 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_ROM_256_WORDS 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_ROM_512_WORDS 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_ROM_1024_WORDS 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_ROM_2048_WORDS 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_ROM_0_WORDS 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FW_ROM_4096_WORDS 0x00000005 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ECC_SIZE 15:14 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ECC_SIZE_0 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ECC_SIZE_256 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ECC_SIZE_512 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ECC_SIZE_1024 0x00000003 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_RSA_SIZE 18:16 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_RSA_SIZE_0 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_RSA_SIZE_512 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_RSA_SIZE_1024 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_RSA_SIZE_2048 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_RSA_SIZE_4096 0x00000004 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ALU_SIZE 20:19 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ALU_SIZE_32 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ALU_SIZE_64 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ALU_SIZE_128 0x00000002 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_ALU_SIZE_256 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FORMAT_TYPE 31:30 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FORMAT_TYPE_0 0x00000000 /* R---V */
|
|
#define NV_SSE_SE_PKA_BUILD_CONFIGURATION_BC_FORMAT_TYPE_1 0x00000001 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_FUNCTION_STACK_POINT 0x00004010 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_FUNCTION_STACK_POINT__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_FUNCTION_STACK_POINT_FSTACK_POINTER 3:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FUNCTION_STACK_POINT_FSTACK_POINTER_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_INSTRUCTIONS_SINCE_GO 0x00004014 /* R-I4R */
|
|
#define NV_SSE_SE_PKA_INSTRUCTIONS_SINCE_GO__PROT_PLVL /* */
|
|
#define NV_SSE_SE_PKA_INSTRUCTIONS_SINCE_GO_INSTRUCTIONS_SINCE_GO 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_INSTRUCTIONS_SINCE_GO_INSTRUCTIONS_SINCE_GO_CLEAR 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_INSTRUCTIONS_SINCE_GO__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_PKA_PARAMETER_STACK_POINT 0x00004018 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_PARAMETER_STACK_POINT__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_PARAMETER_STACK_POINT_PSTACK_POINTER 5:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_PARAMETER_STACK_POINT_PSTACK_POINTER_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION 0x0000401c /* RWI4R */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_CFG_DPA_ALT_ACCESS 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_CFG_DPA_ALT_ACCESS_NORMAL_C_MEMORY_ACCESS 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_CFG_DPA_ALT_ACCESS_SWITCH_C_MEMORY_ACCESS 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_CFG_ENDIAN_BYTE_SWAP 26:26 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_CFG_ENDIAN_BYTE_SWAP_LITTEL_ENDIAN 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CONFIGURATION_CFG_ENDIAN_BYTE_SWAP_BIG_ENDIAN 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_STATUS 0x00004020 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_STATUS__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_STATUS_STAT_IRQ 30:30 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_STATUS_STAT_IRQ_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_STATUS_STAT_IRQ_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS 0x00004024 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_FLAGS__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_ZERO 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_ZERO_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_ZERO_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_MEMBIT 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_MEMBIT_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_MEMBIT_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_BORROW 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_BORROW_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_BORROW_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_CARRY 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_CARRY_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_CARRY_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F0 4:4 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F0_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F0_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F1 5:5 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F1_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F1_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F2 6:6 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F2_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F2_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F3 7:7 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F3_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_FLAGS_FLAG_F3_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_WATCHDOG 0x00004028 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_WATCHDOG__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_WATCHDOG_INSTRUCTIONS_UNTIL_HALT 31:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_WATCHDOG_INSTRUCTIONS_UNTIL_HALT_MAX 0xffffffff /* RWI-V */
|
|
#define NV_SSE_SE_PKA_CYCLES_SINCE_GO 0x0000402c /* R-I4R */
|
|
#define NV_SSE_SE_PKA_CYCLES_SINCE_GO__PROT_PLVL /* */
|
|
#define NV_SSE_SE_PKA_CYCLES_SINCE_GO_CYCLES_SINCE_GO 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKA_CYCLES_SINCE_GO_CYCLES_SINCE_GO_CLEAR 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKA_CYCLES_SINCE_GO__PRIV_LEVEL_MASK NV_SSE_SE_CTRL_PKA_DEBUG_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_PKA_INDEX_I 0x00004030 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_INDEX_I__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_INDEX_I_INDEX_I 15:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_INDEX_I_INDEX_I_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_INDEX_J 0x00004034 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_INDEX_J__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_INDEX_J_INDEX_J 15:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_INDEX_J_INDEX_J_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_INDEX_K 0x00004038 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_INDEX_K__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_INDEX_K_INDEX_K 15:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_INDEX_K_INDEX_K_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_INDEX_L 0x0000403c /* RWI4R */
|
|
#define NV_SSE_SE_PKA_INDEX_L__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_INDEX_L_INDEX_L 15:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_INDEX_L_INDEX_L_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE 0x00004040 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE_IE_IRQ_EN 30:30 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE_IE_IRQ_EN_SET 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_INTERRUPT_ENABLE_IE_IRQ_EN_UNSET 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_JUMP_PROBABILITY 0x00004044 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_JUMP_PROBABILITY__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_JUMP_PROBABILITY_JUMP_PROBABILITY 12:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_JUMP_PROBABILITY_JUMP_PROBABILITY_MAX 0x00001fff /* RW--V */
|
|
#define NV_SSE_SE_PKA_JUMP_PROBABILITY_JUMP_PROBABILITY_CLEAR 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_PROBABILITY_LFSR_SEED 0x00004048 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_PROBABILITY_LFSR_SEED__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_PROBABILITY_LFSR_SEED_PROBABILITY_LFSR_SEED 12:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_PROBABILITY_LFSR_SEED_PROBABILITY_LFSR_SEED_DEFAULT 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_A 0x00004050 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_A__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_A_BANK_SW_A 1:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_A_BANK_SW_A_BANK_0 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_A_BANK_SW_A_BANK_1 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_A_BANK_SW_A_BANK_2 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_A_BANK_SW_A_BANK_3 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_B 0x00004054 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_B__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_B_BANK_SW_B 1:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_B_BANK_SW_B_BANK_0 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_B_BANK_SW_B_BANK_1 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_B_BANK_SW_B_BANK_2 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_B_BANK_SW_B_BANK_3 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_C 0x00004058 /* RWI4R */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_C__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_C_BANK_SW_C 1:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_C_BANK_SW_C_BANK_0 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_C_BANK_SW_C_BANK_1 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_C_BANK_SW_C_BANK_2 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_C_BANK_SW_C_BANK_3 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_D 0x0000405c /* RWI4R */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_D__PROT_PMTX /* */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_D_BANK_SW_D 1:0 /* RWIVF */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_D_BANK_SW_D_BANK_0 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_D_BANK_SW_D_BANK_1 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_D_BANK_SW_D_BANK_2 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_PKA_BANK_SWITCH_D_BANK_SW_D_BANK_3 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_FUSE_PK_SEL 0x00003100 /* R-I4R */
|
|
#define NV_SSE_SE_FUSE_PK_SEL_LOCATION 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_FUSE_PK_SEL_LOCATION_HW 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_FUSE_PK_SEL_LOCATION_FUSE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_VALUE(i) (0x00003000+(i*4)) /* R-I4A */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_VALUE__SIZE_1 8 /* */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_VALUE_VALUE 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_VALUE_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_VALUE(i) (0x00003020+(i*4)) /* R-I4A */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_VALUE__SIZE_1 2 /* */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_VALUE_VALUE 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_VALUE_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL 0x00003040 /* RWI4R */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_VALID 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_BUSY 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_BUSY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_RELOAD 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_PKEYHASH_AUTOLOAD_CTL_RELOAD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL 0x00003044 /* RWI4R */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_VALID 0:0 /* R-IVF */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_BUSY 1:1 /* R-IVF */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_BUSY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_RELOAD 2:2 /* RWIVF */
|
|
#define NV_SSE_SE_PDI_AUTOLOAD_CTL_RELOAD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_SLAVE_TIMEOUT 0x00003104 /* RWI4R */
|
|
#define NV_SSE_SE_SWITCH_SLAVE_TIMEOUT_MULTI 7:0 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_SLAVE_TIMEOUT_MULTI_DEFAULT 0x00000005 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_SLAVE_TIMEOUT__PRIV_LEVEL_MASK NV_SSE_SE_TIMEOUT_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER 0x00003108 /* R-I4R */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_VALUE 23:0 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_MASTER 31:24 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_MASTER_NO_INFLIGHT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_MASTER_PMU 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_MASTER_NVDEC 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_MASTER_SEC 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_DISP_COUNTER_MASTER_GSP 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER 0x0000310c /* R-I4R */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_VALUE 23:0 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_MASTER 31:24 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_MASTER_NO_INFLIGHT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_MASTER_PMU 0x00000001 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_MASTER_NVDEC 0x00000002 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_MASTER_SEC 0x00000003 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_BSI_COUNTER_MASTER_GSP 0x00000004 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_INFO 0x00003110 /* R-I4R */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_INFO_VALUE 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_INFO_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL 0x00003114 /* RWI4R */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_VALID 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_RW 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_RW_WRITE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_RW_READ 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_MASTER 31:24 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_MASTER_PRIV 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_MASTER_PMU 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_MASTER_NVDEC 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_MASTER_SEC 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_DISP_ERROR_CTRL_MASTER_DPU 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_INFO 0x00003118 /* R-I4R */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_INFO_VALUE 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_INFO_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL 0x0000311c /* RWI4R */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_VALID 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_RW 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_RW_WRITE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_RW_READ 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_MASTER 31:24 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_MASTER_PRIV 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_MASTER_PMU 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_MASTER_NVDEC 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_MASTER_SEC 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_BSI_ERROR_CTRL_MASTER_DPU 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_INFO 0x00003120 /* R-I4R */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_INFO_VALUE 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_INFO_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_INFO_VALUE_ADDR_HOLE 0xbadf5040 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_INFO_VALUE_PLM_ERROR 0xbadf5100 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_INFO_PLM_ERROR_MASK 3:0 /* R--VF */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_INFO_PLM_ERROR_LEVEL 6:4 /* R--VF */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL 0x00003124 /* RWI4R */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_VALID 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_RW 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_RW_WRITE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_RW_READ 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_MASTER 31:24 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_MASTER_PRIV 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_MASTER_PMU 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_MASTER_NVDEC 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_MASTER_SEC 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_CTRL_ERROR_CTRL_MASTER_DPU 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_INFO 0x00003128 /* R-I4R */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_INFO_VALUE 31:0 /* R-IVF */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_INFO_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_INFO_VALUE_ADDR_HOLE 0xbadf5040 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_INFO_VALUE_PLM_ERROR 0xbadf5100 /* R---V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_INFO_PLM_ERROR_MASK 3:0 /* R--VF */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_INFO_PLM_ERROR_LEVEL 6:4 /* R--VF */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL 0x0000312c /* RWI4R */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_VALID 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_RW 1:1 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_RW_WRITE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_RW_READ 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_MASTER 31:24 /* RWIVF */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_MASTER_PRIV 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_MASTER_PMU 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_MASTER_NVDEC 0x00000002 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_MASTER_SEC 0x00000003 /* RW--V */
|
|
#define NV_SSE_SE_SWITCH_MUTEX_ERROR_CTRL_MASTER_DPU 0x00000004 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK 0x00008100 /* RWI4R */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK__PROT_PLVL /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION 2:0 /* RWIVF */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* RWI-V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_VIOLATION 3:3 /* RWIVF */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION 6:4 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x00000007 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* RWIVF */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* RWIVF */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* RWIVF */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_VIOLATION 7:7 /* RWIVF */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_CTL 0x00008130 /* RWI4R */
|
|
#define NV_SSE_SE_VHR_SCRUB_CTL_XVE_RESET 0:0 /* RWIVF */
|
|
#define NV_SSE_SE_VHR_SCRUB_CTL_XVE_RESET_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_SSE_SE_VHR_SCRUB_CTL_XVE_RESET_FALSE 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_VHR_SCRUB_CTL__PRIV_LEVEL_MASK NV_SSE_SE_VHR_SCRUB_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK(i) (0x00008e00+(i)*80) /* RWE4A */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK__SIZE_1 3 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION 2:0 /* RWEVF */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_0_READ_PROTECTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_1_READ_PROTECTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_2_READ_PROTECTION_INIT 0x00000004 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION 3:3 /* RWEVF */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION 6:4 /* RWEVF */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_INIT 0x00000000 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_INIT 0x00000004 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION 7:7 /* RWEVF */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID(i) (0x00008e04+(i)*80) /* R-I4A */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID__SIZE_1 3 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_VALUE 7:0 /* R-IVF */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_VALUE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_VALUE_NOT_AVAIL 0x000000ff /* R---V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID__PRIV_LEVEL_MASK NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_RELEASE(i) (0x00008e08+(i)*80) /* RWI4A */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_RELEASE__SIZE_1 3 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_RELEASE_VALUE 7:0 /* RWIVF */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_RELEASE_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_ID_RELEASE__PRIV_LEVEL_MASK NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_MUTEX(i,j) (0x00008e0c+(i)*80+(j)*4) /* RWI4A */
|
|
#define NV_SSE_SE_COMMON_MUTEX_MUTEX__SIZE_1 3 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_MUTEX__SIZE_2 16 /* */
|
|
#define NV_SSE_SE_COMMON_MUTEX_MUTEX_VALUE 7:0 /* RWIVF */
|
|
#define NV_SSE_SE_COMMON_MUTEX_MUTEX_VALUE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_SSE_SE_COMMON_MUTEX_MUTEX__PRIV_LEVEL_MASK NV_SSE_SE_COMMON_MUTEX_PRIV_LEVEL_MASK /* */
|
|
#endif // __ga102_dev_se_seb_h__
|