5062 lines
656 KiB
C
5062 lines
656 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_fbfalcon_pri_h__
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#define __ga102_dev_fbfalcon_pri_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PFBFALCON 0x009A5FFF:0x009A4000 /* RW--D */
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#define NV_PFBFALCON_LOGGING NV_PFBFALCON_SECURE_WR_SCRATCH(0)
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#define NV_PFBFALCON_LOGGING_MASK 15:0
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#define NV_PFBFALCON_LOGGING_LEVEL 23:16
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#define NV_PFBFALCON_LOGGING_MODE 31:31
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#define NV_PFBFALCON_LOGGING_MODE_ENABLED 0x00000001
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#define NV_PFBFALCON_LOGGING_MODE_DISABLED 0x00000000
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#define NV_PFBFALCON_BOOTTIME_TRAINING_STATUS NV_PFBFALCON_SECURE_WR_SCRATCH(7)
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#define NV_PFBFALCON_BOOTTIME_TRAINING_STATUS_CODE 15:0
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#define NV_PFBFALCON_BOOTTIME_TRAINING_STATUS_CODE_TRAINING_STARTED 0x0001
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#define NV_PFBFALCON_BOOTTIME_TRAINING_STATUS_CODE_TRAINING_COMPLETED 0x0002
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#define NV_PFBFALCON_BOOTTIME_TRAINING_STATUS_CODE_TRAINING_SUCCESS 0x0003
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#define NV_PFBFALCON_BOOTTIME_TRAINING_STATUS_ERROR 31:16
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK 0x009a4280 /* RWI4R */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK 0x009a4284 /* RWI4R */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x009a4288 /* RWI4R */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK 0x009a428c /* RWI4R */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x009a4290 /* RWI4R */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x009a4294 /* RWI4R */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK 0x009a40e8 /* RWI4R */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK 0x009a4298 /* RWI4R */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK 0x009a429c /* RWI4R */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x009a43d0 /* RWI4R */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK 0x009a43c4 /* RWI4R */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x009a43f0 /* RWI4R */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x009a43f4 /* RWI4R */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x009a43f8 /* RWI4R */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x009a43fc /* RWI4R */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x009a418c+(i)*16) /* RW-4A */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x009a42b0+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK 0x009a4190 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x009a4194 /* RW-4R */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK 0x009a4198 /* RW-4R */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x009a419c /* RW-4R */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK 0x009a41a0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x009a41a4 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x009a41a8 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK 0x009a41ac /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK 0x009a41bc /* RW-4R */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x009a41e0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x009a41e4 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK 0x009a41e8 /* RW-4R */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK 0x009a41ec /* RW-4R */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x009a41f0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK 0x009a41f4 /* RW-4R */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x009a41f8 /* RW-4R */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK 0x009a41fc /* RW-4R */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFBFALCON_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK 0x009a4220 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x009a4224 /* RW-4R */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK 0x009a4228 /* RW-4R */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK 0x009a422c /* RW-4R */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSSET 0x009a4000 /* -W-4R */
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#define NV_PFBFALCON_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ1_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ2_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ3_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ4_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ5_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ6_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ7_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_EXT_EXTIRQ8_SET 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR 0x009a4004 /* -W-4R */
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#define NV_PFBFALCON_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT 15:8 /* */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQSTAT 0x009a4008 /* R--4R */
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#define NV_PFBFALCON_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT 15:8 /* */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMODE 0x009a400c /* RW-4R */
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#define NV_PFBFALCON_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x009a4290 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK 0x009a40e0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x009a41a4 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 1 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0 /* */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQMSET 0x009a4010 /* -W-4R */
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#define NV_PFBFALCON_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x009a4290 /* */
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#define NV_PFBFALCON_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_HALT 4:4 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT 15:8 /* */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMSET_DMA 16:16 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR 0x009a4014 /* -W-4R */
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#define NV_PFBFALCON_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x009a4290 /* */
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#define NV_PFBFALCON_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT 15:8 /* */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */
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#define NV_PFBFALCON_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_IRQMASK 0x009a4018 /* R--4R */
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#define NV_PFBFALCON_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT 15:8 /* */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IRQDEST 0x009a401c /* RW-4R */
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#define NV_PFBFALCON_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x009a4290 /* */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT 15:8 /* */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST2 0x009a403c /* RW-4R */
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#define NV_PFBFALCON_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x009a4290 /* */
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#define NV_PFBFALCON_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_GPTMRINT 0x009a4020 /* RW-4R */
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#define NV_PFBFALCON_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x009a41a0 /* */
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#define NV_PFBFALCON_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_GPTMRVAL 0x009a4024 /* RW-4R */
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#define NV_PFBFALCON_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x009a41a0 /* */
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#define NV_PFBFALCON_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_GPTMRCTL 0x009a4028 /* RW-4R */
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#define NV_PFBFALCON_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x009a41a0 /* */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_PTIMER0 0x009a402c /* R--4R */
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#define NV_PFBFALCON_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x009a41bc /* */
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#define NV_PFBFALCON_FALCON_PTIMER0_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_PTIMER1 0x009a4030 /* R--4R */
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#define NV_PFBFALCON_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x009a41bc /* */
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#define NV_PFBFALCON_FALCON_PTIMER1_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_WDTMRVAL 0x009a4034 /* RW-4R */
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#define NV_PFBFALCON_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x009a429c /* */
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#define NV_PFBFALCON_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMRCTL 0x009a4038 /* RW-4R */
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#define NV_PFBFALCON_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x009a429c /* */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDDATA 0x009a4064 /* R--4R */
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#define NV_PFBFALCON_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */
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#define NV_PFBFALCON_FALCON_MTHDID 0x009a4068 /* RW-4R */
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#define NV_PFBFALCON_FALCON_MTHDID__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_MTHDID_ID 11:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */
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#define NV_PFBFALCON_FALCON_MTHDID_PRIV 15:15 /* RWXVF */
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#define NV_PFBFALCON_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_MTHDID_WPEND 16:16 /* R-XVF */
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#define NV_PFBFALCON_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_MTHDWDAT 0x009a406c /* RW-4R */
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#define NV_PFBFALCON_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_MTHDCOUNT 0x009a4070 /* R--4R */
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#define NV_PFBFALCON_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_MTHDPOP 0x009a4074 /* -W-4R */
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#define NV_PFBFALCON_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_MTHDPOP_POP 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_MTHDRAMSZ 0x009a4078 /* RW-4R */
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#define NV_PFBFALCON_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CURCTX 0x009a4050 /* RW-4R */
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#define NV_PFBFALCON_FALCON_CURCTX__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_NXTCTX 0x009a4054 /* RW-4R */
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#define NV_PFBFALCON_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CTXACK 0x009a4058 /* -W-4R */
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#define NV_PFBFALCON_FALCON_CTXACK__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_MAILBOX0 0x009a4040 /* RW-4R */
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#define NV_PFBFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_MAILBOX1 0x009a4044 /* RW-4R */
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#define NV_PFBFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ITFEN 0x009a4048 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ITFEN__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */
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#define NV_PFBFALCON_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IDLESTATE 0x009a404c /* RW-4R */
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#define NV_PFBFALCON_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x009a41e0 /* */
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#define NV_PFBFALCON_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_FHSTATE 0x009a405c /* R--4R */
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#define NV_PFBFALCON_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x009a41e4 /* */
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#define NV_PFBFALCON_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */
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#define NV_PFBFALCON_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */
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#define NV_PFBFALCON_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */
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#define NV_PFBFALCON_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE 0x009a4060 /* RW-4R */
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#define NV_PFBFALCON_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x009a43d0 /* */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_SFTRESET 0x009a407c /* RW-4R */
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#define NV_PFBFALCON_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_SFTRESET_EXT 0:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL 0x009a40a4 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */
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#define NV_PFBFALCON_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */
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#define NV_PFBFALCON_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_ADDR 0x009a40ac /* RW-4R */
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#define NV_PFBFALCON_FALCON_ADDR__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_ADDR_LSB 5:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ADDR_LSB_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ADDR_MSB 11:6 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ADDR_EXT 11:0 /* */
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#define NV_PFBFALCON_FALCON_DMACTL 0x009a410c /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMACTL__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMATRFBASE 0x009a4110 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMATRFMOFFS 0x009a4114 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD 0x009a4118 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMATRFFBOFFS 0x009a411c /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB 0x009a4120 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP 0x009a4124 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMATRFBASE1 0x009a4128 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMATRFBASE1_BASE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x009a42c0 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x009a42c4 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x009a42c8 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x009a42cc /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x009a42d0 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x009a42d4 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x009a42d8 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x009a42dc /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL 0x009a42e0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMAINFO_ERR_TAG_HIGH 0x009a42e4 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_DMAINFO_ERR_TAG_LOW 0x009a42e8 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x009a4190 /* */
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#define NV_PFBFALCON_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_IMEMC(i) (0x009a4180+(i)*16) /* RW-4A */
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#define NV_PFBFALCON_FALCON_IMEMC__SIZE_1 1 /* */
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#define NV_PFBFALCON_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEMC_BLK 23:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IMEMD(i) (0x009a4184+(i)*16) /* RW-4A */
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#define NV_PFBFALCON_FALCON_IMEMD__SIZE_1 1 /* */
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#define NV_PFBFALCON_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_FALCON_IMEMD_DATA 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_IMEMT(i) (0x009a4188+(i)*16) /* RW-4A */
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#define NV_PFBFALCON_FALCON_IMEMT__SIZE_1 1 /* */
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#define NV_PFBFALCON_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PFBFALCON_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_FALCON_IMEMT_TAG 15:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMEMC(i) (0x009a41c0+(i)*8) /* RW-4A */
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#define NV_PFBFALCON_FALCON_DMEMC__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMC_OFFS 7:2 /* */
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#define NV_PFBFALCON_FALCON_DMEMC_OFFS_INIT 0 /* */
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#define NV_PFBFALCON_FALCON_DMEMC_BLK 23:8 /* */
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#define NV_PFBFALCON_FALCON_DMEMC_BLK_INIT 0 /* */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_VA 28:28 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMC_MISS 29:29 /* R-IVF */
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#define NV_PFBFALCON_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
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#define NV_PFBFALCON_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
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#define NV_PFBFALCON_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_DMEMD(i) (0x009a41c4+(i)*8) /* RW-4A */
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#define NV_PFBFALCON_FALCON_DMEMD__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_FALCON_DMEMD_DATA 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMEMT(i) (0x009a4210+(i)*4) /* -W-4A */
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#define NV_PFBFALCON_FALCON_DMEMT__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_FALCON_DMEMT_TAG 15:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_DMEML(i) (0x009a42a0+(i)*4) /* -W-4A */
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#define NV_PFBFALCON_FALCON_DMEML__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_DMEML__PRIV_LEVEL_MASK NV_PFBFALCON_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_FALCON_DMEML_LVL 2:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE0 0x009a4174 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE0__PRIV_LEVEL_MASK 0x009a41ac /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE0_START_BLOCK 15:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE0_START_BLOCK_INIT 0x0000ffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE0_END_BLOCK 31:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE0_END_BLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE1 0x009a4178 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE1__PRIV_LEVEL_MASK 0x009a41ac /* */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE1_START_BLOCK 15:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE1_START_BLOCK_INIT 0x0000ffff /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE1_END_BLOCK 31:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEM_PRIV_RANGE1_END_BLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEM_DUMMY 0x009a4258 /* R--4R */
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#define NV_PFBFALCON_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x009a4284 /* */
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#define NV_PFBFALCON_FALCON_IMEM_DUMMY 0x009a41b4 /* R--4R */
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#define NV_PFBFALCON_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x009a4280 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x009a4300+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x009a43f0 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x009a4310+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x009a43f4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x009a4320+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x009a43f8 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x009a4330+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x009a43fc /* */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PRGNVER 0x009a43d4 /* R-I4R */
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#define NV_PFBFALCON_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */
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#define NV_PFBFALCON_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */
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#define NV_PFBFALCON_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */
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#define NV_PFBFALCON_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG 0x009a4108 /* R--4R */
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#define NV_PFBFALCON_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */
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#define NV_PFBFALCON_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */
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#define NV_PFBFALCON_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG1 0x009a412c /* R--4R */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000002 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000004 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000001 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000001 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000001 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */
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#define NV_PFBFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */
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#define NV_PFBFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2 0x009a40f4 /* R--4R */
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#define NV_PFBFALCON_FALCON_HWCFG2_SHA 0:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_BMEM 1:1 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_KMEM 4:4 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_VHR 7:7 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_HS 8:8 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_HWCFG3 0x009a4278 /* R--4R */
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#define NV_PFBFALCON_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */
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#define NV_PFBFALCON_FALCON_CGCTL 0x009a40a0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2 0x009a4134 /* RWI4R */
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#define NV_PFBFALCON_FALCON_CG2__PRIV_LEVEL_MASK 0x009a41e8 /* */
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#define NV_PFBFALCON_FALCON_CG2_SLCG 17:1 /* */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_ENABLED 0 /* */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */
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#define NV_PFBFALCON_FALCON_CG2_SLCG__PROD 0x000A0 /* */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_ENGINE 0x009a43c0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ENGINE__PRIV_LEVEL_MASK 0x009a43c4 /* */
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#define NV_PFBFALCON_FALCON_ENGINE_RESET 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL 0x009a4240 /* RW-4R */
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#define NV_PFBFALCON_FALCON_SCTL__PRIV_LEVEL_MASK 0x009a4298 /* */
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#define NV_PFBFALCON_FALCON_SCTL_LSMODE 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_HSMODE 1:1 /* R--VF */
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#define NV_PFBFALCON_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_UCODE_LEVEL 5:4 /* */
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#define NV_PFBFALCON_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */
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#define NV_PFBFALCON_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL1 0x009a4250 /* RW-4R */
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#define NV_PFBFALCON_FALCON_SCTL1__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL 0x009a40e4 /* RW-4R */
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#define NV_PFBFALCON_FALCON_HSCTL__PRIV_LEVEL_MASK 0x009a40e8 /* */
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#define NV_PFBFALCON_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_OS 0x009a4080 /* RW-4R */
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#define NV_PFBFALCON_FALCON_OS_VERSION 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_RM 0x009a4084 /* RW-4R */
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#define NV_PFBFALCON_FALCON_RM_CONFIG 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SOFT_PM 0x009a4088 /* RW-4R */
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#define NV_PFBFALCON_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x009a41ec /* */
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#define NV_PFBFALCON_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_SOFT_MODE 0x009a408c /* RW-4R */
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#define NV_PFBFALCON_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x009a41ec /* */
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#define NV_PFBFALCON_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM 0x009a40a8 /* RW-4R */
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#define NV_PFBFALCON_FALCON_PMM__PRIV_LEVEL_MASK 0x009a41ec /* */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x00000006 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0x0000000e /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */
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#define NV_PFBFALCON_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DEBUG1 0x009a4090 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x009a4294 /* */
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#define NV_PFBFALCON_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DEBUGINFO 0x009a4094 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_SP_MIN 0x009a4270 /* RW-4R */
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#define NV_PFBFALCON_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x009a41f0 /* */
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#define NV_PFBFALCON_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXCI 0x009a40d0 /* R--4R */
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#define NV_PFBFALCON_FALCON_EXCI__PRIV_LEVEL_MASK 0x009a41f4 /* */
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#define NV_PFBFALCON_FALCON_EXCI_EXPC 19:0 /* R-XVF */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */
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#define NV_PFBFALCON_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */
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#define NV_PFBFALCON_FALCON_EXCI2 0x009a40bc /* R--4R */
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#define NV_PFBFALCON_FALCON_EXCI2__PRIV_LEVEL_MASK 0x009a41f4 /* */
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#define NV_PFBFALCON_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */
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#define NV_PFBFALCON_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR 0x009a40d4 /* R--4R */
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#define NV_PFBFALCON_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x009a41f8 /* */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_CPUCTL 0x009a4100 /* RW-4R */
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#define NV_PFBFALCON_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x009a4288 /* */
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#define NV_PFBFALCON_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS 0x009a4130 /* -W-4R */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
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#define NV_PFBFALCON_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
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#define NV_PFBFALCON_FALCON_STACKCFG 0x009a4138 /* RW-4R */
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#define NV_PFBFALCON_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_BOOTVEC 0x009a4104 /* RW-4R */
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#define NV_PFBFALCON_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x009a4194 /* */
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#define NV_PFBFALCON_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL 0x009a4254 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x009a41a8 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_VAL 9:0 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_VAL_INIT 0 /* */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_DBGCTL_CYA 31:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT1 0x009a4098 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x009a41fc /* */
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#define NV_PFBFALCON_FALCON_IBRKPT1_PC 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_EN 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT2 0x009a409c /* RW-4R */
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#define NV_PFBFALCON_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x009a41fc /* */
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#define NV_PFBFALCON_FALCON_IBRKPT2_PC 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_EN 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT3 0x009a40b0 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x009a41fc /* */
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#define NV_PFBFALCON_FALCON_IBRKPT3_PC 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_EN 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT4 0x009a40b4 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x009a41fc /* */
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#define NV_PFBFALCON_FALCON_IBRKPT4_PC 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_EN 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT5 0x009a40b8 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x009a41fc /* */
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#define NV_PFBFALCON_FALCON_IBRKPT5_PC 23:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_EN 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD 0x009a4200 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x009a4220 /* */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_PARM 31:16 /* */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK 31:16 /* */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_ADDR 0x009a4204 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x009a4220 /* */
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#define NV_PFBFALCON_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_WDATA 0x009a4208 /* RW-4R */
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#define NV_PFBFALCON_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x009a4220 /* */
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#define NV_PFBFALCON_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_ICD_RDATA 0x009a420c /* R--4R */
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#define NV_PFBFALCON_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x009a4220 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */
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#define NV_PFBFALCON_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0 0x009a40d8 /* R--4R */
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#define NV_PFBFALCON_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x009a4224 /* */
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#define NV_PFBFALCON_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_VALID 28:28 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3 0x009a40dc /* R--4R */
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#define NV_PFBFALCON_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */
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#define NV_PFBFALCON_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */
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#define NV_PFBFALCON_FALCON_TRACEIDX 0x009a4148 /* RW-4R */
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#define NV_PFBFALCON_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x009a419c /* */
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#define NV_PFBFALCON_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */
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#define NV_PFBFALCON_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */
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#define NV_PFBFALCON_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_TRACEPC 0x009a414c /* R--4R */
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#define NV_PFBFALCON_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x009a419c /* */
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#define NV_PFBFALCON_FALCON_TRACEPC_PC 23:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_TRACEINFO 0x009a417c /* R--4R */
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#define NV_PFBFALCON_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x009a419c /* */
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#define NV_PFBFALCON_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_IMCTL 0x009a4140 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IMCTL__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_IMCTL_CMD 26:24 /* RWXVF */
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#define NV_PFBFALCON_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMCTL_DEBUG 0x009a415c /* RW-4R */
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#define NV_PFBFALCON_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */
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#define NV_PFBFALCON_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_IMSTAT 0x009a4144 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_IMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_IMFILLRNG0 0x009a4150 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMFILLRNG1 0x009a4154 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_IMFILLCTL 0x009a4158 /* RW-4R */
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#define NV_PFBFALCON_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMCTL 0x009a4260 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMCTL__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD 26:24 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMSTAT 0x009a4264 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_DMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PFBFALCON_FALCON_DMVACTL 0x009a4268 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x009a4198 /* */
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#define NV_PFBFALCON_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMVACTL_BOUND_INIT 0x00000100 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CMEMBASE 0x009a4160 /* RW-4R */
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#define NV_PFBFALCON_FALCON_CMEMBASE__PRIV_LEVEL_MASK 0x009a4198 /* */
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#define NV_PFBFALCON_FALCON_CMEMBASE_VAL 31:18 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CMEMBASE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMAPERT 0x009a4164 /* RW-4R */
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#define NV_PFBFALCON_FALCON_DMEMAPERT__PRIV_LEVEL_MASK 0x009a428c /* */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_TIME_OUT 7:0 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_TIME_OUT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_TIME_UNIT 11:8 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_TIME_UNIT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_ENABLE 16:16 /* RWIVF */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_DMEMAPERT_LDSTQ_NUM 19:17 /* R--VF */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT 0x009a416c /* RW-4R */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT__PRIV_LEVEL_MASK 0x009a4228 /* */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_PC 23:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_STAT 27:24 /* R--VF */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_STAT_ACK_POS 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_STAT_ACK_TOUT 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_VALID 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_VALID_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERRSTAT_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_EXTERRADDR 0x009a4168 /* R--4R */
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#define NV_PFBFALCON_FALCON_EXTERRADDR__PRIV_LEVEL_MASK 0x009a4228 /* */
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#define NV_PFBFALCON_FALCON_EXTERRADDR_ADDR 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_EXTERR_INFO 0x009a425c /* R--4R */
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#define NV_PFBFALCON_FALCON_EXTERR_INFO__PRIV_LEVEL_MASK 0x009a4228 /* */
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#define NV_PFBFALCON_FALCON_EXTERR_INFO_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT 0x009a4244 /* RW-4R */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x009a422c /* */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FALCON_CSBERR_ADDR 0x009a424c /* R--4R */
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#define NV_PFBFALCON_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x009a422c /* */
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#define NV_PFBFALCON_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FALCON_CSBERR_INFO 0x009a4248 /* R--4R */
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#define NV_PFBFALCON_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x009a422c /* */
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#define NV_PFBFALCON_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK 0x009a4670 /* RWI4R */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG(i) (0x009a4600+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
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#define NV_PFBFALCON_FBIF_TRANSCFG__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_TARGET_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_MEM_TYPE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_WR_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_RD_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK0_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK0_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK0_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK1_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_WACHK1_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK0_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK0_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK0_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK1_ENABLE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_TRANSCFG_RACHK1_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_INSTBLK 0x009a4620 /* R--4R */
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#define NV_PFBFALCON_FBIF_INSTBLK_PTR 27:0 /* R--VF */
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#define NV_PFBFALCON_FBIF_INSTBLK_TARGET 29:28 /* R--VF */
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#define NV_PFBFALCON_FBIF_INSTBLK_TARGET_LOCAL_FB 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_CTL 0x009a4624 /* RW-4R */
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#define NV_PFBFALCON_FBIF_CTL_FLUSH 0:0 /* RW-VF */
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#define NV_PFBFALCON_FBIF_CTL_FLUSH_SET 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_FLUSH_CLEAR 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */
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#define NV_PFBFALCON_FBIF_CTL_INVAL_CONTEXT_SET 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */
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#define NV_PFBFALCON_FBIF_CTL_CLR_BWCOUNT_SET 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_ENABLE 4:4 /* RWIVF */
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#define NV_PFBFALCON_FBIF_CTL_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_CTL_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */
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#define NV_PFBFALCON_FBIF_CTL_CLR_IDLEWDERR_SET 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_RESET 6:6 /* RW-VF */
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#define NV_PFBFALCON_FBIF_CTL_RESET_SET 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_RESET_CLEAR 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
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#define NV_PFBFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_IDLE 8:8 /* R--VF */
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#define NV_PFBFALCON_FBIF_CTL_IDLE_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_CTL_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */
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#define NV_PFBFALCON_FBIF_CTL_IDLEWDERR_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_CTL_IDLEWDERR_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_CTL_SRTOUT 10:10 /* R--VF */
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#define NV_PFBFALCON_FBIF_CTL_SRTOUT_TRUE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_CTL_SRTOUT_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */
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#define NV_PFBFALCON_FBIF_CTL_CLR_SRTOUT_SET 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_CLR_SRTOUT_CLEAR 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */
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#define NV_PFBFALCON_FBIF_CTL_SRTOVAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_THROTTLE 0x009a462c /* RW-4R */
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#define NV_PFBFALCON_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_PFBFALCON_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */
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#define NV_PFBFALCON_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_PFBFALCON_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_PFBFALCON_FBIF_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FBIF_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */
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#define NV_PFBFALCON_FBIF_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */
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#define NV_PFBFALCON_FBIF_REGIONCFG 0x009a466c /* RW-4R */
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#define NV_PFBFALCON_FBIF_REGIONCFG__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T0 3:0 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T0_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T1 7:4 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T1_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T2 11:8 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T2_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T3 15:12 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T3_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T4 19:16 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T4_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T5 23:20 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T5_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T6 27:24 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T6_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T7 31:28 /* RWIVF */
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#define NV_PFBFALCON_FBIF_REGIONCFG_T7_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FBIF_CG1 0x009a4674 /* RW-4R */
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#define NV_PFBFALCON_FBIF_CG1_SLCG 3:0 /* */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_ENABLED 0 /* */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_DISABLED 0xF /* */
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#define NV_PFBFALCON_FBIF_CG1_SLCG__PROD 0x0 /* */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_MSD0_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_MSD0_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_MSD1_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_MSD1_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_FB0_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_FB0_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_FB1_ENABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FBIF_CG1_SLCG_FB1_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFBFALCON_FBIF_ACHK_BLK(i) (0x009a4630+(i)*8) /* RW-4A */
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#define NV_PFBFALCON_FBIF_ACHK_BLK__SIZE_1 2 /* */
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#define NV_PFBFALCON_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */
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#define NV_PFBFALCON_FBIF_ACHK_CTL(i) (0x009a4634+(i)*8) /* RW-4A */
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#define NV_PFBFALCON_FBIF_ACHK_CTL__SIZE_1 2 /* */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_TYPE_INSIDE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_STATE_DISABLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_STATE_ENABLE 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0 0x009a4640 /* R--4R */
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#define NV_PFBFALCON_FBIF_DBG_STAT0__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE 3:0 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_CHECK 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_ALLOC 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_ISSUE 0x00000003 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_WDAT 0x00000004 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_FLT_FLUSH 0x00000005 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_HALT 0x00000006 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_INST 0x00000007 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_INST_ACK 0x00000008 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_OBJ 0x00000009 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DSP_STATE_FLUSH 0x0000000a /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_INST_VLD 4:4 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_INST_BOUND 5:5 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_RICF_HAS_DATA 6:6 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_ARQ_HAS_DATA 7:7 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_MRQ_HAS_DATA 8:8 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_FAULT_OR_HALT 9:9 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_ORQ_NOT_FULL 10:10 /* R-IUF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_ORQ_NOT_FULL_TRUE 0x00000001 /* R-I-V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_ORQ_NOT_FULL_FLASE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_FLUSH_OUTSTANDING 11:11 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DISPATCH_IDLE 12:12 /* R-IUF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DISPATCH_IDLE_TRUE 0x00000001 /* R-I-V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_DISPATCH_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_MWF_FSM_STATE 17:16 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_MWF_FSM_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_MWF_FSM_STATE_COMMIT 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_MWF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_MWF_HAS_DATA 18:18 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_MWF_COMMIT_COUNT 24:19 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_STALL_RQQ_FULL 25:25 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_STALL_WDF_FULL 26:26 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_STALL_FB_BUSY 27:27 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_STALL_ORQ_FULL 28:28 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_STALL_RDM_ALLOC 29:29 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_STALL_RDM_PORTQ 30:30 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT0_STALL_RDM_CLIENT 31:31 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1 0x009a4644 /* R--4R */
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#define NV_PFBFALCON_FBIF_DBG_STAT1__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FLT_STATE 1:0 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FLT_FAULTED 2:2 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FLT_BUSY 3:3 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_ACKF_HAS_DATA 4:4 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_ORQ_HAS_DATA 5:5 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_ALL_READS_DONE 6:6 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FBR_IDLE 8:8 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FBR_FAULTED 9:9 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FBR_FB_BUSY 10:10 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FBR_PKT2FB_VLD 11:11 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FBR_RCV_DATA_VALID 12:12 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_FBR_RCV_DATA_TYPE 15:14 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_WDF_FSM_STATE 17:16 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_WDF_FSM_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_WDF_FSM_STATE_COMMIT 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_WDF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_WDF_HAS_DATA 18:18 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_WDF_COMMIT_COUNT 23:19 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDM_STATE 25:24 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDM_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDM_STATE_WAITBUF 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDM_STATE_SAVEBUF 0x00000002 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDM_ANY_READY 26:26 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDM_DAQ_HAS_DATA 27:27 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDM_DEALLOC_COUNT 30:28 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT1_RDATA_WAIT 31:31 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT2 0x009a4648 /* R--4R */
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#define NV_PFBFALCON_FBIF_DBG_STAT2__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_DBG_STAT2_FAULTED_PORTID 5:0 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT2_FAULTED_SUBID 12:6 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT2_FAULTED_SRCQ 13:13 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_STAT2_FAULTED_SRCQ_ARQ 0x00000001 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT2_FAULTED_SRCQ_MRQ 0x00000000 /* R---V */
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#define NV_PFBFALCON_FBIF_DBG_STAT2_FAULTED_VLD 14:14 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_RDCOUNT_LO 0x009a4650 /* R--4R */
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#define NV_PFBFALCON_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_DBG_RDCOUNT_LO_DATA 31:0 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_RDCOUNT_HI 0x009a4654 /* R--4R */
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#define NV_PFBFALCON_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_DBG_RDCOUNT_HI_DATA 31:0 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_WRCOUNT_LO 0x009a4658 /* R--4R */
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#define NV_PFBFALCON_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_DBG_WRCOUNT_LO_DATA 31:0 /* R--UF */
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#define NV_PFBFALCON_FBIF_DBG_WRCOUNT_HI 0x009a465c /* R--4R */
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#define NV_PFBFALCON_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK 0x009a4670 /* */
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#define NV_PFBFALCON_FBIF_DBG_WRCOUNT_HI_DATA 31:0 /* R--UF */
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#define NV_PFBFALCON_FBIF_BW_ALLOC 0x009a464c /* RW-4R */
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#define NV_PFBFALCON_FBIF_BW_ALLOC_VAL 31:0 /* */
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#define NV_PFBFALCON_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */
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#define NV_PFBFALCON_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */
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#define NV_PFBFALCON_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */
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#define NV_PFBFALCON_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK 0x009a44d0 /* RW-4R */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon" /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon" /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_FIRMWARE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX(i) (0x009a4400+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX__SIZE_1 16 /* */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX__PRIV_LEVEL_MASK 0x009a44d0 /* */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_VALUE_NONE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_VALUE_PASS 0x00000001 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_VALUE_FAIL 0x00000002 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_VALUE_MAGIC 0x12345678 /* RW--V */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_SET(i) (0x009a4440+(i)*4) /* -W-4A */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_SET__SIZE_1 2 /* */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_SET__PRIV_LEVEL_MASK 0x009a44d0 /* */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_SET_VALUE 31:0 /* -W-VF */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_CLEAR(i) (0x009a4448+(i)*4) /* -W-4A */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_CLEAR__SIZE_1 2 /* */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_CLEAR__PRIV_LEVEL_MASK 0x009a44d0 /* */
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#define NV_PFBFALCON_FIRMWARE_MAILBOX_CLEAR_VALUE 31:0 /* -W-VF */
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#define NV_PFBFALCON_MAILBOX0_INTRSTAT 0x009a44c0 /* RW-4R */
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#define NV_PFBFALCON_MAILBOX0_INTRSTAT__PRIV_LEVEL_MASK 0x009a44d0 /* */
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#define NV_PFBFALCON_MAILBOX0_INTRSTAT_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_MAILBOX0_INTRSTAT_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_MAILBOX0_INTRSTAT_VALUE_OK_TO_SWITCH 0x00000001 /* RW--V */
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#define NV_PFBFALCON_MAILBOX0_INTREN 0x009a44c4 /* RW-4R */
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#define NV_PFBFALCON_MAILBOX0_INTREN__PRIV_LEVEL_MASK 0x009a44d0 /* */
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#define NV_PFBFALCON_MAILBOX0_INTREN_UPDATE 31:0 /* RWIVF */
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#define NV_PFBFALCON_MAILBOX0_INTREN_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_MAILBOX0_INTREN_UPDATE_OK_TO_SWITCH 0x00000001 /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK 0x009a4490 /* RW-4R */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon_secure_wr_scratch" /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon_secure_wr_scratch" /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH(i) (0x009a4450+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH__SIZE_1 8 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH__PRIV_LEVEL_MASK 0x009a4490 /* */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_VALUE_NONE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_SECURE_WR_SCRATCH_VALUE_MAGIC 0x12345678 /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK 0x009a4494 /* RW-4R */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon_secure_rd_wr_scratch" /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon_secure_rd_wr_scratch" /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH(i) (0x009a4470+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH__SIZE_1 8 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH__PRIV_LEVEL_MASK 0x009a4494 /* */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_VALUE_NONE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_SECURE_RD_WR_SCRATCH_VALUE_MAGIC 0x12345678 /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK 0x009a44ac /* RWB4R */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "pa_falcon_sync" /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pa_falcon_sync" /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_SYNC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_SYNC_STATUS 0x009a44a0 /* RW-4R */
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#define NV_PFBFALCON_SYNC_STATUS__PRIV_LEVEL_MASK 0x009a44ac /* */
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#define NV_PFBFALCON_SYNC_STATUS_AND_DATA 31:0 /* RWIVF */
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#define NV_PFBFALCON_SYNC_STATUS_AND_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_SYNC_STATUS2 0x009a44a8 /* RW-4R */
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#define NV_PFBFALCON_SYNC_STATUS2__PRIV_LEVEL_MASK 0x009a44ac /* */
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#define NV_PFBFALCON_SYNC_STATUS2_OR_DATA 31:0 /* RWIVF */
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#define NV_PFBFALCON_SYNC_STATUS2_OR_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_SYNC_CTRL 0x009a44a4 /* RW-4R */
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#define NV_PFBFALCON_SYNC_CTRL__PRIV_LEVEL_MASK 0x009a44ac /* */
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#define NV_PFBFALCON_SYNC_CTRL_CMD 7:0 /* RWIVF */
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#define NV_PFBFALCON_SYNC_CTRL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_SYNC_CTRL_CMD_START 0x00000001 /* RW--V */
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#define NV_PFBFALCON_SYNC_CTRL_CMD_START_MCLK_SWITCH 0x00000001 /* RW--V */
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#define NV_PFBFALCON_SYNC_CTRL_SEGMENT 15:8 /* RWIVF */
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#define NV_PFBFALCON_SYNC_CTRL_SEGMENT_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_SYNC_CTRL_SEGMENT_MAX 0x000000ff /* RW--V */
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#define NV_PFBFALCON_SYNC_CTRL_ARG 31:16 /* RWIVF */
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#define NV_PFBFALCON_SYNC_CTRL_ARG_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_SYNC_CTRL_ARG_START 0x00000001 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK 0x009a44b4 /* RWB4R */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "pa_memory_temperature" /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pa_memory_temperature" /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE 0x009a44b0 /* RW-4R */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE__PRIV_LEVEL_MASK 0x009a44b4 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_DATA 15:0 /* RWIVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_STATE 31:31 /* RWIVF */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_STATE_VALID 0x00000001 /* RW--V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_STATE_INVALID 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_FIXED_POINT 13:0 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_FIXED_POINT_ZERO 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_FIXED_POINT_MIN 0x00003B00 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_FIXED_POINT_MAX 0x00001180 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_VALUE 15:15 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_VALUE_VALID 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_VALUE_INVALID 0x00000000 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_SENSOR 31:31 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_SENSOR_ENABLED 0x00000001 /* */
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#define NV_PFBFALCON_MEMORY_TEMPERATURE_SENSOR_DISABLED 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK 0x009a45c8 /* RWB4R */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon" /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon" /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x00080000 /* RWB-V */
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#define NV_PFBFALCON_INTERN_SCRATCH(i) (0x009a45d0+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_INTERN_SCRATCH__SIZE_1 4 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH__PRIV_LEVEL_MASK 0x009a45c8 /* */
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#define NV_PFBFALCON_INTERN_SCRATCH_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_INTERN_SCRATCH_VALUE_NONE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_INTERN_SCRATCH_VALUE_PASS 0x00000001 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_VALUE_FAIL 0x00000002 /* RW--V */
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#define NV_PFBFALCON_INTERN_SCRATCH_VALUE_MAGIC 0x12345678 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK 0x009a44d4 /* RWB4R */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_bar0_priv" /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_bar0_priv" /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_BAR0_PRIV_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x00080000 /* RWB-V */
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#define NV_PFBFALCON_BAR0_PRIV_ADDR 0x009a44d8 /* RW-4R */
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#define NV_PFBFALCON_BAR0_PRIV_ADDR__PRIV_LEVEL_MASK 0x009a44d4 /* */
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#define NV_PFBFALCON_BAR0_PRIV_ADDR_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_BAR0_PRIV_ADDR_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_BAR0_PRIV_WRDATA 0x009a44dc /* RW-4R */
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#define NV_PFBFALCON_BAR0_PRIV_WRDATA__PRIV_LEVEL_MASK 0x009a44d4 /* */
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#define NV_PFBFALCON_BAR0_PRIV_WRDATA_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_BAR0_PRIV_WRDATA_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_BAR0_PRIV_RDDATA 0x009a44ec /* R--4R */
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#define NV_PFBFALCON_BAR0_PRIV_RDDATA__PRIV_LEVEL_MASK 0x009a44d4 /* */
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#define NV_PFBFALCON_BAR0_PRIV_RDDATA_VALUE 31:0 /* R-IVF */
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#define NV_PFBFALCON_BAR0_PRIV_RDDATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR 0x009a44e0 /* RW-4R */
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#define NV_PFBFALCON_BAR0_PRIV_CSR__PRIV_LEVEL_MASK 0x009a44d4 /* */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_CMD 2:0 /* RWIVF */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_CMD_READ 0x00000001 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_CMD_WRITE 0x00000002 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_CMD_WRITE_POSTED 0x00000003 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_CMD_UNDEFINED 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_STATUS 10:8 /* R-IVF */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_STATUS_IDLE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_STATUS_DIRECT 0x00000001 /* R---V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_STATUS_BUSY 0x00000002 /* R---V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_STATUS_TMOUT 0x00000003 /* R---V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_STATUS_PENDING 0x00000004 /* R---V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_STATUS_ERR 0x00000007 /* R---V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_LEVEL 17:16 /* R--VF */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_TRIG 31:31 /* RWIVF */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_TRIG_FALSE 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_BAR0_PRIV_CSR_TRIG_TRUE 0x00000001 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_TIMEOUT 0x009a44e4 /* RW-4R */
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#define NV_PFBFALCON_BAR0_PRIV_TIMEOUT__PRIV_LEVEL_MASK 0x009a44d0 /* */
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#define NV_PFBFALCON_BAR0_PRIV_TIMEOUT_VALUE 23:0 /* RWIVF */
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#define NV_PFBFALCON_BAR0_PRIV_TIMEOUT_VALUE_INIT 0x0000f000 /* RWI-V */
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#define NV_PFBFALCON_BAR0_PRIV_CTRL 0x009a44e8 /* RW-4R */
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#define NV_PFBFALCON_BAR0_PRIV_CTRL__PRIV_LEVEL_MASK 0x009a44d4 /* */
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#define NV_PFBFALCON_BAR0_PRIV_CTRL_DEBUG_MONITOR 16:16 /* RWIVF */
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#define NV_PFBFALCON_BAR0_PRIV_CTRL_DEBUG_MONITOR_ENABLED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_BAR0_PRIV_CTRL_DEBUG_MONITOR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_PRIV_MONITOR(i) (0x009a44f0+(i)*4) /* R--4A */
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#define NV_PFBFALCON_PRIV_MONITOR__SIZE_1 4 /* */
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#define NV_PFBFALCON_PRIV_MONITOR_VALUE 31:0 /* R-IVF */
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#define NV_PFBFALCON_PRIV_MONITOR_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK(i) (0x009a45e0+(i)*4) /* RWB4A */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK__SIZE_1 4 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon_cmdq" /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon_cmdq" /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_CMD_QUEUE_HEAD(i) (0x009a4500+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_CMD_QUEUE_HEAD__SIZE_1 4 /* */
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#define NV_PFBFALCON_CMD_QUEUE_HEAD__PRIV_LEVEL_MASK NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_CMD_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
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#define NV_PFBFALCON_CMD_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_CMD_QUEUE_TAIL(i) (0x009a4510+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_CMD_QUEUE_TAIL__SIZE_1 4 /* */
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#define NV_PFBFALCON_CMD_QUEUE_TAIL__PRIV_LEVEL_MASK NV_PFBFALCON_CMDQ_PRIV_LEVEL_MASK /* */
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#define NV_PFBFALCON_CMD_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */
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#define NV_PFBFALCON_CMD_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK 0x009a45f0 /* RWB4R */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon_cmdq_ctrl" /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon_cmdq_ctrl" /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_CMDQ_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT 0x009a4520 /* RW-4R */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT__PRIV_LEVEL_MASK 0x009a45f0 /* */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_0 0:0 /* RWIVF */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_0_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_0_UPDATED 0x00000001 /* R---V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_0_CLEAR 0x00000001 /* -W--C */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_1 1:1 /* RWIVF */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_1_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_1_UPDATED 0x00000001 /* R---V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_1_CLEAR 0x00000001 /* -W--C */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_2 2:2 /* RWIVF */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_2_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_2_UPDATED 0x00000001 /* R---V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_2_CLEAR 0x00000001 /* -W--C */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_3 3:3 /* RWIVF */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_3_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_3_UPDATED 0x00000001 /* R---V */
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#define NV_PFBFALCON_CMD_HEAD_INTRSTAT_3_CLEAR 0x00000001 /* -W--C */
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#define NV_PFBFALCON_CMD_INTREN 0x009a4524 /* RW-4R */
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#define NV_PFBFALCON_CMD_INTREN__PRIV_LEVEL_MASK 0x009a45f0 /* */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_0_UPDATE 0:0 /* RWIVF */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_0_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_0_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_0_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_1_UPDATE 1:1 /* RWIVF */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_1_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_1_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_1_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_2_UPDATE 2:2 /* RWIVF */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_2_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_2_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_2_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_3_UPDATE 3:3 /* RWIVF */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_3_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_3_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PFBFALCON_CMD_INTREN_HEAD_3_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK 0x009a45f8 /* RWB4R */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon" /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon" /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_MSGQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_MSGQ_HEAD(i) (0x009a4530+(i)*8) /* RW-4A */
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#define NV_PFBFALCON_MSGQ_HEAD__SIZE_1 1 /* */
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#define NV_PFBFALCON_MSGQ_HEAD__PRIV_LEVEL_MASK 0x009a45f8 /* */
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#define NV_PFBFALCON_MSGQ_HEAD_VAL 31:0 /* RWIUF */
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#define NV_PFBFALCON_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_MSGQ_TAIL(i) (0x009a4534+(i)*8) /* RW-4A */
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#define NV_PFBFALCON_MSGQ_TAIL__SIZE_1 1 /* */
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#define NV_PFBFALCON_MSGQ_TAIL__PRIV_LEVEL_MASK 0x009a45f8 /* */
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#define NV_PFBFALCON_MSGQ_TAIL_VAL 31:0 /* RWIUF */
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#define NV_PFBFALCON_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK 0x009a45a0 /* RWB4R */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon_mutex" /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon_mutex" /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK 0x009a45c4 /* RWB4R */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon_mutex_id" /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon_mutex_id" /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_MUTEX_ID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_MUTEX_ID 0x009a4540 /* R--4R */
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#define NV_PFBFALCON_MUTEX_ID__PRIV_LEVEL_MASK 0x009a45c4 /* */
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#define NV_PFBFALCON_MUTEX_ID_VALUE 7:0 /* R-IUF */
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#define NV_PFBFALCON_MUTEX_ID_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_MUTEX_ID_VALUE_NOT_AVAIL 0x000000ff /* R---V */
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#define NV_PFBFALCON_MUTEX_ID_RELEASE 0x009a4544 /* RW-4R */
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#define NV_PFBFALCON_MUTEX_ID_RELEASE__PRIV_LEVEL_MASK 0x009a45a0 /* */
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#define NV_PFBFALCON_MUTEX_ID_RELEASE_VALUE 7:0 /* RWIUF */
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#define NV_PFBFALCON_MUTEX_ID_RELEASE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_MUTEX(i) (0x009a4550+(i)*4) /* RW-4A */
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#define NV_PFBFALCON_MUTEX__SIZE_1 4 /* */
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#define NV_PFBFALCON_MUTEX__PRIV_LEVEL_MASK 0x009a45a0 /* */
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#define NV_PFBFALCON_MUTEX_VALUE 7:0 /* RWIUF */
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#define NV_PFBFALCON_MUTEX_VALUE_INITIAL_LOCK 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK 0x009a45fc /* RWB4R */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fb_falcon_tctrl" /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fb_falcon_tctrl" /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PFBFALCON_TCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PFBFALCON_TIMER_0_INTERVAL 0x009a4570 /* RW-4R */
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#define NV_PFBFALCON_TIMER_0_INTERVAL__PRIV_LEVEL_MASK 0x009a45fc /* */
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#define NV_PFBFALCON_TIMER_0_INTERVAL_VALUE 31:0 /* RWIVF */
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#define NV_PFBFALCON_TIMER_0_INTERVAL_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_TIMER_0_COUNT 0x009a4574 /* R--4R */
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#define NV_PFBFALCON_TIMER_0_COUNT_VALUE 31:0 /* R--VF */
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#define NV_PFBFALCON_TIMER_0_COUNT_VALUE_INIT 0xffffffff /* R---V */
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#define NV_PFBFALCON_TIMER_CTRL 0x009a4578 /* RW-4R */
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#define NV_PFBFALCON_TIMER_CTRL__PRIV_LEVEL_MASK 0x009a45fc /* */
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#define NV_PFBFALCON_TIMER_CTRL_GATE 0:0 /* RWIVF */
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#define NV_PFBFALCON_TIMER_CTRL_GATE_STOP 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_TIMER_CTRL_GATE_RUN 0x00000001 /* RW--V */
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#define NV_PFBFALCON_TIMER_CTRL_SOURCE 4:4 /* RWIVF */
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#define NV_PFBFALCON_TIMER_CTRL_SOURCE_SEC_CLK 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_TIMER_CTRL_SOURCE_SYS_CLK 0x00000000 /* RW--V */
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#define NV_PFBFALCON_TIMER_CTRL_SOURCE_PTIMER_1US 0x00000001 /* RW--V */
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#define NV_PFBFALCON_TIMER_CTRL_MODE 8:8 /* RWIVF */
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#define NV_PFBFALCON_TIMER_CTRL_MODE_ONE_SHOT 0x00000000 /* RWI-V */
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#define NV_PFBFALCON_TIMER_CTRL_MODE_CONTINUOUS 0x00000001 /* RW--V */
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#define NV_PFBFALCON_TIMER_CTRL_RESET 12:12 /* RWIVF */
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#define NV_PFBFALCON_TIMER_CTRL_RESET_DONE 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_TIMER_CTRL_RESET_NOT_DONE 0x00000001 /* R---V */
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#define NV_PFBFALCON_TIMER_CTRL_RESET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PFBFALCON_IP_VER 0x009a4580 /* R--4R */
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#define NV_PFBFALCON_IP_VER_DEV 7:0 /* R-IVF */
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#define NV_PFBFALCON_IP_VER_DEV_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_IP_VER_ECO 15:8 /* R-IVF */
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#define NV_PFBFALCON_IP_VER_ECO_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_IP_VER_MINOR 23:16 /* R-IVF */
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#define NV_PFBFALCON_IP_VER_MINOR_INIT 0x00000000 /* R-I-V */
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#define NV_PFBFALCON_IP_VER_MAJOR 31:24 /* R-IVF */
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#define NV_PFBFALCON_IP_VER_MAJOR_INIT 0x00000010 /* R-I-V */
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#endif // __ga102_dev_fbfalcon_pri_h__
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