95 lines
8.0 KiB
C
95 lines
8.0 KiB
C
// --------------------------------------------------------------------------------
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//
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x00404488 /* RWE4R */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS 15:0 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS_INIT 0x0000 /* RWE-V */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR 27:16 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR_INIT 0x000 /* RWE-V */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE 29:29 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE0 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE1 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ 30:30 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_DONE 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_TRIGGER 0x1 /* -W--T */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_DONE 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 0x1 /* -W--T */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x0040448C /* RWE4R */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V 31:0 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V_INIT 0x0 /* RWE-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR 0x00404490 /* RWE4R */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA 0:0 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA 1:1 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE 2:2 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT 3:3 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT 4:4 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS 5:5 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS 6:6 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD 7:7 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS 16:16 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB 17:17 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG 18:18 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW 19:19 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE 20:20 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_NOT_PENDING 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_PENDING 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP 29:29 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_DISABLED 0x0 /* RWE-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_ENABLED 0x1 /* RW--V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 /* -WEVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_V_0 0x0 /* -WE-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 /* RWEVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_DISABLE 0x0 /* RW--V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO 0x00404494 /* R--4R */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC 11:0 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_INIT 0x000 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MACRO_ADDRESS 19:12 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MACRO_ADDRESS_INIT 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID 27:28-6 /* C--VF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID_0 0x00000000 /* C---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID 28:28 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID_INIT 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX 0x004044A4 /* R--4R */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_FIFO_SIZE 7:0 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_FIFO_SIZE_INIT 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE 8:8 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE_MTHD 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE_DMA 0x1 /* R---V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2 0x0040449c /* R--4R */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR 31:0 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR_INIT 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3 0x004044A8 /* R--4R */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3_IR 31:0 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3_IR_INIT 0x0 /* R-E-V */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4 0x004044AC /* R--4R */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4_IR 31:0 /* R-EVF */
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#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4_IR_INIT 0x0 /* R-E-V */
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//
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// --------------------------------------------------------------------------------
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