377 lines
30 KiB
C
377 lines
30 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_ram_h__
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#define __ga102_dev_ram_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */
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#define NV_RAMIN /* ----G */
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#define NV_RAMIN_BASE_SHIFT 12 /* */
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#define NV_RAMIN_ALLOC_SIZE 4096 /* */
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#define NV_RAMIN_RAMFC (127*32+31):(0*32+0) /* RWXUF */
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#define NV_RAMIN_PAGE_DIR_BASE_TARGET (128*32+1):(128*32+0) /* RWXUF */
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#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_TARGET_INVALID 0x00000001 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_VOL (128*32+2):(128*32+2) /* RWXUF */
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#define NV_RAMIN_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */
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#define NV_RAMIN_MIN_MEM_GRANULE (128*32+3):(128*32+3) /* RWXUF */
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#define NV_RAMIN_MIN_MEM_GRANULE_4KB 0x00000000 /* RW--V */
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#define NV_RAMIN_MIN_MEM_GRANULE_64KB 0x00000001 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX (128*32+4):(128*32+4) /* RWXUF */
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#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX_DISABLED 0x00000000 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX_ENABLED 0x00000001 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC (128*32+5):(128*32+5) /* RWXUF */
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#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC_DISABLED 0x00000000 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC_ENABLED 0x00000001 /* RW--V */
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#define NV_RAMIN_NUM_VA_BITS (128*32+11):(128*32+6) /* RWXUF */
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#define NV_RAMIN_USE_NEW_PT_FORMAT (128*32+10):(128*32+10) /* RWXUF */
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#define NV_RAMIN_USE_NEW_PT_FORMAT_FALSE 0x00000000 /* RW--V */
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#define NV_RAMIN_USE_NEW_PT_FORMAT_TRUE 0x00000001 /* RW--V */
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#define NV_RAMIN_USE_VER2_PT_FORMAT (128*32+10):(128*32+10) /* */
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#define NV_RAMIN_USE_VER2_PT_FORMAT_FALSE 0x00000000 /* */
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#define NV_RAMIN_USE_VER2_PT_FORMAT_TRUE 0x00000001 /* */
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#define NV_RAMIN_BIG_PAGE_SIZE (128*32+11):(128*32+11) /* RWXUF */
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#define NV_RAMIN_BIG_PAGE_SIZE_128KB 0x00000000 /* RW--V */
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#define NV_RAMIN_BIG_PAGE_SIZE_64KB 0x00000001 /* RW--V */
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#define NV_RAMIN_PAGE_DIR_BASE_LO (128*32+31):(128*32+12) /* RWXUF */
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#define NV_RAMIN_PAGE_DIR_BASE_HI (129*32+31):(129*32+0) /* RWXUF */
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#define NV_RAMIN_ENGINE_CS (132*32+3):(132*32+3) /* */
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#define NV_RAMIN_ENGINE_CS_WFI 0x00000000 /* */
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#define NV_RAMIN_ENGINE_CS_FG 0x00000001 /* */
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#define NV_RAMIN_ENGINE_WFI_TARGET (132*32+1):(132*32+0) /* */
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#define NV_RAMIN_ENGINE_WFI_TARGET_LOCAL_MEM 0x00000000 /* */
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#define NV_RAMIN_ENGINE_WFI_TARGET_SYS_MEM_COHERENT 0x00000002 /* */
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#define NV_RAMIN_ENGINE_WFI_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* */
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#define NV_RAMIN_ENGINE_WFI_MODE (132*32+2):(132*32+2) /* */
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#define NV_RAMIN_ENGINE_WFI_MODE_PHYSICAL 0x00000000 /* */
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#define NV_RAMIN_ENGINE_WFI_MODE_VIRTUAL 0x00000001 /* */
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#define NV_RAMIN_ENGINE_WFI_PTR_LO (132*32+31):(132*32+12) /* */
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#define NV_RAMIN_ENGINE_WFI_PTR_HI (133*32+7):(133*32+0) /* */
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#define NV_RAMIN_ENGINE_WFI_VEID (134*32+(6-1)):(134*32+0) /* */
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#define NV_RAMIN_ENABLE_ATS (135*32+31):(135*32+31) /* RWXUF */
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#define NV_RAMIN_ENABLE_ATS_TRUE 0x00000001 /* RW--V */
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#define NV_RAMIN_ENABLE_ATS_FALSE 0x00000000 /* RW--V */
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#define NV_RAMIN_PASID (135*32+(20-1)):(135*32+0) /* RWXUF */
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#define NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO (136*32+31):(136*32+0) /* RWXUF */
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#define NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI (137*32+(((49-1)-32))):(137*32+0) /* RWXUF */
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#define NV_RAMIN_SC_PDB_VALID(i) (166*32+(i)):(166*32+(i)) /* RWXUF */
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#define NV_RAMIN_SC_PDB_VALID__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PDB_VALID_FALSE 0x00000000 /* RW--V */
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#define NV_RAMIN_SC_PDB_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET(i) ((168+(i)*4)*32+1):((168+(i)*4)*32+0) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_INVALID 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL(i) ((168+(i)*4)*32+2):((168+(i)*4)*32+2) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */
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#define NV_RAMIN_SC_MIN_MEM_GRANULE(i) ((168+(i)*4)*32+3):((168+(i)*4)*32+3) /* RWXUF */
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#define NV_RAMIN_SC_MIN_MEM_GRANULE__SIZE_1 64 /* */
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#define NV_RAMIN_SC_MIN_MEM_GRANULE_4KB 0x00000000 /* RW--V */
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#define NV_RAMIN_SC_MIN_MEM_GRANULE_64KB 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX(i) ((168+(i)*4)*32+4):((168+(i)*4)*32+4) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_DISABLED 0x00000000 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_ENABLED 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC(i) ((168+(i)*4)*32+5):((168+(i)*4)*32+5) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_DISABLED 0x00000000 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_ENABLED 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_NUM_VA_BITS(i) ((168+(i)*4)*32+11):((168+(i)*4)*32+6) /* RWXUF */
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#define NV_RAMIN_SC_NUM_VA_BITS__SIZE_1 64 /* */
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#define NV_RAMIN_SC_USE_VER2_PT_FORMAT(i) ((168+(i)*4)*32+10):((168+(i)*4)*32+10) /* RWXUF */
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#define NV_RAMIN_SC_USE_VER2_PT_FORMAT__SIZE_1 64 /* */
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#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_FALSE 0x00000000 /* RW--V */
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#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_TRUE 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_BIG_PAGE_SIZE(i) ((168+(i)*4)*32+11):((168+(i)*4)*32+11) /* RWXUF */
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#define NV_RAMIN_SC_BIG_PAGE_SIZE__SIZE_1 64 /* */
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#define NV_RAMIN_SC_BIG_PAGE_SIZE_64KB 0x00000001 /* RW--V */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_LO(i) ((168+(i)*4)*32+31):((168+(i)*4)*32+12) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_LO__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_HI(i) ((169+(i)*4)*32+31):((169+(i)*4)*32+0) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_HI__SIZE_1 64 /* */
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#define NV_RAMIN_SC_ENABLE_ATS(i) ((170+(i)*4)*32+31):((170+(i)*4)*32+31) /* RWXUF */
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#define NV_RAMIN_SC_ENABLE_ATS__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PASID(i) ((170+(i)*4)*32+(20-1)):((170+(i)*4)*32+0) /* RWXUF */
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#define NV_RAMIN_SC_PASID__SIZE_1 64 /* */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_0 ((168+0*4)*32+1):((168+0*4)*32+0) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_0 ((168+0*4)*32+2):((168+0*4)*32+2) /* RWXUF */
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#define NV_RAMIN_SC_MIN_MEM_GRANULE_0 ((168+0*4)*32+3):((168+0*4)*32+3) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_0 ((168+0*4)*32+4):((168+0*4)*32+4) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_0 ((168+0*4)*32+5):((168+0*4)*32+5) /* RWXUF */
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#define NV_RAMIN_SC_NUM_VA_BITS_0 ((168+0*4)*32+11):((168+0*4)*32+6) /* RWXUF */
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#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_0 ((168+0*4)*32+10):((168+0*4)*32+10) /* RWXUF */
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#define NV_RAMIN_SC_BIG_PAGE_SIZE_0 ((168+0*4)*32+11):((168+0*4)*32+11) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_LO_0 ((168+0*4)*32+31):((168+0*4)*32+12) /* RWXUF */
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#define NV_RAMIN_SC_PAGE_DIR_BASE_HI_0 ((169+0*4)*32+31):((169+0*4)*32+0) /* RWXUF */
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#define NV_RAMIN_SC_ENABLE_ATS_0 ((170+0*4)*32+31):((170+0*4)*32+31) /* RWXUF */
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#define NV_RAMIN_SC_PASID_0 ((170+0*4)*32+(20-1)):((170+0*4)*32+0) /* RWXUF */
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#define NV_RAMFC /* ----G */
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#define NV_RAMFC_BASE_SHIFT 12 /* */
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#define NV_RAMFC_SIZE_VAL 0x00000200 /* */
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#define NV_RAMFC_HOST_STATE_SIZE_VAL 64 /* */
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#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) /* RW-UF */
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#define NV_RAMFC_MEM_OP_A (1*32+31):(1*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED2 (2*32+31):(2*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED3 (3*32+31):(3*32+0) /* RW-UF */
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#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) /* RW-UF */
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#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) /* RW-UF */
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#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) /* RW-UF */
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#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) /* RW-UF */
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#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) /* RW-UF */
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#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) /* RW-UF */
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#define NV_RAMFC_REF (10*32+31):(10*32+0) /* RW-UF */
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#define NV_RAMFC_RUNTIME (11*32+31):(11*32+0) /* RW-UF */
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#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) /* RW-UF */
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#define NV_RAMFC_ACQUIRE_DEADLINE (13*32+31):(13*32+0) /* RW-UF */
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#define NV_RAMFC_SEM_ADDR_HI (14*32+31):(14*32+0) /* RW-UF */
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#define NV_RAMFC_SEM_ADDR_LO (15*32+31):(15*32+0) /* RW-UF */
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#define NV_RAMFC_SEM_PAYLOAD_LO (16*32+31):(16*32+0) /* RW-UF */
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#define NV_RAMFC_SEM_EXECUTE (17*32+31):(17*32+0) /* RW-UF */
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#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) /* RW-UF */
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#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) /* RW-UF */
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#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED21 (21*32+31):(21*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED22 (22*32+31):(22*32+0) /* RW-UF */
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#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) /* RW-UF */
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#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) /* RW-UF */
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#define NV_RAMFC_MEM_OP_B (25*32+31):(25*32+0) /* RW-UF */
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#define NV_RAMFC_PB_DATA3 (26*32+31):(26*32+0) /* RW-UF */
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#define NV_RAMFC_HDR_SHADOW (27*32+31):(27*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED28 (28*32+31):(28*32+0) /* RW-UF */
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#define NV_RAMFC_GP_CRC (29*32+31):(29*32+0) /* RW-UF */
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#define NV_RAMFC_SPLITTER_REM_LINES (30*32+31):(30*32+0) /* RW-UF */
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#define NV_RAMFC_SPLITTER_OFFSET_IN_LOWER (31*32+31):(31*32+0) /* RW-UF */
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#define NV_RAMFC_SPLITTER_OFFSET_IN_UPPER (32*32+31):(32*32+0) /* RW-UF */
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#define NV_RAMFC_PB_HEADER (33*32+31):(33*32+0) /* RW-UF */
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#define NV_RAMFC_PB_COUNT (34*32+31):(34*32+0) /* RW-UF */
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#define NV_RAMFC_PB_DATA0 (35*32+31):(35*32+0) /* RW-UF */
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#define NV_RAMFC_PB_DATA1 (36*32+31):(36*32+0) /* RW-UF */
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#define NV_RAMFC_SUBDEVICE (37*32+31):(37*32+0) /* RW-UF */
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#define NV_RAMFC_PB_CRC (38*32+31):(38*32+0) /* RW-UF */
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#define NV_RAMFC_SEM_PAYLOAD_HI (39*32+31):(39*32+0) /* RW-UF */
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#define NV_RAMFC_MEM_OP_C (40*32+31):(40*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED41 (41*32+31):(41*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED42 (42*32+31):(42*32+0) /* RW-UF */
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#define NV_RAMFC_TARGET (43*32+31):(43*32+0) /* RW-UF */
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#define NV_RAMFC_RESERVED44 (44*32+31):(44*32+0) /* RW-UF */
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#define NV_RAMFC_SPLITTER_REM_PIXELS (45*32+31):(45*32+0) /* RW-UF */
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#define NV_RAMFC_SPLITTER_OFFSET_OUT_LOWER (46*32+31):(46*32+0) /* RW-UF */
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#define NV_RAMFC_SPLITTER_OFFSET_OUT_UPPER (47*32+31):(47*32+0) /* RW-UF */
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#define NV_RAMFC_METHOD(i) ((48+(i)*2)*32+31):((48+(i)*2)*32+0) /* RW-UF */
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#define NV_RAMFC_METHOD__SIZE_1 4 /* */
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#define NV_RAMFC_DATA(i) ((49+(i)*2)*32+31):((49+(i)*2)*32+0) /* RW-UF */
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#define NV_RAMFC_DATA__SIZE_1 4 /* */
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#define NV_RAMFC_METHOD0 (48*32+31):(48*32+0) /* RW-UF */
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#define NV_RAMFC_DATA0 (49*32+31):(49*32+0) /* RW-UF */
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#define NV_RAMFC_METHOD1 (50*32+31):(50*32+0) /* RW-UF */
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#define NV_RAMFC_DATA1 (51*32+31):(51*32+0) /* RW-UF */
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#define NV_RAMFC_METHOD2 (52*32+31):(52*32+0) /* RW-UF */
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#define NV_RAMFC_DATA2 (53*32+31):(53*32+0) /* RW-UF */
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#define NV_RAMFC_METHOD3 (54*32+31):(54*32+0) /* RW-UF */
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#define NV_RAMFC_DATA3 (55*32+31):(55*32+0) /* RW-UF */
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#define NV_RAMFC_SPARE56 (56*32+31):(56*32+0) /* RW-UF */
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#define NV_RAMFC_HCE_CTRL (57*32+31):(57*32+0) /* RW-UF */
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#define NV_RAMFC_ALLOWED_SYNCPOINTS (58*32+31):(58*32+0) /* RW-UF */
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#define NV_RAMFC_GP_PEEK (59*32+31):(59*32+0) /* RW-UF */
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#define NV_RAMFC_PB_DATA2 (60*32+31):(60*32+0) /* RW-UF */
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#define NV_RAMFC_CONFIG (61*32+31):(61*32+0) /* RW-UF */
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#define NV_RAMFC_INTR_NOTIFY (62*32+31):(62*32+0) /* RW-UF */
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#define NV_RAMFC_SET_CHANNEL_INFO (63*32+31):(63*32+0) /* RW-UF */
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#define NV_RAMFC_CHID (58*32+31):(58*32+0) /* */
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#define NV_RAMFC_CHID_ID 11:0 /* */
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#define NV_RAMFC_CE_METHOD_STATE(i) (((i)+64)*32+31):(((i)+64)*32+0) /* RW-UF */
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#define NV_RAMFC_CE_METHOD_STATE__SIZE_1 42 /* */
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#define NV_RAMFC_CE_METHOD_STATE_SHIFT 8 /* */
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#define NV_RAMFC_HOST_FETCH_SIZE_VAL (64+42)*4
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#define NV_RAMUSERD /* ----G */
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#define NV_RAMUSERD_BASE_SHIFT 9 /* */
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#define NV_RAMUSERD_CHAN_SIZE 512 /* */
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#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) /* RW-UF */
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#define NV_RAMUSERD_GET (17*32+31):(17*32+0) /* RW-UF */
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#define NV_RAMUSERD_REF (18*32+31):(18*32+0) /* RW-UF */
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#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) /* RW-UF */
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#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RW-UF */
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#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RW-UF */
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#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) /* RW-UF */
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#define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RW-UF */
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#define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RW-UF */
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#define NV_RAMRL_ENTRY_RANGE 0xF:0x00000000 /* RW--M */
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#define NV_RAMRL_ENTRY /* ----G */
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#define NV_RAMRL_ENTRY_SIZE 16 /* */
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#define NV_RAMRL_ENTRY_BASE_SHIFT 10 /* */
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#define NV_RAMRL_ENTRY_TYPE (0+0*32):(0+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_TYPE_CHAN 0x00000000 /* RW--V */
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#define NV_RAMRL_ENTRY_TYPE_TSG 0x00000001 /* RW--V */
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#define NV_RAMRL_ENTRY_ID (11+2*32):(0+2*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_ID_HW 10:0 /* RWXUF */
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#define NV_RAMRL_ENTRY_ID_MAX (2048-1) /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_RUNQUEUE_SELECTOR (1+0*32):(1+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_INST_TARGET (5+0*32):(4+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_VID_MEM 0x00000000 /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET (7+0*32):(6+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_VID_MEM 0x00000000 /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_VID_MEM_NVLINK_COHERENT 0x00000001 /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
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#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI (31+1*32):(0+1*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI_HW (7+1*32):(0+1*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_CHID (11+2*32):(0+2*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_INST_PTR_LO (31+2*32):(12+2*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_INST_PTR_HI (31+3*32):(0+3*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_INST_PTR_HI_HW (7+3*32):(0+3*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_CHAN_INST_PTR_ALIGN_SHIFT 12 /* */
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#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_ALIGN_SHIFT 8 /* */
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#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_FB_BIND_SHIFT 28 /* */
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#define NV_RAMRL_ENTRY_TSG_GFID (11+0*32):(4+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_TSG_TIMESLICE_SCALE (19+0*32):(16+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_TSG_TIMESLICE_SCALE_3 0x00000003 /* RWI-V */
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#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT (31+0*32):(24+0*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */
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#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT_1 0x00000000 /* RW--V */
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#define NV_RAMRL_ENTRY_TSG_LENGTH (7+1*32):(0+1*32) /* RWXUF */
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#define NV_RAMRL_ENTRY_TSG_LENGTH_INIT 0x00000000 /* RW--V */
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#define NV_RAMRL_ENTRY_TSG_LENGTH_MIN 0x00000001 /* RW--V */
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#define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000080 /* RW--V */
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#define NV_RAMRL_ENTRY_TSG_TSGID (11+2*32):(0+2*32) /* RWXUF */
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#define NV_FIFO_DMA_PB_ENTRY_SIZE 4 /* */
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#define NV_FIFO_DMA /* ----G */
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#define NV_FIFO_DMA_METHOD_ADDRESS_OLD 12:2 /* RWXUF */
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#define NV_FIFO_DMA_METHOD_ADDRESS 11:0 /* RWXUF */
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#define NV_FIFO_DMA_SUBDEVICE_MASK 15:4 /* RWXUF */
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#define NV_FIFO_DMA_METHOD_SUBCHANNEL 15:13 /* RWXUF */
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#define NV_FIFO_DMA_TERT_OP 17:16 /* RWXUF */
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#define NV_FIFO_DMA_TERT_OP_GRP0_INC_METHOD 0x00000000 /* RW--V */
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#define NV_FIFO_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK 0x00000001 /* RW--V */
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#define NV_FIFO_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK 0x00000002 /* RW--V */
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#define NV_FIFO_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK 0x00000003 /* RW--V */
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#define NV_FIFO_DMA_TERT_OP_GRP2_NON_INC_METHOD 0x00000000 /* RW--V */
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#define NV_FIFO_DMA_METHOD_COUNT_OLD 28:18 /* RWXUF */
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#define NV_FIFO_DMA_METHOD_COUNT 28:16 /* RWXUF */
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#define NV_FIFO_DMA_SEC_OP 31:29 /* RWXUF */
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#define NV_FIFO_DMA_SEC_OP_GRP0_USE_TERT 0x00000000 /* RW--V */
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#define NV_FIFO_DMA_SEC_OP_INC_METHOD 0x00000001 /* RW--V */
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#define NV_FIFO_DMA_SEC_OP_GRP2_USE_TERT 0x00000002 /* RW--V */
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#define NV_FIFO_DMA_SEC_OP_NON_INC_METHOD 0x00000003 /* RW--V */
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#define NV_FIFO_DMA_SEC_OP_IMMD_DATA_METHOD 0x00000004 /* RW--V */
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#define NV_FIFO_DMA_SEC_OP_ONE_INC 0x00000005 /* RW--V */
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#define NV_FIFO_DMA_SEC_OP_RESERVED6 0x00000006 /* RW--V */
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#define NV_FIFO_DMA_SEC_OP_END_PB_SEGMENT 0x00000007 /* RW--V */
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#define NV_FIFO_DMA_INCR /* ----G */
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#define NV_FIFO_DMA_INCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */
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#define NV_FIFO_DMA_INCR_OPCODE_VALUE 0x00000001 /* ----V */
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#define NV_FIFO_DMA_INCR_COUNT (0*32+28):(0*32+16) /* RWXUF */
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#define NV_FIFO_DMA_INCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */
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#define NV_FIFO_DMA_INCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */
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#define NV_FIFO_DMA_INCR_DATA (1*32+31):(1*32+0) /* RWXUF */
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#define NV_FIFO_DMA_NONINCR /* ----G */
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#define NV_FIFO_DMA_NONINCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */
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#define NV_FIFO_DMA_NONINCR_OPCODE_VALUE 0x00000003 /* ----V */
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#define NV_FIFO_DMA_NONINCR_COUNT (0*32+28):(0*32+16) /* RWXUF */
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#define NV_FIFO_DMA_NONINCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */
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#define NV_FIFO_DMA_NONINCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */
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#define NV_FIFO_DMA_NONINCR_DATA (1*32+31):(1*32+0) /* RWXUF */
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#define NV_FIFO_DMA_ONEINCR /* ----G */
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#define NV_FIFO_DMA_ONEINCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */
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#define NV_FIFO_DMA_ONEINCR_OPCODE_VALUE 0x00000005 /* ----V */
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#define NV_FIFO_DMA_ONEINCR_COUNT (0*32+28):(0*32+16) /* RWXUF */
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#define NV_FIFO_DMA_ONEINCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */
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#define NV_FIFO_DMA_ONEINCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */
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#define NV_FIFO_DMA_ONEINCR_DATA (1*32+31):(1*32+0) /* RWXUF */
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#define NV_FIFO_DMA_NOP 0x00000000 /* ----C */
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#define NV_FIFO_DMA_IMMD /* ----G */
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#define NV_FIFO_DMA_IMMD_ADDRESS 11:0 /* RWXUF */
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#define NV_FIFO_DMA_IMMD_SUBCHANNEL 15:13 /* RWXUF */
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#define NV_FIFO_DMA_IMMD_DATA 28:16 /* RWXUF */
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#define NV_FIFO_DMA_IMMD_OPCODE 31:29 /* RWXUF */
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#define NV_FIFO_DMA_IMMD_OPCODE_VALUE 0x00000004 /* ----V */
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#define NV_FIFO_DMA_SET_SUBDEVICE_MASK /* ----G */
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#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 /* RWXUF */
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#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */
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#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE 0x00000001 /* ----V */
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#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK /* ----G */
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#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 /* RWXUF */
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#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */
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#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE 0x00000002 /* ----V */
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#define NV_FIFO_DMA_USE_SUBDEVICE_MASK /* ----G */
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#define NV_FIFO_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */
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#define NV_FIFO_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE 0x00000003 /* ----V */
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#define NV_FIFO_DMA_ENDSEG_OPCODE 31:29 /* RWXUF */
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#define NV_FIFO_DMA_ENDSEG_OPCODE_VALUE 0x00000007 /* ----V */
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#define NV_FIFO_DMA_OPCODE (0*32+31):(0*32+29) /* RWXUF */
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#define NV_FIFO_DMA_OPCODE_METHOD 0x00000000 /* ----V */
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#define NV_FIFO_DMA_OPCODE_NONINC_METHOD 0x00000002 /* ----V */
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#define NV_FIFO_DMA_OPCODE3_NONE 0x00000000 /* ----V */
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#define NV_FIFO_DMA_OPCODE2 (0*32+1):(0*32+0) /* RWXUF */
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#define NV_FIFO_DMA_OPCODE2_NONE 0x00000000 /* ----V */
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#define NV_FIFO_DMA_DATA (1*32+31):(1*32+0) /* RWXUF */
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#define NV_SUBCHAN /* ----G */
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#define NV_SUBCHAN_CTX_SWITCH (0*32+31):(0*32+0) /* RWXUF */
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#define NV_SUBCHAN_DMA_INSTANCE (1*32+15):(1*32+0) /* RWXUF */
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#define NV_SUBCHAN_NOTIFY_INSTANCE (1*32+31):(1*32+16) /* RWXUF */
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#define NV_SUBCHAN_MEMFMT_INSTANCE (2*32+15):(2*32+0) /* RWXUF */
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#define NV_SUBCHAN_MEMFMT_LINEAR (2*32+16):(2*32+16) /* RWXUF */
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#define NV_SUBCHAN_MEMFMT_LINEAR_OUT 0x00000000 /* RW--V */
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#define NV_SUBCHAN_MEMFMT_LINEAR_IN 0x00000001 /* RW--V */
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#define NV_DMA_PRIV (0*32+21):(0*32+20) /* RWXVF */
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#define NV_DMA_PRIV_FROM_PTE 0x00000000 /* RW--V */
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#define NV_DMA_PRIV_ANY 0x00000001 /* RW--V */
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#define NV_DMA_PRIV_PRIVILEGED 0x00000002 /* RW--V */
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#define NV_PRAMIN_DATA032(i) (0x00700000+(i)*4) /* RW-4A */
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#define NV_PRAMIN_DATA032__SIZE_1 262144 /* */
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#define NV_PRAMIN_DATA032_VALUE 31:0 /* RWXUF */
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#define NV_PRAMIN_DATA016(i) (0x00700000+(i)*2) /* RW-2A */
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#define NV_PRAMIN_DATA016__SIZE_1 524288 /* */
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#define NV_PRAMIN_DATA016_VALUE 15:0 /* RWXUF */
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#define NV_PRAMIN_DATA008(i) (0x00700000+(i)) /* RW-1A */
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#define NV_PRAMIN_DATA008__SIZE_1 1048576 /* */
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#define NV_PRAMIN_DATA008_VALUE 7:0 /* RWXUF */
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#define NV_NOTIFY 0x0000000F:0x00000000 /* RW--M */
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#define NV_NOTIFY_TIME_0 (0*32+31):(0*32+5) /* RWXUF */
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#define NV_NOTIFY_TIME_1 (1*32+28):(1*32+0) /* RWXUF */
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#define NV_NOTIFY_RETURN_VALUE (2*32+31):(2*32+0) /* RWXVF */
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#define NV_NOTIFY_ERROR_CODE (3*32+15):(3*32+0) /* RWXUF */
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#define NV_NOTIFY_STATUS (3*32+31):(3*32+24) /* RWXUF */
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#define NV_NOTIFY_STATUS_COMPLETED 0x00000000 /* RW--V */
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#define NV_NOTIFY_STATUS_IN_PROCESS 0x00000001 /* RW--V */
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#define NV_RAMSEMAPHORE /* ----G */
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#define NV_RAMSEMAPHORE_PAYLOAD (0*32+31):(0*32+0) /* RWXUF */
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#define NV_RAMSEMAPHORE_PAYLOAD_HI (1*32+31):(1*32+0) /* RWXUF */
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#define NV_RAMSEMAPHORE_TIMESTAMP_LO (2*32+31):(2*32+0) /* RWXUF */
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#define NV_RAMSEMAPHORE_TIMESTAMP_HI (3*32+31):(3*32+0) /* RWXUF */
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#define NV_MONITORED_FENCE 0x08:0x00 /* RW--M */
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#define NV_MONITORED_FENCE_THRESHOLD_LOWER (31+0*32):(0+0*32) /* RWXUF */
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#define NV_MONITORED_FENCE_THRESHOLD_UPPER (31+1*32):(0+1*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT 0x20:0x00 /* RW--M */
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#define NV_MONITORED_FENCE_EXT_THRESHOLD_LOWER (31+0*32):(0+0*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_THRESHOLD_UPPER (31+1*32):(0+1*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_ADDRESS_LOW (31+2*32):(2+2*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_ADDRESS_HIGH (7+3*32):(0+3*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_EVENT_HANDLE (31+4*32):(0+4*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_ADDRESS_TYPE (4+6*32):(4+6*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_ADDRESS_TYPE_ABSOLUTE 0x0 /* RW-UV */
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#define NV_MONITORED_FENCE_EXT_ADDRESS_TYPE_OFFSET 0x1 /* RW-UV */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_INTERRUPT (0+6*32):(0+6*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_INTERRUPT_DISABLE 0x0 /* RW-UV */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_INTERRUPT_ENABLE 0x1 /* RW-UV */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_MEMORY_WRITE (1+6*32):(1+6*32) /* RWXUF */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_MEMORY_WRITE_DISABLE 0x0 /* RW-UV */
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#define NV_MONITORED_FENCE_EXT_SIGNAL_MEMORY_WRITE_ENABLE 0x1 /* RW-UV */
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#endif // __ga102_dev_ram_h__
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