418 lines
53 KiB
C
418 lines
53 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_pri_ringmaster_h__
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#define __ga102_dev_pri_ringmaster_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PPRIV_MASTER 0x1203ff:0x120000 /* RW--D */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK 0x001200a4 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ring_priv_level_wr_secure" /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS(i) (0x00120000+(i)*4) /* RW-4A */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS__SIZE_1 8 /* */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0 1:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0_VW 0x00000002 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT0_PRIV_RW_VW 0x00000003 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1 4:3 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1_PRIV_RW 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT1_PRIV_RW_VW 0x00000003 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2 7:6 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT2_PRIV_RW_VW 0x00000003 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3 10:9 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT3_PRIV_RW_VW 0x00000003 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4 13:12 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT4_PRIV_RW_VW 0x00000003 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5 16:15 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5_VW 0x00000002 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT5_PRIV_RW_VW 0x00000003 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6 19:18 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6_PRIV_RW 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT6_PRIV_RW_VW 0x00000003 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7 22:21 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT7_PRIV_RW_VW 0x00000003 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8 25:24 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT8_PRIV_RW_VW 0x00000003 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9 28:27 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9_PRIV_RW 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9_VW 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_SLOT_RESERVATIONS_RSV_SLOT9_PRIV_RW_VW 0x00000003 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_STATUS 0x00120040 /* R--4R */
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#define NV_PPRIV_MASTER_RING_STATUS_TOTAL_RING_SLOTS (8-1):0 /* R--VF */
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#define NV_PPRIV_MASTER_RING_STATUS_ASYNC_FIFO_ENTRIES_USED 13:8 /* R--VF */
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#define NV_PPRIV_MASTER_RING_STATUS_RD_WR_TRANSACTIONS_USED (16+8-1):16 /* R--VF */
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#define NV_PPRIV_MASTER_RING_STATUS_VW_TRANSACTIONS_USED (24+8-1):24 /* R--VF */
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#define NV_PPRIV_MASTER_RING_LOOP_CONFIG 0x00120044 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_LOOP_CONFIG__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_LOOP_CONFIG_WATERMARK 5:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_LOOP_CONFIG_WATERMARK_INIT 0x00000012 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_COMMAND 0x0012004c /* RW-4R */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD 5:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_CMD 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_START_RING 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ACK_INTERRUPT 0x00000002 /* RW--T */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS 0x00000003 /* RW--T */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_AND_START_RING 0x00000004 /* RW--T */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_NO_TAG_ENUMERATE_AND_START_RING 0x00000005 /* RW--T */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP 9:6 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_ALL 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_GPC 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_FBP 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYS 0x00000003 /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_L2 0x00000004 /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_SYSC 0x00000006 /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_ALL 0x00000008 /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_GPC 0x00000009 /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_FBP 0x0000000a /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYS 0x0000000b /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_L2 0x0000000c /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_CMD_ENUMERATE_STATIONS_BC_GRP_NO_TAG_SYSC 0x0000000e /* RW--V */
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#define NV_PPRIV_MASTER_RING_COMMAND_DATA 0x00120048 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_COMMAND_DATA_START_RING_SEED 7:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_COMMAND_DATA_START_RING_SEED_INIT 0x00000053 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_START_RESULTS 0x00120050 /* R--4R */
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#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY 0:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_PASS 0x00000001 /* R---V */
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#define NV_PPRIV_MASTER_RING_START_RESULTS_CONNECTIVITY_FAIL 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0 0x00120058 /* R--4R */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP 31:16 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_FBP_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS 8:8 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYS_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSC 10:10 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GBL_WRITE_ERROR_SYSC_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT 0:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_START_CONN_FAULT_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT 1:1 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_DISCONNECT_FAULT_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT 2:2 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_OVERFLOW_FAULT_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT 3:3 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_RING_ENUMERATION_FAULT_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT 4:4 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS0_GPC_RS_MAP_CONFIG_FAULT_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1 0x0012005c /* R--4R */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC 31:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_INTERRUPT_STATUS1_GBL_WRITE_ERROR_GPC_V 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK 0x001200a0 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ring_reset_priv_level_wr_secure" /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */
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#define NV_PPRIV_MASTER_RING_GLOBAL_CTL 0x00120060 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_GLOBAL_CTL__PRIV_LEVEL_MASK 0x001200a0 /* */
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#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET 0:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_ASSERTED 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_GLOBAL_CTL_RING_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_DEBUG_MASTER 0x00120064 /* R--4R */
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#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_OUT_STATE 5:0 /* R--VF */
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#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_ALIVE 6:6 /* R--VF */
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#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_IDLE 7:7 /* R--VF */
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#define NV_PPRIV_MASTER_RING_DEBUG_MASTER_IN_STATE 13:8 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_CONFIG 0x001200b0 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_RUN_CONFIG_IDLE_REVOLUTIONS_UNTIL_SHUTDOWN 7:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_CONFIG_IDLE_REVOLUTIONS_UNTIL_SHUTDOWN_INIT 0x00000004 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS 0x001200b4 /* R--4R */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_IDLE_REVOLUTIONS 7:0 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_FECS_AUTO_SHUTDOWN 8:8 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_HOST_AUTO_SHUTDOWN 9:9 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_PMU_AUTO_SHUTDOWN 10:10 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_SHUTDOWN 11:11 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_SHUTDOWN_ENABLED 0x00000001 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_SHUTDOWN_DISABLED 0x00000000 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_WAKEUP 16:16 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_WAKEUP_ENABLED 0x00000001 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_AUTO_WAKEUP_DISABLED 0x00000000 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE 27:24 /* R--VF */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_SHUTTING_DOWN 0x00000001 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_ASLEEP 0x00000002 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_WAKEUP 0x00000004 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_STATUS_STATE_AWAKE 0x00000008 /* R---V */
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#define NV_PPRIV_MASTER_RING_RUN_SET 0x001200b8 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_RUN_SET__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FECS_AUTO_SHUTDOWN 8:8 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FECS_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FECS_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_SET_HOST_AUTO_SHUTDOWN 9:9 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_SET_HOST_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_SET_HOST_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_SET_PMU_AUTO_SHUTDOWN 10:10 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_SET_PMU_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_SET_PMU_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_SET_AUTO_WAKEUP 16:16 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_SET_AUTO_WAKEUP_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_SET_AUTO_WAKEUP_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_WAKEUP 24:24 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_WAKEUP_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_WAKEUP_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_SHUTDOWN 25:25 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_SHUTDOWN_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_SET_FORCE_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR 0x001200bc /* RW-4R */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_FECS_AUTO_SHUTDOWN 8:8 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_FECS_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_FECS_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_HOST_AUTO_SHUTDOWN 9:9 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_HOST_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_HOST_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_PMU_AUTO_SHUTDOWN 10:10 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_PMU_AUTO_SHUTDOWN_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_PMU_AUTO_SHUTDOWN_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_AUTO_WAKEUP 16:16 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_AUTO_WAKEUP_NONE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_RUN_CLEAR_AUTO_WAKEUP_TRIGGER 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS 0x00120070 /* R--4R */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_COUNT 4:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_COUNT_NONE 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_C_COUNT 24:20 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_SYS_C_COUNT_NONE 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP 0x00120074 /* R--4R */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT 4:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_FBP_COUNT_NONE 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC 0x00120078 /* R--4R */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT 4:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_GPC_COUNT_NONE 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_L2 0x0012006c /* R--4R */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_L2_COUNT 4:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_ENUMERATE_RESULTS_L2_COUNT_NONE 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_SYS_INSTANCE 0x0012007c /* R--4R */
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#define NV_PPRIV_MASTER_RING_SYS_INSTANCE_ID 3:0 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_SYS_INSTANCE_ID_NONE 0x0000000f /* R-B-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG 0x00120080 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD 3:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_NO_CMD 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H 0x00000002 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H 0x00000003 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_C1 0x00000004 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_C1 0x00000005 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H_C1 0x00000006 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H_C1 0x00000007 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_C2 0x00000008 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_C2 0x00000009 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H_C2 0x0000000a /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H_C2 0x0000000b /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_C1_C2 0x0000000c /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_C1_C2 0x0000000d /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_WRITE_H_C1_C2 0x0000000e /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_CMD_READ_WRITE_H_C1_C2 0x0000000f /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_READ 0:0 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_READ_DISABLE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_READ_ENABLE 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_H 1:1 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_H_DISABLE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_H_ENABLE 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C1 2:2 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C1_DISABLE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C1_ENABLE 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C2 3:3 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C2_DISABLE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_SUBCMD_WRITE_C2_ENABLE 0x00000001 /* RW--T */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS 5:4 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_NOMATCH 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS 0x00000001 /* R---V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY 0x00000002 /* R---V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_SUCCESS 0x00000003 /* R---V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS_BIT 4:4 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS_BIT_NOMATCH 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_SUCCESS_BIT_SUCCESS 0x00000001 /* R---V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_BIT 5:5 /* R-BVF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_BIT_IDLE 0x00000000 /* R-B-V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_STATUS_BUSY_BIT_BUSY 0x00000001 /* R---V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM 9:8 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM_FALSE 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM_TRUE 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SLOT_NUM_NOT 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION 11:10 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_FALSE 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_TRUE 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_NOT 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_TARGET_STATION_GROUP 0x00000003 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION 13:12 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_FALSE 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_TRUE 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_NOT 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_SENDING_STATION_GROUP 0x00000003 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV 15:14 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV_FALSE 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV_TRUE 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_RSV_NOT 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE 17:16 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE_FALSE 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE_TRUE 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_PAYLOAD_TYPE_NOT 0x00000002 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_WHICH 18:18 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_WHICH_FIRST 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_WHICH_ALL 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_LOOP 19:19 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_LOOP_ONCE 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_LOOP_INF 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER 0x00120084 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_SLOT_NUM (8-1):0 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_TARGET_STATION (8+8-1):8 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_SENDING_STATION (16+8-1):16 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_RSV 25:24 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_CONFIG_MATCH_HEADER_PAYLOAD_TYPE 31:26 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER 0x00120088 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_SLOT_NUM (7-1):0 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_UNUSED (8-1):7 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_RAMCHAIN_SIZE 8:8 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_TARGET_STATION 16:9 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_PHYS_ADDR 17:17 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_IR 18:18 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_SENDING_STATION 26:19 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_LOCAL_ORDERING 27:27 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_RC 28:28 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_RSV 30:29 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_HI 0x00120094 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_HI__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_HEADER_HI_PAYLOAD_TYPE 5:0 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1 0x0012008c /* RW-4R */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_REG_ID 23:0 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_SUB_ID 31:24 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_HI 0x00120098 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_HI__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE1_HI_PRIV_LEVEL 1:0 /* RW-VF */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE2 0x00120090 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE2__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_RING_MANAGE_RING_SLOTS_CYCLE2_BITS 31:0 /* RW-VF */
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#define NV_PPRIV_MASTER_CG1 0x001200a8 /* RW-4R */
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#define NV_PPRIV_MASTER_CG1_SLCG 0:0 /* RWBVF */
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#define NV_PPRIV_MASTER_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_CG1_SLCG_DISABLED 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_CYA_SETTINGS 0x001200ac /* RW-4R */
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#define NV_PPRIV_MASTER_CYA_SETTINGS__PRIV_LEVEL_MASK 0x001200a4 /* */
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#define NV_PPRIV_MASTER_CYA_SETTINGS_VWIRE_NO_WAKEUP 0:0 /* RWBVF */
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#define NV_PPRIV_MASTER_CYA_SETTINGS_VWIRE_NO_WAKEUP_ENABLED 0x00000001 /* RWB-V */
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#define NV_PPRIV_MASTER_CYA_SETTINGS_VWIRE_NO_WAKEUP_DISABLED 0x00000000 /* RW--V */
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#define NV_PPRIV_MASTER_GPC_RS_MAP(i) (0x001200c0+(i)*4) /* RW-4A */
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#define NV_PPRIV_MASTER_GPC_RS_MAP__SIZE_1 7 /* */
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#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENABLE 31:31 /* RWBVF */
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#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENABLE_FALSE 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_ID 8+1-1:8 /* RWBVF */
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#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_ID_INIT 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_LOCAL_CLUSTER_ID 3-1:0 /* RWBVF */
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#define NV_PPRIV_MASTER_GPC_RS_MAP_SMC_ENGINE_LOCAL_CLUSTER_ID_INIT 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_DEBUG 0x00120068 /* RW-4R */
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#define NV_PPRIV_MASTER_RING_DEBUG_GPC_RS_MAP_STATUS (7-1):0 /* R--VF */
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#define NV_PPRIV_MASTER_RING_DEBUG_GPC_RS_MAP_STATUS_INVALID 0x00000000 /* R---V */
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#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_TIMEOUT 27:24 /* RWBVF */
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#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_TIMEOUT_INIT 0x00000000 /* RWB-V */
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#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_STATE 30:28 /* R--VF */
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#define NV_PPRIV_MASTER_RING_DEBUG_RS_MAP_STATE_INVALID 0x00000000 /* R---V */
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#endif // __ga102_dev_pri_ringmaster_h__
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