1785 lines
228 KiB
C
1785 lines
228 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
#ifndef __ga102_dev_riscv_pri_h__
|
|
#define __ga102_dev_riscv_pri_h__
|
|
/* This file is autogenerated. Do not edit */
|
|
#define NV_FALCON2_GSP_BASE 0x00111000
|
|
#define NV_FALCON2_PWR_BASE 0x0010b000
|
|
#define NV_FALCON2_SEC_BASE 0x00841000
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK 0x00000304 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK 0x00000308 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK 0x00000300 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK 0x00000314 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK 0x00000310 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK 0x00000664 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK 0x00000690 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK 0x0000030c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK 0x00000318 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PLM /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK 0x0000031c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQMSET 0x00000520 /* -W-4R */
|
|
#define NV_PRISCV_RISCV_IRQMSET__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET__PRIV_LEVEL_MASK NV_PRISCV_FALCON_IRQTMR_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_HALT 4:4 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT 15:8 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ1 8:8 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ1_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ2 9:9 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ2_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ3 10:10 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ3_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ4 11:11 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ4_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ5 12:12 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ5_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ6 13:13 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ6_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ7 14:14 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ7_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ8 15:15 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_EXT_EXTIRQ8_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMSET_DMA 16:16 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_SHA 17:17 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_ICD 22:22 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMSET_CORE_MISMATCH 24:24 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR 0x00000524 /* -W-4R */
|
|
#define NV_PRISCV_RISCV_IRQMCLR__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR__PRIV_LEVEL_MASK NV_PRISCV_FALCON_IRQTMR_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_GPTMR 0:0 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_WDTMR 1:1 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_MTHD 2:2 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_CTXSW 3:3 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_HALT 4:4 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_HALT_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXTERR 5:5 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_SWGEN0 6:6 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_SWGEN1 7:7 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT 15:8 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ1 8:8 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ1_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ2 9:9 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ2_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ3 10:10 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ3_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ4 11:11 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ4_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ5 12:12 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ5_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ6 13:13 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ6_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ7 14:14 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ7_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ8 15:15 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_EXT_EXTIRQ8_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_DMA 16:16 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_DMA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_SHA 17:17 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_SHA_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_MEMERR 18:18 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_MEMERR_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_ICD 22:22 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_ICD_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_IOPMP 23:23 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_IRQMCLR_IOPMP_SET 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_IRQMASK 0x00000528 /* R-I4R */
|
|
#define NV_PRISCV_RISCV_IRQMASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_GPTMR 0:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_GPTMR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_GPTMR_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_WDTMR 1:1 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_WDTMR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_WDTMR_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_MTHD 2:2 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_MTHD_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_MTHD_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_CTXSW 3:3 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_CTXSW_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_CTXSW_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_HALT 4:4 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_HALT_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_HALT_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXTERR 5:5 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXTERR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXTERR_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SWGEN0 6:6 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SWGEN0_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SWGEN0_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SWGEN1 7:7 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SWGEN1_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SWGEN1_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT 15:8 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ1_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ1_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ2_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ2_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ3_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ3_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ4_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ4_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ5_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ5_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ6_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ6_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ7_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ7_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ8_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_EXT_EXTIRQ8_SET 1 /* */
|
|
#define NV_PRISCV_RISCV_IRQMASK_DMA 16:16 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_DMA_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_DMA_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SHA 17:17 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SHA_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_SHA_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_MEMERR 18:18 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_MEMERR_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_MEMERR_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_ICD 22:22 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_ICD_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_ICD_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_IOPMP 23:23 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_IOPMP_UNSET 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_IOPMP_SET 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQDEST 0x0000052c /* RW-4R */
|
|
#define NV_PRISCV_RISCV_IRQDEST__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_IRQDEST__PRIV_LEVEL_MASK NV_PRISCV_FALCON_IRQTMR_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IRQDEST_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_GPTMR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_GPTMR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_WDTMR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_WDTMR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_MTHD_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_MTHD_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_CTXSW_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_CTXSW_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_HALT 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_HALT_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_HALT_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXTERR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXTERR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SWGEN0_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SWGEN0_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SWGEN1_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SWGEN1_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT 15:8 /* */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ1 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ1_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ2 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ2_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ3 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ3_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ4 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ4_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ5 12:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ5_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ6 13:13 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ6_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ7 14:14 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ7_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ8 15:15 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ8_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_DMA 16:16 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_DMA_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_DMA_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SHA 17:17 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SHA_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_SHA_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_MEMERR_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_MEMERR_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_ICD 22:22 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_ICD_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_ICD_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_IOPMP_RISCV 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_IOPMP_HOST 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQDEST_CORE_MISMATCH_RISCV 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_IRQDEST_CORE_MISMATCH_HOST 0x00000001 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE 0x00000530 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IRQTYPE__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_IRQTYPE__PRIV_LEVEL_MASK NV_PRISCV_FALCON_IRQTMR_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_GPTMR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_WDTMR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_MTHD_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_CTXSW_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_HALT 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_HALT_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXTERR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SWGEN0_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SWGEN1_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT 15:8 /* */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ1 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ2 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ3 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ4 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ5 12:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ6 13:13 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ7 14:14 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ8 15:15 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_DMA 16:16 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_DMA_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_DMA_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SHA 17:17 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SHA_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_SHA_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_MEMERR_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_MEMERR_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_ICD 22:22 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_ICD_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_ICD_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_IOPMP_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_IOPMP_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_CORE_MISMATCH 24:24 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NORMAL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NONSTALL 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG 0x00000534 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IRQDELEG__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_IRQDELEG__PRIV_LEVEL_MASK NV_PRISCV_FALCON_IRQTMR_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_GPTMR 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_GPTMR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_GPTMR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_WDTMR 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_WDTMR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_WDTMR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_MTHD 2:2 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_MTHD_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_MTHD_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_CTXSW 3:3 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_CTXSW_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_CTXSW_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_HALT 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_HALT_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_HALT_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXTERR 5:5 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXTERR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXTERR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SWGEN0 6:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SWGEN0_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SWGEN0_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SWGEN1 7:7 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SWGEN1_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SWGEN1_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT 15:8 /* */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ1 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ1_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ1_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ2 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ2_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ2_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ3 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ3_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ3_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ4 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ4_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ4_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ5 12:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ5_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ5_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ6 13:13 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ6_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ6_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ7 14:14 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ7_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ7_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ8 15:15 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ8_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_EXT_EXTIRQ8_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_DMA 16:16 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_DMA_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_DMA_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SHA 17:17 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SHA_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_SHA_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_MEMERR 18:18 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_MEMERR_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_MEMERR_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_ICD 22:22 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_ICD_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_ICD_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_IOPMP 23:23 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_IOPMP_RISCV_MEIP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_IOPMP_RISCV_SEIP 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_CORE_MISMATCH 24:24 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_MEIP 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_SEIP 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_HI 0x00000384 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_HI__PRIV_LEVEL_MASK 0x00000310 /* */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_HI_VECTOR 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_HI_VECTOR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_LO 0x00000380 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_LO__PRIV_LEVEL_MASK 0x00000310 /* */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_LO_VECTOR 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BOOT_VECTOR_LO_VECTOR_INIT 0x00080000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL 0x00000388 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_CPUCTL__PRIV_LEVEL_MASK 0x00000308 /* */
|
|
#define NV_PRISCV_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_HALTED_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG 0x00000390 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_NVCONFIG__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG__PRIV_LEVEL_MASK 0x0000030c /* */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_WR_ALLOC_EN 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_WR_ALLOC_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_LD_MERGE_EN 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_LD_MERGE_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN 2:2 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN 3:3 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_VB_FWD_EN 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_VB_FWD_EN_RST 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_WRITE_BACK_EN 6:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_WRITE_BACK_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN 7:7 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_TLB_FIX_SIZE_EN 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_TLB_FIX_SIZE_EN_RST 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_SYSOP_CSR_EN 9:9 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_SYSOP_CSR_EN_RST 0x00000001 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_FENCE_FBFLUSH_EN 10:10 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_NVCONFIG_FENCE_FBFLUSH_EN_RST 0x00000001 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_CG 0x00000398 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_CG__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_CG__PRIV_LEVEL_MASK 0x00000304 /* */
|
|
#define NV_PRISCV_RISCV_CG_SLCG 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CG_SLCG_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CG_SLCG_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CG_SLCG_DISABLED 0 /* */
|
|
#define NV_PRISCV_RISCV_CG_SLCG_ENABLED 1 /* */
|
|
#define NV_PRISCV_RISCV_CG_SLCG__PROD 1 /* */
|
|
#define NV_PRISCV_RISCV_CG_CORE_SLCG 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CG_CORE_SLCG_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_CG_CORE_SLCG_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_CG_RSVD 31:2 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_CG_RSVD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_CYA 0x0000039c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_CYA__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_CYA__PRIV_LEVEL_MASK 0x00000304 /* */
|
|
#define NV_PRISCV_RISCV_CYA_RSVD 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_CYA_RSVD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL 0x000003c8 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_DBGCTL__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL__PRIV_LEVEL_MASK 0x00000314 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_RSVD1 2:2 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_J 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_J_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_J_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_EMASK 5:5 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RREG 6:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WREG 7:7 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RDM 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WDM 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WDM_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WDM_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RSTAT 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RCSR 12:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RCSR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RCSR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WCSR 13:13 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WCSR_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WCSR_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RPC 14:14 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RPC_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RPC_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RFREG 15:15 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RFREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_RFREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WFREG 16:16 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WFREG_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_ICD_CMDWL_WFREG_ENABLE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_RSVD 29:17 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_RSVD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_START_IN_ICD 30:30 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_START_IN_ICD_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_START_IN_ICD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_SINGLE_STEP_MODE 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_SINGLE_STEP_MODE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_SINGLE_STEP_MODE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK 0x000003cc /* RW-4R */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK__PRIV_LEVEL_MASK 0x00000314 /* */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_RSVD1 2:2 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP 3:3 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_J 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK 5:5 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG 6:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG 7:7 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM 9:9 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT 10:10 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR 12:12 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR 13:13 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC 14:14 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG 15:15 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG 16:16 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_RSVD 30:17 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_RSVD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD 0x000003d0 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_ICD_CMD__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC 4:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_STOP 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_J 0x00000006 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RCSR 0x00000010 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_WCSR 0x00000011 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RPC 0x00000012 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_RFREG 0x00000013 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_OPC_WFREG 0x00000014 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_SZ 7:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_SZ_B 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_SZ_HW 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_SZ_W 0x00000002 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_SZ_DW 0x00000003 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX 12:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG0 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG16 0x00000010 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG17 0x00000011 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG18 0x00000012 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG19 0x00000013 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG20 0x00000014 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG21 0x00000015 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG22 0x00000016 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG23 0x00000017 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG24 0x00000018 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG25 0x00000019 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG26 0x0000001a /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG27 0x0000001b /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG28 0x0000001c /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG29 0x0000001e /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG30 0x0000001e /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_REG31 0x0000001f /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_ERROR 14:14 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_ERROR_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_BUSY 15:15 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_BUSY_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_PARM 31:16 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_CMD_PARM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR0 0x000003d4 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR0__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR0_ADDR 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR0_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR1 0x000003d8 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR1__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR1_ADDR 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_ADDR1_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA0 0x000003dc /* RW-4R */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA0__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA0_DATA 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA0_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA1 0x000003e0 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA1__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA1_DATA 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_ICD_WDATA1_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0 0x000003e4 /* R--4R */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_DATA 31:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_ROB_FULL 0:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_SSINT 1:1 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_SSINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_SSINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MSINT 3:3 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MSINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MSINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_STINT 5:5 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_STINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_STINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MTINT 7:7 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MTINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MTINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_SEINT 9:9 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_SEINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_SEINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MEINT 11:11 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MEINT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT3_MEINT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE 1:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ACTIVE 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_INACTIVE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ICD 0x00000002 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_RS0 3:2 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_RS0_VALUE 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_TRIGGER_HIT_INDEX 10:4 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_RS1 31:11 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA0_RSTAT4_RS1_VALUE 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1 0x000003e8 /* R--4R */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_DATA 31:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IAMA 0:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IAMA_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IAMA_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IFAULT 1:1 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_ILL 2:2 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_ILL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_ILL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_BKPT 3:3 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_BKPT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_BKPT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LAMA 4:4 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LAMA_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LAMA_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LFAULT 5:5 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SAMA 6:6 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SAMA_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SAMA_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SFAULT 7:7 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_UCALL 8:8 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_UCALL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_UCALL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SCALL 9:9 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SCALL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SCALL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_MCALL 11:11 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_MCALL_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_MCALL_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IPFAULT 12:12 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LPFAULT 13:13 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SPFAULT 15:15 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP 28:28 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP 29:29 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_EXPT 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT4_RS 31:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_ICD_RDATA1_RSTAT4_RS_VALUE 0x00000000 /* R---V */
|
|
#define NV_PRISCV_RISCV_RPC 0x000003ec /* R--4R */
|
|
#define NV_PRISCV_RISCV_RPC__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_RPC_PC_LO 31:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0 0x000003f0 /* R--4R */
|
|
#define NV_PRISCV_RISCV_RSTAT0__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_RSTAT0_ROB_FULL 0:0 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */
|
|
#define NV_PRISCV_RISCV_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */
|
|
#define NV_PRISCV_RISCV_TRACECTL 0x00000400 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_TRACECTL__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_TRACECTL__PRIV_LEVEL_MASK 0x00000318 /* */
|
|
#define NV_PRISCV_RISCV_TRACECTL_LOW_THSHD 7:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_LOW_THSHD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_HIGH_THSHD 15:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_HIGH_THSHD_INIT 0x000000ff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE 20:20 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_UMODE_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE 21:21 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_SMODE_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE 23:23 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_MMODE_ENABLE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_MODE 25:24 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_MODE_FULL 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_MODE_REDUCED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_MODE_STACK 0x00000002 /* RW--V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_BELOW_LO 27:27 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_BELOW_LO_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_ABOVE_HI 28:28 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_ABOVE_HI_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE 29:29 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_INTR_ENABLE_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_FULL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACECTL_EMPTY 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACECTL_EMPTY_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX 0x00000404 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX__PRIV_LEVEL_MASK 0x00000318 /* */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_RDIDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD0 15:8 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD0_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_MAXIDX_INIT 0x0000003f /* R-I-V */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD1 31:24 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_TRACE_RDIDX_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_TRACE_WTIDX 0x00000408 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_TRACE_WTIDX__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_TRACE_WTIDX__PRIV_LEVEL_MASK 0x00000318 /* */
|
|
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACE_WTIDX_WTIDX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACE_WTIDX_RSVD1 23:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_TRACE_WTIDX_RSVD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_TRACEPC_HI 0x00000410 /* RW-4R */
|
|
#define NV_PRISCV_RISCV_TRACEPC_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_TRACEPC_HI__PRIV_LEVEL_MASK 0x00000318 /* */
|
|
#define NV_PRISCV_RISCV_TRACEPC_HI_PC 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEPC_HI_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_TRACEPC_LO 0x0000040c /* RW-4R */
|
|
#define NV_PRISCV_RISCV_TRACEPC_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_DEBUG /* */
|
|
#define NV_PRISCV_RISCV_TRACEPC_LO__PRIV_LEVEL_MASK 0x00000318 /* */
|
|
#define NV_PRISCV_RISCV_TRACEPC_LO_PC 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_TRACEPC_LO_PC_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_HI 0x000003c4 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_HI__PRIV_LEVEL_MASK 0x00000300 /* */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_HI_VALUE 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_HI_VALUE_INIT 0xffffffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_LO 0x000003c0 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_LO__PRIV_LEVEL_MASK 0x00000300 /* */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_LO_VALUE 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MTIMECMP_LO_VALUE_INIT 0xffffffff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS 0x00000394 /* R-I4R */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS__PRIV_LEVEL_MASK 0x00000300 /* */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_S_SOFTWARE_INTR 5:5 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_S_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_S_EXTERNAL_INTR 4:4 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_S_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_S_TIMER_INTR 3:3 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_S_TIMER_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_SOFTWARE_INTR 2:2 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_M_SOFTWARE_INTR 2:2 /* */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_M_SOFTWARE_INTR_INIT 0 /* */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_EXTERNAL_INTR 1:1 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_M_EXTERNAL_INTR 1:1 /* */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_M_EXTERNAL_INTR_INT 0 /* */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_TIMER_INTR 0:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_TIMER_INTR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_M_TIMER_INTR 0:0 /* */
|
|
#define NV_PRISCV_RISCV_INTR_STATUS_M_TIMER_INTR_INIT 0 /* */
|
|
#define NV_PRISCV_RISCV_MSIP 0x0000038c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_MSIP__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_MSIP__PRIV_LEVEL_MASK 0x0000031c /* */
|
|
#define NV_PRISCV_RISCV_MSIP_VLD 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_MSIP_VLD_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_MSIP_VLD_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT 0x00000500 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT__PRIV_LEVEL_MASK NV_PRISCV_FALCON_EXE_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT_RESERVED 30:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_INFO 0x00000504 /* R-I4R */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_INFO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_INFO__PRIV_LEVEL_MASK NV_PRISCV_FALCON_EXE_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_INFO_ERROR_INFO 31:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_INFO_ERROR_INFO_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR 0x00000508 /* R-I4R */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR__PRIV_LEVEL_MASK NV_PRISCV_FALCON_EXE_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI 0x0000050c /* R-I4R */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI__PRIV_LEVEL_MASK NV_PRISCV_FALCON_EXE_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_PRIV_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT 0x00000510 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_PIC /* */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT__PRIV_LEVEL_MASK NV_PRISCV_FALCON_EXE_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT_RESERVED 30:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_HUB_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_INDEX 0x00000590 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_INDEX__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_ROM_PATCH /* */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_INDEX_INDEX 4:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_INDEX_INDEX_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_ADDR_VALID 0x00000594 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_ADDR_VALID__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_ROM_PATCH /* */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR 17:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_DATA 0x00000598 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_DATA__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_ROM_PATCH /* */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_DATA_DATA 15:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_CAM_DATA_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_SECURE 0x0000059c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_SECURE__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_ROM_PATCH /* */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK_INIT 0x00000001 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_INDEX 0x000005b0 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_INDEX__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_INDEX__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_INDEX_VAL 4:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_INDEX_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG 0x000005b4 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_READ 0:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_READ_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_READ_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_WRITE 1:1 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_WRITE_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_WRITE_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER 15:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_ALL_MASTERS_ENABLED 0x00000ff7 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_FBDMA 4:4 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_FBDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_FBDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_CPDMA 5:5 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_CPDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_CPDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_SHA 6:6 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_SHA_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_SHA_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_PMB(i) (8+(i)):(8+(i)) /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_PMB__SIZE_1 8 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_PMB_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_MASTER_PMB_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_LOCK 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_CFG_LOCK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_HI 0x000005bc /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_HI__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_HI_VAL 28:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO 0x000005b8 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO_VAL 31:0 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO_ABOVE1K 31:7 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO_ABOVE1K_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO_1K 6:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ADDR_LO_1K_INIT 0x0000007f /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE(i) (0x000005c0+(i)*4) /* RWI4A */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE__SIZE_1 2 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE_VAL_ENTRY(i) (1+2*(i)):(2*(i)) /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE_VAL_ENTRY__SIZE_1 16 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE_VAL_ENTRY_OFF 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_MODE_VAL_ENTRY_NAPOT 0x00000003 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_STAT 0x000005e0 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_STAT__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_STAT__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_STAT_VALID 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_STAT_VALID_TURE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO 0x000005e4 /* R-I4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER 3:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_FBDMA 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_CPDMA 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_SHA 0x00000002 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB0 0x00000004 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB1 0x00000005 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB2 0x00000006 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB3 0x00000007 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB4 0x00000008 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB5 0x00000009 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB6 0x0000000a /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_MASTER_PMB7 0x0000000b /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_READ 4:4 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_READ_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_READ_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_ENTRY 21:16 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_INFO_ENTRY_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_HI 0x000005ec /* R-I4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_HI__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_LO 0x000005e8 /* R-I4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_LO__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_LO_ADDR 31:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_ADDR_LO_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN 0x000005f0 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_IOPMP /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER 11:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_ALL_MASTERS_ENABLED 0x00000fff /* RWI-V */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA 0:0 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA 1:1 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA 2:2 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB(i) (4+(i)):(4+(i)) /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB__SIZE_1 8 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFMOFFS 0x00000570 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFMOFFS__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_SCP /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFMOFFS__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFMOFFS_OFFS 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD 0x00000574 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_SCP /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SUPPRESS 2:2 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SUPPRESS_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SUPPRESS_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SHORTCUT 3:3 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SHORTCUT_DISABLE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SHORTCUT_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_IMEM 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_IMEM_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_WRITE 5:5 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_WRITE_FALSE 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_GPR 8:6 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_GPR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SIZE 8:6 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SIZE_16B 2 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SIZE_32B 3 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SIZE_64B 4 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SIZE_128B 5 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_SIZE_256B 6 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_CCI_EX 15:15 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_CCI_EX_SCPDMA 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_CCI_EX_CCI 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_CCI_CMD 31:16 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_CCI_CMD_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_RY 19:16 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_RX_OR_IMM 25:20 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE 31:26 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_NOP 0 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_MOV 1 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_PUSH 2 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_FETCH 3 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_RAND 4 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE0 5 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE0 6 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE1 7 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE1 8 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_CHMOD 10 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_XOR 11 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_ADD 12 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_AND 13 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_BSWAP 14 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_CMAC_SK 15 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_SECRET 16 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_KEY 17 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_RKEY10 18 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_RKEY1 19 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT 20 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_DECRYPT 21 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_COMPARE_SIG 22 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT_SIG 23 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMATRFCMD_OPCODE_FORGET_SIG 24 /* */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL 0x00000578 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_SCP /* */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_DMA_ACTIVE 0:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_DMA_ACTIVE_IDLE 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_DMA_ACTIVE_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_ERROR_CLR 4:4 /* -WXVF */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_ERROR_CODE 9:8 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_ERROR_CODE_NO_ERROR 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_ERROR_CODE_NOT_SIZE_ALIGNED 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_ERROR_CODE_SECRET_NOT_ALLOWED 0x00000002 /* R---V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_WCOUNT 19:16 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_WCOUNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_RCOUNT 23:20 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_RCOUNT_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_REQQ_NUM 27:24 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_REQQ_NUM_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_SCPDMAPOLL_REQQ_DEPTH 31:28 /* R-XVF */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK(i) (0x00000580+(i)*4) /* RWI4A */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK__SIZE_1 2 /* */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_KEY /* */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_LOCK(i) (0x00000588+(i)*4) /* RWI4A */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_LOCK__SIZE_1 2 /* */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_LOCK__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_KEY /* */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_LOCK__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_LOCK_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_SCP_SECRET_MASK_LOCK_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE 0x0000065c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_RESULT 1:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_RESULT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_RESULT_RUNNING 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_RESULT_FAIL 0x00000002 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_RESULT_PASS 0x00000003 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE 7:2 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_ENTRY 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_INIT_DEVICE 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_LOAD_PUBLIC_KEY 0x00000002 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_LOAD_PKC_BOOT_PARAM 0x00000003 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_SHA_MANIFEST 0x00000004 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_VERIFY_MANIFEST_SIGNATURE 0x00000005 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_DECRYPT_MANIFEST 0x00000006 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_SANITIZE_MANIFEST 0x00000007 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_LOAD_FMC 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_VERIFY_FMC_DIGEST 0x00000009 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_DECRYPT_FMC 0x0000000a /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_DECRYPT_FUSEKEY 0x0000000b /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_REVOKE_RESOURCE 0x0000000c /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_PHASE_CONFIGURE_FMC_ENV 0x0000000d /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME 17:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_DMA_FB_ADDRESS_ERROR 0x00000020 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_DMA_NACK_ERROR 0x00000021 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SHA_ACQUIRE_MUTEX_ERROR 0x00000040 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SHA_EXECUTION_ERROR 0x00000041 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_DIO_READ_ERROR 0x00000060 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_DIO_WRITE_ERROR 0x00000061 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SE_PDI_INVALID_ERROR 0x00000080 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SE_PKEYHASH_INVALID_ERROR 0x00000081 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SW_PKEY_DIGEST_ERROR 0x00000082 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SE_PKA_RETURN_CODE_ERROR 0x00000083 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SCP_LOAD_SECRET_ERROR 0x000000a0 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_SCP_TRAPPED_DMA_NOT_ALIGNED_ERROR 0x000000a1 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CODE_SIZE_ERROR 0x000000c0 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CORE_PMP_RESERVATION_ERROR 0x000000c1 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DATA_SIZE_ERROR 0x000000c2 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DEVICEMAP_BR_UNLOCK_ERROR 0x000000c3 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_FAMILY_ID_ERROR 0x000000c4 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_MSPM_VALUE_ERROR 0x000000c5 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_PAD_INFO_MASK_ERROR 0x000000c6 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ADDRESS_ERROR 0x000000c7 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ENTRY_NUM_ERROR 0x000000c8 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_ERROR 0x000000c9 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_LOCK_ERROR 0x000000ca /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SIGNATURE_ERROR 0x000000cb /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_ID_ERROR 0x000000cc /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_VERSION_ERROR 0x000000cd /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_FMC_DIGEST_ERROR 0x000000e0 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_BAD_HEADER_ERROR 0x00000100 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_KEYGLOB_INVALID_ERROR 0x00000101 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_PROTECT_INFO_ERROR 0x00000102 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_SIGNATURE_ERROR 0x00000103 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_KMEM_DISPOSE_KSLOT_ERROR 0x00000120 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_KMEM_KEY_SLOT_K3_ERROR 0x00000121 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_KMEM_LOAD_KSLOT2SCP_ERROR 0x00000122 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_KMEM_READ_ERROR 0x00000123 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_KMEM_WRITE_ERROR 0x00000124 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_IOPMP_ERROR 0x00000141 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_MMIO_ERROR 0x00000142 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_SYNDROME_OK 0x000003ff /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO 31:18 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_DMA_WAIT_FOR_IDLE_HANG 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_SHA_HANG 0x00000002 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_DIO_READ_HANG 0x00000004 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_DIO_WAIT_FREE_ENTRY_HANG 0x00000008 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_DIO_WRITE_HANG 0x00000010 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_SE_ACQUIRE_MUTEX_HANG 0x00000020 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_SE_PDI_LOAD_HANG 0x00000040 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_SE_PKEYHASH_LOAD_HANG 0x00000080 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_PKA_POLL_RESULT_HANG 0x00000100 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_SCP_PIPELINE_RESET_HANG 0x00000200 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_TRAPPED_DMA_HANG 0x00000400 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_FUSEKEY_KEYGLOB_LOAD_HANG 0x00000800 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_RETCODE_INFO_KMEM_CMD_EXECUTE_HANG 0x00001000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN 0x00000660 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_MMODE /* */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN__PRIV_LEVEL_MASK NV_PRISCV_FALCON_NO_ACCESS_PRIV_LEVEL_MASK /* */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN_LOCK 0:0 /* RW-VF */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN_LOCK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN_LOCK_UNLOCKED 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_FALSE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_TRUE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_FALSE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_TRUE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL 0x00000668 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_VALID_FALSE 0x00000000 /* R-I-V */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT 4:4 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_FALCON 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_CORE_SELECT_RISCV 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH 8:8 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_TRUE 0x00000001 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_CTRL_BRFETCH_FALSE 0x00000000 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG 0x0000066c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET 1:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_LOCAL_FB 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_COHERENT_SYSMEM 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK 31:31 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_LOCK_LOCKED 0x00000001 /* RW--V */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC 0x00000694 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC__PRIV_LEVEL_MASK 0x00000690 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_WPRID 1:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMACFG_SEC_WPRID_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO 0x00000670 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI 0x00000674 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO 0x00000678 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI 0x0000067c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO 0x00000680 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI 0x00000684 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_LO 0x00000688 /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_LO__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_LO__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_HI 0x0000068c /* RWI4R */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_HI__DEVICE_MAP NV_PRISCV_DEVICE_MAP_GROUP_BROM /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_HI__PRIV_LEVEL_MASK 0x00000664 /* */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL 6:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE(i) (0x00000610+(i)*8) /* RWI4A */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE__SIZE_1 4 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_VAL_INIT 0x33333333 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_READ__SIZE_1 8 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_READ_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_READ_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_WRITE__SIZE_1 8 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_WRITE_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_WRITE_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_LOCK(i) (3+4*(i)):(3+4*(i)) /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_LOCK__SIZE_1 8 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_LOCK_LOCKED 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVMMODE_LOCK_UNLOCKED 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE(i) (0x00000614+(i)*8) /* RWI4A */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE__SIZE_1 4 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL 31:0 /* RWIVF */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL_INIT 0x33333333 /* RWI-V */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_READ__SIZE_1 8 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_DISABLE 0x00000000 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE__SIZE_1 8 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_ENABLE 0x00000001 /* */
|
|
#define NV_PRISCV_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_DISABLE 0x00000000 /* */
|
|
#endif // __ga102_dev_riscv_pri_h__
|