98 lines
9.4 KiB
C
98 lines
9.4 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_smcarb_h__
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#define __ga102_dev_smcarb_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PSMCARB 0x0000CDFF:0x0000CC00 /* RW--D */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP(i) (0x0000CC00+(i)*4) /* RW-4A */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP__SIZE_1 7 /* */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_SYS_PIPE_LOCAL_GPC_ID 5-1:0 /* RWBVF */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_SYS_PIPE_LOCAL_GPC_ID_INIT 0 /* RWB-V */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_SYS_PIPE_ID 5+7:8 /* RWBVF */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_SYS_PIPE_ID_INIT 0 /* RWB-V */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_PHYSICAL_GPC_ID 5+15:16 /* R-XVF */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_UGPU_ID 24:24 /* R-XVF */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_VALID 31:31 /* RWBVF */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_VALID_TRUE 1 /* RW--V */
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#define NV_PSMCARB_SMC_PARTITION_GPC_MAP_VALID_FALSE 0 /* RWB-V */
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#define NV_PSMCARB_SYS_PIPE_INFO 0x0000CC80 /* RW-4R */
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#define NV_PSMCARB_SYS_PIPE_INFO_MODE 0:0 /* RWBVF */
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#define NV_PSMCARB_SYS_PIPE_INFO_MODE_LEGACY 0 /* RWB-V */
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#define NV_PSMCARB_SYS_PIPE_INFO_MODE_SMC 1 /* RW--V */
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#define NV_PSMCARB_UGPU_GPC_COUNT 0x0000CC84 /* R--4R */
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#define NV_PSMCARB_UGPU_GPC_COUNT_UGPU0 5-1:0 /* R-XVF */
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#define NV_PSMCARB_UGPU_GPC_COUNT_UGPU1 5+7:8 /* R-XVF */
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#define NV_PSMCARB_TIMESTAMP_CTRL 0x0000CC8C /* RW-4R */
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#define NV_PSMCARB_TIMESTAMP_CTRL_DISABLE_TICK 0:0 /* RWBVF */
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#define NV_PSMCARB_TIMESTAMP_CTRL_DISABLE_TICK_TRUE 0x00000001 /* RW--V */
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#define NV_PSMCARB_TIMESTAMP_CTRL_DISABLE_TICK_FALSE 0x00000000 /* RW--V */
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#define NV_PSMCARB_TIMESTAMP_CTRL_DISABLE_TICK_INIT 0x00000001 /* RWB-V */
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#define NV_PSMCARB_TIMESTAMP_CTRL_DISABLE_TICK__PROD 0x00000000 /* RW--V */
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#define NV_PSMCARB_TIMESTAMP_CTRL_ZERO_TIMESTAMP 1:1 /* RWBVF */
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#define NV_PSMCARB_TIMESTAMP_CTRL_ZERO_TIMESTAMP_TRUE 0x00000001 /* RW--V */
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#define NV_PSMCARB_TIMESTAMP_CTRL_ZERO_TIMESTAMP_FALSE 0x00000000 /* RWB-V */
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#define NV_PSMCARB_DEBUG 0x0000CC90 /* R--4R */
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#define NV_PSMCARB_DEBUG_LAUNCH_ARB_STATUS 2:0 /* R-XVF */
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#define NV_PSMCARB_DEBUG_SMCARB2XBAR_OTMP_STATUS 5:3 /* R-XVF */
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#define NV_PSMCARB_DEBUG_PRI_STATUS 8:6 /* R-XVF */
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#define NV_PSMCARB_DEBUG_TIMESTAMP_STATUS 11:9 /* R-XVF */
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#define NV_PSMCARB_RELEASE_STATUS 0x0000CC94 /* R--4R */
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#define NV_PSMCARB_RELEASE_STATUS_UI_IDLE 7-1:0 /* R-XVF */
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#define NV_PSMCARB_RELEASE_STATUS_S2P_IDLE 7+15:16 /* R-XVF */
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#define NV_PSMCARB_PM 0x0000CC98 /* RW-4R */
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#define NV_PSMCARB_PM_SEL 5:0 /* RWBVF */
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#define NV_PSMCARB_PM_SEL_OUTPUT_STALL 0x00000000 /* RWB-V */
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#define NV_PSMCARB_PM_SEL_CREDIT_STALL 0x00000001 /* RW--V */
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#define NV_PSMCARB_PM_SEL_CWD_PVLD 0x00000002 /* RW--V */
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#define NV_PSMCARB_PM_SEL_COMPUTE_BUNDLE 0x00000003 /* RW--V */
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#define NV_PSMCARB_PM_SEL_GRID_CTA 0x00000004 /* RW--V */
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#define NV_PSMCARB_PM_SEL_QUEUE_CTA_ONE 0x00000005 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC0_STATUS 0x00000006 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC1_STATUS 0x00000007 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC2_STATUS 0x00000008 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC3_STATUS 0x00000009 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC4_STATUS 0x0000000A /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC5_STATUS 0x0000000B /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC6_STATUS 0x0000000C /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC7_STATUS 0x0000000D /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC0_CONN_GPC 0x0000000E /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC1_CONN_GPC 0x0000000F /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC2_CONN_GPC 0x00000010 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC3_CONN_GPC 0x00000011 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC4_CONN_GPC 0x00000012 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC5_CONN_GPC 0x00000013 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC6_CONN_GPC 0x00000014 /* RW--V */
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#define NV_PSMCARB_PM_SEL_SMC7_CONN_GPC 0x00000015 /* RW--V */
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#define NV_PSMCARB_PM_SEL_STATIC_GROUP_55_8 0x00000016 /* RW--V */
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#define NV_PSMCARB_PM_SEL_STATIC_GROUP_AA_8 0x00000017 /* RW--V */
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#define NV_PSMCARB_PM_ENABLE 31:31 /* RWBVF */
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#define NV_PSMCARB_PM_ENABLE_OFF 0x00000000 /* RWB-V */
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#define NV_PSMCARB_PM_ENABLE_ON 0x00000001 /* RW--V */
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#define NV_PSMCARB_CYA 0x0000CC9C /* RW-4R */
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#define NV_PSMCARB_CYA_REVERT_TO_GA100_HALT_STATUS 0:0 /* RWBVF */
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#define NV_PSMCARB_CYA_REVERT_TO_GA100_HALT_STATUS_TRUE 0x00000001 /* RW--V */
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#define NV_PSMCARB_CYA_REVERT_TO_GA100_HALT_STATUS_FALSE 0x00000000 /* RWB-V */
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#define NV_PSMCARB_ALLOWED_SWIZ_ID_FULL_MEM 0 /* */
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#define NV_PSMCARB_ALLOWED_SWIZ_ID_HALF_MEM(i) ((i)+1) /* */
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#define NV_PSMCARB_ALLOWED_SWIZ_ID_HALF_MEM__SIZE_1 2 /* */
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#define NV_PSMCARB_ALLOWED_SWIZ_ID_QUARTER_MEM(i) ((i)+3) /* */
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#define NV_PSMCARB_ALLOWED_SWIZ_ID_QUARTER_MEM__SIZE_1 4 /* */
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#define NV_PSMCARB_ALLOWED_SWIZ_ID_EIGHTHED_MEM(i) ((i)+7) /* */
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#define NV_PSMCARB_ALLOWED_SWIZ_ID_EIGHTHED_MEM__SIZE_1 8 /* */
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#define NV_PSMCARB_ALLOWED_UGPU(i,j) (((i)==0) || (((i)==1) && ((j)==0)) || (((i)==2) && ((j)==0))) /* */
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#define NV_PSMCARB_ALLOWED_UGPU__SIZE_1 3 /* */
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#define NV_PSMCARB_ALLOWED_UGPU__SIZE_2 1 /* */
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#define NV_PSMCARB_UGPU_NUM 1 /* */
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#define NV_PSMCARB_MAX_PARTITIONABLE_SYS_PIPES 2 /* */
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#define NV_PSMCARB_ALLOWED_SWIZZID(i) (((i)==0) || ((i)==1) || ((i)==2)) /* */
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#define NV_PSMCARB_ALLOWED_SWIZZID__SIZE_1 3 /* */
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#endif // __ga102_dev_smcarb_h__
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