15334 lines
1.8 MiB
15334 lines
1.8 MiB
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_trim_h__
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#define __ga102_dev_trim_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PTRIM 0x00138FFF:0x00130000 /* RW--D */
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#define NV_PVTRIM 0x0000FFFF:0x0000E800 /* RW--D */
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#define NV_PTRIM_CLK /* ----G */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX 8:0 /* RW-VF */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_DEBUGPORTCLK 0x0000000f /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_DRAMCLK 0x00000020 /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_GPC2CLK 0x00000000 /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_HUB2CLK 0x00000008 /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_LEGCLK 0x00000009 /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_LTC2CLK 0x00000001 /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_NVDCLK 0x0000000e /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_PWRCLK 0x0000000c /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_REFCLK 0x00000021 /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_RSTCLK 0x0000000a /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_SYS2CLK 0x00000007 /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_UTILSCLK 0x0000000b /* R---V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_XBAR2CLK 0x00000002 /* R---V */
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#define NV_PVTRIM_CLK /* ----G */
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#define NV_PVTRIM_CLK_NAMEMAP_INDEX 8:0 /* RW-VF */
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#define NV_PVTRIM_CLK_NAMEMAP_INDEX_AZA2BITCLK 0x00000019 /* R---V */
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#define NV_PVTRIM_CLK_NAMEMAP_INDEX_DISPCLK 0x00000018 /* R---V */
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#define NV_PVTRIM_CLK_NAMEMAP_INDEX_MAUDCLK 0x0000001c /* R---V */
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#define NV_PVTRIM_CLK_NAMEMAP_INDEX_SPDIFCLK 0x0000001a /* R---V */
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#define NV_PVTRIM_CLK_NAMEMAP_INDEX_VCLK(i) 0x00000010+(i)*1 /* R---V */
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#define NV_PVTRIM_CLK_NAMEMAP_INDEX_VCLK__SIZE_1 4 /* R---V */
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#define NV_PTRIM_PLL /* ----G */
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#define NV_PTRIM_PLL_NAMEMAP_INDEX 8:0 /* RW-VF */
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#define NV_PTRIM_PLL_NAMEMAP_INDEX_DRAMPLL 0x00000020 /* R---V */
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#define NV_PTRIM_PLL_NAMEMAP_INDEX_GPCPLL 0x00000000 /* R---V */
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#define NV_PTRIM_PLL_NAMEMAP_INDEX_LTCPLL 0x00000001 /* R---V */
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#define NV_PTRIM_PLL_NAMEMAP_INDEX_REFMPLL 0x00000021 /* R---V */
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#define NV_PTRIM_PLL_NAMEMAP_INDEX_SYSPLL 0x00000007 /* R---V */
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#define NV_PTRIM_PLL_NAMEMAP_INDEX_XBARPLL 0x00000002 /* R---V */
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#define NV_PVTRIM_PLL /* ----G */
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#define NV_PVTRIM_PLL_NAMEMAP_INDEX 8:0 /* RW-VF */
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#define NV_PVTRIM_PLL_NAMEMAP_INDEX_SPPLL0 0x00000030 /* R---V */
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#define NV_PVTRIM_PLL_NAMEMAP_INDEX_SPPLL1 0x00000031 /* R---V */
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#define NV_PVTRIM_PLL_NAMEMAP_INDEX_VPLL(i) 0x00000010+(i)*1 /* R---V */
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#define NV_PVTRIM_PLL_NAMEMAP_INDEX_VPLL__SIZE_1 4 /* R---V */
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#define NV_PTRIM_GPC_BCAST 0x00132BFF:0x00132800 /* RW--D */
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#define NV_PTRIM_GPC 0x001E3FFF:0x001E0000 /* RW--D */
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#define NV_PTRIM_GPC_ARRAY_STRIDE 1024 /* */
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#define NV_PTRIM_GPC_ARRAY_SIZE 7 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK(i) (0x001e03a0+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK(i) (0x001e03b0+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK 0x00137b00 /* RW-4R */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK 0x00137b40 /* RW-4R */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK 0x00137b80 /* RW-4R */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK 0x00137bc0 /* RW-4R */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK 0x00137c14 /* RW-4R */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK 0x00137c54 /* RW-4R */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PCIE_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK 0x00137c94 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_STATIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK 0x00137cd4 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_XTAL4X_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK 0x00137f44 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL_L2 0x0000000C /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_CLOCKDEBUG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK(i) (0x001e0140+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ONLY_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_poison_pill" /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK 0x00137f30 /* RW-4R */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ONLY_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_poison_pill" /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK 0x00137f34 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "utilsclk_priv_secure" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_UTILSCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_IFF_GSP_ENABLED 0x0000004E /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK 0x00137f38 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_pwrclk" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_PWRCLK_SWITCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_IFF_GSP_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK 0x00137f3c /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "tsense_clk_priv_secure" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK 0x00137f40 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "trimmer_ctrl_priv_secure" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x00137f48 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "syspll_physical_damage" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x00137f4c /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xbarpll_physical_damage" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XBARPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x00137f50 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "nvdpll_physical_damage" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x00137f8c /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gpcpll_physical_damage" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GPCPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK 0x00137f58 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWC-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "xtal4x_priv_secure" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_XTAL4X_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_IFF_GSP_ENABLED 0x0000004E /* RWC-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK 0x00137f68 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWFVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWF-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWFVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWF-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_mclk" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWFVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWFVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWFVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWFVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWFVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_MCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_FBFALCON_ENABLED 0x0000204E /* RWF-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK 0x00137f70 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK 0x00137f74 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK 0x00137f78 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_BYPASSCTRL_SYS_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK 0x00137f7c /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_AVFS_REFCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK 0x00137f80 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GLOBAL_SRC_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK 0x00137f84 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_pwrclk" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_GC5_STOPCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_SEC2_IFF_ENABLED 0x00000044 /* RWI-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK(i) (0x001e014c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "tsense_clk_priv_secure" /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK(i) (0x001e0150+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "trimmer_ctrl_priv_secure" /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK 0x00137f5c /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fuse_clk" /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_FUSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK 0x00137f60 /* RW-4R */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL_ALL 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_PRIV_SECURE_HOSTCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_GPC_SEL_VCO(i) (0x001e0044+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_SEL_VCO__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_SEL_VCO__PRIV_LEVEL_MASK NV_PTRIM_GPC_POISON_PILL_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_SEL_VCO_GPC2CLK_OUT 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_SEL_VCO_GPC2CLK_OUT_BYPASS 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_SEL_VCO_GPC2CLK_OUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_SEL_VCO_GPC2CLK_OUT_VCO 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_SEL_VCO_GPC2CLK_OUT_OVERRIDE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_SEL_VCO_GPC2CLK_OUT_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO(i) (0x001e0054+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO_GPC2CLK_OUT 0:0 /* R--UF */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO_GPC2CLK_OUT_BYPASS 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO_GPC2CLK_OUT_VCO 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL(i) (0x001e0058+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC 1:0 /* RWEUF */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY2 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY3 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY4 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_GPCCLK_MODE 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_GPCCLK_MODE_GPCNAFLL 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_GPCCLK_MODE_GPCPLL 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_GPCCLK_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_GPCPLL_CLK_DIVIDE_GPC 5:4 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_GPCPLL_CLK_DIVIDE_GPC_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_BYPASS 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_BYPASS_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_ASYNC_MODE 8:7 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_OUT(i) (0x001e0060+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCCLK_OUT__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV 5:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY10P5 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY11P5 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY12P5 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY13P5 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY14P5 0x0000001B /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY15P5 0x0000001D /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY16P5 0x0000001F /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY1P5 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY2P5 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY3P5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY4P5 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY5P5 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY6P5 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY7P5 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY8P5 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_BY9P5 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_BYPDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV 13:8 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY10P5 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY11P5 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY12P5 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY13P5 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY14P5 0x0000001B /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY15P5 0x0000001D /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY16P5 0x0000001F /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY1P5 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY2P5 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY3P5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY4P5 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY5P5 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY6P5 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY7P5 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY8P5 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_BY9P5 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_VCODIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_LOAD_CNT 21:20 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_OUT_LOAD_CNT_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_GATECLKDLY 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_OUT_GATECLKDLY_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_INT_CLOCK_GATING 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_OUT_INT_CLOCK_GATING_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_INT_CLOCK_GATING_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_INT_CLOCK_GATING_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_INT_CLOCK_GATING__PROD 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_SDIV14 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_OUT_SDIV14_INDIV1_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_SDIV14_INDIV4_MODE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_OUT_SDIV14_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW(i) (0x001e0064+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_PDIV_DELAY_CYCLES 1:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_PDIV_DELAY_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_CLK2PWR_USE_OVERRIDE 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_CLK2PWR_USE_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_CLK2PWR_FPDIV_ACK_OVERRIDE 21:21 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_CLK2PWR_FPDIV_ACK_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_FPDIV_SM_STATE 26:24 /* R--UF */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_FPDIV_ACK 27:27 /* R--UF */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_ASYNC_MODE 28:28 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_PDIV_SLOW_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG(i) (0x001e0070+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT 15:0 /* RWEUF */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPC2CLK_OUT 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCCLK_PHASEGEN 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_FINAL_MUX 17:16 /* RWIUF */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_FINAL_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_MUX_INTERNAL 28:24 /* RWIUF */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_MUX_INTERNAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DATA(i) (0x001e0074+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DATA_READ_DATA 5:0 /* R--UF */
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#define NV_PTRIM_GPC_DEBUG_OUT(i) (0x001e0100+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_DEBUG_OUT__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_DEBUG_OUT_GPCPLL_PROBE_SEL 3:0 /* RWEUF */
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#define NV_PTRIM_GPC_DEBUG_OUT_GPCPLL_PROBE_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_IND_GPC_SPARE(i) (0x001e0114+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_IND_GPC_SPARE__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_IND_GPC_SPARE_CYA0 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_IND_GPC_SPARE_CYA0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_IND_GPC_SPARE_CYA0_ZEROS 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_CONTROL_0(i) (0x001e0120+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_CONTROL_0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_CONTROL_0_GPCCLK_GR_STOPPED 30:30 /* R--UF */
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#define NV_PTRIM_GPC_CONTROL_0_GPCCLK_GR_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_CONTROL_0_GPCCLK_GR_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_CONTROL_0_GPCCLK_STOPPED 31:31 /* R--UF */
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#define NV_PTRIM_GPC_CONTROL_0_GPCCLK_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_CONTROL_0_GPCCLK_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_SPARE_0(i) (0x001e0190+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_SPARE_0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_SPARE_0_SPARECTRL_S1_NCGPCCLK 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_SPARE_0_SPARECTRL_S1_NCGPCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_SPARE_0_SPARECTRL_S2_NCGPCCLK 15:8 /* RWIUF */
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#define NV_PTRIM_GPC_SPARE_0_SPARECTRL_S2_NCGPCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0(i) (0x001e01f4+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0_CHIPLETID 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0_CHIPLETID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN 30:30 /* RWIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD0__PRIV_LEVEL_MASK NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1(i) (0x001e01f8+(i)*1024) /* -W-4A */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_PARTITIONID 7:0 /* -WIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_PARTITIONID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_MACROID 15:8 /* -WIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_MACROID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_TRIMMERID 23:16 /* -WIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_TRIMMERID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_TRIMVAL 28:24 /* -WIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_TRIMVAL_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_OP 30:30 /* -WIUF */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1_OP_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_TRIMCAST_CONTROL_CMD1__PRIV_LEVEL_MASK NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_TRIMCAST_STATUS(i) (0x001e01fc+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_TRIMCAST_STATUS__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_TRIMCAST_STATUS_VALID 0:0 /* R--UF */
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#define NV_PTRIM_GPC_TRIMCAST_STATUS_TRIMVALMATCH 1:1 /* R--UF */
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#define NV_PTRIM_GPC_TRIMCAST_STATUS__PRIV_LEVEL_MASK NV_PTRIM_GPC_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1(i) (0x001e0200+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_TESTMODE 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_BYPASSFLL 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_BYPASSFLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_BYPASSFLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_BYPASSFLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_CLK_PRE_SKP 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_CLK_PRE_SKP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_CLK_PRE_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_CLK_PRE_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_PRB_CLKOUT 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_PRB_CLKOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_PRB_CLKOUT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_PRB_CLKOUT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_RESET 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SLEEP_EN_CYA 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SLEEP_EN_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_OFFSET 10:9 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_EN_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_FLL_LOCK 16:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_FLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_FLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_DVCO_MIN_REACHED 17:17 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_DVCO_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_DVCO_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_LOCK_OR_MIN_REACHED 18:18 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_LOCK_OR_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_LOCK_OR_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_FREQLOCK 19:19 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_FREQLOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_FREQLOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SEL_PRB 21:20 /* RWEUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SEL_PRB_CLKIN 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SEL_PRB_CLKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SEL_PRB_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SEL_PRB_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_SEL_PRB_PRB_CLKIN 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG1_VFGAIN_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF(i) (0x001e0204+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV 4:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV 21:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_PDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_FLL_FRUG_MAIN 27:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_FLL_FRUG_MAIN_INIT 0x00000009 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_FLL_FRUG_FAST 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_COEFF_FLL_FRUG_FAST_INIT 0x0000000B /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2(i) (0x001e0208+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FLL_INIT 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FLL_INIT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FLL_LDMEM 15:8 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FLL_LDMEM_FORCE_LOCK 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FLL_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FLL_SWITCH_LDMEM 20:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FLL_SWITCH_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FREQLOCK_HYST 27:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_FREQLOCK_HYST_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_DVCO_MIN_REACH_HYST 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG2_DVCO_MIN_REACH_HYST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3(i) (0x001e020c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE 31:26 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW 23:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1(i) (0x001e0210+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_INIT 0x0000000C /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL 3:2 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_1 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_8 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE 8:7 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE 10:9 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI 12:11 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI_LL_MASTER 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI_LW_MASTER 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL 13:13 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK 14:14 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV 16:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK 17:17 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE 19:19 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DVCO_SPARE 23:20 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DVCO_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DUTY_TUNE 28:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DUTY_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DUTY_SKEW_EN 29:29 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DUTY_SKEW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DVCO_PD_NEB 30:30 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DVCO_PD_NEB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2(i) (0x001e0214+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL 2:1 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO1X 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO2X 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_DEBUG_SEL 11:8 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_DEBUG_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_EN_DROPCODE 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_EN_DROPCODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD 23:20 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_CHAIN_INIT 27:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_CHAIN_INIT_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_CTRL2_SRAM_VFGAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_MISC(i) (0x001e0218+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_MISC__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_MISC_DEBUG_DATA 15:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_MISC_DROPCODE_A 20:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_MISC_DROPCODE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_MISC_DROPCODE_B 25:21 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_MISC_DROPCODE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_COEFF(i) (0x001e021c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_COEFF__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_COEFF_SKP_DIVIDEND 23:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_COEFF_SKP_DIVIDEND_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_COEFF_SKP_DIVISOR 31:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_COEFF_SKP_DIVISOR_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL(i) (0x001e0220+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_EN 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_CTRL 2:1 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MIN 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_CTRL_OVERRIDE_RATIO 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_RAMP_RATE 7:3 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_RAMP_RATE_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_INRESET 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_INRESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR 12:12 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL 24:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW(i) (0x001e0224+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P14 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P33 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P5 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_2 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_4 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_FLL_TIMEOUT 11:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_FLL_TIMEOUT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_TRANSITION 12:12 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACK 13:13 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG 14:14 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA 16:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE 17:17 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA 18:18 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE 19:19 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACTIVE 20:20 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR(i) (0x001e0240+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA(i) (0x001e0244+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL0_NDIV 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL0_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL1_NDIV 24:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_DATA_VAL1_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR(i) (0x001e0248+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_READ_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_READ_DATA(i) (0x001e024c+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCLUT_READ_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_READ_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_DATA_VAL0_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_DATA_VAL1_NDIV 24:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS(i) (0x001e0250+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCLUT_STATUS__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV_OFFSET_A 12:9 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_DVCO_OFFSET_A 15:13 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_NDIV_OFFSET_B 19:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_DVCO_OFFSET_B 22:20 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_EN_OFFSET_A 23:23 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_EN_OFFSET_B 24:24 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_OFFSET_STICKY_PARITY 29:28 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_OFFSET_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_OFFSET_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_OFFSET_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_STATUS_OFFSET_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_CFG(i) (0x001e0254+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_CFG__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_CFG_TEMP_INDEX 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_CFG_TEMP_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_CFG_RAM_READ_EN 12:12 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_CFG_RAM_READ_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_CFG_RAM_READ_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_CFG_RAM_READ_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_CFG_SKIP_BAD_DOUT 25:25 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_CFG_SKIP_BAD_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_CFG_INJECT_PARITY_ERROR 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_CFG_INJECT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_CFG_STICKY_PARITY_CLEAR 27:27 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_CFG_STICKY_PARITY_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ(i) (0x001e0258+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV 3:2 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_HW_REQ 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_SW_REQ 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_NDIV 12:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_A 16:13 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_A 19:17 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_B 23:20 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_B 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE(i) (0x001e025c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_ADC_DOUT 8:1 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_ADC_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC 17:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_HW 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_SW 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_ADC_OVERRIDE_HW_ADC_DOUT 30:24 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_ACK(i) (0x001e0260+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_ACK__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_ACK_INIT_READ_LUT_DATA 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_ACK_INIT_READ_LUT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_ACK_RDACK_LUT_DEBUG 3:3 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_ACK_INIT_READ_LUT_OFFSET_DATA 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_ACK_INIT_READ_LUT_OFFSET_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_ACK_RDACK_LUT_OFFSET_DATA 5:5 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_ACK_INIT_READ_LUT_CPM_DATA 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_ACK_INIT_READ_LUT_CPM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_ACK_RDACK_LUT_CPM_DATA 7:7 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA(i) (0x001e0264+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_A 3:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_A 6:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_B 10:7 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_B 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_A 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_A 22:20 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_B 26:23 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_B 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA(i) (0x001e0268+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL0_NDIV_OFFSET_A 3:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL0_DVCO_OFFSET_A 6:4 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL0_NDIV_OFFSET_B 10:7 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL0_DVCO_OFFSET_B 13:11 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL1_NDIV_OFFSET_A 19:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL1_DVCO_OFFSET_A 22:20 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL1_NDIV_OFFSET_B 26:23 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_OFFSET_DATA_VAL1_DVCO_OFFSET_B 29:27 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA(i) (0x001e02c4+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL0_CPM_OFFSET_MAX 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL0_CPM_OFFSET_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL1_CPM_OFFSET_MAX 24:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_WRITE_CPM_DATA_VAL1_CPM_OFFSET_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_READ_CPM_DATA(i) (0x001e02c8+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCLUT_READ_CPM_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_READ_CPM_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_CPM_DATA_VAL0_CPM_OFFSET_MAX 8:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_CPM_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_READ_CPM_DATA_VAL1_CPM_OFFSET_MAX 24:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM(i) (0x001e02cc+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM_USE_HW_MAX 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM_USE_SW_MAX 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_OFFSET_MAX 12:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_OFFSET_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_HW_CPM_OFFSET_MAX 24:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_ACC_ENABLE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_ACC_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_ACC_CLEAR 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_ACC_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_ACC_CAPTURE 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_GPCLUT_SW_CTRL_CPM_CPM_ACC_CAPTURE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCLUT_CPM_ACC_DATA(i) (0x001e02d0+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCLUT_CPM_ACC_DATA__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_CPM_ACC_DATA_VALUE_LSB 31:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_CPM_ACC_DATA2(i) (0x001e02d4+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCLUT_CPM_ACC_DATA2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCLUT_CPM_ACC_DATA2_NUM_SAMPLES 27:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCLUT_CPM_ACC_DATA2_VALUE_MSB 31:28 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG1(i) (0x001e0330+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG1_REQ_EXT_TIME 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG1_REQ_EXT_TIME_INIT 0x00000400 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG1_REQ_EXT_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2(i) (0x001e0334+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2_ACK_WAIT_TIME 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2_ACK_WAIT_TIME_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2_ACK_WAIT_TIME_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2_ACK_CLR_TIME 23:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2_ACK_CLR_TIME_INIT 0x000003FD /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CFG2_ACK_CLR_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL(i) (0x001e0338+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR 18:16 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_ACK 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_CLR_ACK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_EXTEND 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_IDLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_REQ 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_REQ_CNTR(i) (0x001e033c+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_REQ_CNTR__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_REQ_CNTR_VAL 31:0 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG1(i) (0x001e0340+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG1_REQ_EXT_TIME 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG1_REQ_EXT_TIME_INIT 0x00000400 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG1_REQ_EXT_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2(i) (0x001e0344+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_WAIT_TIME 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_WAIT_TIME_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_WAIT_TIME_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_CLR_TIME 23:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_CLR_TIME_INIT 0x000003FD /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_CLR_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL(i) (0x001e0348+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR 18:16 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_ACK 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_CLR_ACK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_EXTEND 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_IDLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_REQ 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_REQ_CNTR(i) (0x001e034c+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_REQ_CNTR__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_QUICK_SLOWDOWN_B_REQ_CNTR_VAL 31:0 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG(i) (0x001e0350+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_EN 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_COMMON_INST_CONFIG 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_COMMON_INST_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_AVFS_OVERRIDE 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_AVFS_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_HARD_MACRO_UPDATE 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_HARD_MACRO_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_FAILURE_COUNT_MODE 12:12 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_FAILURE_COUNT_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_FAILURE_COUNT_THRESH 17:13 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_FAILURE_COUNT_THRESH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_PATH_COUNT_THRESH 22:18 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_PATH_COUNT_THRESH_INIT 0x0000001E /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_SPARE_CONFIG 31:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_SPARE_CONFIG_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_SPARE_CONFIG_VALID_WAIT_THRESHOLD 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CFG_CPM_SPARE_CONFIG_VALID_WAIT_THRESHOLD_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_FSM_CTRL(i) (0x001e0354+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_FSM_CTRL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_FSM_CTRL_CPM_FSM_CTRL_CONFIG 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_FSM_CTRL_CPM_FSM_CTRL_CONFIG_INIT 0x3F33FFFF /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE(i) (0x001e0358+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_OUTPUT_VALID 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_OUTPUT_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL_EN 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL 15:4 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_TIMING_STATUS 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE_TIMING_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE2(i) (0x001e035c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE2_TIMING_FAILURE_COUNT 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE2_TIMING_FAILURE_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE2_MACRO_FAILURE_COUNT 16:12 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_OVERRIDE2_MACRO_FAILURE_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS0(i) (0x001e0360+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS0_CPM_OUTPUT_VALID 0:0 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS0_CPM_TIMING_FAILURE_COUNT 9:1 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS0_CPM_MACRO_TIMING_STATUS 31:16 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS1(i) (0x001e0364+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS1_CPM_HARD_MACRO_CTRL 11:0 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_STATUS1_CPM_INSTANCE_PROGRAMMED 31:16 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_MISC(i) (0x001e0368+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_AVFS_CPM_MISC__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_MISC_CPM_MISC_OUT 23:0 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG(i) (0x001e036c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_PAUSE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_PAUSE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_PAUSE_SET 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_PAUSE_UNSET 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_CLEAR 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_CLEAR_SET 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_CLEAR_UNSET 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN 5:4 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN 7:6 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG 9:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN 11:10 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_SAMPLE_WINDOW 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_CLK_CFG_SAMPLE_WINDOW_INIT 0x00000800 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_LOW(i) (0x001e0370+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_LOW__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_LOW_THRESHOLD_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_LOW_THRESHOLD_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_HIGH(i) (0x001e0374+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_HIGH__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_HIGH_THRESHOLD_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_THRESHOLD_HIGH_THRESHOLD_HIGH_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_DEBUG(i) (0x001e0378+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_AVFS_CPM_DEBUG__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_DEBUG_CURRENT_CPM_OFFSET 8:0 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_DEBUG2(i) (0x001e037c+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_AVFS_CPM_DEBUG2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_DEBUG2_SAMPLED_ERROR_COUNT 31:0 /* R--UF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0(i) (0x001e0380+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_0_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_0_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_0_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_0_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_0_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_0_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_1_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_1_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_1_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_1_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_1_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_1_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_2_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_2_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_2_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_2_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_2_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_2_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_3_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_3_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_3_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_3_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_3_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG0_CPM_PATH_3_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1(i) (0x001e0384+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_4_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_4_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_4_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_4_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_4_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_4_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_5_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_5_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_5_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_5_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_5_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_5_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_6_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_6_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_6_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_6_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_6_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_6_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_7_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_7_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_7_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_7_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_7_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG1_CPM_PATH_7_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2(i) (0x001e0388+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_8_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_8_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_8_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_8_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_8_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_8_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_9_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_9_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_9_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_9_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_9_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_9_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_10_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_10_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_10_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_10_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_10_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_10_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_11_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_11_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_11_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_11_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_11_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG2_CPM_PATH_11_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3(i) (0x001e038c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_12_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_12_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_12_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_12_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_12_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_12_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_13_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_13_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_13_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_13_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_13_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_13_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_14_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_14_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_14_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_14_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_14_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_14_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_15_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_15_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_15_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_15_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_15_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG3_CPM_PATH_15_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4(i) (0x001e0390+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_16_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_16_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_16_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_16_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_16_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_16_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_17_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_17_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_17_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_17_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_17_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_17_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_18_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_18_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_18_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_18_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_18_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_18_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_19_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_19_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_19_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_19_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_19_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG4_CPM_PATH_19_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5(i) (0x001e0394+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_20_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_20_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_20_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_20_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_20_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_20_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_21_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_21_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_21_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_21_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_21_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_21_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_22_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_22_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_22_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_22_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_22_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_22_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_23_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_23_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_23_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_23_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_23_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG5_CPM_PATH_23_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6(i) (0x001e0398+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_24_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_24_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_24_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_24_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_24_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_24_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_25_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_25_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_25_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_25_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_25_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_25_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_26_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_26_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_26_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_26_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_26_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_26_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_27_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_27_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_27_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_27_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_27_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG6_CPM_PATH_27_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7(i) (0x001e039c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_28_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_28_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_28_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_28_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_28_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_28_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_29_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_29_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_29_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_29_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_29_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_29_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_30_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_30_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_30_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_30_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_30_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_30_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_31_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_31_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_31_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_31_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_31_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_AVFS_CPM_PATH_CFG7_CPM_PATH_31_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG(i) (0x001e0270+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPC2CLK_NAFLL 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCCLK_NOBG_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCCLK_NOEG_CTS_PROBE 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCNAFLL_CLKOUT_PRE_SKP 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCNAFLL_UPD_CLK 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCPLL_OUT 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPC_CHIPLET_TCLKOUT 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CNT0(i) (0x001e0274+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CNT0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CNT1(i) (0x001e0278+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CNT1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG(i) (0x001e027c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_AVFS_REFCLK 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPC2CLK_NAFLL 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCCLK_NOBG_CTS_PROBE 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCCLK_NOEG_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCNAFLL_CLKOUT_PRE_SKP 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCNAFLL_UPD_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCPLL_DIV2_FMON 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT0(i) (0x001e0280+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT1(i) (0x001e0284+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL(i) (0x001e0290+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_IDDQ_SETTLE_DELAY_US 0x00000007 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ZERO_UV 0x0006DDD0 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_STEP_SIZE_UV 0x0000186A /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_IDDQ 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_RESET 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SETUP 19:4 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_CLR 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_CLR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_CLR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_CLR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_ENABLE 21:21 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CAPTURE_ACC 22:22 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CAPTURE_ACC_CONTINUAL_CAPTURE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CAPTURE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CAPTURE_ACC_PAUSE_CAPTURE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_SEL 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_SEL_CALIBRATED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ACC_SEL_UNCALIBRATED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT 28:25 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_OUT 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_UNBUF 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_0P85V_UNCAL_OUT 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_ADC_TESTIN_OUT 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_CVDD_SENSE_OUT 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_GNDA_OUT 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_HIZ 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_INBUF_OUTN_OUT 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_INBUF_OUTP_OUT 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_IREFIN100U_TEST_IN 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_IREFOUT50U_TEST_OUT 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_SPARE 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VBG 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VINPTEST_EXT_IN 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VREFN_OUT 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VREFP_OUT 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE_BG 30:30 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE_BG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_ENABLE_BG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_RDACK_ADC_ACC 31:31 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_RDACK_ADC_ACC_CONTINUAL_CAPTURE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL_RDACK_ADC_ACC_PAUSE_CAPTURE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_MONITOR(i) (0x001e0294+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_MONITOR__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_MONITOR_ADC_DOUT 9:2 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_MONITOR_ADC_STAT 23:16 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_ACC(i) (0x001e029c+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_ACC__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_ACC_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_NUM_SAMPLES(i) (0x001e02a0+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_NUM_SAMPLES__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_NUM_SAMPLES_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL(i) (0x001e02a4+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_GAIN 12:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_GAIN_INIT 0x00000400 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_OFFSET 25:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_DISABLE 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_DISABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CAL_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2(i) (0x001e02a8+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OFFSET 6:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL 9:8 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE 10:10 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT 11:11 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_GAIN 20:16 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_GAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL3(i) (0x001e02ac+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL3__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL3_SETUP2 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL3_SETUP2_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL4(i) (0x001e02b0+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL4__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL4_SETUP3 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCNAFLL_ADC_CTRL4_SETUP3_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_HIGH_GPCCLK_DIV2(i) (0x001e02f0+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_HIGH_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_HIGH_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_HIGH_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_HIGH_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_LOW_GPCCLK_DIV2(i) (0x001e02f4+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_LOW_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_LOW_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_LOW_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_THRESHOLD_LOW_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2(i) (0x001e02f8+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2(i) (0x001e02fc+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2(i) (0x001e0300+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2(i) (0x001e0304+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2(i) (0x001e0308+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2(i) (0x001e030c+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_TEST_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2(i) (0x001e0310+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2(i) (0x001e0314+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2(i) (0x001e0318+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_2_GPCCLK_DIV2(i) (0x001e031c+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_2_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_2_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_LOAD_DATA_STATUS_2_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2(i) (0x001e0320+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2(i) (0x001e0324+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2(i) (0x001e0328+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_1_GPCCLK_DIV2(i) (0x001e032c+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_1_GPCCLK_DIV2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_1_GPCCLK_DIV2__PRIV_LEVEL_MASK NV_PTRIM_GPC_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_GPC_FMON_DEBUG_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0(i) (0x001e00b0+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ 5:0 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ_FORCE 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_DELAYADJ_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG 9:7 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE 10:10 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_READ_ADDR 18:11 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_READ_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_READ_ADDR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_READ_ADDR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_RO_SELECT 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_RO_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_RO_SELECT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_RO_SELECT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_MODE_CFG 27:22 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_MODE_CFG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_MODE_CFG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_MODE_CFG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_TRIGGER_SEL 30:28 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_TRIGGER_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_TRIGGER_SEL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_TRIGGER_SEL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_ENABLE 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_0_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1(i) (0x001e00b4+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL_ALT_CLK 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL_MAIN_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL 3:2 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK0 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK1 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK3 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_TEST_DATA_IN 15:4 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_TEST_DATA_IN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_TEST_DATA_IN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_TEST_DATA_IN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_DEBUG 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_DEBUG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_DEBUG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_LOCAL_RESETN 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_LOCAL_RESETN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_LOCAL_RESETN_NO 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_LOCAL_RESETN_YES 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE 21:21 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE 22:22 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CNTADJ 26:23 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CNTADJ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CNTADJ_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_CNTADJ_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ 30:27 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ_FORCE 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_1_OPDADJ_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2(i) (0x001e00b8+(i)*1024) /* R--4A */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2_DATA_OUT0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2_DATA_OUT0_FALSE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2_DATA_OUT0_TRUE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2_DATA_OUT1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2_DATA_OUT1_FALSE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_JITTER_MEASUREMENT_2_DATA_OUT1_TRUE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS(i) (0x001e0090+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE_VALUE 6:1 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_VALUE 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_DEBUG_PRB2(i) (0x001e0080+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_DEBUG_PRB2__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL 3:0 /* RWEUF */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_FAST_STEP_EN_GPCCLK 0x0000000b /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_FAST_STEP_EN_XBARCLK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_FAST_STEP_EN_XBARCLK_FROM_FBP 0x0000000a /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_QUICKSLOWDOWN_ACK2SM_0 0x0000000d /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_QUICKSLOWDOWN_ACK2SM_1 0x0000000f /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_QUICKSLOWDOWN_REQ2NAFLL_0 0x0000000c /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_QUICKSLOWDOWN_REQ2NAFLL_1 0x0000000e /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_QUICKSLOWDOWN_SM_REQ 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_DEBUG_PRB2_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG 0x00137000 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CFG_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_SYNC_MODE 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_TESTMODE 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_SSA 18:18 /* R--UF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_SSD 19:19 /* R--UF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_BYPASSPLL_CYA 21:21 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_LOOP_CTRL 23:22 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_RESETB 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_RESETB_ASSERT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_RESETB_DEASSERT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_RESETB_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG_SEL_TESTOUT 28:26 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF 0x00137004 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_NDIV_INIT 0x00000020 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_PLDIV 21:16 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CTRL 0x00137008 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_FLL_FRUG 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_FLL_FRUG_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_FLL_DIV 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_FLL_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_FLL_LD_MEM 11:4 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_FLL_LD_MEM_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_PLL_FRUG 19:12 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_PLL_FRUG_INIT 0x00000072 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_PLL_LD_MEM 27:20 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_PLL_LD_MEM_INIT 0x0000001F /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_PLL_LD_TOL 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CTRL_PLL_LD_TOL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_MISC 0x0013700c /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_MISC_EXT_FRU 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_MISC_EXT_FRU_INIT 0x00008000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2 0x00137010 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_LDIV 1:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_LDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_KP_HI 4:2 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_KP_HI_INIT 0x00000007 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_KP_LO 7:5 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_KP_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_KP_STEP_TIMER 10:8 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_KP_STEP_TIMER_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_FRAC_STEP_TIMER 13:11 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_FRAC_STEP_TIMER_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_SEL_IREF 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_SEL_IREF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_FRAC_STEP 30:15 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG2_FRAC_STEP_INIT 0x000003E8 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG3 0x00137014 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CFG3_NDIV_FRAC_SSC_MIN 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG3_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG3_NDIV_FRAC_SSC_MAX 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG3_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG4 0x00137018 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CFG4_NDIV_FRAC 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG4_NDIV_FRAC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG5 0x0013701c /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CFG5_SSC_MODE 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG5_SSC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG5_SSC_DLF 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG5_SSC_DLF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG5_SSC_DLF__PROD 0x00001388 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG6 0x00137020 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSC_DIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSC_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSC_STEP 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSC_STEP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSUG_HI 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSUG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSUG_HI__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSUG_LO 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSUG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSUG_LO__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_SSC_READY 24:24 /* R--UF */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_EN_SSC 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG6_EN_SSC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_CFG7 0x00137024 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_CFG7_HPLL_CTRL 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_CFG7_HPLL_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_SECURE 0x00137028 /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_SETUP 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_VREG10V_CTRL 29:28 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_XBARPLL_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_SECURE__PRIV_LEVEL_MASK 0x00137f4c /* */
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#define NV_PTRIM_SYS_XBARPLL_DYN 0x0013702c /* RW-4R */
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#define NV_PTRIM_SYS_XBARPLL_DYN_MODE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARPLL_DYN_MODE_DYNPLL 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARPLL_DYN_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_XBARPLL_DYN_MODE_NAFLL 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG 0x00137030 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CFG_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_SYNC_MODE 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_TESTMODE 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_SSA 18:18 /* R--UF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_SSD 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_BYPASSPLL_CYA 21:21 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_LOOP_CTRL 23:22 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_RESETB 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_RESETB_ASSERT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_RESETB_DEASSERT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_RESETB_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG_SEL_TESTOUT 28:26 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_COEFF 0x00137034 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_NDIV_INIT 0x00000020 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_PLDIV 21:16 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_COEFF__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_CTRL 0x00137038 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_FLL_FRUG 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_FLL_FRUG_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_FLL_DIV 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_FLL_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_FLL_LD_MEM 11:4 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_FLL_LD_MEM_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_PLL_FRUG 19:12 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_PLL_FRUG_INIT 0x00000072 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_PLL_LD_MEM 27:20 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_PLL_LD_MEM_INIT 0x0000001F /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_PLL_LD_TOL 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CTRL_PLL_LD_TOL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CTRL__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_MISC 0x0013703c /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_MISC_EXT_FRU 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_MISC_EXT_FRU_INIT 0x00008000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PTRIM_SYS_NVDPLL_MISC__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_CFG2 0x00137040 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_LDIV 1:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_LDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_KP_HI 4:2 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_KP_HI_INIT 0x00000007 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_KP_LO 7:5 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_KP_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_KP_STEP_TIMER 10:8 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_KP_STEP_TIMER_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_FRAC_STEP_TIMER 13:11 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_FRAC_STEP_TIMER_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_SEL_IREF 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_SEL_IREF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_FRAC_STEP 30:15 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG2_FRAC_STEP_INIT 0x000003E8 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG2__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_CFG3 0x00137044 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CFG3_NDIV_FRAC_SSC_MIN 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG3_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG3_NDIV_FRAC_SSC_MAX 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG3_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG3__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_CFG4 0x00137048 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CFG4_NDIV_FRAC 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG4_NDIV_FRAC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG4__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_CFG5 0x0013704c /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CFG5_SSC_MODE 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG5_SSC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG5_SSC_DLF 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG5_SSC_DLF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG5_SSC_DLF__PROD 0x00001388 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG5__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_CFG6 0x00137050 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSC_DIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSC_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSC_STEP 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSC_STEP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSUG_HI 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSUG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSUG_HI__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSUG_LO 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSUG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSUG_LO__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_SSC_READY 24:24 /* R--UF */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_EN_SSC 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG6_EN_SSC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG6__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_CFG7 0x00137054 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_CFG7_HPLL_CTRL 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_CFG7_HPLL_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_CFG7__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_NVDPLL_SECURE 0x00137058 /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_SETUP 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_VREG10V_CTRL 29:28 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVDPLL_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_SECURE__PRIV_LEVEL_MASK 0x00137f50 /* */
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#define NV_PTRIM_SYS_NVDPLL_DYN 0x0013705c /* RW-4R */
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#define NV_PTRIM_SYS_NVDPLL_DYN_MODE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDPLL_DYN_MODE_DYNPLL 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_DYN_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVDPLL_DYN_MODE_NAFLL 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDPLL_DYN__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_XTAL4X_CFG 0x00137090 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CFG_IDDQ 1:1 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_IDDQ_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SYNC_MODE 2:2 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SYNC_MODE_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SKIP_LOCK_POLL 3:3 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SKIP_LOCK_POLL_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SKIP_LOCK_POLL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_SKIP_LOCK_POLL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY 15:4 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_16US 0x000001B1 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_1US 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_2US 0x00000037 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_32US 0x00000361 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_40US 0x00000439 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_4US 0x0000006D /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_5US 0x00000088 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_80US 0x00000871 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_8US 0x000000D9 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_ENABLE_DELAY_INIT 0x00000088 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_CLK_GOOD 16:16 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_CLK_GOOD_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_CLK_GOOD_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_SSA 24:24 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_SSD 25:25 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_TESTMODE 26:26 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_TESTMODE_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG_STOP_SYNCMUX 30:30 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_COEFF 0x00137094 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_MDIV 7:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_MDIV_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_NDIV 15:8 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_NDIV_INIT 0x0000003C /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_PLDIV 21:16 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_PLDIV_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_COEFF__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CTRL 0x00137098 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLL_BYPASSPLL_CYA 16:16 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLL_BYPASSPLL_CYA_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_LOOP_CTRL 20:19 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_LOOP_CTRL_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_IDDQ_CYA 23:23 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_IDDQ_CYA_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_IDDQ_CYA_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_IDDQ_CYA_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_ENABLE_CYA 24:24 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_ENABLE_CYA_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_ENABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_ENABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_BYPASSPLL_CYA 25:25 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_BYPASSPLL_CYA_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_BYPASSPLL_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_BYPASSPLL_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLL_FREQLOCK 26:26 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA 31:27 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA_BY16 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA_BY2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA_BY32 0x0000001F /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA_BY4 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA_BY8 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL_PLLOUT_DIV_CYA_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CFG2 0x0013709c /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_NDIV_FRAC 15:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_NDIV_FRAC_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_LDIV 25:24 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_LDIV_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_RESETB 28:28 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_RESETB_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_RESETB_NO 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_RESETB_YES 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_SEL_TESTOUT 31:29 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG2__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2 0x001370a0 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_FLL_FRUG 2:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_FLL_FRUG_INIT 0x00000005 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_FLL_DIV 3:3 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_FLL_DIV_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_FLL_LD_MEM 11:4 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_FLL_LD_MEM_INIT 0x0000000F /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_PLL_FRUG 19:12 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_PLL_FRUG_INIT 0x00000072 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_PLL_LD_MEM 27:20 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_PLL_LD_MEM_INIT 0x0000001F /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_PLL_LD_TOL 31:28 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2_PLL_LD_TOL_INIT 0x00000004 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CTRL2__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_MISC 0x001370a4 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_MISC_EXT_FRU 15:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_MISC_EXT_FRU_INIT 0x00008000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_MISC__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CFG3 0x001370a8 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_KP_HI 5:3 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_KP_HI_INIT 0x00000007 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_KP_LO 8:6 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_KP_LO_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_KP_STEP_TIMER 11:9 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_KP_STEP_TIMER_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_FRAC_STEP_TIMER 14:12 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_FRAC_STEP_TIMER_INIT 0x00000003 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_SEL_IREF 15:15 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_SEL_IREF_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_FRAC_STEP 31:16 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG3_FRAC_STEP_INIT 0x000003E8 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG3__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CFG4 0x001370ac /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CFG4_NDIV_FRAC_SSC_MIN 15:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG4_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG4_NDIV_FRAC_SSC_MAX 31:16 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG4_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG4__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CFG5 0x001370b0 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CFG5_HPLL_CTRL 31:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG5_HPLL_CTRL_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG5__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CFG6 0x001370b4 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CFG6_SSC_MODE 15:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG6_SSC_MODE_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG6_SSC_DLF 31:16 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG6_SSC_DLF_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG6__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_CFG7 0x001370b8 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSC_DIV 7:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSC_DIV_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSC_STEP 15:8 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSC_STEP_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSUG_HI 19:16 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSUG_HI_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSUG_LO 23:20 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSUG_LO_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE 27:24 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_BYPASS 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_CLK_GOOD 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_DISABLE 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_ENABLE 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_IDDQ_DELAY 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_IDDQ_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_IDDQ_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_UNBYPASS 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_FSM_CURRENT_STATE_UNBYPASS_DELAY 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_SSC_READY 30:30 /* R--UF */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_EN_SSC 31:31 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_CFG7_EN_SSC_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_CFG7__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_XTAL4X_SECURE 0x001370bc /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_SETUP 23:0 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_SETUP_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_VREG10V_CTRL 29:28 /* RWCUF */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_XTAL4X_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWC-V */
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#define NV_PTRIM_SYS_XTAL4X_SECURE__PRIV_LEVEL_MASK 0x00137f58 /* */
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#define NV_PTRIM_SYS_GPCPLL_CFG 0x00137060 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_TESTMODE 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_SSA 18:18 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_SSD 19:19 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_BYPASSPLL_CYA 21:21 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_LOOP_CTRL 23:22 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_RESETB 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_RESETB_ASSERT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_RESETB_DEASSERT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_RESETB_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG_SEL_TESTOUT 28:26 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF 0x00137064 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV_INIT 0x00000020 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV 21:16 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CTRL 0x00137068 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_FLL_FRUG 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_FLL_FRUG_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_FLL_DIV 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_FLL_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_FLL_LD_MEM 11:4 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_FLL_LD_MEM_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_PLL_FRUG 19:12 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_PLL_FRUG_INIT 0x00000072 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_PLL_LD_MEM 27:20 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_PLL_LD_MEM_INIT 0x0000001F /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_PLL_LD_TOL 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CTRL_PLL_LD_TOL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_MISC 0x0013706c /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_MISC_EXT_FRU 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_MISC_EXT_FRU_INIT 0x00008000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2 0x00137070 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_LDIV 1:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_LDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_KP_HI 4:2 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_KP_HI_INIT 0x00000007 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_KP_LO 7:5 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_KP_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_KP_STEP_TIMER 10:8 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_KP_STEP_TIMER_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_FRAC_STEP_TIMER 13:11 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_FRAC_STEP_TIMER_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_SEL_IREF 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_SEL_IREF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_FRAC_STEP 30:15 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG2_FRAC_STEP_INIT 0x000003E8 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG3 0x00137074 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CFG3_NDIV_FRAC_SSC_MIN 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG3_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG3_NDIV_FRAC_SSC_MAX 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG3_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG4 0x00137078 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CFG4_NDIV_FRAC 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG4_NDIV_FRAC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG5 0x0013707c /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CFG5_SSC_MODE 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG5_SSC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG5_SSC_DLF 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG5_SSC_DLF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG5_SSC_DLF__PROD 0x00001388 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG6 0x00137080 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSC_DIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSC_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSC_STEP 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSC_STEP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSUG_HI 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSUG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSUG_HI__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSUG_LO 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSUG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSUG_LO__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_SSC_READY 24:24 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_EN_SSC 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG6_EN_SSC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CFG7 0x00137084 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CFG7_HPLL_CTRL 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CFG7_HPLL_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_SECURE 0x00137088 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_SETUP 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_VREG10V_CTRL 29:28 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_GPCPLL_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_SECURE__PRIV_LEVEL_MASK 0x00137f8c /* */
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#define NV_PTRIM_SYS_GPCPLL_DYN 0x0013708c /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_DYN_MODE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_DYN_MODE_DYNPLL 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_DYN_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_DYN_MODE_NAFLL 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG 0x001370d0 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CFG_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_SYNC_MODE 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_TESTMODE 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_SSA 18:18 /* R--UF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_SSD 19:19 /* R--UF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_BYPASSPLL_CYA 21:21 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_LOOP_CTRL 23:22 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_RESETB 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_RESETB_ASSERT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_RESETB_DEASSERT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_RESETB_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG_SEL_TESTOUT 28:26 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_COEFF 0x001370d4 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_MDIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_NDIV 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_NDIV_INIT 0x00000020 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_PLDIV 21:16 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_COEFF__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_CTRL 0x001370d8 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_FLL_FRUG 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_FLL_FRUG_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_FLL_DIV 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_FLL_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_FLL_LD_MEM 11:4 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_FLL_LD_MEM_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_PLL_FRUG 19:12 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_PLL_FRUG_INIT 0x00000072 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_PLL_LD_MEM 27:20 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_PLL_LD_MEM_INIT 0x0000001F /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_PLL_LD_TOL 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CTRL_PLL_LD_TOL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CTRL__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_MISC 0x001370dc /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_MISC_EXT_FRU 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_MISC_EXT_FRU_INIT 0x00008000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PTRIM_SYS_SYSPLL_MISC__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_CFG2 0x001370e0 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_LDIV 1:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_LDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_KP_HI 4:2 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_KP_HI_INIT 0x00000007 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_KP_LO 7:5 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_KP_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_KP_STEP_TIMER 10:8 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_KP_STEP_TIMER_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_FRAC_STEP_TIMER 13:11 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_FRAC_STEP_TIMER_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_SEL_IREF 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_SEL_IREF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_FRAC_STEP 30:15 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG2_FRAC_STEP_INIT 0x000003E8 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG2__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_CFG3 0x001370e4 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CFG3_NDIV_FRAC_SSC_MIN 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG3_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG3_NDIV_FRAC_SSC_MAX 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG3_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG3__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_CFG4 0x001370e8 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CFG4_NDIV_FRAC 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG4_NDIV_FRAC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG4__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_CFG5 0x001370ec /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CFG5_SSC_MODE 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG5_SSC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG5_SSC_DLF 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG5_SSC_DLF_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG5_SSC_DLF__PROD 0x00001388 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG5__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_CFG6 0x001370f0 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSC_DIV 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSC_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSC_STEP 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSC_STEP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSUG_HI 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSUG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSUG_HI__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSUG_LO 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSUG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSUG_LO__PROD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_SSC_READY 24:24 /* R--UF */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_EN_SSC 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG6_EN_SSC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG6__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_CFG7 0x001370f4 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_CFG7_HPLL_CTRL 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_CFG7_HPLL_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_CFG7__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_SYSPLL_SECURE 0x001370f8 /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_SETUP 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_VREG10V_CTRL 29:28 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_SYSPLL_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_SECURE__PRIV_LEVEL_MASK 0x00137f48 /* */
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#define NV_PTRIM_SYS_SYSPLL_DYN 0x001370fc /* RW-4R */
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#define NV_PTRIM_SYS_SYSPLL_DYN_MODE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSPLL_DYN_MODE_DYNPLL 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_DYN_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_SYSPLL_DYN_MODE_NAFLL 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSPLL_DYN__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER 0x00137124 /* RW-4R */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWEUF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000002 /* RWE-V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWEUF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWEUF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000002 /* RWE-V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWEUF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_SPARE 24:21 /* RWEUF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PTRIM_SYS_GLOBAL_SRC_CLK_SWITCH_DIVIDER__PRIV_LEVEL_MASK 0x00137f80 /* */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER 0x00137164 /* RW-4R */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x0000003C /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_GPCPLL 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL4X 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_SPARE 24:21 /* RWIUF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PTRIM_SYS_GPCPLL_CLK_SWITCH_DIVIDER__PRIV_LEVEL_MASK 0x00137f30 /* */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL 0x00137178 /* RW-4R */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL_AVFS_REFCLK_DIVIDE_SYS 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL_AVFS_REFCLK_DIVIDE_SYS_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL_AVFS_REFCLK_DIVIDE_SYS_BY2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL_AVFS_REFCLK_DIVIDE_SYS_BY3 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL_AVFS_REFCLK_DIVIDE_SYS_BY4 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL_AVFS_REFCLK_DIVIDE_SYS_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_AVFS_REFCLK_CONTROL__PRIV_LEVEL_MASK 0x00137f7c /* */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL 0x00137190 /* RW-4R */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL__PRIV_LEVEL_MASK 0x00137f34 /* */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL 5:1 /* RWEUF */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY10 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY11 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY12 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY13 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY14 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY15 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY16 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY17 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY18 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY19 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY20 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY21 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY22 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY23 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY24 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY25 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY26 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY27 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY28 0x0000001B /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY29 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY3 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY30 0x0000001D /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY31 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY32 0x0000001F /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY4 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY5 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY6 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY7 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY8 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_BY9 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_DIVIDER_SEL_INIT 0x0000000E /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_ASYNC_MODE 11:8 /* RWEUF */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SOURCE_SEL 15:12 /* RWEUF */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SOURCE_SEL_INIT 0x00000002 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SOURCE_SEL_PEX_REFCLK 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SOURCE_SEL_XTAL_CLK_0 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SOURCE_SEL_XTAL_CLK_2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SEL_OVERRIDE 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SEL_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SEL_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLOCK_SEL_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE_VALUE 19:19 /* RWEUF */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE_VALUE_ASSERT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE_VALUE_DEASSERT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE_VALUE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE 20:20 /* RWEUF */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_READY_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_SPARE 24:21 /* RWEUF */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_SPARE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_XTAL4X_UNIV_SEC_CLK_CTRL_CLK_READY 25:25 /* R--UF */
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#define NV_PTRIM_SYS_PWRCLK_CTRL 0x00137294 /* RW-4R */
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#define NV_PTRIM_SYS_PWRCLK_CTRL__PRIV_LEVEL_MASK 0x00137f38 /* */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL 5:1 /* RWIUF */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY10 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY11 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY12 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY13 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY14 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY15 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY16 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY17 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY18 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY19 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY20 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY21 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY22 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY23 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY24 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY25 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY26 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY27 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY28 0x0000001B /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY29 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY3 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY30 0x0000001D /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY31 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY32 0x0000001F /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY4 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY5 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY6 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY7 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY8 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_BY9 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_DIVIDER_SEL_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_ASYNC_MODE 9:8 /* RWIUF */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SOURCE_SEL 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SEL_OVERRIDE 18:18 /* RWIUF */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SEL_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SEL_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLOCK_SEL_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_SPARE 24:21 /* RWIUF */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PWRCLK_CTRL_CLK_READY 25:25 /* R--UF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER 0x001371a0 /* RW-4R */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWIUF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWIUF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_VCOCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_SPARE 24:21 /* RWIUF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PTRIM_SYS_SYSCLK_OUT_SWITCH_DIVIDER__PRIV_LEVEL_MASK 0x00137f74 /* */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER 0x001371a4 /* RW-4R */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWIUF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_VCOCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_SPARE 24:21 /* RWIUF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PTRIM_SYS_NVDCLK_OUT_SWITCH_DIVIDER__PRIV_LEVEL_MASK 0x00137f70 /* */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER 0x001371a8 /* RW-4R */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000004 /* RWI-V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWIUF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000008 /* RWI-V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_VCOCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL4X 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_SPARE 24:21 /* RWIUF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PTRIM_SYS_XBARCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER 0x001371c0 /* RW-4R */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x0000001C /* RWE-V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWEUF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWEUF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000002 /* RWE-V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWEUF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_SPARE 24:21 /* RWEUF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PTRIM_SYS_NVL_COMMON_CLK_ALT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER 0x00137304 /* RW-4R */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWFUF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWFUF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWFUF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DEFROST_CLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWFUF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWFUF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_SPARE 24:21 /* RWFUF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PTRIM_SYS_DRAMCLK_ALT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS 0x00137340 /* RW-4R */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_LTCPLL 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_LTCPLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_LTCPLL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_LTCPLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_XBARPLL 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_XBARPLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_XBARPLL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_XBARPLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_NVDPLL 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_NVDPLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_NVDPLL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_NVDPLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_SYSPLL 7:7 /* RWIUF */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_SYSPLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_SYSPLL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS_SYSPLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_SYS__PRIV_LEVEL_MASK 0x00137f78 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_SYSCLK 0x00137674 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_SYSCLK_SYSCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_SYSCLK_SYSCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_SYSCLK 0x00137678 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_SYSCLK_SYSCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_SYSCLK_SYSCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_SYSCLK 0x0013767c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_SYSCLK_SYSCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_SYSCLK_SYSCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SYSCLK 0x00137680 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SYSCLK_SYSCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_SYSCLK_SYSCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK 0x00137684 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_SYSCLK_SYSCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK 0x00137688 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_SYSCLK_SYSCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK 0x0013768c /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_SYSCLK_SYSCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK 0x00137690 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_SYSCLK_SYSCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK 0x00137694 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_SYSCLK_SYSCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_SYSCLK 0x00137698 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_SYSCLK_SYSCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_SYSCLK_SYSCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_SYSCLK_SYSCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_SYSCLK_SYSCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_SYSCLK 0x0013769c /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_SYSCLK_SYSCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_SYSCLK_SYSCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_SYSCLK 0x001376a0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_SYSCLK_SYSCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK 0x001376a4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_SYSCLK_SYSCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK 0x001376a8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK_SYSCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK_SYSCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_SYSCLK_SYSCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK 0x001376ac /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_SYSCLK_SYSCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_SYSCLK 0x001376b0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_SYSCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_SYSCLK_SYSCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_SYSCLK_SYSCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HUBCLK 0x001376b4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HUBCLK_HUBCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HUBCLK_HUBCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HUBCLK 0x001376b8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HUBCLK_HUBCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HUBCLK_HUBCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HUBCLK 0x001376bc /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HUBCLK_HUBCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HUBCLK_HUBCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HUBCLK 0x001376c0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HUBCLK_HUBCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HUBCLK_HUBCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK 0x001376c4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HUBCLK_HUBCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK 0x001376c8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HUBCLK_HUBCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK 0x001376cc /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HUBCLK_HUBCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK 0x001376d0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HUBCLK_HUBCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK 0x001376d4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HUBCLK_HUBCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HUBCLK 0x001376d8 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HUBCLK_HUBCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HUBCLK_HUBCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HUBCLK_HUBCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HUBCLK_HUBCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HUBCLK 0x001376dc /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HUBCLK_HUBCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HUBCLK_HUBCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_HUBCLK 0x001376e0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_HUBCLK_HUBCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK 0x001376e4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HUBCLK_HUBCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK 0x001376e8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK_HUBCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK_HUBCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HUBCLK_HUBCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK 0x001376ec /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HUBCLK_HUBCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HUBCLK 0x001376f0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HUBCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HUBCLK_HUBCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HUBCLK_HUBCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PWRCLK 0x001376f4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PWRCLK_PWRCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PWRCLK_PWRCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PWRCLK 0x001376f8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PWRCLK_PWRCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PWRCLK_PWRCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PWRCLK 0x001376fc /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PWRCLK_PWRCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PWRCLK_PWRCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PWRCLK 0x00137700 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PWRCLK_PWRCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PWRCLK_PWRCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK 0x00137704 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PWRCLK_PWRCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK 0x00137708 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PWRCLK_PWRCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK 0x0013770c /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PWRCLK_PWRCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK 0x00137710 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PWRCLK_PWRCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK 0x00137714 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PWRCLK_PWRCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PWRCLK 0x00137718 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PWRCLK_PWRCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PWRCLK_PWRCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PWRCLK_PWRCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PWRCLK_PWRCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PWRCLK 0x0013771c /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PWRCLK_PWRCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PWRCLK_PWRCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_PWRCLK 0x00137720 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_PWRCLK_PWRCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK 0x00137724 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PWRCLK_PWRCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK 0x00137728 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK_PWRCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK_PWRCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PWRCLK_PWRCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK 0x0013772c /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PWRCLK_PWRCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PWRCLK 0x00137730 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PWRCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PWRCLK_PWRCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PWRCLK_PWRCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_UTILSCLK 0x00137734 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_UTILSCLK_UTILSCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_UTILSCLK_UTILSCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_UTILSCLK 0x00137738 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_UTILSCLK_UTILSCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_UTILSCLK_UTILSCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_UTILSCLK 0x0013773c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_UTILSCLK_UTILSCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_UTILSCLK_UTILSCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_UTILSCLK 0x00137740 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_UTILSCLK_UTILSCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_UTILSCLK_UTILSCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK 0x00137744 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_UTILSCLK_UTILSCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK 0x00137748 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_UTILSCLK_UTILSCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK 0x0013774c /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_UTILSCLK_UTILSCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK 0x00137750 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_UTILSCLK_UTILSCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK 0x00137754 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_UTILSCLK 0x00137758 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_UTILSCLK 0x0013775c /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_UTILSCLK 0x00137760 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_UTILSCLK_UTILSCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK 0x00137764 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_UTILSCLK_UTILSCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK 0x00137768 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK_UTILSCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK_UTILSCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_UTILSCLK_UTILSCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK 0x0013776c /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_UTILSCLK_UTILSCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_UTILSCLK 0x00137770 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_UTILSCLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_UTILSCLK_UTILSCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_UTILSCLK_UTILSCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HOSTCLK 0x00137774 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HOSTCLK_HOSTCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_HOSTCLK_HOSTCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HOSTCLK 0x00137778 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HOSTCLK_HOSTCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_HOSTCLK_HOSTCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HOSTCLK 0x0013777c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HOSTCLK_HOSTCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_HOSTCLK_HOSTCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HOSTCLK 0x00137780 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HOSTCLK_HOSTCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_HOSTCLK_HOSTCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK 0x00137784 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_HOSTCLK_HOSTCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK 0x00137788 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_HOSTCLK_HOSTCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK 0x0013778c /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_HOSTCLK_HOSTCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK 0x00137790 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_HOSTCLK_HOSTCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK 0x00137794 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HOSTCLK 0x00137798 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HOSTCLK 0x0013779c /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_HOSTCLK 0x001377a0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_HOSTCLK_HOSTCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK 0x001377a4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_HOSTCLK_HOSTCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK 0x001377a8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK_HOSTCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK_HOSTCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_HOSTCLK_HOSTCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK 0x001377ac /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_HOSTCLK_HOSTCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HOSTCLK 0x001377b0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HOSTCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HOSTCLK_HOSTCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_HOSTCLK_HOSTCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_FUSE_CLK 0x001377f4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_FUSE_CLK_FUSE_CLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_FUSE_CLK_FUSE_CLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000C0F /* RWE-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_FUSE_CLK 0x001377f8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_FUSE_CLK_FUSE_CLK_FMON_COUNT_THRESH_LOW 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_FUSE_CLK_FUSE_CLK_FMON_COUNT_THRESH_LOW_INIT 0x00000B5B /* RWE-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_FUSE_CLK 0x001377fc /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_FUSE_CLK_FUSE_CLK_FMON_REF_WINDOW_COUNT 23:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_FUSE_CLK_FUSE_CLK_FMON_REF_WINDOW_COUNT_INIT 0x0000032A /* RWE-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_FUSE_CLK 0x00137800 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_FUSE_CLK_FUSE_CLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_FUSE_CLK_FUSE_CLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00FFFFFF /* RWE-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK 0x00137804 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_RESET_REQ 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_DC_RESET_REQ 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_DC_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_DC_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_FUSE_CLK_FUSE_CLK_FMON_ACTION_DC_RESET_REQ_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK 0x00137808 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK 0x0013780c /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_FUSE_CLK_FUSE_CLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK 0x00137810 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK__PRIV_LEVEL_MASK 0x00137cd4 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_CLEAR 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_DC_FAULT 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_DC_FAULT_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_OVERFLOW_ERROR 3:3 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_OUT_STATUS 4:4 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_FUSE_CLK_FUSE_CLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK 0x00137814 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_SEL 2:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_FUSE_CLK 0x00137818 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_DONE 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_FUSE_CLK 0x0013781c /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_FUSE_CLK 0x00137820 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_FUSE_CLK_FUSE_CLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK 0x00137824 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_FUSE_CLK_FUSE_CLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK 0x00137828 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_DEBUG 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK_FUSE_CLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REF_WINDOW 1:1 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_FUSE_CLK_FUSE_CLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK 0x0013782c /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_FUSE_CLK_FUSE_CLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_FUSE_CLK 0x00137830 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-EUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_FUSE_CLK_FUSE_CLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_FMON_CNTR_OVERFLOW_CTRL_FUSE_CLK 0x00137834 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CNTR_OVERFLOW_CTRL_FUSE_CLK__PRIV_LEVEL_MASK 0x00137c94 /* */
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#define NV_PTRIM_SYS_FMON_CNTR_OVERFLOW_CTRL_FUSE_CLK_FUSE_CLK_FMON_OVERFLOW_BIT_SEL_FIELD 4:0 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CNTR_OVERFLOW_CTRL_FUSE_CLK_FUSE_CLK_FMON_OVERFLOW_BIT_SEL_FIELD_INIT 0x0000000C /* RWE-V */
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#define NV_PTRIM_SYS_FMON_CNTR_OVERFLOW_CTRL_FUSE_CLK_FUSE_CLK_USE_CNTR_OVERFLOW_DC_FAULT 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_FMON_CNTR_OVERFLOW_CTRL_FUSE_CLK_FUSE_CLK_USE_CNTR_OVERFLOW_DC_FAULT_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PEX_REFCLK 0x001377b4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PEX_REFCLK 0x001377b8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PEX_REFCLK 0x001377bc /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PEX_REFCLK_PEX_REFCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_PEX_REFCLK_PEX_REFCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX_REFCLK 0x001377c0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX_REFCLK_PEX_REFCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_PEX_REFCLK_PEX_REFCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK 0x001377c4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_PEX_REFCLK_PEX_REFCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK 0x001377c8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK 0x001377cc /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK 0x001377d0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c54 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_PEX_REFCLK_PEX_REFCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK 0x001377d4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PEX_REFCLK 0x001377d8 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PEX_REFCLK 0x001377dc /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_PEX_REFCLK 0x001377e0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_PEX_REFCLK_PEX_REFCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK 0x001377e4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_PEX_REFCLK_PEX_REFCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK 0x001377e8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_PEX_REFCLK_PEX_REFCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK 0x001377ec /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_PEX_REFCLK_PEX_REFCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PEX_REFCLK 0x001377f0 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PEX_REFCLK__PRIV_LEVEL_MASK 0x00137c14 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_PEX_REFCLK_PEX_REFCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XCLK 0x00137900 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XCLK_XCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XCLK_XCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XCLK 0x00137904 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XCLK_XCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XCLK_XCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XCLK 0x00137908 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XCLK_XCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XCLK_XCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XCLK 0x0013790c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XCLK_XCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XCLK_XCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK 0x00137910 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XCLK_XCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK 0x00137914 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XCLK_XCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK 0x00137918 /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XCLK_XCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK 0x0013791c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK__PRIV_LEVEL_MASK 0x00137c54 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XCLK_XCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK 0x00137920 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XCLK_XCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XCLK 0x00137924 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XCLK_XCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XCLK_XCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XCLK_XCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XCLK_XCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XCLK 0x00137928 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XCLK_XCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XCLK_XCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_XCLK 0x0013792c /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_XCLK_XCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK 0x00137930 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XCLK_XCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK 0x00137934 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK_XCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK_XCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK_XCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK_XCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK_XCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XCLK_XCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK 0x00137938 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XCLK_XCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XCLK 0x0013793c /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XCLK__PRIV_LEVEL_MASK 0x00137bc0 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XCLK_XCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XCLK_XCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVL_COMMON_CLK 0x00137940 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVL_COMMON_CLK 0x00137944 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVL_COMMON_CLK 0x00137948 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVL_COMMON_CLK 0x0013794c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK 0x00137950 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK 0x00137954 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK 0x00137958 /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK 0x0013795c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK 0x00137960 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVL_COMMON_CLK 0x00137964 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVL_COMMON_CLK 0x00137968 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_NVL_COMMON_CLK 0x0013796c /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK 0x00137970 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK 0x00137974 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVL_COMMON_CLK_NVL_COMMON_CLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK 0x00137978 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVL_COMMON_CLK 0x0013797c /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVL_COMMON_CLK__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVL_COMMON_CLK_NVL_COMMON_CLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XBARCLK_DIV2 0x00137980 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XBARCLK_DIV2 0x00137984 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XBARCLK_DIV2 0x00137988 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XBARCLK_DIV2 0x0013798c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2 0x00137990 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2 0x00137994 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2 0x00137998 /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2 0x0013799c /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_XBARCLK_DIV2_XBARCLK_DIV2_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2 0x001379a0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XBARCLK_DIV2 0x001379a4 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XBARCLK_DIV2 0x001379a8 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_XBARCLK_DIV2 0x001379ac /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_XBARCLK_DIV2_XBARCLK_DIV2_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2 0x001379b0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_XBARCLK_DIV2_XBARCLK_DIV2_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2 0x001379b4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_XBARCLK_DIV2_XBARCLK_DIV2_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2 0x001379b8 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XBARCLK_DIV2 0x001379bc /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XBARCLK_DIV2__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_XBARCLK_DIV2_XBARCLK_DIV2_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVDCLK 0x001379c0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVDCLK_NVDCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_HIGH_NVDCLK_NVDCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVDCLK 0x001379c4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVDCLK_NVDCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_THRESHOLD_LOW_NVDCLK_NVDCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVDCLK 0x001379c8 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVDCLK_NVDCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_COUNT_NVDCLK_NVDCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDCLK 0x001379cc /* RW-4R */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDCLK_NVDCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_REF_WINDOW_DC_CHECK_COUNT_NVDCLK_NVDCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK 0x001379d0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_ACTION_NVDCLK_NVDCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK 0x001379d4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_CONFIG_NVDCLK_NVDCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK 0x001379d8 /* R--4R */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_ENABLE_STATUS_NVDCLK_NVDCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK 0x001379dc /* RW-4R */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK__PRIV_LEVEL_MASK 0x00137b80 /* */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_FAULT_STATUS_NVDCLK_NVDCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK 0x001379e0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_CTRL_NVDCLK_NVDCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVDCLK 0x001379e4 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVDCLK_NVDCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVDCLK_NVDCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVDCLK_NVDCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_0_NVDCLK_NVDCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVDCLK 0x001379e8 /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVDCLK_NVDCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_1_NVDCLK_NVDCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_NVDCLK 0x001379ec /* R--4R */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_LOAD_DATA_STATUS_2_NVDCLK_NVDCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK 0x001379f0 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_CLEAR_COUNTER_NVDCLK_NVDCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK 0x001379f4 /* RW-4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK_NVDCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK_NVDCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_CONFIG_NVDCLK_NVDCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK 0x001379f8 /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_0_NVDCLK_NVDCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVDCLK 0x001379fc /* R--4R */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVDCLK__PRIV_LEVEL_MASK 0x00137b00 /* */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVDCLK_NVDCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_DEBUG_STATUS_1_NVDCLK_NVDCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_MASTER_STATUS_REGISTER 0x00137a00 /* R--4R */
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#define NV_PTRIM_SYS_FMON_MASTER_STATUS_REGISTER__PRIV_LEVEL_MASK 0x00137b40 /* */
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#define NV_PTRIM_SYS_FMON_MASTER_STATUS_REGISTER_FINAL_FMON_FAULT_OUT_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_SYS_FMON_MASTER_STATUS_REGISTER_FINAL_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FMON_MASTER_STATUS_REGISTER_FINAL_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_SYS_FMON_MASTER_STATUS_REGISTER_FINAL_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_XBARCLK_DIV2_PHASEGEN_CONTROL 0x00137a08 /* RW-4R */
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#define NV_PTRIM_SYS_XBARCLK_DIV2_PHASEGEN_CONTROL_XBARCLK_CLKOUT_DIV2_FORCE_DIV1 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_XBARCLK_DIV2_PHASEGEN_CONTROL_XBARCLK_CLKOUT_DIV2_FORCE_DIV1_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_XBARCLK_DIV2_PHASEGEN_CONTROL_XBARCLK_CLKOUT_DIV2_FORCE_DIV1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_XBARCLK_DIV2_PHASEGEN_CONTROL_XBARCLK_CLKOUT_DIV2_FORCE_DIV1_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_DIV2_PHASEGEN_CONTROL(i) (0x001e0130+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_GPCCLK_DIV2_PHASEGEN_CONTROL__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_TSENSE_CLK(i) (0x001e0148+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_TSENSE_CLK__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_TSENSE_CLK__PRIV_LEVEL_MASK NV_PTRIM_GPC_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_GPC_TSENSE_CLK_DIV_SEL_TS_CLK 9:0 /* RWEUF */
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#define NV_PTRIM_GPC_TSENSE_CLK_DIV_SEL_TS_CLK_INIT 0x00000008 /* RWE-V */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST 0x00137360 /* RW-4R */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_DRAMPLL 0:0 /* RWFUF */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_DRAMPLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_DRAMPLL_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_DRAMPLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_REFMPLL 1:1 /* RWFUF */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_REFMPLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_REFMPLL_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST_REFMPLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_BYPASSCTRL_BCAST__PRIV_LEVEL_MASK 0x00137f68 /* */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST 0x00137380 /* RW-4R */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_DRAMPLL 0:0 /* RWFUF */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_DRAMPLL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_DRAMPLL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_DRAMPLL_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_REFMPLL 1:1 /* RWFUF */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_REFMPLL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_REFMPLL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST_REFMPLL_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_SYNC_MODE_BCAST__PRIV_LEVEL_MASK 0x00137f68 /* */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS 0x00137390 /* R--4R */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL0_PLL_LOCK 1:1 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL0_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL0_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL1_PLL_LOCK 3:3 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL1_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL1_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL2_PLL_LOCK 5:5 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL2_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL2_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL3_PLL_LOCK 7:7 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL3_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL3_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL4_PLL_LOCK 9:9 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL4_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL4_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL5_PLL_LOCK 11:11 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL5_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_DRAMPLL5_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL0_PLL_LOCK 17:17 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL0_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL0_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL2_PLL_LOCK 19:19 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL2_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL2_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL4_PLL_LOCK 21:21 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL4_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_REFMPLL4_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_HBMPLL_PLL_READY 24:24 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_HBMPLL_PLL_LOCK 25:25 /* R--UF */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_HBMPLL_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_MEM_PLL_STATUS_HBMPLL_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_JTAGINTFC 0x001373a0 /* RW-4R */
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#define NV_PTRIM_SYS_JTAGINTFC__PRIV_LEVEL_MASK 0x00137f5c /* */
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#define NV_PTRIM_SYS_JTAGINTFC_JTAGTM_INTFC_CLK_EN 3:3 /* RWEUF */
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#define NV_PTRIM_SYS_JTAGINTFC_JTAGTM_INTFC_CLK_EN_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_JTAGINTFC_JTAGTM_INTFC_CLK_EN_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_JTAGINTFC_JTAGTM_INTFC_CLK_EN_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL 0x001373a8 /* RW-4R */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL__PRIV_LEVEL_MASK 0x00137f44 /* */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_GPCCLK_DFD_HALT_EN 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_GPCCLK_DFD_HALT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_GPCCLK_DFD_HALT_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_GPCCLK_DFD_HALT_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_XBARCLK_DFD_HALT_EN 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_XBARCLK_DFD_HALT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_XBARCLK_DFD_HALT_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_XBARCLK_DFD_HALT_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_SYSCLK_DFD_HALT_EN 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_SYSCLK_DFD_HALT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_SYSCLK_DFD_HALT_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_SYSCLK_DFD_HALT_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_NVDCLK_DFD_HALT_EN 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_NVDCLK_DFD_HALT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_NVDCLK_DFD_HALT_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_MISC_DEBUG_CTRL_NVDCLK_DFD_HALT_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CG 0x001373b0 /* RW-4R */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_GPCCLK_EN 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_GPCCLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_GPCCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_GPCCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_XBARCLK_EN 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_XBARCLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_XBARCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CG_MSCG_STOPCLK_XBARCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CLK_STATUS 0x001373b4 /* R--4R */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_STOPPED 0:0 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_XBARCLK_STOPPED 1:1 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_XBARCLK_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_XBARCLK_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_STOPPED 2:2 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC0_STOPPED 3:3 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC1_STOPPED 4:4 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC1_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC1_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC2_STOPPED 5:5 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC2_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC2_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC3_STOPPED 6:6 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC3_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC3_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC4_STOPPED 7:7 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC4_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC4_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC5_STOPPED 8:8 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC5_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC5_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC6_STOPPED 9:9 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC6_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_GPCCLK_GPC6_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_GR_STOPPED 11:11 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_GR_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_GR_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_XBARCLK_GR_STOPPED 12:12 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_XBARCLK_GR_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_XBARCLK_GR_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_UTILSCLK_SEQ_STOPPED 20:20 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_UTILSCLK_SEQ_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_UTILSCLK_SEQ_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_OFA0_STOPPED 28:28 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_OFA0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_OFA0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_OFA0_STOPPED 29:29 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_OFA0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_OFA0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_SEC0_STOPPED 30:30 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_SEC0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_NVDCLK_SEC0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_SEC0_STOPPED 31:31 /* R--UF */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_SEC0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_STATUS_SYSCLK_SEC0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS 0x001373b8 /* R--4R */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE0_STOPPED 0:0 /* R--UF */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE1_STOPPED 1:1 /* R--UF */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE1_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE1_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE2_STOPPED 2:2 /* R--UF */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE2_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE2_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE3_STOPPED 3:3 /* R--UF */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE3_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE3_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE4_STOPPED 4:4 /* R--UF */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE4_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE4_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE5_STOPPED 5:5 /* R--UF */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE5_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PCE_CLK_STATUS_SYSCLK_PCE5_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVENC_CLK_STATUS 0x001373bc /* R--4R */
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#define NV_PTRIM_SYS_NVENC_CLK_STATUS_NVDCLK_NVENC0_STOPPED 0:0 /* R--UF */
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#define NV_PTRIM_SYS_NVENC_CLK_STATUS_NVDCLK_NVENC0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVENC_CLK_STATUS_NVDCLK_NVENC0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVENC_CLK_STATUS_SYSCLK_NVENC0_STOPPED 1:1 /* R--UF */
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#define NV_PTRIM_SYS_NVENC_CLK_STATUS_SYSCLK_NVENC0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVENC_CLK_STATUS_SYSCLK_NVENC0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS 0x001373c0 /* R--4R */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_NVDCLK_NVDEC0_STOPPED 0:0 /* R--UF */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_NVDCLK_NVDEC0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_NVDCLK_NVDEC0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_SYSCLK_NVDEC0_STOPPED 1:1 /* R--UF */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_SYSCLK_NVDEC0_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_SYSCLK_NVDEC0_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_NVDCLK_NVDEC1_STOPPED 2:2 /* R--UF */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_NVDCLK_NVDEC1_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_NVDCLK_NVDEC1_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_SYSCLK_NVDEC1_STOPPED 3:3 /* R--UF */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_SYSCLK_NVDEC1_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVDEC_CLK_STATUS_SYSCLK_NVDEC1_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_CDB2PEXTSTCLK_DIVSEL 0x001373e4 /* RW-4R */
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#define NV_PTRIM_SYS_CDB2PEXTSTCLK_DIVSEL_CDB2PEXTSTCLK_DIVSEL 1:0 /* RWIUF */
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#define NV_PTRIM_SYS_CDB2PEXTSTCLK_DIVSEL_CDB2PEXTSTCLK_DIVSEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FBIO_STATUS 0x001373e8 /* R--4R */
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#define NV_PTRIM_SYS_FBIO_STATUS_PAD_IO_RESET_N 0:0 /* R--UF */
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#define NV_PTRIM_SYS_FBIO_STATUS_CORE_FB_CLAMP 4:4 /* R--UF */
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#define NV_PTRIM_SYS_FBIO_CFG 0x001373ec /* RW-4R */
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#define NV_PTRIM_SYS_FBIO_CFG_CFG10_RCVR_SEL 17:16 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_CFG_CFG10_RCVR_SEL_DIFF_AMP 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_CFG_CFG10_RCVR_SEL_HSSA 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_CFG_CFG10_RCVR_SEL_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_CFG_CFG10_RCVR_SEL_LEGACY_SCHMITT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_CFG_CFG10_RCVR_SEL_LSSA 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_CFG__PRIV_LEVEL_MASK 0x00137f68 /* */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH 0x001373f4 /* RW-4R */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_DRAMCLK_MODE 1:0 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_DRAMCLK_MODE_DRAMPLL 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_DRAMCLK_MODE_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_DRAMCLK_MODE_ONESOURCE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_DRAMCLK_MODE_REFMPLL 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_ONESOURCE_STOP 4:4 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_ONESOURCE_STOP_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_ONESOURCE_STOP_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_ONESOURCE_STOP_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_CLAMP_P0 8:8 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_CLAMP_P0_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_CLAMP_P0_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_CLAMP_P0_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_STOP_SYNCMUX 16:16 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_STOP_SYNCMUX_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_CLKOUT_EN 17:17 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_CLKOUT_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_CLKOUT_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH_REFMPLL_CLKOUT_EN_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_MODE_SWITCH__PRIV_LEVEL_MASK 0x00137f68 /* */
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#define NV_PTRIM_SYS_FBIO_SPARE 0x001373f8 /* RW-4R */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE 15:0 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_CLK_DISABLE 0x00001000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_INIT 0x00000555 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_TRAINING_EN 0x00003000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO0_MAIN_REGULATOR_PWR 0:0 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO0_MAIN_REGULATOR_PWR_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO0_MAIN_REGULATOR_PWR_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO0_MAIN_REGULATOR_PWR_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO1_MAIN_REGULATOR_PWR 2:2 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO1_MAIN_REGULATOR_PWR_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO1_MAIN_REGULATOR_PWR_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO1_MAIN_REGULATOR_PWR_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO2_MAIN_REGULATOR_PWR 4:4 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO2_MAIN_REGULATOR_PWR_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO2_MAIN_REGULATOR_PWR_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO2_MAIN_REGULATOR_PWR_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO3_MAIN_REGULATOR_PWR 6:6 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO3_MAIN_REGULATOR_PWR_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO3_MAIN_REGULATOR_PWR_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO3_MAIN_REGULATOR_PWR_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO4_MAIN_REGULATOR_PWR 8:8 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO4_MAIN_REGULATOR_PWR_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO4_MAIN_REGULATOR_PWR_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO4_MAIN_REGULATOR_PWR_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO5_MAIN_REGULATOR_PWR 10:10 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO5_MAIN_REGULATOR_PWR_INIT 0x00000001 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO5_MAIN_REGULATOR_PWR_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_FBIO5_MAIN_REGULATOR_PWR_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_TX_PWRD 14:14 /* RWFUF */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_TX_PWRD_INIT 0x00000000 /* RWF-V */
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#define NV_PTRIM_SYS_FBIO_SPARE_FBIO_SPARE_TX_PWRD_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_SPARE__PRIV_LEVEL_MASK 0x00137f68 /* */
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#define NV_PTRIM_SYS_FBIO_DEBUG 0x001373fc /* RW-4R */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_FREQOUT_GRP0 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_FREQOUT_GRP1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_00_01 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_02_03 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_10_11 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_12_13 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_20_21 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_22_23 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_30_31 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_32_33 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_40_41 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_42_43 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_50_51 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_DRAMPLL_52_53 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_HBMPLL_0_1 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_HBMPLL_2_3 0x00000021 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_REFMPLL0 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_REFMPLL1 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_REFMPLL2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_MUX_CONTROL_TOP_CLOCKS_PLL_TESTOUT_REFMPLL3 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_OBSVCLK_EN 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_FBIO_DEBUG_OBSVCLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_HBMCLK_SELECT 9:9 /* RWIUF */
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#define NV_PTRIM_SYS_FBIO_DEBUG_HBMCLK_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_DRAMPLL_DIV 18:16 /* RWIUF */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_DRAMPLL_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_REFMPLL_DIV 26:24 /* RWIUF */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_REFMPLL_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_HBMPLL_DIV 29:27 /* RWIUF */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_HBMPLL_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_ENABLE 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_FBIO_DEBUG_PDIV_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG 0x00137400 /* RW-4R */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT 15:0 /* RWEUF */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_DEBUGPORTCLK_OUT 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_DRAMCLK_ALT 0x00000031 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPC2CLK_ALT 0x00000041 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPC2CLK_OUT 0x00000040 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPC2CLK_REF 0x00000042 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCPLL0_DFS_TEST_OUT 0x00000070 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_HOSTCLK_ALT 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_HUB2CLK_OUT 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_LTC2CLK_ALT 0x00000051 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_LTC2CLK_OUT 0x00000050 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_LTC2CLK_REF 0x00000052 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_NVDCLK_OUT 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_PWRCLK_OUT 0x00000021 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_REFCLK_REFMPLL 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_SYS2CLK_OUT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_SYS2CLK_REF 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_UTILSCLK_OUT 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_XBAR2CLK_ALT 0x00000061 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_XBAR2CLK_OUT 0x00000060 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_XBAR2CLK_REF 0x00000062 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_XCLK_ALT 0x00000023 /* RW--V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_FINAL_MUX 17:16 /* RWIUF */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_FINAL_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_MUX_INTERNAL 28:24 /* RWIUF */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_MUX_INTERNAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DATA 0x00137404 /* R--4R */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DATA_READ_DATA 7:0 /* R--UF */
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#define NV_PTRIM_SYS_CONTROL_0 0x00137420 /* RW-4R */
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#define NV_PTRIM_SYS_CONTROL_0_UTILSCLK_UPHY_ASYNC_MODE 30:29 /* RWEUF */
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#define NV_PTRIM_SYS_CONTROL_0_UTILSCLK_UPHY_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_CONTROL_0_UPHY_MGMT_CLK_SEL 31:31 /* RWCUF */
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#define NV_PTRIM_SYS_CONTROL_0_UPHY_MGMT_CLK_SEL_INIT 0x00000001 /* RWC-V */
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#define NV_PTRIM_SYS_CONTROL_0_UPHY_MGMT_CLK_SEL_PEX_REFCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CONTROL_0_UPHY_MGMT_CLK_SEL_XTAL4X 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT 0x0013742c /* RW-4R */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_ALT_SYS2CLK 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_CLOCKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_SYNCCLOCKOUT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_SYS2CLK_DVCO 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_SYS2CLK_LDIV_VCO_IP 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_SYS2CLK_OP 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT 6:4 /* RWIUF */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_ALT_XBAR2CLK 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_CLOCKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_SYNCCLOCKOUT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_XBAR2CLK_LDIV_VCO_IP 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_XBAR2CLK_OP 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_NVDPLL_SELECT 14:12 /* RWIUF */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_NVDPLL_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_PEX_REFCLK_CTRL 0x00137430 /* RW-4R */
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#define NV_PTRIM_SYS_PEX_REFCLK_CTRL_PEX_REFCLK_NVVDD_SEL 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_PEX_REFCLK_CTRL_PEX_REFCLK_NVVDD_SEL_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PEX_REFCLK_CTRL_PEX_REFCLK_NVVDD_SEL_PEX_REFCLK_FROM_PEXVDD 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PEX_REFCLK_CTRL_PEX_REFCLK_NVVDD_SEL_XTAL_IN 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PEX_REFCLK_CTRL_PEX_REFCLK_NVVDD_ASYNC_MODE 2:1 /* RWEUF */
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#define NV_PTRIM_SYS_PEX_REFCLK_CTRL_PEX_REFCLK_NVVDD_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_HOSTCLK_XCLK3X_COEFF 0x00137434 /* RW-4R */
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#define NV_PTRIM_SYS_HOSTCLK_XCLK3X_COEFF_PDIV 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_HOSTCLK_XCLK3X_COEFF_PDIV_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_HOSTCLK_XCLK45X_COEFF 0x00137438 /* RW-4R */
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#define NV_PTRIM_SYS_HOSTCLK_XCLK45X_COEFF_PDIV 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_HOSTCLK_XCLK45X_COEFF_PDIV_INIT 0x00000002 /* RWE-V */
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#define NV_PTRIM_SYS_XTXCLK_125_COEFF 0x0013743c /* RW-4R */
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#define NV_PTRIM_SYS_XTXCLK_125_COEFF_PDIV 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_XTXCLK_125_COEFF_PDIV_INIT 0x00000003 /* RWE-V */
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#define NV_PTRIM_SYS_XTXCLK_250_COEFF 0x00137440 /* RW-4R */
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#define NV_PTRIM_SYS_XTXCLK_250_COEFF_PDIV 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_XTXCLK_250_COEFF_PDIV_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_XTXCLK_DIV8_COEFF 0x00137444 /* RW-4R */
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#define NV_PTRIM_SYS_XTXCLK_DIV8_COEFF_PDIV 4:0 /* RWEUF */
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#define NV_PTRIM_SYS_XTXCLK_DIV8_COEFF_PDIV_INIT 0x00000007 /* RWE-V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE 0x00137448 /* RW-4R */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_MGMT_CLK_DISABLE 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_MGMT_CLK_DISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_MGMT_CLK_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_MGMT_CLK_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_MGMT_CLK_STOPPED 1:1 /* R--UF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_HOSTCLK_DISABLE 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_HOSTCLK_DISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_HOSTCLK_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_HOSTCLK_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_HOSTCLK_STOPPED 3:3 /* R--UF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_NVL_COMMON_CLK_DISABLE 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_NVL_COMMON_CLK_DISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_NVL_COMMON_CLK_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_NVL_COMMON_CLK_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_NVL_COMMON_CLK_STOPPED 5:5 /* R--UF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_XCLK_DISABLE 6:6 /* RWEUF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_XCLK_DISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_XCLK_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_XCLK_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_ALT_XCLK_STOPPED 7:7 /* R--UF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_SYSCLK_XPXV_DISABLE 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_SYSCLK_XPXV_DISABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_SYSCLK_XPXV_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FGC6_CLK_GATE_SYSCLK_XPXV_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING 0x0013744c /* RW-4R */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_HOSTCLK_GATING 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_HOSTCLK_GATING_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_HOSTCLK_GATING_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_HOSTCLK_GATING_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_SYSCLK_GATING 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_SYSCLK_GATING_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_SYSCLK_GATING_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_ENABLE_MLPC2CLKS_GATING_ENABLE_MLPC2CLKS_SYSCLK_GATING_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET 0x00137450 /* RW-4R */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_WAIT_DLY_LENGTH 19:0 /* RWEUF */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_WAIT_DLY_LENGTH_CANCEL 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_WAIT_DLY_LENGTH_INIT 0x0000032A /* RWE-V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_WAIT_DLY_LENGTH_MAX 0x000FFFFD /* RW--V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_WAIT_DLY_LENGTH_MIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_RCAL_DONE_TIMEOUT_VALUE 28:20 /* RWEUF */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_RCAL_DONE_TIMEOUT_VALUE_10US 0x0000010E /* RW--V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_RCAL_DONE_TIMEOUT_VALUE_INIT 0x0000010E /* RWE-V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_OVERRIDE_PLL_LOCKDET 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_OVERRIDE_PLL_LOCKDET_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_OVERRIDE_PLL_LOCKDET_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_PEXPLL_LOCKDET_OVERRIDE_PLL_LOCKDET_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL 0x00137454 /* RW-4R */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_OVERRIDE 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_SELECT 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_SELECT_HOSTCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_SELECT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_SELECT_XCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_DISABLE 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_DISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_SWITCH_ASYNC_MODE 4:3 /* RWEUF */
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#define NV_PTRIM_SYS_LA_CLK_CTRL_LA_CLK_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV 0x00137458 /* RW-4R */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_DIV_SEL_RDET 9:0 /* RWEUF */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_DIV_SEL_RDET_INIT 0x0000031F /* RWE-V */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_RX_BYPASS_REFCLK_DIV 15:11 /* RWEUF */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_RX_BYPASS_REFCLK_DIV_INIT 0x00000007 /* RWE-V */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_RX_BYPASS_REFCLK_DISABLE 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_RX_BYPASS_REFCLK_DISABLE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_RX_BYPASS_REFCLK_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_RX_BYPASS_REFCLK_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_PCIE_DIS_OVRD 17:17 /* RWEUF */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_PCIE_DIS_OVRD_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_PCIE_DIS 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_PCIE_DIS_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_PCIE_DEBUG4 0x00137460 /* R--4R */
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#define NV_PTRIM_SYS_PCIE_DEBUG4_FLAG_CAL_VALID_LOW 0:0 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_DEBUG4_FLAG_CAL_VALID_MID 1:1 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_DEBUG4_FLAG_CAL_VALID_HIGH 2:2 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1 0x00137470 /* R--4R */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_CURRENT_STATE 5:0 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_NEXT_STATE 13:8 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_SEL_PEX_REFCLK_ALT 16:16 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_PEX_PLL_XCLK_DISABLE 17:17 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_PEX_PLL_TXCLK_DISABLE 18:18 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_PEX_REFCLK_DISABLE 19:19 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_OFF_PEX_PLL_XCLK_XCLK3X 25:25 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_OFF_PEX_PLL_XTXCLK1X 26:26 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG1_PEX_REFCLK_ALT_RDY 28:28 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2 0x00137474 /* R--4R */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT 7:0 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_BYPASSCLK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_NAFLL 0x00000040 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_PEX_REFCLK 0x00000004 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_TXCLKREF 0x00000020 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_XDIGCLK_DIV1 0x00000080 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_XDIGCLK_DIV2 0x00000010 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_XDIGCLK_DIV3 0x00000008 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_HOSTCLK_SRC_SELECT_XTAL 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_CURRENT_STATE_PCIE_UPHY_FSM 11:8 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_CURRENT_STATE_PCIE_UPHY_RCAL 13:12 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_RCAL_FSM_TIMED_OUT 14:14 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_RCAL_FSM_TIMED_OUT_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_RCAL_FSM_TIMED_OUT_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT 23:16 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT_ALT_XCLK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT_PEX_REFCLK 0x00000004 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT_TXCLKREF_DIV1 0x00000020 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT_TXCLKREF_DIV2 0x00000010 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT_TXCLKREF_DIV4 0x00000008 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT_TXCLKREF_DIV8 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_XCLK_SRC_SELECT_XDIGCLK 0x00000040 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT 31:24 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT_ALT_XCLK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT_PEX_REFCLK 0x00000004 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT_TXCLKREF_DIV1 0x00000020 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT_TXCLKREF_DIV2 0x00000010 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT_TXCLKREF_DIV4 0x00000008 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT_TXCLKREF_DIV8 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG2_TXCLK_SRC_SELECT_XDIGCLK 0x00000040 /* R---V */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3 0x00137478 /* R--4R */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_ALT 0:0 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_REFCLK 1:1 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_277 2:2 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_417 3:3 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_500 4:4 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_571 5:5 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_1000 6:6 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_1142 7:7 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_HOSTCLK_NAFLL 8:8 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_XCLK_ALT 16:16 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_XCLK_REFCLK 17:17 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_XCLK_125 18:18 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_XCLK_250 19:19 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_XCLK_500 20:20 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_XCLK_1000 21:21 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_TXCLK_ALT 24:24 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_TXCLK_REFCLK 25:25 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_TXCLK_125 26:26 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_TXCLK_250 27:27 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_TXCLK_500 28:28 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_GEN3_DEBUG3_CLK2XP_RDY_TXCLK_1000 29:29 /* R--UF */
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#define NV_PTRIM_SYS_PCIE_SUPPORT_RECAL 0x00137480 /* RW-4R */
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#define NV_PTRIM_SYS_PCIE_SUPPORT_RECAL_RECALIBRATE_PLL_GC 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_PCIE_SUPPORT_RECAL_RECALIBRATE_PLL_GC_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_PCIE_SUPPORT_RECAL_RECALIBRATE_PLL_SC 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_PCIE_SUPPORT_RECAL_RECALIBRATE_PLL_SC_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_PCIE_SPARE_RW 0x0013748c /* RW-4R */
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#define NV_PTRIM_SYS_PCIE_SPARE_RW_PCIE_SPARE_RW 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_PCIE_SPARE_RW_PCIE_SPARE_RW_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_PCIE_SPARE_RO 0x00137490 /* R--4R */
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#define NV_PTRIM_SYS_PCIE_SPARE_RO_PCIE_SPARE_RO 31:0 /* R--UF */
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#define NV_PTRIM_SYS_TSENSE_CLK 0x00137498 /* RW-4R */
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#define NV_PTRIM_SYS_TSENSE_CLK__PRIV_LEVEL_MASK 0x00137f3c /* */
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#define NV_PTRIM_SYS_TSENSE_CLK_DIV_SEL_TS_CLK 9:0 /* RWEUF */
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#define NV_PTRIM_SYS_TSENSE_CLK_DIV_SEL_TS_CLK_INIT 0x0000001A /* RWE-V */
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#define NV_PTRIM_SYS_TSENSE_XBAR_CLK 0x0013749c /* RW-4R */
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#define NV_PTRIM_SYS_TSENSE_XBAR_CLK__PRIV_LEVEL_MASK 0x00137f3c /* */
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#define NV_PTRIM_SYS_TSENSE_XBAR_CLK_DIV_SEL_TS_CLK_XBAR 9:0 /* RWEUF */
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#define NV_PTRIM_SYS_TSENSE_XBAR_CLK_DIV_SEL_TS_CLK_XBAR_INIT 0x00000008 /* RWE-V */
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#define NV_PTRIM_SYS_SPARE_0 0x001374f0 /* RW-4R */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_NCLTCPLL 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_NCLTCPLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_NCSGPCPLL 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_NCSGPCPLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_S1_NCSYSPLL 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_S1_NCSYSPLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_S2_NCSYSPLL 31:24 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_0_SPARECTRL_S2_NCSYSPLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_1 0x001374f4 /* RW-4R */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_NCXBARPLL 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_NCXBARPLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_NCXTAL4X 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_NCXTAL4X_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_S1_NCOSMCORE 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_S1_NCOSMCORE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_S2_NCOSMCORE 31:24 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_1_SPARECTRL_S2_NCOSMCORE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_2 0x001374f8 /* RW-4R */
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#define NV_PTRIM_SYS_SPARE_2_SPARECTRL_NCCSYS 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_2_SPARECTRL_NCCSYS_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_2_SPARECTRL_NCPEX 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_2_SPARECTRL_NCPEX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPARE_2_SPARECTRL_NCCORE_DISP 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_SPARE_2_SPARECTRL_NCCORE_DISP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG 0x00137620 /* RW-4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_SOURCE_HOSTCLK_MUX 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_SOURCE_JTAG_REG_CLK_CTS_PROBE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_SOURCE_PEX_REFCLKP_XCLK3X_SYS 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CFG_SOURCE_XCLK_MUX 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CNT0 0x00137624 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CNT1 0x00137628 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEXCLKS_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG 0x0013762c /* RW-4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYS2CLK_NAFLL 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYSCLK_NOBG_CTS_PROBE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYSCLK_NOEG_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYSNAFLL_CLKOUT_PRE_SKP 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYSNAFLL_UPD_CLK 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYSPLL_O 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYSPLL_REFCLK 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CNT0 0x00137630 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CNT1 0x00137634 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG 0x00137638 /* RW-4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_SOURCE_HOSTCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CNT0 0x0013763c /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CNT1 0x00137640 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_NCOSMCORE_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG 0x00137650 /* RW-4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_SOURCE_PWRCLK_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CFG_SOURCE_PWRCLK_DIV32_FTM 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CNT0 0x00137654 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CNT1 0x00137658 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_MISCCLKS_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG 0x0013765c /* RW-4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_SOURCE_UTILSCLK_DIV32_FTM 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CFG_SOURCE_XTAL_FTM 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CNT0 0x00137660 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CNT1 0x00137664 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_UTILS_XTAL_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG 0x00137668 /* RW-4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CFG_SOURCE_PEX_PAD_TCLKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CNT0 0x0013766c /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CNT1 0x00137670 /* R--4R */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_PEX_PAD_TCLKS_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC 0x00137c00 /* RW-4R */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_AUTO 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_AUTO_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_AUTO_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_AUTO_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK 9:6 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_BYPASSCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_NAFLL 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_PEX_REFCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_XCLK 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_XCLK_500 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_XCLK_GEN2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_XCLK_GEN3 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_XTAL 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_SWITCH_ASYNC_MODE 17:10 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_HOSTCLK_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_ASYNC_MODE_PCIE_RX_LANE_CLK_SWITCH 19:18 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_ASYNC_MODE_PCIE_RX_LANE_CLK_SWITCH_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_ASYNC_MODE_PEX_PLL_XTXCLK1X_GATED 21:20 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_ASYNC_MODE_PEX_PLL_XTXCLK1X_GATED_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_ASYNC_MODE_PEX_REFCLKP_XCLK3X_STOPPED 23:22 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC_ASYNC_MODE_PEX_REFCLKP_XCLK3X_STOPPED_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLKSRC__PRIV_LEVEL_MASK 0x00137f60 /* */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK 0x00137c04 /* RW-4R */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BYPASS 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BYPASS_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BYPASS_XTAL4X 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BYPASS_XTAL_IN 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_PEXREF_BYPASS_ASYNC_MODE 4:3 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_PEXREF_BYPASS_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BUF_EN 6:6 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BUF_EN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BUF_EN_CYA 8:8 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BUF_EN_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BUF_EN_OVERRIDE 12:12 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_REFCLK_BUF_EN_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_ASYNC_MODE_PEX_REFCLKP_REFCLKBUF_OR_MUX 14:13 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_REFCLK_ASYNC_MODE_PEX_REFCLKP_REFCLKBUF_OR_MUX_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_SPARE 0x00137c0c /* RW-4R */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_SPARE_CYA0 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_SPARE_CYA0_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_SPARE_CYA0_ZEROS 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL 0x00137c10 /* RW-4R */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_AUTO 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_AUTO_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_AUTO_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_AUTO_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK 6:4 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_ALT_XCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_PEX_REFCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_XCLK_DIV1 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_XCLK_DIV2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_XCLK_DIV4 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_XCLK_DIV8 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_XDIGCLK 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_AUTO 12:12 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_AUTO_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_AUTO_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_AUTO_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK 15:13 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_ALT_XCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_PEX_REFCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_TXCLK_DIV1 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_TXCLK_DIV2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_TXCLK_DIV4 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_TXCLK_DIV8 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_XDIGCLK 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_SWITCH_ASYNC_MODE 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_XCLK_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_SWITCH_ASYNC_MODE 31:24 /* RWEUF */
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#define NV_PTRIM_SYS_IND_SYS_CORE_CLK_PEXCLK_CTRL_TXCLK_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_EMULATOR_CFG0 0x00137da0 /* RW-4R */
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#define NV_PTRIM_SYS_EMULATOR_CFG0_PLL_CONFIG_SELECT 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_EMULATOR_CFG0_PLL_CONFIG_SELECT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_EMULATOR_CFG1 0x00137da4 /* RW-4R */
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#define NV_PTRIM_SYS_EMULATOR_CFG1_VOLTAGE_SELECT 15:0 /* RWEUF */
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#define NV_PTRIM_SYS_EMULATOR_CFG1_VOLTAGE_SELECT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_SWITCH_ASYNC_MODE 0x00137ef0 /* RW-4R */
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#define NV_PTRIM_SYS_SWITCH_ASYNC_MODE_ASYNC_MODE_FUSE_CLK_SWITCH 5:4 /* RWEUF */
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#define NV_PTRIM_SYS_SWITCH_ASYNC_MODE_ASYNC_MODE_FUSE_CLK_SWITCH_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_SWITCH_ASYNC_MODE_ASYNC_MODE_SROM_CLK 7:6 /* RWEUF */
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#define NV_PTRIM_SYS_SWITCH_ASYNC_MODE_ASYNC_MODE_SROM_CLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_SWITCH_ASYNC_MODE_ASYNC_MODE_GPCPLL_BYPASS 17:14 /* RWIUF */
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#define NV_PTRIM_SYS_SWITCH_ASYNC_MODE_ASYNC_MODE_GPCPLL_BYPASS_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_FT_CLK_FS_CTRL 0x00137ef4 /* RW-4R */
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#define NV_PTRIM_SYS_FT_CLK_FS_CTRL_FBP_FT_CLK_FS_OVR 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_FT_CLK_FS_CTRL_FBP_FT_CLK_FS_OVR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0 0x00137f00 /* R--4R */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_GPCPLL_CAPABILITY 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_GPCPLL_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_GPCPLL_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_GPCPLL_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_LTCPLL_CAPABILITY 1:1 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_LTCPLL_CAPABILITY_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_LTCPLL_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_LTCPLL_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_XBARPLL_CAPABILITY 2:2 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_XBARPLL_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_XBARPLL_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_XBARPLL_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPPLL_CAPABILITY 3:3 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPPLL_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPPLL_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPPLL_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_XTAL16X_CAPABILITY 4:4 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_XTAL16X_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPHUBPLL_CAPABILITY 5:5 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPHUBPLL_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPHUBPLL_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_DISPHUBPLL_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_SYSPLL_CAPABILITY 7:7 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_SYSPLL_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_SYSPLL_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_SYSPLL_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL_CAPABILITY(i) (16+(i)):(16+(i)) /* */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL_CAPABILITY__SIZE_1 4 /* */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL_CAPABILITY_REMOVED 0x00000000 /* */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL_CAPABILITY_PRESENT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL0_CAPABILITY 16:16 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL0_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL0_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL0_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL1_CAPABILITY 17:17 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL1_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL1_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL1_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL2_CAPABILITY 18:18 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL2_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL2_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL2_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL3_CAPABILITY 19:19 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL3_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL3_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_0_VPLL3_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1 0x00137f04 /* R--4R */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL0_CAPABILITY 16:16 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL0_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL0_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL0_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL1_CAPABILITY 17:17 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL1_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL1_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_PLLS_1_SPPLL1_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_IST_CTRL 0x00137f10 /* RW-4R */
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#define NV_PTRIM_SYS_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ALT_SEL 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ALT_SEL_DEFROST 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ALT_SEL_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ALT_SEL_PEX_REFCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ROOT_CG_EN 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ROOT_CG_EN_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ROOT_CG_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_ROOT_CG_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_MODE 3:3 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_IST_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_DIV 8:4 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_DIV_INIT 0x0000001F /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_ASYNC_MODE_DEFROST_OR_PEX_REF_CLK 10:9 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_ASYNC_MODE_DEFROST_OR_PEX_REF_CLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_BTI_DIV 21:12 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_BTI_DIV_INIT 0x000003FF /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_CLOCK_STOP_TRIGGER_IST_CLK_FAST_STOP_ENABLE 22:22 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_CLOCK_STOP_TRIGGER_IST_CLK_FAST_STOP_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_CLOCK_STOP_TRIGGER_HOSTCLK_FAST_STOP_ENABLE 23:23 /* RWEUF */
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#define NV_PTRIM_SYS_IST_CTRL_CLOCK_STOP_TRIGGER_HOSTCLK_FAST_STOP_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_IST_CTRL_IST_CLK_DIVISION_DONE 24:24 /* R---F */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0 0x00137f20 /* R--4R */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPC2CLK_CAPABILITY 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPC2CLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPC2CLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPC2CLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTC2CLK_CAPABILITY 1:1 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTC2CLK_CAPABILITY_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTC2CLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTC2CLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBAR2CLK_CAPABILITY 2:2 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBAR2CLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBAR2CLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBAR2CLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYS2CLK_CAPABILITY 7:7 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYS2CLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYS2CLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYS2CLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUB2CLK_CAPABILITY 8:8 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUB2CLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUB2CLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUB2CLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LEGCLK_CAPABILITY 9:9 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LEGCLK_CAPABILITY_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LEGCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LEGCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_RSTCLK_CAPABILITY 10:10 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_RSTCLK_CAPABILITY_INIT 0x00000000 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_RSTCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_RSTCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_UTILSCLK_CAPABILITY 11:11 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_UTILSCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_UTILSCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_UTILSCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_PWRCLK_CAPABILITY 12:12 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_PWRCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_PWRCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_PWRCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_NVDCLK_CAPABILITY 14:14 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_NVDCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_NVDCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_NVDCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK0_CAPABILITY 16:16 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK0_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK0_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK0_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK1_CAPABILITY 17:17 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK1_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK1_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK1_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK2_CAPABILITY 18:18 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK2_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK2_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK2_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK3_CAPABILITY 19:19 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK3_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK3_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK3_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_DISPCLK_CAPABILITY 24:24 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_DISPCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_DISPCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_DISPCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_AZA2BITCLK_CAPABILITY 25:25 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_AZA2BITCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_AZA2BITCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_AZA2BITCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_MAUDCLK_CAPABILITY 28:28 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_MAUDCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_MAUDCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_MAUDCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK_CAPABILITY(i) (16+(i)):(16+(i)) /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK_CAPABILITY__SIZE_1 4 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK_CAPABILITY_REMOVED 0x00000000 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_VCLK_CAPABILITY_PRESENT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_1 0x00137f24 /* R--4R */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_1_MCLK_CAPABILITY 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_1_MCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_1_MCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_1_MCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2 0x00137f28 /* R--4R */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_HOSTCLK_CAPABILITY 0:0 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_HOSTCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_HOSTCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_HOSTCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_XCLK_CAPABILITY 1:1 /* R-EUF */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_XCLK_CAPABILITY_INIT 0x00000001 /* R-E-V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_XCLK_CAPABILITY_PRESENT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_2_XCLK_CAPABILITY_REMOVED 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE 0x00137f2c /* RW-4R */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_GPCCLK_CLK_DIST_MODE 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_GPCCLK_CLK_DIST_MODE_1XCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_GPCCLK_CLK_DIST_MODE_2XCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_GPCCLK_CLK_DIST_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_XBARCLK_CLK_DIST_MODE 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_XBARCLK_CLK_DIST_MODE_1XCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_XBARCLK_CLK_DIST_MODE_2XCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_XBARCLK_CLK_DIST_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_LTCCLK_CLK_DIST_MODE 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_LTCCLK_CLK_DIST_MODE_1XCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_LTCCLK_CLK_DIST_MODE_2XCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_LTCCLK_CLK_DIST_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_SYSCLK_CLK_DIST_MODE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_SYSCLK_CLK_DIST_MODE_1XCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_SYSCLK_CLK_DIST_MODE_2XCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_SYSCLK_CLK_DIST_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_NVDCLK_CLK_DIST_MODE 28:28 /* RWIUF */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_NVDCLK_CLK_DIST_MODE_1XCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_NVDCLK_CLK_DIST_MODE_2XCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_CLK_DIST_MODE_NVDCLK_CLK_DIST_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_SPI_CONFIG 0x00137f64 /* RW-4R */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET0 4:0 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET0_INIT 0x0000000e /* RWE-V */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET1 10:6 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET1_INIT 0x0000000a /* RWE-V */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET2 16:12 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET2_INIT 0x00000007 /* RWE-V */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET3 22:18 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIVISOR_SET3_INIT 0x00000006 /* RWE-V */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIV_SET_SEL_OVR 24:24 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIV_SET_SEL_OVR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIV_SET_SEL_VAL 26:25 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_DIV_SET_SEL_VAL_INIT 0x00000003 /* RWE-V */
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#define NV_PTRIM_SYS_SPI_CONFIG_REFCLK_SEL_OVR 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_REFCLK_SEL_OVR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_SPI_CONFIG_REFCLK_SEL_VAL 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_SPI_CONFIG_REFCLK_SEL_VAL_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL 0x001371b0 /* RW-4R */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_STOPCLK 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_STOPCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_STOPCLK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_STOPCLK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_COND_STOPCLK_EN 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_COND_STOPCLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_COND_STOPCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_SYS2CLK_COND_STOPCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_STOPCLK 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_STOPCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_STOPCLK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_STOPCLK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_COND_STOPCLK_EN 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_COND_STOPCLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_COND_STOPCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_NVD2CLK_COND_STOPCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_STOPCLK 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_STOPCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_STOPCLK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_STOPCLK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_COND_STOPCLK_EN 7:7 /* RWIUF */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_COND_STOPCLK_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_COND_STOPCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL_PWRCLK_COND_STOPCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_GC5_STOPCLK_CTRL__PRIV_LEVEL_MASK 0x00137f84 /* */
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#define NV_PTRIM_SYS_DEBUG_UPHY_PLL_SELECT 0x00137fd4 /* RW-4R */
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#define NV_PTRIM_SYS_DEBUG_UPHY_PLL_SELECT_SEL 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_DEBUG_UPHY_PLL_SELECT_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_DEBUG_UPHY_PLL_SELECT_SEL_NVHS_COMBINED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_UPHY_PLL_SELECT_SEL_PEX_PAD 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_UPHY_PLL_SELECT_SEL_UPHY_USB3_DP_BRICK 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_SYS 0x00137fc0 /* RW-4R */
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#define NV_PTRIM_SYS_DEBUG_PRB2_SYS_SEL 3:0 /* RWEUF */
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#define NV_PTRIM_SYS_DEBUG_PRB2_SYS_SEL_FAST_STEP_EN_NVDCLK 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_SYS_SEL_FAST_STEP_EN_SYSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_SYS_SEL_FAST_STEP_EN_XBARCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_SYS_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_SYS_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR 0x00137fc4 /* RW-4R */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_FAST_STEP_EN_SYSCLK 0x00000032 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_FAST_STEP_EN_XBARCLK 0x00000031 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_FFF0_FAST_STEP_EN 0x00000038 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_FFF1_FAST_STEP_EN 0x00000020 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_FFF2_FAST_STEP_EN 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_FFF3_FAST_STEP_EN 0x00000034 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC0_FAST_STEP_EN 0x00000039 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC1_FAST_STEP_EN 0x0000003a /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC2_FAST_STEP_EN 0x00000021 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC3_FAST_STEP_EN 0x00000022 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC4_FAST_STEP_EN 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC5_FAST_STEP_EN 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC6_FAST_STEP_EN 0x00000035 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_GPC7_FAST_STEP_EN 0x00000036 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_LNK0_FAST_STEP_EN 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_MMS0_FAST_STEP_EN 0x00000030 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_GA100_SYS0_FAST_STEP_EN 0x00000033 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_XBAR_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_NVENC 0x00137fc8 /* RW-4R */
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#define NV_PTRIM_SYS_DEBUG_PRB2_NVENC_SEL 2:0 /* RWEUF */
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#define NV_PTRIM_SYS_DEBUG_PRB2_NVENC_SEL_FAST_STEP_EN_NVDCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_NVENC_SEL_FAST_STEP_EN_SYSCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_NVENC_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MMS 0x00137fcc /* RW-4R */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MMS_SEL 2:0 /* RWEUF */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MMS_SEL_FAST_STEP_EN_NVDCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MMS_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MMS_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MATHS 0x00137fd8 /* RW-4R */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MATHS_SEL 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MATHS_SEL_FAST_STEP_EN_SYSCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MATHS_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_DEBUG_PRB2_MATHS_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SWITCH_CTRL 0x00137fd0 /* RW-4R */
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#define NV_PTRIM_SYS_SWITCH_CTRL_XCLK_ALT_SEL 19:19 /* RWEUF */
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#define NV_PTRIM_SYS_SWITCH_CTRL_XCLK_ALT_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_SWITCH_CTRL_XCLK_ALT_SEL_PEX_REFCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_SWITCH_CTRL_XCLK_ALT_SEL_XTAL_PLL_REFCLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_SWITCH_CTRL_XCLK_ALT_ASYNC_MODE 21:20 /* RWEUF */
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#define NV_PTRIM_SYS_SWITCH_CTRL_XCLK_ALT_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0 0x001371f4 /* RW-4R */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0_CHIPLETID 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0_CHIPLETID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN 30:30 /* RWIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD0__PRIV_LEVEL_MASK 0x00137f40 /* */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1 0x001371f8 /* -W-4R */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_PARTITIONID 7:0 /* -WIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_PARTITIONID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_MACROID 15:8 /* -WIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_MACROID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_TRIMMERID 23:16 /* -WIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_TRIMMERID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_TRIMVAL 28:24 /* -WIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_TRIMVAL_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_OP 30:30 /* -WIUF */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1_OP_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_TRIMCAST_CONTROL_CMD1__PRIV_LEVEL_MASK 0x00137f40 /* */
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#define NV_PTRIM_SYS_TRIMCAST_STATUS 0x001371fc /* R--4R */
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#define NV_PTRIM_SYS_TRIMCAST_STATUS_VALID 0:0 /* R--UF */
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#define NV_PTRIM_SYS_TRIMCAST_STATUS_TRIMVALMATCH 1:1 /* R--UF */
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#define NV_PTRIM_SYS_TRIMCAST_STATUS__PRIV_LEVEL_MASK 0x00137f40 /* */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS 0x00137fa0 /* RW-4R */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_SYS_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR 0x00137fa4 /* RW-4R */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_XBAR_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP 0x00137fa8 /* RW-4R */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_TOP_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS 0x00137fac /* RW-4R */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MATHS_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC 0x00137fb0 /* RW-4R */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_NVENC_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS(i) (0x00137fb4+(i)*4) /* RW-4A */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS__SIZE_1 2 /* */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_TCLKOUT_CTRL_MMS_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC(i) (0x001e01a0+(i)*1024) /* RW-4A */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC__SIZE_1 7 /* */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_GPC_TCLKOUT_CTRL_GPC_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK 0x0000ff04 /* RW-4R */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sppll0_priv_secure" /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK 0x0000ff08 /* RW-4R */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sppll1_priv_secure" /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_SPPLL1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x0000ff0c /* RW-4R */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "vplls_physical_damage" /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_VPLLS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x0000ff00 /* RW-4R */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "disppll_physical_damage" /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x0000fefc /* RW-4R */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "disphubpll_physical_damage" /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWDVF */
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#define NV_PVTRIM_SYS_PRIV_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWD-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG 0x0000e800 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_ENABLE 0:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_IDDQ 1:1 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_IDDQ_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_SYNC_MODE 2:2 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_SYNC_MODE_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_LCKDET 4:4 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_LCKDET_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_LCKDET_POWER_OFF 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_LCKDET_POWER_ON 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_LOCK_OVERRIDE 5:5 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_RESET_LD_PULSE 6:6 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_RESET_LD_PULSE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_PLL_DYNRAMP 8:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_PLL_DYNRAMP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_PLL_DYNRAMP_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_EN_PLL_DYNRAMP_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_DYNRAMP_DONE 9:9 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_DYNRAMP_DONE_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_DYNRAMP_DONE_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_TESTMODE 16:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_TESTMODE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_SSA 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_SSD 25:25 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_STOP_SYNCMUX 30:30 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF 0x0000e804 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_MDIV 7:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_MDIV_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV 15:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_INIT 0x00000064 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_MIN 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_VCO_1620M 0x0000003C /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_VCO_2700M 0x00000064 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_NEW 29:22 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_NEW_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_NEW_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF_NDIV_NEW_MIN 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2 0x0000e808 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVA 5:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVA_INIT 0x00000004 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVA_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVA_MIN 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVA_POWERDOWN 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVB 13:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVB_INIT 0x00000007 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVB_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVB_MIN 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIVB_POWERDOWN 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIV 21:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIV_DIV_BY_10 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIV_DIV_BY_6 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIV_INIT 0x0000000A /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIV_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2_PDIV_POWERDOWN 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_COEFF2__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL 0x0000e80c /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_BYPASSPLL_CYA 16:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_BYPASSPLL_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_KCP 19:18 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_KCP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_KVCO 20:20 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_KVCO_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_PLL_FREQLOCK 28:28 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_PLL_FREQLOCK_NO 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_PLL_FREQLOCK_YES 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL_SDM_TESTOUT 31:29 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL0_CTRL__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2 0x0000e810 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SDM 8:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SDM_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SDM_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SDM_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SSC 9:9 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SSC_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SSC_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_SSC_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_DITHER 11:11 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_DITHER_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_DITHER_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_DITHER_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_SDM_RESET 12:12 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_SDM_RESET_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_SDM_RESET_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_SDM_RESET_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_DITHER2 13:13 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SSD_EN_DITHER2_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_VREGBG_TST_CTRL 16:14 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_VREGBG_TST_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SEL_TESTOUT 19:17 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_CFG2__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_SSD0 0x0000e814 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_SSD0_SDM_SSC_STEP 15:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SSD0_SDM_SSC_STEP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SSD0_SDM_DIN 31:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SSD0_SDM_DIN_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SSD0__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_SSD1 0x0000e818 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_SSD1_SDM_SSC_MAX 15:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SSD1_SDM_SSC_MAX_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SSD1_SDM_SSC_MIN 31:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SSD1_SDM_SSC_MIN_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SSD1__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_DYN 0x0000e81c /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_DYN_PLL_STEPA 7:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_DYN_PLL_STEPA_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_DYN_PLL_STEPB 15:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_DYN_PLL_STEPB_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_DYN_SDM_DIN_NEW 31:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_DYN_SDM_DIN_NEW_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_DYN__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE 0x0000e820 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_SETUP 15:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_SETUP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_SETUP2 27:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_SETUP2_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG10V_CTRL 29:28 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG14V_CTRL 31:30 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG14V_CTRL_1V35 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG14V_CTRL_1V4 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG14V_CTRL_1V55 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG14V_CTRL_1V6 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE_VREG14V_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL0_SECURE__PRIV_LEVEL_MASK 0x0000ff04 /* */
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#define NV_PVTRIM_SYS_SPPLL1_CFG 0x0000e830 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_ENABLE 0:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_IDDQ 1:1 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_IDDQ_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_SYNC_MODE 2:2 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_SYNC_MODE_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_LCKDET 4:4 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_LCKDET_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_LCKDET_POWER_OFF 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_LCKDET_POWER_ON 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_LOCK_OVERRIDE 5:5 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_RESET_LD_PULSE 6:6 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_RESET_LD_PULSE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_PLL_DYNRAMP 8:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_PLL_DYNRAMP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_PLL_DYNRAMP_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_EN_PLL_DYNRAMP_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_DYNRAMP_DONE 9:9 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_DYNRAMP_DONE_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_DYNRAMP_DONE_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_TESTMODE 16:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_TESTMODE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_SSA 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_SSD 25:25 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_STOP_SYNCMUX 30:30 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF 0x0000e834 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_MDIV 7:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_MDIV_INIT 0x00000001 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV 15:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_INIT 0x00000064 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_MIN 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_VCO_1620M 0x0000003C /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_VCO_2700M 0x00000064 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_NEW 29:22 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_NEW_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_NEW_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF_NDIV_NEW_MIN 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2 0x0000e838 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVA 5:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVA_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVA_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVA_MIN 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVA_POWERDOWN 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVB 13:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVB_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVB_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVB_MIN 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIVB_POWERDOWN 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIV 21:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIV_DIV_BY_10 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIV_DIV_BY_6 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIV_INIT 0x0000000A /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIV_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2_PDIV_POWERDOWN 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_COEFF2__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL 0x0000e83c /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_BYPASSPLL_CYA 16:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_BYPASSPLL_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_KCP 19:18 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_KCP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_KVCO 20:20 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_KVCO_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_PLL_FREQLOCK 28:28 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_PLL_FREQLOCK_NO 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_PLL_FREQLOCK_YES 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL_SDM_TESTOUT 31:29 /* R--UF */
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#define NV_PVTRIM_SYS_SPPLL1_CTRL__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2 0x0000e840 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SDM 8:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SDM_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SDM_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SDM_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SSC 9:9 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SSC_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SSC_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_SSC_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_DITHER 11:11 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_DITHER_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_DITHER_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_DITHER_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_SDM_RESET 12:12 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_SDM_RESET_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_SDM_RESET_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_SDM_RESET_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_DITHER2 13:13 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SSD_EN_DITHER2_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_VREGBG_TST_CTRL 16:14 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_VREGBG_TST_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SEL_TESTOUT 19:17 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_CFG2__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_SSD0 0x0000e844 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_SSD0_SDM_SSC_STEP 15:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SSD0_SDM_SSC_STEP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SSD0_SDM_DIN 31:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SSD0_SDM_DIN_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SSD0__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_SSD1 0x0000e848 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_SSD1_SDM_SSC_MAX 15:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SSD1_SDM_SSC_MAX_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SSD1_SDM_SSC_MIN 31:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SSD1_SDM_SSC_MIN_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SSD1__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_DYN 0x0000e84c /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_DYN_PLL_STEPA 7:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_DYN_PLL_STEPA_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_DYN_PLL_STEPB 15:8 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_DYN_PLL_STEPB_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_DYN_SDM_DIN_NEW 31:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_DYN_SDM_DIN_NEW_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_DYN__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE 0x0000e850 /* RW-4R */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_SETUP 15:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_SETUP_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_SETUP2 27:16 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_SETUP2_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG10V_CTRL 29:28 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG14V_CTRL 31:30 /* RWEUF */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG14V_CTRL_1V35 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG14V_CTRL_1V4 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG14V_CTRL_1V55 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG14V_CTRL_1V6 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE_VREG14V_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPPLL1_SECURE__PRIV_LEVEL_MASK 0x0000ff08 /* */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG 0x0000e960 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_ENABLE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_IDDQ 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_IDDQ_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_SYNC_MODE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_TESTMODE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_TESTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_SSA 18:18 /* R--UF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_SSD 19:19 /* R--UF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_BYPASSPLL_CYA 21:21 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_LOOP_CTRL 23:22 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_RESETB 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_RESETB_ASSERT 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_RESETB_DEASSERT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_RESETB_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_SEL_TESTOUT 28:26 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_BYPASSPLL 29:29 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_BYPASSPLL_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_BYPASSPLL_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_STOP_SYNCMUX 30:30 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF 0x0000e964 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_MDIV 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_MDIV_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_PLDIV 21:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_PLDIV_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL 0x0000e968 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_FLL_FRUG 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_FLL_FRUG_INIT 0x00000005 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_FLL_DIV 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_FLL_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_FLL_LD_MEM 11:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_FLL_LD_MEM_INIT 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_PLL_FRUG 19:12 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_PLL_FRUG_INIT 0x00000072 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_PLL_LD_MEM 27:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_PLL_LD_MEM_INIT 0x0000001F /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_PLL_LD_TOL 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CTRL_PLL_LD_TOL_INIT 0x00000004 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_MISC 0x0000e96c /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_MISC_EXT_FRU 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_MISC_EXT_FRU_INIT 0x00008000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2 0x0000e970 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_LDIV 1:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_LDIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_KP_HI 4:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_KP_HI_INIT 0x00000007 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_KP_LO 7:5 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_KP_LO_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_KP_STEP_TIMER 10:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_KP_STEP_TIMER_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_FRAC_STEP_TIMER 13:11 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_FRAC_STEP_TIMER_INIT 0x00000003 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_SEL_IREF 14:14 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_SEL_IREF_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_FRAC_STEP 30:15 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG2_FRAC_STEP_INIT 0x000003E8 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG3 0x0000e974 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG3_NDIV_FRAC_SSC_MIN 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG3_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG3_NDIV_FRAC_SSC_MAX 31:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG3_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG4 0x0000e978 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG4_NDIV_FRAC 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG4_NDIV_FRAC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG4_NDIV 23:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG4_NDIV_INIT 0x0000003C /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG4_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG4_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG5 0x0000e97c /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG5_SSC_MODE 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG5_SSC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG5_SSC_DLF 31:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG5_SSC_DLF_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6 0x0000e980 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSC_DIV 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSC_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSC_STEP 15:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSC_STEP_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSUG_HI 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSUG_HI_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSUG_LO 23:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSUG_LO_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_SSC_READY 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_EN_SSC 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG6_EN_SSC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG7 0x0000e984 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG7_HPLL_CTRL 31:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_CFG7_HPLL_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE 0x0000e988 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_SETUP 23:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_SETUP_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_VREG10V_CTRL 29:28 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPHUBPLL_SECURE__PRIV_LEVEL_MASK 0x0000fefc /* */
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#define NV_PVTRIM_SYS_VCLK_CTRL(i) (0x0000e9e0+(i)*4) /* RW-4A */
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#define NV_PVTRIM_SYS_VCLK_CTRL__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC 1:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC_EXT_REFCLKA_IB 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC_EXT_REFCLK_FL 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC_EXT_REFCLK_SLI 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC_FL_REFCLK_IN 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC_FL_REFCLK_IN_DUPLICATE 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC_INIT 0x00000003 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_CONFIG_SRC_XTAL_PLL_REFCLK 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_SETUP_CONTROL_OVERRIDE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_CTRL_SETUP_CONTROL_OVERRIDE_DISABLE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_SETUP_CONTROL_OVERRIDE_ENABLE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_SETUP_CONTROL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_SETUP_CONTROL_STATUS_ENABLE 3:3 /* R--UF */
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#define NV_PVTRIM_SYS_VCLK_CTRL_SETUP_CONTROL_STATUS_ENABLE_NO 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_SETUP_CONTROL_STATUS_ENABLE_YES 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_SEL_STATUS 8:8 /* R--UF */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_SEL_STATUS_EXT_REFCLK 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_CTRL_EXT_REF_SEL_STATUS_XTAL 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH(i) (0x0000e900+(i)*4) /* RW-4A */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_REF_SEL 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_REF_SEL_EXT_REFCLK 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_REF_SEL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_REF_SEL_XTAL_PLL_REFCLK 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_REF_ASYNC_MODE 2:1 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_REF_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK_SEL_OVERRIDE 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK_SEL_OVERRIDE_VALUE 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK_NON_QUAL 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VCLK_REF_SWITCH_EXT_REFCLK_QUAL 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VCLK_OUT_SWITCH(i) (0x0000e9c0+(i)*4) /* RW-4A */
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#define NV_PVTRIM_SYS_VCLK_OUT_SWITCH__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VCLK_OUT_SWITCH_OUT_SEL 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VCLK_OUT_SWITCH_OUT_SEL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VCLK_OUT_SWITCH_OUT_SEL_VPLL_O 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VCLK_OUT_SWITCH_OUT_SEL_XTAL_CLK 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER 0x0000e990 /* RW-4R */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWDUF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY10P5 0x00000013 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY11P5 0x00000015 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY12P5 0x00000017 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY13P5 0x00000019 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY14P5 0x0000001B /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY15P5 0x0000001D /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY16P5 0x0000001F /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY17P5 0x00000021 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY18P5 0x00000023 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY19P5 0x00000025 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY1P5 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY20P5 0x00000027 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY21P5 0x00000029 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY22P5 0x0000002B /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY23P5 0x0000002D /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY24P5 0x0000002F /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY25P5 0x00000031 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY26P5 0x00000033 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY27P5 0x00000035 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY28P5 0x00000037 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY29P5 0x00000039 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY2P5 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY30P5 0x0000003B /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY3P5 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY4P5 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY5P5 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY6P5 0x0000000B /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY7P5 0x0000000D /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY8P5 0x0000000F /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY9P5 0x00000011 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWDUF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWDUF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DISPHUBPLL 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL0 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL1 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWDUF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWDUF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_SPARE 24:22 /* RWDUF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PVTRIM_SYS_HUBCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER 0x0000e9a4 /* RW-4R */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWAUF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWAUF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWAUF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWA-V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL0 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL1 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWAUF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWAUF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_SPARE 24:21 /* RWAUF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PVTRIM_SYS_AZA2XBITCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER 0x0000e9b0 /* RW-4R */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWAUF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWAUF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWAUF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWA-V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL0 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL1 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWAUF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWAUF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_SPARE 24:21 /* RWAUF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PVTRIM_SYS_MAUDCLK_OUT_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG(i) (0x0000e860+(i)*4) /* RW-4A */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG__SIZE_1 6 /* */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_FREQ 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_FREQ_100M 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_FREQ_270M 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_FREQ_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_SRC 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_SRC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_SRC_SPPLL0 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_SRC_SPPLL1 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_POWERDOWN 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_POWERDOWN_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_POWERDOWN_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_LINK_REFCLK_CFG_POWERDOWN_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER 0x0000eac0 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL 5:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY1 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY10 0x00000012 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY11 0x00000014 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY12 0x00000016 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY13 0x00000018 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY14 0x0000001A /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY15 0x0000001C /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY16 0x0000001E /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY17 0x00000020 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY18 0x00000022 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY19 0x00000024 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY2 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY20 0x00000026 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY21 0x00000028 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY22 0x0000002A /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY23 0x0000002C /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY24 0x0000002E /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY25 0x00000030 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY26 0x00000032 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY27 0x00000034 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY28 0x00000036 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY29 0x00000038 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY3 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY30 0x0000003A /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY31 0x0000003C /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY4 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY5 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY6 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY7 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY8 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_BY9 0x00000010 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DIVIDER_SEL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_ASYNC_MODE 11:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL 15:12 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_DISPPLL 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL0 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_SPPLL1 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_CLOCK_SOURCE_SEL_XTAL_PLL_REFCLK 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_GATE_CLOCK 16:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_GATE_CLOCK_GATED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_GATE_CLOCK_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_BYPASS_FSM 17:17 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_BYPASS_FSM_BYPASSED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_BYPASS_FSM_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_SPARE 24:21 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_SPARE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_SWITCH_DIVIDER_DONE 25:25 /* R--UF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DEBUG_OUT_PREVIOUS_STATE 27:26 /* R--UF */
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#define NV_PVTRIM_SYS_DISPCLK_SWITCH_DIVIDER_DEBUG_OUT_STATE 29:28 /* R--UF */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL 0x0000e8cc /* RW-4R */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_STOPCLK 0:0 /* RWAUF */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_STOPCLK_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_STOPCLK_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_STOPCLK_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_COND_STOPCLK_EN 1:1 /* RWAUF */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_COND_STOPCLK_EN_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_COND_STOPCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_AZACLK_COND_STOPCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_STOPCLK 2:2 /* RWAUF */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_STOPCLK_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_STOPCLK_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_STOPCLK_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_COND_STOPCLK_EN 3:3 /* RWAUF */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_COND_STOPCLK_EN_INIT 0x00000000 /* RWA-V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_COND_STOPCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_MAUDCLK_COND_STOPCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_STOPCLK 4:4 /* RWDUF */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_STOPCLK_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_STOPCLK_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_STOPCLK_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_COND_STOPCLK_EN 5:5 /* RWDUF */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_COND_STOPCLK_EN_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_COND_STOPCLK_EN_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_GC5_STOPCLK_CTRL_HUBCLK_COND_STOPCLK_EN_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SPARE_0 0x0000eaf0 /* RW-4R */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_NCDISP 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_NCDISP_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_S1_NCOSM_DISPPLL_REFCLK 15:8 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_S1_NCOSM_DISPPLL_REFCLK_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_S2_NCOSM_DISPPLL_REFCLK 23:16 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_S2_NCOSM_DISPPLL_REFCLK_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_NCSPPLL0 31:24 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_0_SPARECTRL_NCSPPLL0_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_1 0x0000eaf4 /* RW-4R */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCSPPLL1 7:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCSPPLL1_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCVPLL0 15:8 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCVPLL0_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCVPLL1 23:16 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCVPLL1_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCVPLL2 31:24 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_1_SPARECTRL_NCVPLL2_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_2 0x0000eaf8 /* RW-4R */
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#define NV_PVTRIM_SYS_SPARE_2_SPARECTRL_NCVPLL3 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_2_SPARECTRL_NCVPLL3_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SPARE_2_SPARECTRL_NCDISPHUBPLL 15:8 /* RWDUF */
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#define NV_PVTRIM_SYS_SPARE_2_SPARECTRL_NCDISPHUBPLL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG 0x0000eb80 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_ENABLE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_IDDQ 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_IDDQ_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_SYNC_MODE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_TESTMODE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_TESTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_SSA 18:18 /* R--UF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_SSD 19:19 /* R--UF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_BYPASSPLL_CYA 21:21 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_LOOP_CTRL 23:22 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_RESETB 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_RESETB_ASSERT 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_RESETB_DEASSERT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_RESETB_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_SEL_TESTOUT 28:26 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_BYPASSPLL 29:29 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_BYPASSPLL_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_BYPASSPLL_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_STOP_SYNCMUX 30:30 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF 0x0000eb84 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_MDIV 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_MDIV_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_PLDIV 21:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_PLDIV_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL 0x0000eb88 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_FLL_FRUG 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_FLL_FRUG_INIT 0x00000005 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_FLL_DIV 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_FLL_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_FLL_LD_MEM 11:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_FLL_LD_MEM_INIT 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_PLL_FRUG 19:12 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_PLL_FRUG_INIT 0x00000072 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_PLL_LD_MEM 27:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_PLL_LD_MEM_INIT 0x0000001F /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_PLL_LD_TOL 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CTRL_PLL_LD_TOL_INIT 0x00000004 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_MISC 0x0000eb8c /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_MISC_EXT_FRU 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_MISC_EXT_FRU_INIT 0x00008000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2 0x0000eb90 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_LDIV 1:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_LDIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_KP_HI 4:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_KP_HI_INIT 0x00000007 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_KP_LO 7:5 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_KP_LO_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_KP_STEP_TIMER 10:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_KP_STEP_TIMER_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_FRAC_STEP_TIMER 13:11 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_FRAC_STEP_TIMER_INIT 0x00000003 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_SEL_IREF 14:14 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_SEL_IREF_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_FRAC_STEP 30:15 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG2_FRAC_STEP_INIT 0x000003E8 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG3 0x0000eb94 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CFG3_NDIV_FRAC_SSC_MIN 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG3_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG3_NDIV_FRAC_SSC_MAX 31:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG3_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG4 0x0000eb98 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CFG4_NDIV_FRAC 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG4_NDIV_FRAC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG4_NDIV 23:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG4_NDIV_INIT 0x00000028 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG4_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG4_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG5 0x0000eb9c /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CFG5_SSC_MODE 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG5_SSC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG5_SSC_DLF 31:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG5_SSC_DLF_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6 0x0000eba0 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSC_DIV 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSC_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSC_STEP 15:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSC_STEP_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSUG_HI 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSUG_HI_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSUG_LO 23:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSUG_LO_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_SSC_READY 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_EN_SSC 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG6_EN_SSC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_CFG7 0x0000eba4 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_CFG7_HPLL_CTRL 31:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_CFG7_HPLL_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE 0x0000eba8 /* RW-4R */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_SETUP 23:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_SETUP_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_VREG10V_CTRL 29:28 /* RWDUF */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISPPLL_SECURE__PRIV_LEVEL_MASK 0x0000ff00 /* */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL(i) (0x0000ec00+(i)*16) /* RW-4A */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV 3:0 /* RWDUF */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_10 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_11 0x0000000a /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_12 0x0000000b /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_13 0x0000000c /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_14 0x0000000d /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_15 0x0000000e /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_16 0x0000000f /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_3 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_4 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_5 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_6 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_7 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_8 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_BY_9 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_NIBBLE1 4:4 /* RWDUF */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_DIV_NIBBLE1_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_VCLK_SEL 9:8 /* RWDUF */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_VCLK_SEL_HEAD 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_VCLK_SEL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_VCLK_SEL_VCLK1 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_VCLK_SEL_VCLK2 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_RG_CLK_CTRL_VCLK_SEL_VCLK3 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL(i) (0x0000ec04+(i)*16) /* RW-4A */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV 3:0 /* RWDUF */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_10 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_11 0x0000000a /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_12 0x0000000b /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_13 0x0000000c /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_14 0x0000000d /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_15 0x0000000e /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_16 0x0000000f /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_3 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_4 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_5 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_6 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_7 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_8 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_BY_9 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_NIBBLE1 4:4 /* RWDUF */
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#define NV_PVTRIM_SYS_SOR_PLL_REF_CLK_CTRL_DIV_NIBBLE1_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL(i) (0x0000ec08+(i)*16) /* RW-4A */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV 3:0 /* RWDUF */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_10 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_11 0x0000000a /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_12 0x0000000b /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_13 0x0000000c /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_14 0x0000000d /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_15 0x0000000e /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_16 0x0000000f /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_3 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_4 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_5 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_6 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_7 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_8 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_BY_9 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_NIBBLE1 4:4 /* RWDUF */
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#define NV_PVTRIM_SYS_SOR_CLK_CTRL_DIV_NIBBLE1_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG 0x0000ee20 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_AZA2XBITCLK_OUT 0x00000080 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_DISPCLK_OUT 0x00000081 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_MAUDCLK_OUT 0x00000083 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_SPDIFCLK_OUT 0x00000082 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK0_ALT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK0_OUT 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK0_REF 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK1_ALT 0x00000011 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK1_OUT 0x00000010 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK1_REF 0x00000012 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK2_ALT 0x00000021 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK2_OUT 0x00000020 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK2_REF 0x00000022 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK3_ALT 0x00000031 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK3_OUT 0x00000030 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_DIVIDE_SELECT_VCLK3_REF 0x00000032 /* RW--V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_FINAL_MUX 17:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_FINAL_MUX_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_MUX_INTERNAL 28:24 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DEBUG_MUX_INTERNAL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DATA 0x0000ee24 /* R--4R */
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#define NV_PVTRIM_SYS_DISP_LINEARDIV_DATA_READ_DATA 5:0 /* R--UF */
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#define NV_PVTRIM_SYS_DISP_VPLL_DEBUG 0x0000ee28 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_VPLL_DEBUG_MUX_SELECT_PLL 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_VPLL_DEBUG_MUX_SELECT_PLL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_TEST_CTRL 0x0000ee30 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_TEST_CTRL_SOR_FTM_USE_FEEDBACK_CLKS 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_TEST_CTRL_SOR_FTM_USE_FEEDBACK_CLKS_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_TEST_CTRL_SOR_FTM_FEEDBACK_CLK_SEL 2:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_TEST_CTRL_SOR_FTM_FEEDBACK_CLK_SEL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE 0x0000ee34 /* RW-4R */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SPPLL0_O_ASYNC_MODE 1:0 /* RWEUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SPPLL0_O_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SPPLL1_O_ASYNC_MODE 3:2 /* RWEUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SPPLL1_O_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR_FEEDBACK_CLKS_ASYNC_MODE 5:4 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR_FEEDBACK_CLKS_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR0_PLL_REF_CLK_ASYNC_MODE 7:6 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR0_PLL_REF_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR0_CLK_ASYNC_MODE 9:8 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR0_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF0_CLK_ASYNC_MODE 11:10 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF0_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR1_PLL_REF_CLK_ASYNC_MODE 13:12 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR1_PLL_REF_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR1_CLK_ASYNC_MODE 15:14 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR1_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF1_CLK_ASYNC_MODE 17:16 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF1_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR2_PLL_REF_CLK_ASYNC_MODE 19:18 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR2_PLL_REF_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR2_CLK_ASYNC_MODE 21:20 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR2_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF2_CLK_ASYNC_MODE 23:22 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF2_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR3_PLL_REF_CLK_ASYNC_MODE 25:24 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR3_PLL_REF_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR3_CLK_ASYNC_MODE 27:26 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SOR3_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF3_CLK_ASYNC_MODE 29:28 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_SF3_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1 0x0000ee38 /* RW-4R */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG0_PCLK_ASYNC_MODE 1:0 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG0_PCLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG1_PCLK_ASYNC_MODE 3:2 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG1_PCLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG2_PCLK_ASYNC_MODE 5:4 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG2_PCLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG3_PCLK_ASYNC_MODE 7:6 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_1_RG3_PCLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2 0x0000ee3c /* RW-4R */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKA_AFIFO_CLK_ASYNC_MODE 1:0 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKA_AFIFO_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKB_AFIFO_CLK_ASYNC_MODE 3:2 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKB_AFIFO_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKC_AFIFO_CLK_ASYNC_MODE 5:4 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKC_AFIFO_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKD_AFIFO_CLK_ASYNC_MODE 7:6 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKD_AFIFO_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKE_AFIFO_CLK_ASYNC_MODE 9:8 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKE_AFIFO_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKF_AFIFO_CLK_ASYNC_MODE 11:10 /* RWDUF */
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#define NV_PVTRIM_SYS_SWITCH_ASYNC_MODE_2_LINKF_AFIFO_CLK_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG 0x0000ee40 /* RW-4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_ASYNC_MODE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_ONCE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_ONCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REGINTFCLK_TYPE 22:21 /* R-DUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-D-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_RESET 24:24 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_RESET_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_START_COUNT 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_START_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_CONTINOUS_UPDATE 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_SOURCE 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_SOURCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_SOURCE_VCLK0_CLK 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CFG_SOURCE_VPLL0_CLKOUT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CNT0 0x0000ee44 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CNT0_LSB 31:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CNT1 0x0000ee48 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CNT1_MSB 3:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS0_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG 0x0000ee4c /* RW-4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_ASYNC_MODE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_ONCE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_ONCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REGINTFCLK_TYPE 22:21 /* R-DUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-D-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_RESET 24:24 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_RESET_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_START_COUNT 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_START_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_CONTINOUS_UPDATE 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_SOURCE 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_SOURCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_SOURCE_VCLK1_CLK 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CFG_SOURCE_VPLL1_CLKOUT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CNT0 0x0000ee50 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CNT0_LSB 31:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CNT1 0x0000ee54 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CNT1_MSB 3:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS1_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG 0x0000ee58 /* RW-4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_ASYNC_MODE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_ONCE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_ONCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REGINTFCLK_TYPE 22:21 /* R-DUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-D-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_RESET 24:24 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_RESET_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_START_COUNT 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_START_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_CONTINOUS_UPDATE 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_SOURCE 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_SOURCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_SOURCE_VCLK2_CLK 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CFG_SOURCE_VPLL2_CLKOUT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CNT0 0x0000ee5c /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CNT0_LSB 31:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CNT1 0x0000ee60 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CNT1_MSB 3:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS2_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG 0x0000ee64 /* RW-4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_ASYNC_MODE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_ONCE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_ONCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REGINTFCLK_TYPE 22:21 /* R-DUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-D-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_RESET 24:24 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_RESET_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_START_COUNT 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_START_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_CONTINOUS_UPDATE 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_SOURCE 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_SOURCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_SOURCE_VCLK3_CLK 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CFG_SOURCE_VPLL3_CLKOUT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CNT0 0x0000ee68 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CNT0_LSB 31:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CNT1 0x0000ee6c /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CNT1_MSB 3:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_VCLKS3_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG 0x0000ee70 /* RW-4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_ASYNC_MODE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_ONCE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-DUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-D-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_RESET 24:24 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_RESET_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_START_COUNT 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_START_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_SOURCE 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_SOURCE_DISPPLL_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_SOURCE_DISPPLL_O 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CFG_SOURCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CNT0 0x0000ee74 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CNT1 0x0000ee78 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_DISPCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG 0x0000ee84 /* RW-4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_ASYNC_MODE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_ONCE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-DUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-D-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_RESET 24:24 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_RESET_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_START_COUNT 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_START_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_SOURCE 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_SOURCE_DISPHUBPLL_O 0x00000003 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_SOURCE_HUB2CLK_DIV32_FTM 0x00000002 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_SOURCE_HUBCLK_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_SOURCE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_SOURCE_SPPLL0_HUBCLK_PDIV 0x00000004 /* RW--V */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CNT0 0x0000ee88 /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CNT1 0x0000ee8c /* R--4R */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL 0x0000ee80 /* RW-4R */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKA_SRC 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKA_SRC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKA_SRC_VPLL0_REFCLK 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKA_SRC_VPLL1_REFCLK 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKA_SRC_VPLL2_REFCLK 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKA_SRC_VPLL3_REFCLK 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKB_SRC 6:4 /* RWDUF */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKB_SRC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKB_SRC_VPLL0_REFCLK 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKB_SRC_VPLL1_REFCLK 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKB_SRC_VPLL2_REFCLK 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_EXT_REFCLK_CTRL_EXT_REFCLKB_SRC_VPLL3_REFCLK 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_DSC_CLK 0x0000ee90 /* RW-4R */
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#define NV_PVTRIM_SYS_DSC_CLK_DIVISOR 4:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DSC_CLK_DIVISOR_DIV_BY_3 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_DSC_CLK_DIVISOR_DIV_BY_6 0x00000005 /* R---V */
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#define NV_PVTRIM_SYS_DSC_CLK_DIVISOR_INIT 0x00000002 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS 0x0000eea0 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKA_PCLK_REF_SEL_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKA_PCLK_REF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKA_PCLK_REF_SEL_OVERRIDE_VALUE 2:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKA_PCLK_REF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_PCLK_REF_SEL_OVERRIDE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_PCLK_REF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_PCLK_REF_SEL_OVERRIDE_VALUE 6:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_PCLK_REF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKC_PCLK_REF_SEL_OVERRIDE 7:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKC_PCLK_REF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKC_PCLK_REF_SEL_OVERRIDE_VALUE 10:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKC_PCLK_REF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_PCLK_REF_SEL_OVERRIDE 11:11 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_PCLK_REF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_PCLK_REF_SEL_OVERRIDE_VALUE 14:12 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_PCLK_REF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKE_PCLK_REF_SEL_OVERRIDE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKE_PCLK_REF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKE_PCLK_REF_SEL_OVERRIDE_VALUE 18:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKE_PCLK_REF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_PCLK_REF_SEL_OVERRIDE 19:19 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_PCLK_REF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_PCLK_REF_SEL_OVERRIDE_VALUE 22:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_PCLK_REF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_CLK_SEL_OVERRIDE 23:23 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_CLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_CLK_SEL_OVERRIDE_VALUE 24:24 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKB_CLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_CLK_SEL_OVERRIDE 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_CLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_CLK_SEL_OVERRIDE_VALUE 26:26 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKD_CLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_CLK_SEL_OVERRIDE 27:27 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_CLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_CLK_SEL_OVERRIDE_VALUE 28:28 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_DISP_2CLK_LINKF_CLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1 0x0000eea4 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKA_AFIFO_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKA_AFIFO_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKA_AFIFO_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKA_AFIFO_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKB_AFIFO_CLK_SAFE_OVERRIDE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKB_AFIFO_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKB_AFIFO_CLK_SAFE_OVERRIDE_VALUE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKB_AFIFO_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKC_AFIFO_CLK_SAFE_OVERRIDE 4:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKC_AFIFO_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKC_AFIFO_CLK_SAFE_OVERRIDE_VALUE 5:5 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKC_AFIFO_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKD_AFIFO_CLK_SAFE_OVERRIDE 6:6 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKD_AFIFO_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKD_AFIFO_CLK_SAFE_OVERRIDE_VALUE 7:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKD_AFIFO_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKE_AFIFO_CLK_SAFE_OVERRIDE 8:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKE_AFIFO_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKE_AFIFO_CLK_SAFE_OVERRIDE_VALUE 9:9 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKE_AFIFO_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKF_AFIFO_CLK_SAFE_OVERRIDE 10:10 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKF_AFIFO_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKF_AFIFO_CLK_SAFE_OVERRIDE_VALUE 11:11 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_LINK_CONTROLS_1_DISP_2CLK_LINKF_AFIFO_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD0 0x0000eea8 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD0_DISP_2CLK_RG0_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD0_DISP_2CLK_RG0_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD0_DISP_2CLK_RG0_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD0_DISP_2CLK_RG0_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD1 0x0000eeac /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD1_DISP_2CLK_RG1_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD1_DISP_2CLK_RG1_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD1_DISP_2CLK_RG1_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD1_DISP_2CLK_RG1_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD2 0x0000eeb0 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD2_DISP_2CLK_RG2_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD2_DISP_2CLK_RG2_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD2_DISP_2CLK_RG2_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD2_DISP_2CLK_RG2_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD3 0x0000eeb4 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD3_DISP_2CLK_RG3_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD3_DISP_2CLK_RG3_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD3_DISP_2CLK_RG3_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_HEAD3_DISP_2CLK_RG3_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0 0x0000eec4 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_SOR_SEL_OVERRIDE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_SOR_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_SOR_SEL_OVERRIDE_VALUE 5:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SF0_SOR_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_CLK_SAFE_OVERRIDE 7:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_CLK_SAFE_OVERRIDE_VALUE 8:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_DP_SEL_OVERRIDE 14:14 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_DP_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_DP_SEL_OVERRIDE_VALUE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_DP_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_FEEDBKCLK_SEL_OVERRIDE 16:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_FEEDBKCLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_FEEDBKCLK_SEL_OVERRIDE_VALUE 19:17 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_FEEDBKCLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_HEAD_SEL_OVERRIDE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_HEAD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_HEAD_SEL_OVERRIDE_VALUE 23:21 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR0_DISP_2CLK_SOR0_HEAD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0 0x0000eec8 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPAB_SEL_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPAB_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPAB_SEL_OVERRIDE_VALUE 2:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPAB_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPCD_SEL_OVERRIDE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPCD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPCD_SEL_OVERRIDE_VALUE 5:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPCD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPEF_SEL_OVERRIDE 6:6 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPEF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPEF_SEL_OVERRIDE_VALUE 8:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_IFPEF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_PLL_REF_CLK_SAFE_OVERRIDE 9:9 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_PLL_REF_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_PLL_REF_CLK_SAFE_OVERRIDE_VALUE 10:10 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR0_DISP_2CLK_SOR0_PLL_REF_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1 0x0000eecc /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_SOR_SEL_OVERRIDE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_SOR_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_SOR_SEL_OVERRIDE_VALUE 5:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SF1_SOR_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_CLK_SAFE_OVERRIDE 7:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_CLK_SAFE_OVERRIDE_VALUE 8:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_DP_SEL_OVERRIDE 14:14 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_DP_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_DP_SEL_OVERRIDE_VALUE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_DP_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_FEEDBKCLK_SEL_OVERRIDE 16:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_FEEDBKCLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_FEEDBKCLK_SEL_OVERRIDE_VALUE 19:17 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_FEEDBKCLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_HEAD_SEL_OVERRIDE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_HEAD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_HEAD_SEL_OVERRIDE_VALUE 23:21 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR1_DISP_2CLK_SOR1_HEAD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1 0x0000eed0 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPAB_SEL_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPAB_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPAB_SEL_OVERRIDE_VALUE 2:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPAB_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPCD_SEL_OVERRIDE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPCD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPCD_SEL_OVERRIDE_VALUE 5:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPCD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPEF_SEL_OVERRIDE 6:6 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPEF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPEF_SEL_OVERRIDE_VALUE 8:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_IFPEF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_PLL_REF_CLK_SAFE_OVERRIDE 9:9 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_PLL_REF_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_PLL_REF_CLK_SAFE_OVERRIDE_VALUE 10:10 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR1_DISP_2CLK_SOR1_PLL_REF_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2 0x0000eed4 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_SOR_SEL_OVERRIDE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_SOR_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_SOR_SEL_OVERRIDE_VALUE 5:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SF2_SOR_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_CLK_SAFE_OVERRIDE 7:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_CLK_SAFE_OVERRIDE_VALUE 8:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_DP_SEL_OVERRIDE 14:14 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_DP_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_DP_SEL_OVERRIDE_VALUE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_DP_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_FEEDBKCLK_SEL_OVERRIDE 16:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_FEEDBKCLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_FEEDBKCLK_SEL_OVERRIDE_VALUE 19:17 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_FEEDBKCLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_HEAD_SEL_OVERRIDE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_HEAD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_HEAD_SEL_OVERRIDE_VALUE 23:21 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR2_DISP_2CLK_SOR2_HEAD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2 0x0000eed8 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPAB_SEL_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPAB_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPAB_SEL_OVERRIDE_VALUE 2:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPAB_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPCD_SEL_OVERRIDE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPCD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPCD_SEL_OVERRIDE_VALUE 5:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPCD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPEF_SEL_OVERRIDE 6:6 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPEF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPEF_SEL_OVERRIDE_VALUE 8:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_IFPEF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_PLL_REF_CLK_SAFE_OVERRIDE 9:9 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_PLL_REF_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_PLL_REF_CLK_SAFE_OVERRIDE_VALUE 10:10 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR2_DISP_2CLK_SOR2_PLL_REF_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3 0x0000eedc /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_CLK_SAFE_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_CLK_SAFE_OVERRIDE_VALUE 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_SOR_SEL_OVERRIDE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_SOR_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_SOR_SEL_OVERRIDE_VALUE 5:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SF3_SOR_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_CLK_SAFE_OVERRIDE 7:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_CLK_SAFE_OVERRIDE_VALUE 8:8 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_DP_SEL_OVERRIDE 14:14 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_DP_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_DP_SEL_OVERRIDE_VALUE 15:15 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_DP_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_FEEDBKCLK_SEL_OVERRIDE 16:16 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_FEEDBKCLK_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_FEEDBKCLK_SEL_OVERRIDE_VALUE 19:17 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_FEEDBKCLK_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_HEAD_SEL_OVERRIDE 20:20 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_HEAD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_HEAD_SEL_OVERRIDE_VALUE 23:21 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_SOR3_DISP_2CLK_SOR3_HEAD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3 0x0000eee0 /* RW-4R */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPAB_SEL_OVERRIDE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPAB_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPAB_SEL_OVERRIDE_VALUE 2:1 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPAB_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPCD_SEL_OVERRIDE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPCD_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPCD_SEL_OVERRIDE_VALUE 5:4 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPCD_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPEF_SEL_OVERRIDE 6:6 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPEF_SEL_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPEF_SEL_OVERRIDE_VALUE 8:7 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_IFPEF_SEL_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_PLL_REF_CLK_SAFE_OVERRIDE 9:9 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_PLL_REF_CLK_SAFE_OVERRIDE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_PLL_REF_CLK_SAFE_OVERRIDE_VALUE 10:10 /* RWDUF */
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#define NV_PVTRIM_SYS_DISP_2CLK_OVERRIDE_DP_SOR3_DISP_2CLK_SOR3_PLL_REF_CLK_SAFE_OVERRIDE_VALUE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG(i) (0x0000ef00+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CFG__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CFG_ENABLE 0:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_IDDQ 1:1 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_IDDQ_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_SYNC_MODE 2:2 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_SYNC_MODE_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_TESTMODE 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_TESTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_LOCK 17:17 /* R--UF */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_SSA 18:18 /* R--UF */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_SSD 19:19 /* R--UF */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_CFG_BYPASSPLL_CYA 21:21 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_BYPASSPLL_CYA_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_LOOP_CTRL 23:22 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_LOOP_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_FREQLOCK 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_FREQLOCK_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_PLL_FREQLOCK_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_RESETB 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_RESETB_ASSERT 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_RESETB_DEASSERT 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_RESETB_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_SEL_TESTOUT 28:26 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_SEL_TESTOUT_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_BYPASSPLL 29:29 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG_BYPASSPLL_NO 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_BYPASSPLL_YES 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_STOP_SYNCMUX 30:30 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_COEFF(i) (0x0000ef04+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_COEFF__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_COEFF_MDIV 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_COEFF_MDIV_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_COEFF_PLDIV 21:16 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_COEFF_PLDIV_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CTRL(i) (0x0000ef08+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CTRL__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CTRL_FLL_FRUG 2:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CTRL_FLL_FRUG_INIT 0x00000005 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CTRL_FLL_DIV 3:3 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CTRL_FLL_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CTRL_FLL_LD_MEM 11:4 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CTRL_FLL_LD_MEM_INIT 0x0000000F /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CTRL_PLL_FRUG 19:12 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CTRL_PLL_FRUG_INIT 0x00000072 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CTRL_PLL_LD_MEM 27:20 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CTRL_PLL_LD_MEM_INIT 0x0000001F /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CTRL_PLL_LD_TOL 31:28 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CTRL_PLL_LD_TOL_INIT 0x00000004 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_MISC(i) (0x0000ef0c+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_MISC__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_MISC_EXT_FRU 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_MISC_EXT_FRU_INIT 0x00008000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_MISC_DEBUG_DATA 31:16 /* R--UF */
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#define NV_PVTRIM_SYS_VPLL_CFG2(i) (0x0000ef10+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CFG2__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CFG2_LDIV 1:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG2_LDIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG2_KP_HI 4:2 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG2_KP_HI_INIT 0x00000007 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG2_KP_LO 7:5 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG2_KP_LO_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG2_KP_STEP_TIMER 10:8 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG2_KP_STEP_TIMER_INIT 0x00000001 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG2_FRAC_STEP_TIMER 13:11 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG2_FRAC_STEP_TIMER_INIT 0x00000003 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG2_SEL_IREF 14:14 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG2_SEL_IREF_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG2_FRAC_STEP 30:15 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG2_FRAC_STEP_INIT 0x000003E8 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG3(i) (0x0000ef14+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CFG3__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CFG3_NDIV_FRAC_SSC_MIN 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG3_NDIV_FRAC_SSC_MIN_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG3_NDIV_FRAC_SSC_MAX 31:16 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG3_NDIV_FRAC_SSC_MAX_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG4(i) (0x0000ef18+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CFG4__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CFG4_NDIV_FRAC 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG4_NDIV_FRAC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG4_NDIV 23:16 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG4_NDIV_INIT 0x00000020 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG4_NDIV_MAX 0x000000FF /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG4_NDIV_MIN 0x00000001 /* RW--V */
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#define NV_PVTRIM_SYS_VPLL_CFG5(i) (0x0000ef1c+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CFG5__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CFG5_SSC_MODE 15:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG5_SSC_MODE_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG5_SSC_DLF 31:16 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG5_SSC_DLF_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG6(i) (0x0000ef20+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CFG6__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSC_DIV 7:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSC_DIV_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSC_STEP 15:8 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSC_STEP_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSUG_HI 19:16 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSUG_HI_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSUG_LO 23:20 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSUG_LO_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG6_SSC_READY 24:24 /* R--UF */
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#define NV_PVTRIM_SYS_VPLL_CFG6_EN_SSC 25:25 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG6_EN_SSC_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_CFG7(i) (0x0000ef24+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_CFG7__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_CFG7_HPLL_CTRL 31:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_CFG7_HPLL_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_SECURE(i) (0x0000ef28+(i)*64) /* RW-4A */
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#define NV_PVTRIM_SYS_VPLL_SECURE__SIZE_1 4 /* */
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#define NV_PVTRIM_SYS_VPLL_SECURE_SETUP 23:0 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_SECURE_SETUP_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_SECURE_VREG10V_CTRL 29:28 /* RWDUF */
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#define NV_PVTRIM_SYS_VPLL_SECURE_VREG10V_CTRL_0V95 0x00000003 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_SECURE_VREG10V_CTRL_1V0 0x00000000 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_SECURE_VREG10V_CTRL_1V05 0x00000001 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_SECURE_VREG10V_CTRL_1V1 0x00000002 /* R---V */
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#define NV_PVTRIM_SYS_VPLL_SECURE_VREG10V_CTRL_INIT 0x00000000 /* RWD-V */
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#define NV_PVTRIM_SYS_VPLL_SECURE__PRIV_LEVEL_MASK 0x0000ff0c /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK 0x00132ba0 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK 0x00132bb0 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK 0x00132940 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ONLY_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_poison_pill" /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_POISON_PILL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK 0x0013294c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "tsense_clk_priv_secure" /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TSENSE_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK 0x00132950 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "trimmer_ctrl_priv_secure" /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_GPC_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO 0x00132844 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO__PRIV_LEVEL_MASK 0x00132940 /* */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO_GPC2CLK_OUT 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO_GPC2CLK_OUT_BYPASS 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO_GPC2CLK_OUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO_GPC2CLK_OUT_VCO 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO_GPC2CLK_OUT_OVERRIDE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_SEL_VCO_GPC2CLK_OUT_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_STATUS_SEL_VCO 0x00132854 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_STATUS_SEL_VCO_GPC2CLK_OUT 0:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_STATUS_SEL_VCO_GPC2CLK_OUT_BYPASS 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_STATUS_SEL_VCO_GPC2CLK_OUT_VCO 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL 0x00132858 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC 1:0 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY2 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY3 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_BY4 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_DIVIDE_GPC_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_GPCCLK_MODE 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_GPCCLK_MODE_GPCNAFLL 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_GPCCLK_MODE_GPCPLL 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_GPCCLK_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_GPCPLL_CLK_DIVIDE_GPC 5:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_GPCPLL_CLK_DIVIDE_GPC_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_BYPASS 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_BYPASS_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_ASYNC_MODE 8:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_SRC_CONTROL_AVFS_REFCLK_GPC_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT 0x00132860 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV 5:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY10P5 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY11P5 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY12P5 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY13P5 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY14P5 0x0000001B /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY15P5 0x0000001D /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY16P5 0x0000001F /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY1P5 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY2P5 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY3P5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY4P5 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY5P5 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY6P5 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY7P5 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY8P5 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_BY9P5 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_BYPDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV 13:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY10 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY10P5 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY11 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY11P5 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY12 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY12P5 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY13 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY13P5 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY14 0x0000001A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY14P5 0x0000001B /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY15 0x0000001C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY15P5 0x0000001D /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY16 0x0000001E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY16P5 0x0000001F /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY17 0x00000020 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY18 0x00000022 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY19 0x00000024 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY1P5 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY20 0x00000026 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY21 0x00000028 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY22 0x0000002A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY23 0x0000002C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY24 0x0000002E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY25 0x00000030 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY26 0x00000032 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY27 0x00000034 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY28 0x00000036 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY29 0x00000038 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY2P5 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY3 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY30 0x0000003A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY31 0x0000003C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY3P5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY4 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY4P5 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY5 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY5P5 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY6 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY6P5 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY7 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY7P5 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY8 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY8P5 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY9 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_BY9P5 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_VCODIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_LOAD_CNT 21:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_LOAD_CNT_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_GATECLKDLY 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_GATECLKDLY_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_INT_CLOCK_GATING 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_INT_CLOCK_GATING_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_INT_CLOCK_GATING_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_INT_CLOCK_GATING_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_INT_CLOCK_GATING__PROD 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_SDIV14 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_SDIV14_INDIV1_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_SDIV14_INDIV4_MODE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_OUT_SDIV14_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW 0x00132864 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_PDIV_DELAY_CYCLES 1:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_PDIV_DELAY_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_CLK2PWR_USE_OVERRIDE 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_CLK2PWR_USE_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_CLK2PWR_FPDIV_ACK_OVERRIDE 21:21 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_CLK2PWR_FPDIV_ACK_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_FPDIV_SM_STATE 26:24 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_FPDIV_ACK 27:27 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_ASYNC_MODE 28:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_PDIV_SLOW_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG 0x00132870 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT 15:0 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPC2CLK_OUT 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCCLK_PHASEGEN 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_FINAL_MUX 17:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_FINAL_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_MUX_INTERNAL 28:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_MUX_INTERNAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DATA 0x00132874 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DATA_READ_DATA 5:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_DEBUG_OUT 0x00132900 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_DEBUG_OUT_GPCPLL_PROBE_SEL 3:0 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_DEBUG_OUT_GPCPLL_PROBE_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_IND_GPC_SPARE 0x00132914 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_IND_GPC_SPARE_CYA0 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_IND_GPC_SPARE_CYA0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_IND_GPC_SPARE_CYA0_ZEROS 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_CONTROL_0 0x00132920 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_CONTROL_0_GPCCLK_GR_STOPPED 30:30 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_CONTROL_0_GPCCLK_GR_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_CONTROL_0_GPCCLK_GR_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_CONTROL_0_GPCCLK_STOPPED 31:31 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_CONTROL_0_GPCCLK_STOPPED_NO 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_CONTROL_0_GPCCLK_STOPPED_YES 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_SPARE_0 0x00132990 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_SPARE_0_SPARECTRL_S1_NCGPCCLK 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_SPARE_0_SPARECTRL_S1_NCGPCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_SPARE_0_SPARECTRL_S2_NCGPCCLK 15:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_SPARE_0_SPARECTRL_S2_NCGPCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0 0x001329f4 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0_CHIPLETID 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0_CHIPLETID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN 30:30 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD0__PRIV_LEVEL_MASK 0x00132950 /* */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1 0x001329f8 /* -W-4R */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_PARTITIONID 7:0 /* -WIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_PARTITIONID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_MACROID 15:8 /* -WIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_MACROID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_TRIMMERID 23:16 /* -WIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_TRIMMERID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_TRIMVAL 28:24 /* -WIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_TRIMVAL_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_OP 30:30 /* -WIUF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1_OP_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_CONTROL_CMD1__PRIV_LEVEL_MASK 0x00132950 /* */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_STATUS 0x001329fc /* R--4R */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_STATUS_VALID 0:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_STATUS_TRIMVALMATCH 1:1 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_TRIMCAST_STATUS__PRIV_LEVEL_MASK 0x00132950 /* */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1 0x00132a00 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_TESTMODE 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_BYPASSFLL 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_BYPASSFLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_BYPASSFLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_BYPASSFLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_CLK_PRE_SKP 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_CLK_PRE_SKP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_CLK_PRE_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_CLK_PRE_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_PRB_CLKOUT 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_PRB_CLKOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_PRB_CLKOUT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_PRB_CLKOUT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_RESET 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SLEEP_EN_CYA 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SLEEP_EN_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SLEEP_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_OFFSET 10:9 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_EN_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_FLL_LOCK 16:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_FLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_FLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_DVCO_MIN_REACHED 17:17 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_DVCO_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_DVCO_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_LOCK_OR_MIN_REACHED 18:18 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_LOCK_OR_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_LOCK_OR_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_FREQLOCK 19:19 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_FREQLOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_FREQLOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SEL_PRB 21:20 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SEL_PRB_CLKIN 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SEL_PRB_CLKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SEL_PRB_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SEL_PRB_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_SEL_PRB_PRB_CLKIN 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG1_VFGAIN_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF 0x00132a04 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV 4:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV 21:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_PDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_FLL_FRUG_MAIN 27:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_FLL_FRUG_MAIN_INIT 0x00000009 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_FLL_FRUG_FAST 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_COEFF_FLL_FRUG_FAST_INIT 0x0000000B /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2 0x00132a08 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FLL_INIT 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FLL_INIT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FLL_LDMEM 15:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FLL_LDMEM_FORCE_LOCK 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FLL_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FLL_SWITCH_LDMEM 20:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FLL_SWITCH_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FREQLOCK_HYST 27:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_FREQLOCK_HYST_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_DVCO_MIN_REACH_HYST 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG2_DVCO_MIN_REACH_HYST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3 0x00132a0c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE 31:26 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW 23:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1 0x00132a10 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_INIT 0x0000000C /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL 3:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_1 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_8 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE 8:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE 10:9 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI 12:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI_LL_MASTER 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_PD_PRI_LW_MASTER 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL 13:13 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK 14:14 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV 16:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK 17:17 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE 19:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DVCO_SPARE 23:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DVCO_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DUTY_TUNE 28:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DUTY_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DUTY_SKEW_EN 29:29 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DUTY_SKEW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DVCO_PD_NEB 30:30 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DVCO_PD_NEB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2 0x00132a14 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL 2:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO1X 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO2X 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_DEBUG_SEL 11:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_DEBUG_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_EN_DROPCODE 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_EN_DROPCODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD 23:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_CHAIN_INIT 27:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_CHAIN_INIT_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_CTRL2_SRAM_VFGAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_MISC 0x00132a18 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_MISC_DEBUG_DATA 15:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_MISC_DROPCODE_A 20:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_MISC_DROPCODE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_MISC_DROPCODE_B 25:21 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_MISC_DROPCODE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_COEFF 0x00132a1c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_COEFF_SKP_DIVIDEND 23:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_COEFF_SKP_DIVIDEND_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_COEFF_SKP_DIVISOR 31:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_COEFF_SKP_DIVISOR_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL 0x00132a20 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_EN 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_CTRL 2:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MIN 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_CTRL_OVERRIDE_RATIO 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_RAMP_RATE 7:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_RAMP_RATE_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_INRESET 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_INRESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR 12:12 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL 24:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW 0x00132a24 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P14 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P33 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P5 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_2 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_4 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DIVIDE_RATIO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_FLL_TIMEOUT 11:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_FLL_TIMEOUT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_TRANSITION 12:12 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACK 13:13 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG 14:14 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA 16:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE 17:17 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA 18:18 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE 19:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACTIVE 20:20 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR 0x00132a40 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA 0x00132a44 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL0_NDIV 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL0_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL1_NDIV 24:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_DATA_VAL1_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR 0x00132a48 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_DATA 0x00132a4c /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_DATA_VAL0_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_DATA_VAL1_NDIV 24:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS 0x00132a50 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV_OFFSET_A 12:9 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_DVCO_OFFSET_A 15:13 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_NDIV_OFFSET_B 19:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_DVCO_OFFSET_B 22:20 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_EN_OFFSET_A 23:23 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_EN_OFFSET_B 24:24 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_OFFSET_STICKY_PARITY 29:28 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_OFFSET_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_OFFSET_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_OFFSET_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_STATUS_OFFSET_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG 0x00132a54 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_TEMP_INDEX 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_TEMP_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_RAM_READ_EN 12:12 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_RAM_READ_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_RAM_READ_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_RAM_READ_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_SKIP_BAD_DOUT 25:25 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_SKIP_BAD_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_INJECT_PARITY_ERROR 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_INJECT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_STICKY_PARITY_CLEAR 27:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CFG_STICKY_PARITY_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ 0x00132a58 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV 3:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_HW_REQ 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_SW_REQ 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_NDIV 12:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_A 16:13 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_A 19:17 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_B 23:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_B 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_FREQ_REQ_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE 0x00132a5c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_ADC_DOUT 8:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_ADC_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC 17:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_HW 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_SW 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ADC_OVERRIDE_HW_ADC_DOUT 30:24 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK 0x00132a60 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_INIT_READ_LUT_DATA 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_INIT_READ_LUT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_RDACK_LUT_DEBUG 3:3 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_INIT_READ_LUT_OFFSET_DATA 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_INIT_READ_LUT_OFFSET_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_RDACK_LUT_OFFSET_DATA 5:5 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_INIT_READ_LUT_CPM_DATA 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_INIT_READ_LUT_CPM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_ACK_RDACK_LUT_CPM_DATA 7:7 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA 0x00132a64 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_A 3:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_A 6:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_B 10:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_B 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL0_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_A 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_A 22:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_B 26:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_B 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_OFFSET_DATA_VAL1_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA 0x00132a68 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL0_NDIV_OFFSET_A 3:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL0_DVCO_OFFSET_A 6:4 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL0_NDIV_OFFSET_B 10:7 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL0_DVCO_OFFSET_B 13:11 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL1_NDIV_OFFSET_A 19:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL1_DVCO_OFFSET_A 22:20 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL1_NDIV_OFFSET_B 26:23 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_OFFSET_DATA_VAL1_DVCO_OFFSET_B 29:27 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA 0x00132ac4 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL0_CPM_OFFSET_MAX 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL0_CPM_OFFSET_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL1_CPM_OFFSET_MAX 24:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_WRITE_CPM_DATA_VAL1_CPM_OFFSET_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_CPM_DATA 0x00132ac8 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_CPM_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_CPM_DATA_VAL0_CPM_OFFSET_MAX 8:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_CPM_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_READ_CPM_DATA_VAL1_CPM_OFFSET_MAX 24:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM 0x00132acc /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM_USE_HW_MAX 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_SW_OVERRIDE_CPM_USE_SW_MAX 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_OFFSET_MAX 12:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_OFFSET_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_HW_CPM_OFFSET_MAX 24:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_ACC_ENABLE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_ACC_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_ACC_CLEAR 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_ACC_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_ACC_CAPTURE 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_SW_CTRL_CPM_CPM_ACC_CAPTURE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CPM_ACC_DATA 0x00132ad0 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CPM_ACC_DATA_VALUE_LSB 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CPM_ACC_DATA2 0x00132ad4 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CPM_ACC_DATA2_NUM_SAMPLES 27:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCLUT_CPM_ACC_DATA2_VALUE_MSB 31:28 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG1 0x00132b30 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG1_REQ_EXT_TIME 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG1_REQ_EXT_TIME_INIT 0x00000400 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG1_REQ_EXT_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG2 0x00132b34 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG2_ACK_WAIT_TIME 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG2_ACK_WAIT_TIME_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG2_ACK_WAIT_TIME_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG2_ACK_CLR_TIME 23:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG2_ACK_CLR_TIME_INIT 0x000003FD /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CFG2_ACK_CLR_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL 0x00132b38 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_REQ_EXT_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_ACK_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR 18:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_ACK 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_CLR_ACK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_EXTEND 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_IDLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_CTRL_STATE_CUR_REQ 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_REQ_CNTR 0x00132b3c /* R--4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_REQ_CNTR_VAL 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG1 0x00132b40 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG1_REQ_EXT_TIME 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG1_REQ_EXT_TIME_INIT 0x00000400 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG1_REQ_EXT_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG2 0x00132b44 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_WAIT_TIME 7:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_WAIT_TIME_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_WAIT_TIME_MAX 0x000000FF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_CLR_TIME 23:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_CLR_TIME_INIT 0x000003FD /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CFG2_ACK_CLR_TIME_MAX 0x0000FFFF /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL 0x00132b48 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_REQ_EXT_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_ACK_OVR_VAL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR 18:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_ACK 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_CLR_ACK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_EXTEND 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_IDLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_CTRL_STATE_CUR_REQ 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_REQ_CNTR 0x00132b4c /* R--4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_QUICK_SLOWDOWN_B_REQ_CNTR_VAL 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG 0x00132b50 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_EN 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_COMMON_INST_CONFIG 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_COMMON_INST_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_AVFS_OVERRIDE 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_AVFS_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_HARD_MACRO_UPDATE 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_HARD_MACRO_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_FAILURE_COUNT_MODE 12:12 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_FAILURE_COUNT_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_FAILURE_COUNT_THRESH 17:13 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_FAILURE_COUNT_THRESH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_PATH_COUNT_THRESH 22:18 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_PATH_COUNT_THRESH_INIT 0x0000001E /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_SPARE_CONFIG 31:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_SPARE_CONFIG_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_SPARE_CONFIG_VALID_WAIT_THRESHOLD 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CFG_CPM_SPARE_CONFIG_VALID_WAIT_THRESHOLD_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_FSM_CTRL 0x00132b54 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_FSM_CTRL_CPM_FSM_CTRL_CONFIG 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_FSM_CTRL_CPM_FSM_CTRL_CONFIG_INIT 0x3F33FFFF /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE 0x00132b58 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_OUTPUT_VALID 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_OUTPUT_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL_EN 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL 15:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_HARD_MACRO_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_TIMING_STATUS 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE_TIMING_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE2 0x00132b5c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE2_TIMING_FAILURE_COUNT 8:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE2_TIMING_FAILURE_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE2_MACRO_FAILURE_COUNT 16:12 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_OVERRIDE2_MACRO_FAILURE_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_STATUS0 0x00132b60 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_STATUS0_CPM_OUTPUT_VALID 0:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_STATUS0_CPM_TIMING_FAILURE_COUNT 9:1 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_STATUS0_CPM_MACRO_TIMING_STATUS 31:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_STATUS1 0x00132b64 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_STATUS1_CPM_HARD_MACRO_CTRL 11:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_STATUS1_CPM_INSTANCE_PROGRAMMED 31:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_MISC 0x00132b68 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_MISC_CPM_MISC_OUT 23:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG 0x00132b6c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_PAUSE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_PAUSE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_PAUSE_SET 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_PAUSE_UNSET 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_CLEAR 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_CLEAR_SET 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_CLEAR_UNSET 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN 5:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_THERM_SLOWDOWN_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN 7:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_QUICK_SLOWDOWN_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG 9:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_ELCG_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN 11:10 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_CLEAR 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_NONE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_BEHAVIOR_LDIV_SLOWDOWN_PAUSE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_SAMPLE_WINDOW 31:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_CLK_CFG_SAMPLE_WINDOW_INIT 0x00000800 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_THRESHOLD_LOW 0x00132b70 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_THRESHOLD_LOW_THRESHOLD_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_THRESHOLD_LOW_THRESHOLD_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_THRESHOLD_HIGH 0x00132b74 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_THRESHOLD_HIGH_THRESHOLD_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_THRESHOLD_HIGH_THRESHOLD_HIGH_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_DEBUG 0x00132b78 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_DEBUG_CURRENT_CPM_OFFSET 8:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_DEBUG2 0x00132b7c /* R--4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_DEBUG2_SAMPLED_ERROR_COUNT 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0 0x00132b80 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_0_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_0_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_0_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_0_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_0_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_0_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_1_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_1_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_1_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_1_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_1_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_1_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_2_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_2_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_2_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_2_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_2_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_2_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_3_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_3_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_3_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_3_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_3_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG0_CPM_PATH_3_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1 0x00132b84 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_4_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_4_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_4_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_4_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_4_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_4_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_5_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_5_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_5_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_5_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_5_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_5_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_6_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_6_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_6_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_6_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_6_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_6_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_7_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_7_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_7_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_7_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_7_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG1_CPM_PATH_7_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2 0x00132b88 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_8_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_8_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_8_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_8_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_8_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_8_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_9_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_9_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_9_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_9_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_9_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_9_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_10_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_10_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_10_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_10_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_10_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_10_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_11_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_11_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_11_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_11_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_11_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG2_CPM_PATH_11_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3 0x00132b8c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_12_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_12_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_12_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_12_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_12_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_12_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_13_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_13_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_13_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_13_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_13_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_13_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_14_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_14_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_14_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_14_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_14_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_14_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_15_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_15_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_15_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_15_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_15_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG3_CPM_PATH_15_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4 0x00132b90 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_16_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_16_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_16_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_16_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_16_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_16_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_17_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_17_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_17_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_17_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_17_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_17_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_18_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_18_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_18_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_18_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_18_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_18_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_19_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_19_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_19_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_19_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_19_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG4_CPM_PATH_19_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5 0x00132b94 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_20_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_20_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_20_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_20_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_20_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_20_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_21_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_21_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_21_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_21_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_21_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_21_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_22_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_22_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_22_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_22_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_22_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_22_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_23_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_23_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_23_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_23_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_23_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG5_CPM_PATH_23_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6 0x00132b98 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_24_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_24_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_24_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_24_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_24_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_24_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_25_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_25_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_25_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_25_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_25_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_25_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_26_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_26_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_26_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_26_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_26_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_26_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_27_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_27_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_27_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_27_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_27_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG6_CPM_PATH_27_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7 0x00132b9c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_28_LAUNCH_SKEW 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_28_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_28_CAPTURE_SKEW 5:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_28_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_28_MASK 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_28_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_29_LAUNCH_SKEW 10:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_29_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_29_CAPTURE_SKEW 13:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_29_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_29_MASK 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_29_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_30_LAUNCH_SKEW 18:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_30_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_30_CAPTURE_SKEW 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_30_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_30_MASK 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_30_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_31_LAUNCH_SKEW 26:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_31_LAUNCH_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_31_CAPTURE_SKEW 29:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_31_CAPTURE_SKEW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_31_MASK 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_AVFS_CPM_PATH_CFG7_CPM_PATH_31_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG 0x00132a70 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPC2CLK_NAFLL 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCCLK_NOBG_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCCLK_NOEG_CTS_PROBE 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCNAFLL_CLKOUT_PRE_SKP 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCNAFLL_UPD_CLK 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCPLL_OUT 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPC_CHIPLET_TCLKOUT 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CNT0 0x00132a74 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CNT1 0x00132a78 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG 0x00132a7c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_AVFS_REFCLK 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPC2CLK_NAFLL 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCCLK_NOBG_CTS_PROBE 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCCLK_NOEG_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCNAFLL_CLKOUT_PRE_SKP 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCNAFLL_UPD_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCPLL_DIV2_FMON 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT0 0x00132a80 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT1 0x00132a84 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL 0x00132a90 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_IDDQ_SETTLE_DELAY_US 0x00000007 /* */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ZERO_UV 0x0006DDD0 /* */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_STEP_SIZE_UV 0x0000186A /* */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_IDDQ 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_RESET 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SETUP 19:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_CLR 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_CLR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_CLR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_CLR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_ENABLE 21:21 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CAPTURE_ACC 22:22 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CAPTURE_ACC_CONTINUAL_CAPTURE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CAPTURE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CAPTURE_ACC_PAUSE_CAPTURE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE 23:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_CLOCK_GATE_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_SEL 24:24 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_SEL_CALIBRATED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ACC_SEL_UNCALIBRATED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT 28:25 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_OUT 0x00000009 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_UNBUF 0x00000007 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_0P85V_UNCAL_OUT 0x0000000A /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_ADC_TESTIN_OUT 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_CVDD_SENSE_OUT 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_GNDA_OUT 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_HIZ 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_INBUF_OUTN_OUT 0x0000000E /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_INBUF_OUTP_OUT 0x0000000D /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_IREFIN100U_TEST_IN 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_IREFOUT50U_TEST_OUT 0x00000005 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_SPARE 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VBG 0x0000000F /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VINPTEST_EXT_IN 0x00000006 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VREFN_OUT 0x0000000C /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_SEL_TESTOUT_VREFP_OUT 0x0000000B /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE_BG 30:30 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE_BG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_ENABLE_BG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_RDACK_ADC_ACC 31:31 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_RDACK_ADC_ACC_CONTINUAL_CAPTURE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL_RDACK_ADC_ACC_PAUSE_CAPTURE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_MONITOR 0x00132a94 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_MONITOR_ADC_DOUT 9:2 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_MONITOR_ADC_STAT 23:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_ACC 0x00132a9c /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_ACC_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_NUM_SAMPLES 0x00132aa0 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_NUM_SAMPLES_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL 0x00132aa4 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_GAIN 12:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_GAIN_INIT 0x00000400 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_OFFSET 25:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_DISABLE 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_DISABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CAL_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2 0x00132aa8 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OFFSET 6:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL 9:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE 10:10 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT 11:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_GAIN 20:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_GAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET 31:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL3 0x00132aac /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL3_SETUP2 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL3_SETUP2_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL4 0x00132ab0 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL4_SETUP3 15:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCNAFLL_ADC_CTRL4_SETUP3_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_HIGH_GPCCLK_DIV2 0x00132af0 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_HIGH_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_HIGH_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_HIGH_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_LOW_GPCCLK_DIV2 0x00132af4 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_LOW_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_LOW_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_THRESHOLD_LOW_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2 0x00132af8 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2 0x00132afc /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2 0x00132b00 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_ACTION_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2 0x00132b04 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2 0x00132b08 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_ENABLE_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2 0x00132b0c /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132bb0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_FAULT_STATUS_GPCCLK_DIV2_GPCCLK_DIV2_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2 0x00132b10 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_CTRL_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2 0x00132b14 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2 0x00132b18 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_2_GPCCLK_DIV2 0x00132b1c /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_2_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_LOAD_DATA_STATUS_2_GPCCLK_DIV2_GPCCLK_DIV2_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2 0x00132b20 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_CLEAR_COUNTER_GPCCLK_DIV2_GPCCLK_DIV2_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2 0x00132b24 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_CONFIG_GPCCLK_DIV2_GPCCLK_DIV2_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2 0x00132b28 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_0_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_1_GPCCLK_DIV2 0x00132b2c /* R--4R */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_1_GPCCLK_DIV2__PRIV_LEVEL_MASK 0x00132ba0 /* */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_GPC_BCAST_FMON_DEBUG_STATUS_1_GPCCLK_DIV2_GPCCLK_DIV2_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0 0x001328b0 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ 5:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ_FORCE 6:6 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_DELAYADJ_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG 9:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE 10:10 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_HALF_CYCLE_CONFIG_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_READ_ADDR 18:11 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_READ_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_READ_ADDR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_READ_ADDR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_RO_SELECT 21:19 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_RO_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_RO_SELECT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_RO_SELECT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_MODE_CFG 27:22 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_MODE_CFG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_MODE_CFG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_MODE_CFG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_TRIGGER_SEL 30:28 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_TRIGGER_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_TRIGGER_SEL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_TRIGGER_SEL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_ENABLE 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_0_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1 0x001328b4 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL_ALT_CLK 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_SEL_MAIN_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE 1:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CLK_SOURCE_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL 3:2 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK0 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK1 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK2 0x00000002 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_CLK3 0x00000003 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_ALT_CLK_SOURCE_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_TEST_DATA_IN 15:4 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_TEST_DATA_IN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_TEST_DATA_IN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_TEST_DATA_IN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_DEBUG 19:16 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_DEBUG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_DEBUG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_LOCAL_RESETN 20:20 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_LOCAL_RESETN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_LOCAL_RESETN_NO 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_LOCAL_RESETN_YES 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE 21:21 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CYCLE_COUNTER_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE 22:22 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_FIFO_SNAPSHOT_COUNTER_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CNTADJ 26:23 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CNTADJ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CNTADJ_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_CNTADJ_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ 30:27 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ_FORCE 31:31 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ_FORCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ_FORCE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_1_OPDADJ_FORCE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_2 0x001328b8 /* R--4R */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_2_DATA_OUT0 15:0 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_2_DATA_OUT0_FALSE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_2_DATA_OUT0_TRUE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_2_DATA_OUT1 31:16 /* R--UF */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_2_DATA_OUT1_FALSE 0x00000001 /* R---V */
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#define NV_PTRIM_GPC_BCAST_JITTER_MEASUREMENT_2_DATA_OUT1_TRUE 0x00000000 /* R---V */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS 0x00132890 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE_VALUE 6:1 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_LCLPWR2CLK_GPCCLK_SLOW_VAL_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE 7:7 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_VALUE 8:8 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_CLK_OVERRIDE_HW_SIGNALS_PWR2CLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2 0x00132880 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL 3:0 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_FAST_STEP_EN_GPCCLK 0x0000000b /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_FAST_STEP_EN_XBARCLK 0x00000004 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_FAST_STEP_EN_XBARCLK_FROM_FBP 0x0000000a /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_QUICKSLOWDOWN_ACK2SM_0 0x0000000d /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_QUICKSLOWDOWN_ACK2SM_1 0x0000000f /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_QUICKSLOWDOWN_REQ2NAFLL_0 0x0000000c /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_QUICKSLOWDOWN_REQ2NAFLL_1 0x0000000e /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_QUICKSLOWDOWN_SM_REQ 0x00000008 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_DEBUG_PRB2_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_DIV2_PHASEGEN_CONTROL 0x00132930 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1 0:0 /* RWIUF */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_GPC_BCAST_GPCCLK_DIV2_PHASEGEN_CONTROL_GPCCLK_CLKOUT_DIV2_FORCE_DIV1_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_GPC_BCAST_TSENSE_CLK 0x00132948 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_TSENSE_CLK__PRIV_LEVEL_MASK 0x0013294c /* */
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#define NV_PTRIM_GPC_BCAST_TSENSE_CLK_DIV_SEL_TS_CLK 9:0 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_TSENSE_CLK_DIV_SEL_TS_CLK_INIT 0x00000008 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC 0x001329a0 /* RW-4R */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_GPC_BCAST_TCLKOUT_CTRL_GPC_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST 0x001321FF:0x00132000 /* RW--D */
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#define NV_PTRIM_FBPA 0x0013FFFF:0x0012FF00 /* RW--D */
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#define NV_PTRIM_FBPA_ARRAY_STRIDE 256 /* */
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#define NV_PTRIM_FBPA_ARRAY_SIZE 6 /* */
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#define NV_PTRIM_FBPA_SPARE_0(i) (0x00130004+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_SPARE_0__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_SPARE_0_SPARECTRL_S1_NCLTCCLK 7:0 /* RWIUF */
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#define NV_PTRIM_FBPA_SPARE_0_SPARECTRL_S1_NCLTCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_SPARE_0_SPARECTRL_S2_NCLTCCLK 15:8 /* RWIUF */
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#define NV_PTRIM_FBPA_SPARE_0_SPARECTRL_S2_NCLTCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG(i) (0x00130010+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_DRAMFABRIC_CLK1 0x00000003 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_DRAMPA_CLK0 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_DRAMPA_CLK1 0x00000002 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_FBP_CHIPLET_TCLKOUT 0x00000007 /* RW--V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CNT0(i) (0x00130014+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CNT0__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CNT1(i) (0x00130018+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CNT1__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_FBPA_FR_CLK_CNTR_NCLTCCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_FBPA_IST_CTRL(i) (0x00130088+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_IST_CTRL__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE 0:0 /* RWEUF */
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#define NV_PTRIM_FBPA_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_FBPA_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_IST_CTRL_IST_MODE 1:1 /* RWEUF */
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#define NV_PTRIM_FBPA_IST_CTRL_IST_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK(i) (0x001300e0+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ONLY_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK(i) (0x001300e4+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK(i) (0x00130098+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "trimmer_ctrl_priv_secure" /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0(i) (0x001300f4+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0_CHIPLETID 7:0 /* RWIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0_CHIPLETID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN 30:30 /* RWIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN 31:31 /* RWIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD0__PRIV_LEVEL_MASK NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1(i) (0x001300f8+(i)*256) /* -W-4A */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_PARTITIONID 7:0 /* -WIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_PARTITIONID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_MACROID 15:8 /* -WIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_MACROID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_TRIMMERID 23:16 /* -WIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_TRIMMERID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_TRIMVAL 28:24 /* -WIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_TRIMVAL_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_OP 30:30 /* -WIUF */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1_OP_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_TRIMCAST_CONTROL_CMD1__PRIV_LEVEL_MASK NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_TRIMCAST_STATUS(i) (0x001300fc+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_TRIMCAST_STATUS__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_TRIMCAST_STATUS_VALID 0:0 /* R--UF */
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#define NV_PTRIM_FBPA_TRIMCAST_STATUS_TRIMVALMATCH 1:1 /* R--UF */
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#define NV_PTRIM_FBPA_TRIMCAST_STATUS__PRIV_LEVEL_MASK NV_PTRIM_FBPA_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP(i) (0x00130090+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_FBPA_TCLKOUT_CTRL_FBP_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_HIGH_DRAMCLK(i) (0x001300a0+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_HIGH_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_HIGH_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_HIGH_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_HIGH_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_LOW_DRAMCLK(i) (0x001300a4+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_LOW_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_LOW_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_LOW_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_THRESHOLD_LOW_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_COUNT_DRAMCLK(i) (0x001300a8+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_COUNT_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_COUNT_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK(i) (0x001300ac+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK(i) (0x001300b0+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK(i) (0x001300b4+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK(i) (0x001300b8+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK(i) (0x001300bc+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_TEST_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK(i) (0x001300c0+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_0_DRAMCLK(i) (0x001300c4+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_0_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_0_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_1_DRAMCLK(i) (0x001300c8+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_1_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_1_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_1_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_1_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_2_DRAMCLK(i) (0x001300cc+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_2_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_2_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_LOAD_DATA_STATUS_2_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK(i) (0x001300d0+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK(i) (0x001300d4+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK(i) (0x001300d8+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_1_DRAMCLK(i) (0x001300dc+(i)*256) /* R--4A */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_1_DRAMCLK__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_1_DRAMCLK__PRIV_LEVEL_MASK NV_PTRIM_FBPA_DYNAMIC_FMON_PRIV_LEVEL_MASK /* */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_1_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_FBPA_FMON_DEBUG_STATUS_1_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_DEBUG_PRB2(i) (0x00130008+(i)*256) /* RW-4A */
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#define NV_PTRIM_FBPA_DEBUG_PRB2__SIZE_1 6 /* */
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#define NV_PTRIM_FBPA_DEBUG_PRB2_SEL 5:0 /* RWEUF */
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#define NV_PTRIM_FBPA_DEBUG_PRB2_SEL_FAST_STEP_EN_XBARCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_DEBUG_PRB2_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_DEBUG_PRB2_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_SPARE_0 0x00132104 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_SPARE_0_SPARECTRL_S1_NCLTCCLK 7:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_SPARE_0_SPARECTRL_S1_NCLTCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_SPARE_0_SPARECTRL_S2_NCLTCCLK 15:8 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_SPARE_0_SPARECTRL_S2_NCLTCCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG 0x00132110 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_DRAMFABRIC_CLK1 0x00000003 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_DRAMPA_CLK0 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_DRAMPA_CLK1 0x00000002 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_FBP_CHIPLET_TCLKOUT 0x00000007 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CNT0 0x00132114 /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CNT1 0x00132118 /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_FBPA_BCAST_FR_CLK_CNTR_NCLTCCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_FBPA_BCAST_IST_CTRL 0x00132188 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE 0:0 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_IST_CTRL_IST_MODE 1:1 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_IST_CTRL_IST_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK 0x001321e0 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ONLY_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_DYNAMIC_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK 0x001321e4 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_fmon" /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_TEST_FMON_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK 0x00132198 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "trimmer_ctrl_priv_secure" /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_FBPA_BCAST_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0 0x001321f4 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0_CHIPLETID 7:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0_CHIPLETID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN 30:30 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN 31:31 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD0__PRIV_LEVEL_MASK 0x00132198 /* */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1 0x001321f8 /* -W-4R */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_PARTITIONID 7:0 /* -WIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_PARTITIONID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_MACROID 15:8 /* -WIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_MACROID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_TRIMMERID 23:16 /* -WIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_TRIMMERID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_TRIMVAL 28:24 /* -WIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_TRIMVAL_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_OP 30:30 /* -WIUF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1_OP_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_CONTROL_CMD1__PRIV_LEVEL_MASK 0x00132198 /* */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_STATUS 0x001321fc /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_STATUS_VALID 0:0 /* R--UF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_STATUS_TRIMVALMATCH 1:1 /* R--UF */
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#define NV_PTRIM_FBPA_BCAST_TRIMCAST_STATUS__PRIV_LEVEL_MASK 0x00132198 /* */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP 0x00132190 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_TCLKOUT_CTRL_FBP_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_HIGH_DRAMCLK 0x001321a0 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_HIGH_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_HIGH_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_HIGH 31:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_HIGH_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_HIGH_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_LOW_DRAMCLK 0x001321a4 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_LOW_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_LOW_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_LOW 31:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_THRESHOLD_LOW_DRAMCLK_DRAMCLK_FMON_COUNT_THRESH_LOW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_COUNT_DRAMCLK 0x001321a8 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_COUNT_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK 0x001321ac /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_DC_CHECK_COUNT 23:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_REF_WINDOW_DC_CHECK_COUNT_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_DC_CHECK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK 0x001321b0 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_RESET_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT 1:1 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_ACTION_DRAMCLK_DRAMCLK_FMON_ACTION_FAULT_REPORT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK 0x001321b4 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER 1:1 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN 2:2 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_CLK_WINDOW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR 3:3 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_OVERFLOW_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL 4:4 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_LOW_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL 5:5 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_HIGH_THRESH_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL 6:6 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CONFIG_DRAMCLK_DRAMCLK_FMON_REPORT_DC_FAULT_VIOL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK 0x001321b8 /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_REF_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_ERR_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS 2:2 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_ENABLE_STATUS_DRAMCLK_DRAMCLK_FMON_ENABLE_FMON_CLK_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK 0x001321bc /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK__PRIV_LEVEL_MASK 0x001321e4 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR 31:31 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR_FALSE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_CLEAR_TRUE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_DC_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT 2:2 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR 3:3 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_OVERFLOW_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS 4:4 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_FAULT_STATUS_DRAMCLK_DRAMCLK_FMON_FAULT_OUT_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK 0x001321c0 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL 2:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA 31:31 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_CTRL_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_0_DRAMCLK 0x001321c4 /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_0_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE_DISABLE 0x00000000 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE_ENABLE 0x00000001 /* R---V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_0_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_1_DRAMCLK 0x001321c8 /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_1_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_1_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_STATUS 2:0 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_1_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_SEL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_2_DRAMCLK 0x001321cc /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_2_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_LOAD_DATA_STATUS_2_DRAMCLK_DRAMCLK_FMON_LOAD_DATA_VAL 31:0 /* R--UF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK 0x001321d0 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MIN_MAX_LASTN_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR 1:1 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_MASK_MIN_MAX_COUNT_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_CLEAR_FMON_COUNTER 2:2 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_CLEAR_FMON_COUNTER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_HOLD_COUNT_SAMPLES 3:3 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_CLEAR_COUNTER_DRAMCLK_DRAMCLK_FMON_HOLD_COUNT_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK 0x001321d4 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG 0:0 /* RWIUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_ENABLE_DEBUG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_WINDOW 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_CONFIG_DRAMCLK_DRAMCLK_FMON_REF_WINDOW_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK 0x001321d8 /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_DIV2 0:0 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1 1:1 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_SYNC_FMON_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_ACK 2:2 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_CLK_REF_WINDOW_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2 3:3 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_FMON_REF_CLK_DIV2_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE 4:4 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_REF_CLK_REFERENCE_FEEDBACK_DC_NO_CHANGE_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1 5:5 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_0_DRAMCLK_DRAMCLK_OBS_FMON_ERR_CLK_CLK_COUNT_DEST_DETECTED_CHANGE_D1_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_1_DRAMCLK 0x001321dc /* R--4R */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_1_DRAMCLK__PRIV_LEVEL_MASK 0x001321e0 /* */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_1_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED 31:0 /* R-IUF */
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#define NV_PTRIM_FBPA_BCAST_FMON_DEBUG_STATUS_1_DRAMCLK_DRAMCLK_OBS_FMON_CLK_FMON_CLK_COUNT_LATCHED_INIT 0x00000000 /* R-I-V */
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#define NV_PTRIM_FBPA_BCAST_DEBUG_PRB2 0x00132108 /* RW-4R */
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#define NV_PTRIM_FBPA_BCAST_DEBUG_PRB2_SEL 5:0 /* RWEUF */
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#define NV_PTRIM_FBPA_BCAST_DEBUG_PRB2_SEL_FAST_STEP_EN_XBARCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_FBPA_BCAST_DEBUG_PRB2_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_FBPA_BCAST_DEBUG_PRB2_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK 0x00136ffc /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL_L2 0x0000000C /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_ADC_SENSE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK 0x00136ff8 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_NVDCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK 0x00136ff4 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSCLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK 0x00136ff0 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ACCESS_FUSE1 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "clocks_core_clocks" /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_PRIV_SECURE_SYSNAFLL_ADC_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_SEC2_GSP_IFF_ENABLED 0x0000004E /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR 0x00136240 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA 0x00136244 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL0_NDIV 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL0_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL1_NDIV 24:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_WRITE_DATA_VAL1_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR 0x00136248 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_DATA 0x0013624c /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_DATA_VAL0_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_READ_DATA_VAL1_NDIV 24:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_STATUS 0x00136250 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_STATUS_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_STATUS_NDIV_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_STATUS_NDIV_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_STATUS_NDIV_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG 0x00136254 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_TEMP_INDEX 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_TEMP_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_RAM_READ_EN 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_RAM_READ_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_RAM_READ_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_RAM_READ_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_SKIP_BAD_DOUT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_SKIP_BAD_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_INJECT_PARITY_ERROR 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_INJECT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_STICKY_PARITY_CLEAR 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_CFG_STICKY_PARITY_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ 0x00136258 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV 3:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_HW_REQ 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_SW_REQ 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_NDIV 12:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_NDIV_OFFSET_A 16:13 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_DVCO_OFFSET_A 19:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_NDIV_OFFSET_B 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_DVCO_OFFSET_B 26:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_SW_FREQ_REQ_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE 0x0013625c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_ADC_DOUT 8:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_ADC_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC 17:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_HW 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_SW 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ADC_OVERRIDE_HW_ADC_DOUT 30:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ACK 0x00136260 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ACK_INIT_READ_LUT_DATA 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ACK_INIT_READ_LUT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_LTCLUT_ACK_RDACK_LUT_DEBUG 3:3 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1 0x00136400 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_TESTMODE 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_BYPASSFLL 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_BYPASSFLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_BYPASSFLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_BYPASSFLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_CLK_PRE_SKP 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_CLK_PRE_SKP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_CLK_PRE_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_CLK_PRE_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_PRB_CLKOUT 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_PRB_CLKOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_PRB_CLKOUT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_PRB_CLKOUT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_RESET 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SLEEP_EN_CYA 7:7 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SLEEP_EN_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SLEEP_EN_OVERRIDE 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SLEEP_EN_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SLEEP_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SLEEP_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_OFFSET 10:9 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_EN_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_FLL_LOCK 16:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_FLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_FLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_DVCO_MIN_REACHED 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_DVCO_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_DVCO_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_LOCK_OR_MIN_REACHED 18:18 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_LOCK_OR_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_LOCK_OR_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_FREQLOCK 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_FREQLOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_FREQLOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SEL_PRB 21:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SEL_PRB_CLKIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SEL_PRB_CLKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SEL_PRB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SEL_PRB_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_SEL_PRB_PRB_CLKIN 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG1_VFGAIN_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF 0x00136404 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV 4:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV 21:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_PDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_FLL_FRUG_MAIN 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_FLL_FRUG_MAIN_INIT 0x00000009 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_FLL_FRUG_FAST 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_COEFF_FLL_FRUG_FAST_INIT 0x0000000B /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2 0x00136408 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FLL_INIT 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FLL_INIT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FLL_LDMEM 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FLL_LDMEM_FORCE_LOCK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FLL_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FLL_SWITCH_LDMEM 20:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FLL_SWITCH_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FREQLOCK_HYST 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_FREQLOCK_HYST_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_DVCO_MIN_REACH_HYST 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG2_DVCO_MIN_REACH_HYST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3 0x0013640c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE 31:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1 0x00136410 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_INIT 0x0000000C /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL 3:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_1 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_8 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE 8:7 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE 10:9 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_PD_PRI 12:11 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_PD_PRI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_PD_PRI_LL_MASTER 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_PD_PRI_LW_MASTER 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL 13:13 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_OFOV 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_OFOV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_OFOV_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_OFOV_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE 19:19 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DVCO_SPARE 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DVCO_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DUTY_TUNE 28:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DUTY_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DUTY_SKEW_EN 29:29 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DUTY_SKEW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DVCO_PD_NEB 30:30 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DVCO_PD_NEB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2 0x00136414 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL 2:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO1X 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO2X 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_DEBUG_SEL 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_DEBUG_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_EN_DROPCODE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_EN_DROPCODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_CHAIN_INIT 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_CHAIN_INIT_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_CTRL2_SRAM_VFGAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_MISC 0x00136418 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_MISC_DEBUG_DATA 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_MISC_DROPCODE_A 20:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_MISC_DROPCODE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_MISC_DROPCODE_B 25:21 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_MISC_DROPCODE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_COEFF 0x0013641c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_COEFF_SKP_DIVIDEND 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_COEFF_SKP_DIVIDEND_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_COEFF_SKP_DIVISOR 31:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_COEFF_SKP_DIVISOR_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL 0x00136420 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_EN 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_CTRL 2:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_CTRL_OVERRIDE_RATIO 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_RAMP_RATE 7:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_RAMP_RATE_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_INRESET 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_INRESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_NDIV_OVR 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_NDIV_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL 24:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW 0x00136424 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P14 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P33 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P5 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_4 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DIVIDE_RATIO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_FLL_TIMEOUT 11:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_FLL_TIMEOUT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_TRANSITION 12:12 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACK 13:13 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA 18:18 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE 19:19 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACTIVE 20:20 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR 0x00136440 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA 0x00136444 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL0_NDIV 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL0_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL1_NDIV 24:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_WRITE_DATA_VAL1_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR 0x00136448 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_DATA 0x0013644c /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_DATA_VAL0_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_READ_DATA_VAL1_NDIV 24:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_STATUS 0x00136450 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_STATUS_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_STATUS_NDIV_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_STATUS_NDIV_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_STATUS_NDIV_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG 0x00136454 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_TEMP_INDEX 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_TEMP_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_RAM_READ_EN 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_RAM_READ_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_RAM_READ_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_RAM_READ_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_SKIP_BAD_DOUT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_SKIP_BAD_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_INJECT_PARITY_ERROR 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_INJECT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_STICKY_PARITY_CLEAR 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_CFG_STICKY_PARITY_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ 0x00136458 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV 3:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_HW_REQ 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_SW_REQ 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_NDIV 12:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_NDIV_OFFSET_A 16:13 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_DVCO_OFFSET_A 19:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_NDIV_OFFSET_B 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_DVCO_OFFSET_B 26:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_SW_FREQ_REQ_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE 0x0013645c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_ADC_DOUT 8:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_ADC_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC 17:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_HW 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_SW 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ADC_OVERRIDE_HW_ADC_DOUT 30:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ACK 0x00136460 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ACK_INIT_READ_LUT_DATA 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ACK_INIT_READ_LUT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_XBARLUT_ACK_RDACK_LUT_DEBUG 3:3 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG 0x00136470 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBAR2CLK_NAFLL 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBARCLK_DIV2_FMON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBARCLK_NOBG_DUPLICATE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBARNAFLL_CLKOUT_PRE_SKP 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBARNAFLL_UPD_CLK 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBARPLL_CLKOUT 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBARPLL_REFCLK 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CNT0 0x00136474 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CNT1 0x00136478 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG 0x0013647c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_XBAR2CLK_NAFLL 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_XBARCLK_NOBG_DUPLICATE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_XBARNAFLL_CLKOUT_PRE_SKP 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_XBARNAFLL_UPD_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_XBARPLL_CLKOUT 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_XBARPLL_REFCLK 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CNT0 0x00136480 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CNT1 0x00136484 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1 0x00136600 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_TESTMODE 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_BYPASSFLL 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_BYPASSFLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_BYPASSFLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_BYPASSFLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_CLK_PRE_SKP 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_CLK_PRE_SKP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_CLK_PRE_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_CLK_PRE_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_PRB_CLKOUT 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_PRB_CLKOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_PRB_CLKOUT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_PRB_CLKOUT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_RESET 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SLEEP_EN_CYA 7:7 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SLEEP_EN_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SLEEP_EN_OVERRIDE 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SLEEP_EN_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SLEEP_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SLEEP_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_OFFSET 10:9 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_EN_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_FLL_LOCK 16:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_FLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_FLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_DVCO_MIN_REACHED 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_DVCO_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_DVCO_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_LOCK_OR_MIN_REACHED 18:18 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_LOCK_OR_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_LOCK_OR_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_FREQLOCK 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_FREQLOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_FREQLOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SEL_PRB 21:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SEL_PRB_CLKIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SEL_PRB_CLKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SEL_PRB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SEL_PRB_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_SEL_PRB_PRB_CLKIN 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1_VFGAIN_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG1__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF 0x00136604 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV 4:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV 21:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_PDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_FLL_FRUG_MAIN 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_FLL_FRUG_MAIN_INIT 0x00000009 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_FLL_FRUG_FAST 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF_FLL_FRUG_FAST_INIT 0x0000000B /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_COEFF__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2 0x00136608 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FLL_INIT 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FLL_INIT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FLL_LDMEM 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FLL_LDMEM_FORCE_LOCK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FLL_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FLL_SWITCH_LDMEM 20:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FLL_SWITCH_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FREQLOCK_HYST 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_FREQLOCK_HYST_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_DVCO_MIN_REACH_HYST 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2_DVCO_MIN_REACH_HYST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG2__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3 0x0013660c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE 31:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CFG3__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1 0x00136610 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_INIT 0x0000000C /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL 3:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_1 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_8 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE 8:7 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE 10:9 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_PD_PRI 12:11 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_PD_PRI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_PD_PRI_LL_MASTER 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_PD_PRI_LW_MASTER 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL 13:13 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_OFOV 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_OFOV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_OFOV_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_OFOV_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE 19:19 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DVCO_SPARE 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DVCO_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DUTY_TUNE 28:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DUTY_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DUTY_SKEW_EN 29:29 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DUTY_SKEW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DVCO_PD_NEB 30:30 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DVCO_PD_NEB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL1__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2 0x00136614 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL 2:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO1X 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO2X 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_DEBUG_SEL 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_DEBUG_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_EN_DROPCODE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_EN_DROPCODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_CHAIN_INIT 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_CHAIN_INIT_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2_SRAM_VFGAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_CTRL2__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_MISC 0x00136618 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_MISC_DEBUG_DATA 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_MISC_DROPCODE_A 20:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_MISC_DROPCODE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_MISC_DROPCODE_B 25:21 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_MISC_DROPCODE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_MISC__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_COEFF 0x0013661c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_COEFF_SKP_DIVIDEND 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_COEFF_SKP_DIVIDEND_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_COEFF_SKP_DIVISOR 31:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_COEFF_SKP_DIVISOR_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_COEFF__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL 0x00136620 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_EN 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_CTRL 2:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_CTRL_OVERRIDE_RATIO 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_RAMP_RATE 7:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_RAMP_RATE_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_INRESET 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_INRESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_NDIV_OVR 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_NDIV_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL 24:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_SKP_CTRL__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW 0x00136624 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P14 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P33 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P5 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_4 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DIVIDE_RATIO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_FLL_TIMEOUT 11:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_FLL_TIMEOUT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_TRANSITION 12:12 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACK 13:13 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA 18:18 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE 19:19 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACTIVE 20:20 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDNAFLL_DVCO_SLOW__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR 0x00136640 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_ADDR__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA 0x00136644 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL0_NDIV 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL0_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL1_NDIV 24:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA_VAL1_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_WRITE_DATA__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR 0x00136648 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_ADDR__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_DATA 0x0013664c /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_DATA_VAL0_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_READ_DATA_VAL1_NDIV 24:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_STATUS 0x00136650 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_STATUS_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_STATUS_NDIV_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_STATUS_NDIV_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_STATUS_NDIV_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG 0x00136654 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_TEMP_INDEX 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_TEMP_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_RAM_READ_EN 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_RAM_READ_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_RAM_READ_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_RAM_READ_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_SKIP_BAD_DOUT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_SKIP_BAD_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_INJECT_PARITY_ERROR 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_INJECT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_STICKY_PARITY_CLEAR 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG_STICKY_PARITY_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_CFG__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ 0x00136658 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV 3:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_HW_REQ 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_SW_REQ 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_NDIV 12:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_NDIV_OFFSET_A 16:13 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_DVCO_OFFSET_A 19:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_NDIV_OFFSET_B 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_DVCO_OFFSET_B 26:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_SW_FREQ_REQ__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE 0x0013665c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_ADC_DOUT 8:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_ADC_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC 17:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_HW 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_SW 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE_HW_ADC_DOUT 30:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ADC_OVERRIDE__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ACK 0x00136660 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ACK_INIT_READ_LUT_DATA 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ACK_INIT_READ_LUT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ACK_RDACK_LUT_DEBUG 3:3 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_NVDLUT_ACK__PRIV_LEVEL_MASK 0x00136ff8 /* */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG 0x00136670 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVD2CLK_NAFLL 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVDCLK_NOBG_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVDCLK_NOBG_CTS_PROBE_DUPLICATE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVDNAFLL_CLKOUT_PRE_SKP 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVDNAFLL_UPD_CLK 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVDPLL_OUT 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVDPLL_REFCLK 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CNT0 0x00136674 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CNT1 0x00136678 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG 0x0013667c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVD2CLK_NAFLL 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVDCLK_NOBG_DUPLICATE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVDNAFLL_CLKOUT_PRE_SKP 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVDNAFLL_CLKOUT_PRE_SKP_DUPLICATE 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVDNAFLL_UPD_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVDPLL_OUT 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVDPLL_REFCLK 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CNT0 0x00136680 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CNT1 0x00136684 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1 0x00136800 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_ENABLE 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_IDDQ 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_IDDQ_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_TESTMODE 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_TESTMODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_BYPASSFLL 3:3 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_BYPASSFLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_BYPASSFLL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_BYPASSFLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_CLK_PRE_SKP 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_CLK_PRE_SKP_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_CLK_PRE_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_CLK_PRE_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_PRB_CLKOUT 5:5 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_PRB_CLKOUT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_PRB_CLKOUT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_PRB_CLKOUT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_RESET 6:6 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_RESET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SLEEP_EN_CYA 7:7 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SLEEP_EN_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SLEEP_EN_OVERRIDE 8:8 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SLEEP_EN_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SLEEP_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SLEEP_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_OFFSET 10:9 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_EN_OFFSET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_FLL_LOCK 16:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_FLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_FLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_DVCO_MIN_REACHED 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_DVCO_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_DVCO_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_LOCK_OR_MIN_REACHED 18:18 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_LOCK_OR_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_LOCK_OR_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_FREQLOCK 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_FREQLOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_FREQLOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SEL_PRB 21:20 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SEL_PRB_CLKIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SEL_PRB_CLKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SEL_PRB_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SEL_PRB_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_SEL_PRB_PRB_CLKIN 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_VFGAIN 31:28 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG1_VFGAIN_INIT 0x00000003 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF 0x00136804 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV 4:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_MDIV_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV 21:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_PDIV_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_FLL_FRUG_MAIN 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_FLL_FRUG_MAIN_INIT 0x00000009 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_FLL_FRUG_FAST 31:28 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_COEFF_FLL_FRUG_FAST_INIT 0x0000000B /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2 0x00136808 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FLL_INIT 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FLL_INIT_INIT 0x0000000A /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FLL_LDMEM 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FLL_LDMEM_FORCE_LOCK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FLL_LDMEM_INIT 0x0000000A /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FLL_SWITCH_LDMEM 20:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FLL_SWITCH_LDMEM_INIT 0x0000000A /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FREQLOCK_HYST 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_FREQLOCK_HYST_INIT 0x00000003 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_DVCO_MIN_REACH_HYST 31:28 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG2_DVCO_MIN_REACH_HYST_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3 0x0013680c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE 31:26 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL 8:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1 0x00136810 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL 15:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_INIT 0x0000000C /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL 3:2 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_1 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_8 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_INIT 0x00000003 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC 6:6 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE 8:7 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE 10:9 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_PD_PRI 12:11 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_PD_PRI_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_PD_PRI_LL_MASTER 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_PD_PRI_LW_MASTER 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL 13:13 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK 14:14 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP 31:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_OFOV 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_OFOV_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_OFOV_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_OFOV_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK 17:17 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE 19:19 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DVCO_SPARE 23:20 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DVCO_SPARE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DUTY_TUNE 28:24 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DUTY_TUNE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DUTY_SKEW_EN 29:29 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DUTY_SKEW_EN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DVCO_PD_NEB 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DVCO_PD_NEB_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2 0x00136814 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_INIT 0x0000000A /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL 2:1 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO1X 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO2X 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP 3:3 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_DEBUG_SEL 11:8 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_DEBUG_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_EN_DROPCODE 15:15 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_EN_DROPCODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM 19:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_INIT 0x00000005 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD 23:20 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_INIT 0x00000002 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_CHAIN_INIT 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_CHAIN_INIT_INIT 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_VFGAIN 31:28 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_CTRL2_SRAM_VFGAIN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_MISC 0x00136818 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_MISC_DEBUG_DATA 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_MISC_DROPCODE_A 20:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_MISC_DROPCODE_A_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_MISC_DROPCODE_B 25:21 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_MISC_DROPCODE_B_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_COEFF 0x0013681c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_COEFF_SKP_DIVIDEND 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_COEFF_SKP_DIVIDEND_INIT 0x000000FF /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_COEFF_SKP_DIVISOR 31:24 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_COEFF_SKP_DIVISOR_INIT 0x000000FF /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL 0x00136820 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_EN 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_EN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_CTRL 2:1 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_CTRL_OVERRIDE_RATIO 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_RAMP_RATE 7:3 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_RAMP_RATE_INIT 0x00000005 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_INRESET 8:8 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_INRESET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_NDIV_OVR 12:12 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_NDIV_OVR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL 24:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW 0x00136824 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO 2:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P14 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P33 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P5 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_4 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DIVIDE_RATIO_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_FLL_TIMEOUT 11:4 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_FLL_TIMEOUT_INIT 0x0000000A /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_TRANSITION 12:12 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACK 13:13 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG 14:14 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ 15:15 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE 17:17 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE 19:19 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACTIVE 20:20 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR 0x00136840 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR_OFFSET 8:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR_OFFSET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR_AUTO_INC 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR_AUTO_INC_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA 0x00136844 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL0 15:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL0_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL1 31:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL1_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL0_NDIV 8:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL0_NDIV_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL1_NDIV 24:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_WRITE_DATA_VAL1_NDIV_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR 0x00136848 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR_OFFSET 8:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR_OFFSET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR_AUTO_INC 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR_AUTO_INC_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_DATA 0x0013684c /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_DATA_VAL0_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_READ_DATA_VAL1_NDIV 24:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_STATUS 0x00136850 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_STATUS_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_STATUS_NDIV_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_STATUS_NDIV_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_STATUS_NDIV_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG 0x00136854 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_TEMP_INDEX 2:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_TEMP_INDEX_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_RAM_READ_EN 12:12 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_RAM_READ_EN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_RAM_READ_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_RAM_READ_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_SKIP_BAD_DOUT 25:25 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_SKIP_BAD_DOUT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_INJECT_PARITY_ERROR 26:26 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_INJECT_PARITY_ERROR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_STICKY_PARITY_CLEAR 27:27 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_CFG_STICKY_PARITY_CLEAR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ 0x00136858 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV 3:2 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_HW_REQ 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_SW_REQ 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_NDIV 12:4 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_NDIV_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_NDIV_OFFSET_A 16:13 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_NDIV_OFFSET_A_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_DVCO_OFFSET_A 19:17 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_DVCO_OFFSET_A_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_NDIV_OFFSET_B 23:20 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_NDIV_OFFSET_B_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_DVCO_OFFSET_B 26:24 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_SW_FREQ_REQ_DVCO_OFFSET_B_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE 0x0013685c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_ADC_DOUT 8:1 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_ADC_DOUT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC 17:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_HW 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_SW 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ADC_OVERRIDE_HW_ADC_DOUT 30:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ACK 0x00136860 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ACK_INIT_READ_LUT_DATA 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ACK_INIT_READ_LUT_DATA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_HOSTLUT_ACK_RDACK_LUT_DEBUG 3:3 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG 0x0013687c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_SOURCE_HOSTCLK_NAFLL_BUF 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_SOURCE_HOSTCLK_NOBG_DUPLICATE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_SOURCE_HOSTNAFLL_CLKOUT_PRE_SKP 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_SOURCE_HOSTNAFLL_UPD_CLK_BUF 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CNT0 0x00136880 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CNT1 0x00136884 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCHOSTNAFLL_FREQ_PID_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1 0x00136e00 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_IDDQ 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_TESTMODE 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_BYPASSFLL 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_BYPASSFLL_BYPASSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_BYPASSFLL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_BYPASSFLL_VCO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_CLK_PRE_SKP 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_CLK_PRE_SKP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_CLK_PRE_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_CLK_PRE_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_PRB_CLKOUT 5:5 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_PRB_CLKOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_PRB_CLKOUT_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_PRB_CLKOUT_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_RESET 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SLEEP_EN_CYA 7:7 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SLEEP_EN_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SLEEP_EN_OVERRIDE 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SLEEP_EN_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SLEEP_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SLEEP_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_OFFSET 10:9 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_EN_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_FLL_LOCK 16:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_FLL_LOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_FLL_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_DVCO_MIN_REACHED 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_DVCO_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_DVCO_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_LOCK_OR_MIN_REACHED 18:18 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_LOCK_OR_MIN_REACHED_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_LOCK_OR_MIN_REACHED_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_FREQLOCK 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_FREQLOCK_FALSE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_FREQLOCK_TRUE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SEL_PRB 21:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SEL_PRB_CLKIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SEL_PRB_CLKOUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SEL_PRB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SEL_PRB_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_SEL_PRB_PRB_CLKIN 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1_VFGAIN_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG1__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF 0x00136e04 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV 4:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV 21:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_CLAMPED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV1 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV10 0x0000000a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV11 0x0000000b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV12 0x0000000c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV13 0x0000000d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV14 0x0000000e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV15 0x0000000f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV16 0x00000010 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV17 0x00000011 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV18 0x00000012 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV19 0x00000013 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV2 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV20 0x00000014 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV21 0x00000015 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV22 0x00000016 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV23 0x00000017 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV24 0x00000018 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV25 0x00000019 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV26 0x0000001a /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV27 0x0000001b /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV28 0x0000001c /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV29 0x0000001d /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV3 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV30 0x0000001e /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV31 0x0000001f /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV4 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV5 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV6 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV7 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV8 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_DIV9 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_PDIV_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_FLL_FRUG_MAIN 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_FLL_FRUG_MAIN_INIT 0x00000009 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_FLL_FRUG_FAST 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF_FLL_FRUG_FAST_INIT 0x0000000B /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_COEFF__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2 0x00136e08 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FLL_INIT 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FLL_INIT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FLL_LDMEM 15:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FLL_LDMEM_FORCE_LOCK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FLL_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FLL_SWITCH_LDMEM 20:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FLL_SWITCH_LDMEM_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FREQLOCK_HYST 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_FREQLOCK_HYST_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_DVCO_MIN_REACH_HYST 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2_DVCO_MIN_REACH_HYST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG2__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3 0x00136e0c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE 31:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_PD_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LW_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3_DVCO_DLY_TUNE_OVERRIDE_CODE_LL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CFG3__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1 0x00136e10 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_INIT 0x0000000C /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_CLEAR_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL 3:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_1 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_DIV_BY_8 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_ASYMMETRIC_BW_CTRL_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DVCO_PD_TEST_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC 6:6 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_USE_DROPCODE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE 8:7 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DROPCODE_A_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE 10:9 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DROPCODE_B_RATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_PD_PRI 12:11 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_PD_PRI_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_PD_PRI_LL_MASTER 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_PD_PRI_LW_MASTER 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL 13:13 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DVCO_DIV_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_BY_4 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_FLL_CTRL_DIV_UPD_CLK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_OFOV 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_OFOV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_OFOV_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_OFOV_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_FLL_LOCK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE 19:19 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_FORCE_OFOV_SLAVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DVCO_SPARE 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DVCO_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DUTY_TUNE 28:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DUTY_TUNE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DUTY_SKEW_EN 29:29 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DUTY_SKEW_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DVCO_PD_NEB 30:30 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DVCO_PD_NEB_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1_SETUP_DISABLE_SYNC3D_MUX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL1__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2 0x00136e14 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_DVCO_CTRL_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL 2:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO1X 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_DVCO2X 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_FLL_SEL_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP 3:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_BYPASS_SKP_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_FLL_OVERRIDE_USE_NEW_SKIPPER_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_DEBUG_SEL 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_DEBUG_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_EN_DROPCODE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_EN_DROPCODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_CHAIN_STATUS_ACCU_NUM_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_CHAIN_STATUS_THRESHOLD_INIT 0x00000002 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_CHAIN_INIT 27:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_CHAIN_INIT_INIT 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_VFGAIN 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2_SRAM_VFGAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_CTRL2__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_MISC 0x00136e18 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_MISC_DEBUG_DATA 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_MISC_DROPCODE_A 20:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_MISC_DROPCODE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_MISC_DROPCODE_B 25:21 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_MISC_DROPCODE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_MISC__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_COEFF 0x00136e1c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_COEFF_SKP_DIVIDEND 23:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_COEFF_SKP_DIVIDEND_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_COEFF_SKP_DIVISOR 31:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_COEFF_SKP_DIVISOR_INIT 0x000000FF /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_COEFF__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL 0x00136e20 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_EN 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_CTRL 2:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MIN 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_CTRL_AUTO_MODE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_CTRL_OVERRIDE_RATIO 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_RAMP_RATE 7:3 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_RAMP_RATE_INIT 0x00000005 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_INRESET 8:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_INRESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_NDIV_OVR 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_NDIV_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL 24:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL_SKP_NDIV_OVR_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_SKP_CTRL__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW 0x00136e24 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P14 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P33 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_1P5 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_2 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO_DIV_BY_4 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DIVIDE_RATIO_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_FLL_TIMEOUT 11:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_FLL_TIMEOUT_INIT 0x0000000A /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_TRANSITION 12:12 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACK 13:13 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG 14:14 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA 16:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE 17:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_REQ_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA 18:18 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE 19:19 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_MSG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW_DVCO_SLOWDOWN_ACTIVE 20:20 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_DVCO_SLOW__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR 0x00136e40 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_ADDR__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA 0x00136e44 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL0 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL0_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL1 31:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL1_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL0_NDIV 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL0_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL1_NDIV 24:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA_VAL1_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_WRITE_DATA__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR 0x00136e48 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR_OFFSET 8:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR_OFFSET_MAX 0x000000BF /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR_AUTO_INC 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR_AUTO_INC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR_AUTO_INC_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR_AUTO_INC_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_ADDR__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_DATA 0x00136e4c /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_DATA_VAL0 15:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_DATA_VAL1 31:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_DATA_VAL0_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_READ_DATA_VAL1_NDIV 24:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_STATUS 0x00136e50 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_STATUS_NDIV 8:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_STATUS_NDIV_STICKY_PARITY 31:30 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_HIGH 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_STATUS_NDIV_STICKY_PARITY_LATENT_FAULT_LOW 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_STATUS_NDIV_STICKY_PARITY_OK 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_STATUS_NDIV_STICKY_PARITY_PARITY_FAULT 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG 0x00136e54 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_TEMP_INDEX 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_TEMP_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_RAM_READ_EN 12:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_RAM_READ_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_RAM_READ_EN_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_RAM_READ_EN_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_SKIP_BAD_DOUT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_SKIP_BAD_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_INJECT_PARITY_ERROR 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_INJECT_PARITY_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_STICKY_PARITY_CLEAR 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG_STICKY_PARITY_CLEAR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_CFG__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ 0x00136e58 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV 3:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_HW_REQ 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_SW_OVERRIDE_NDIV_USE_SW_REQ 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_NDIV 12:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_NDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_NDIV_OFFSET_A 16:13 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_NDIV_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_DVCO_OFFSET_A 19:17 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_DVCO_OFFSET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_NDIV_OFFSET_B 23:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_NDIV_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_DVCO_OFFSET_B 26:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ_DVCO_OFFSET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_SW_FREQ_REQ__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE 0x00136e5c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_ADC_DOUT 8:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_ADC_DOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC 17:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_HW 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_MIN 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_SW_OVERRIDE_ADC_USE_SW 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE_HW_ADC_DOUT 30:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ADC_OVERRIDE__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ACK 0x00136e60 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ACK_INIT_READ_LUT_DATA 4:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ACK_INIT_READ_LUT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ACK_RDACK_LUT_DEBUG 3:3 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSLUT_ACK__PRIV_LEVEL_MASK 0x00136ff4 /* */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG 0x00136e7c /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYS2CLK_NAFLL 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYSCLK_NOBG_CTS_PROBE 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYSCLK_NOEG_CTS_PROBE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYSNAFLL_CLKOUT_PRE_SKP 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYSNAFLL_UPD_CLK 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYSPLL_O 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYSPLL_REFCLK 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CNT0 0x00136e80 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CNT1 0x00136e84 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL 0x00136e90 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_IDDQ_SETTLE_DELAY_US 0x00000007 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ZERO_UV 0x0006DDD0 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_STEP_SIZE_UV 0x0000186A /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_IDDQ 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_IDDQ_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_RESET 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_RESET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SETUP 19:4 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SETUP_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_CLR 20:20 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_CLR_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_CLR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_CLR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_ENABLE 21:21 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_ENABLE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CAPTURE_ACC 22:22 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CAPTURE_ACC_CONTINUAL_CAPTURE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CAPTURE_ACC_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CAPTURE_ACC_PAUSE_CAPTURE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CLOCK_GATE_DISABLE 23:23 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CLOCK_GATE_DISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CLOCK_GATE_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_CLOCK_GATE_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_SEL 24:24 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_SEL_CALIBRATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ACC_SEL_UNCALIBRATED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT 28:25 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_OUT 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_UNBUF 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_0P85V_UNCAL_OUT 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_ADC_TESTIN_OUT 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_CVDD_SENSE_OUT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_GNDA_OUT 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_HIZ 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_INBUF_OUTN_OUT 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_INBUF_OUTP_OUT 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_IREFIN100U_TEST_IN 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_IREFOUT50U_TEST_OUT 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_SPARE 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_VBG 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_VINPTEST_EXT_IN 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_VREFN_OUT 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_SEL_TESTOUT_VREFP_OUT 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE_BG 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE_BG_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE_BG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_ENABLE_BG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_RDACK_ADC_ACC 31:31 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_RDACK_ADC_ACC_CONTINUAL_CAPTURE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL_RDACK_ADC_ACC_PAUSE_CAPTURE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL__PRIV_LEVEL_MASK 0x00136ff0 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_MONITOR 0x00136e94 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_MONITOR_ADC_DOUT 9:2 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_MONITOR_ADC_STAT 23:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_ACC 0x00136e9c /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_ACC_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_NUM_SAMPLES 0x00136ea0 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_NUM_SAMPLES_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL 0x00136ea4 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_GAIN 12:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_GAIN_INIT 0x00000400 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_OFFSET 25:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_OFFSET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_DISABLE 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_DISABLE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CAL__PRIV_LEVEL_MASK 0x00136ff0 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2 0x00136ea8 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_OFFSET 6:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_OFFSET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL 9:8 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE 10:10 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT 11:11 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_GAIN 20:16 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_GAIN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET 31:28 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL2__PRIV_LEVEL_MASK 0x00136ff0 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL3 0x00136eac /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL3_SETUP2 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL3_SETUP2_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL3__PRIV_LEVEL_MASK 0x00136ff0 /* */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL4 0x00136eb0 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL4_SETUP3 15:0 /* RWEUF */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL4_SETUP3_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NAFLL_SYSNAFLL_NVVDD_ADC_CTRL4__PRIV_LEVEL_MASK 0x00136ff0 /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL 0x00136ee0 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_IDDQ_SETTLE_DELAY_US 0x00000007 /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ZERO_UV 0x0006DDD0 /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_STEP_SIZE_UV 0x0000186A /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_IDDQ 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_IDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_IDDQ_POWER_OFF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_IDDQ_POWER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE 1:1 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_RESET 2:2 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SETUP 19:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SETUP_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_CLR 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_CLR_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_CLR_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_CLR_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_ENABLE 21:21 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CAPTURE_ACC 22:22 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CAPTURE_ACC_CONTINUAL_CAPTURE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CAPTURE_ACC_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CAPTURE_ACC_PAUSE_CAPTURE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CLOCK_GATE_DISABLE 23:23 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CLOCK_GATE_DISABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CLOCK_GATE_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_CLOCK_GATE_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_SEL 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_SEL_CALIBRATED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ACC_SEL_UNCALIBRATED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT 28:25 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_OUT 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_0P85V_CAL_UNBUF 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_0P85V_UNCAL_OUT 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_ADC_TESTIN_OUT 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_GNDA_OUT 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_INBUF_OUTN_OUT 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_INBUF_OUTP_OUT 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_IREFIN100U_TEST_IN 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_IREFOUT50U_TEST_OUT 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_NORMAL_OPERATION_IN 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_VBG 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_VREFN_OUT 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_SEL_TESTOUT_VREFP_OUT 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE_BG 30:30 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE_BG_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_ENABLE_BG_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_RDACK_ADC_ACC 31:31 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_RDACK_ADC_ACC_CONTINUAL_CAPTURE 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL_RDACK_ADC_ACC_PAUSE_CAPTURE 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL__PRIV_LEVEL_MASK 0x00136ffc /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MONITOR 0x00136ee4 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MONITOR_ADC_DOUT 9:2 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MONITOR_ADC_STAT 23:16 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MONITOR__PRIV_LEVEL_MASK 0x00136ffc /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_ACC 0x00136eec /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_ACC_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_NUM_SAMPLES 0x00136ef0 /* R--4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_NUM_SAMPLES_VALUE 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL 0x00136ef4 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_GAIN 12:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_GAIN_INIT 0x00000400 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_OFFSET 25:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_DISABLE 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_DISABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CAL__PRIV_LEVEL_MASK 0x00136ffc /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2 0x00136ef8 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_OFFSET 6:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL 9:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_DUTY_CYCLE_CONTROL_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE 10:10 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_DOUT_MUX_ACTIVE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT 11:11 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_OVERRIDE_VDD_DETECT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_GAIN 20:16 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_GAIN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2_ADC_CTRL_COARSE_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL2__PRIV_LEVEL_MASK 0x00136ffc /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL3 0x00136efc /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL3_SETUP2 31:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL3_SETUP2_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL3__PRIV_LEVEL_MASK 0x00136ffc /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL4 0x00136f00 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL4_SETUP3 15:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL4_SETUP3_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_CTRL4__PRIV_LEVEL_MASK 0x00136ffc /* */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER 0x00136f04 /* RW-4R */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_ENABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_ENABLE_OFF 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_ENABLE_ON 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DIV_SEL 5:4 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DIV_SEL_DIV1 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DIV_SEL_DIV2 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DIV_SEL_DIV3 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DIV_SEL_DIV4 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DIV_SEL_INIT 0x00000003 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_NUM_SAMPLES 11:8 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_NUM_SAMPLES_INIT 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DISCARD_SAMPLES 13:12 /* RWIUF */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER_DISCARD_SAMPLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NAFLL_SYS_PWR_SENSE_ADC_MULTISAMPLER__PRIV_LEVEL_MASK 0x00136ffc /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK 0x001327fc /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "nvlinks_physical_damage" /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_NVLINKS_PHYSICAL_DAMAGE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK 0x001327f8 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ONLY_ACCESS_FUSE1 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "trimmer_ctrl_priv_secure" /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTRIM_SYS_NVLINK_PRIV_SECURE_TRIMMER_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG 0x00132400 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_UPDATE_CYCLES 2:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_UPDATE_CYCLES_EVERY_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_UPDATE_CYCLES_EVERY_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_UPDATE_CYCLES_EVERY_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_UPDATE_CYCLES_EVERY_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_UPDATE_CYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_ASYNC_MODE 20:20 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_ASYNC_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_ASYNC_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_ASYNC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_ONCE 15:15 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_ONCE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_ONCE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_ONCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES 19:16 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_1024 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_12288 0x0000000F /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_128 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_1536 0x0000000C /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_192 0x00000009 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_2048 0x00000005 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_256 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_3072 0x0000000D /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_384 0x0000000A /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_4096 0x00000006 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_512 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_6144 0x0000000E /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_64 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_768 0x0000000B /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_8192 0x00000007 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_96 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_COUNT_NUMCYCLES_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REGINTFCLK_TYPE 22:21 /* R-IUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REGINTFCLK_TYPE_100M 0x00000003 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REGINTFCLK_TYPE_108M 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REGINTFCLK_TYPE_27M 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REGINTFCLK_TYPE_540M 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REGINTFCLK_TYPE_INIT 0x00000001 /* R-I-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_RESET 24:24 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_RESET_ASSERTED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_RESET_DEASSERTED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_START_COUNT 25:25 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_START_COUNT_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_START_COUNT_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_START_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA 26:26 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_REG_INTFC_CLK_SLCG_DISABLE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_CONTINOUS_UPDATE 27:27 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_CONTINOUS_UPDATE_DISABLED 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_CONTINOUS_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_CONTINOUS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_SOURCE 31:28 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_SOURCE_NVHS0_REFCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_SOURCE_NVHS1_REFCLK 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CFG_SOURCE_NVHS2_REFCLK 0x00000003 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CNT0 0x00132404 /* R--4R */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CNT0_LSB 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CNT1 0x00132408 /* R--4R */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CNT1_MSB 3:0 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_LNK_FR_CLK_CNTR_CNT1_STATUS_SWITCH 31:24 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_UPHY_CFG 0x00132410 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_UPHY_CFG_LOCKDECT_WAIT_DLY_LENGTH 9:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_UPHY_CFG_LOCKDECT_WAIT_DLY_LENGTH_INIT 0x0000032A /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_UPHY_CFG_PHY2CLKS_USE_LOCKDET 12:12 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_UPHY_CFG_PHY2CLKS_USE_LOCKDET_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_UPHY_CFG_NVLINK_WAIT_DLY 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_UPHY_CFG_NVLINK_WAIT_DLY_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE 0x00132414 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL0 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL0_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_NVL_RX_LANE_ASYNC_MODE_SEL0 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_NVL_RX_LANE_ASYNC_MODE_SEL0_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_TX_CLK_SWITCH_ASYNC_MODE 8:7 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_TX_CLK_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL1 3:3 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL1_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL2 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL2_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL3 5:5 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_LINKCLK_RX_SW_SWITCH_ASYNC_MODE_SEL3_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_NVL_RX_LANE_ASYNC_MODE_SEL1 6:6 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_NVL_RX_LANE_ASYNC_MODE_SEL1_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_TXCLKREF_SWITCH_ASYNC_MODE 10:9 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_SWITCH_ASYNC_MODE_TXCLKREF_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_IST_CTRL 0x00132518 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_IST_CTRL_IST_SERDES4FCLK_CG_EN_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_IST_CTRL_IST_MODE 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_IST_CTRL_IST_MODE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_FGC6_CLK_GATE 0x0013251c /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_FGC6_CLK_GATE_SYSCLK_LNK_DISABLE 0:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_FGC6_CLK_GATE_SYSCLK_LNK_DISABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_FGC6_CLK_GATE_SYSCLK_LNK_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_FGC6_CLK_GATE_SYSCLK_LNK_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL 0x00132520 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NVLIPT_CTL_CLK_DIVIDE 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NVLIPT_CTL_CLK_DIVIDE_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NVL_PLLCTL_CLK_DIVIDE 7:3 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NVL_PLLCTL_CLK_DIVIDE_INIT 0x00000007 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NVLIPT_CTL_CLK 8:8 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NVLIPT_CTL_CLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NVLIPT_CTL_CLK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NVLIPT_CTL_CLK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NCISOC_CLK 9:9 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NCISOC_CLK_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NCISOC_CLK_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_GATE_NCISOC_CLK_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NCISOC_CLK_SLOWDOWN_DIVIDE 19:10 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NCISOC_CLK_SLOWDOWN_DIVIDE_INIT 0x00000009 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NCISOC_CLK_SLOWDOWN_DISABLE 20:20 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NCISOC_CLK_SLOWDOWN_DISABLE_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NCISOC_CLK_SLOWDOWN_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL_NCISOC_CLK_SLOWDOWN_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_CLK_DIV_CTRL__PRIV_LEVEL_MASK 0x001327fc /* */
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#define NV_PTRIM_SYS_NVLINK_DFT_CTRL 0x00132524 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_DFT_CTRL_RX_LANE_CLK_SEL 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_DFT_CTRL_RX_LANE_CLK_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_DFT_CTRL_RX_LANE_CLK_SEL_RX_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DFT_CTRL_RX_LANE_CLK_SEL_TX_CLK_DFT 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DFT_CTRL__PRIV_LEVEL_MASK 0x001327fc /* */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL 0x00132420 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UNIT2CLKS_PLL_TURN_OFF 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UNIT2CLKS_PLL_TURN_OFF_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UNIT2CLKS_PLL_TURN_OFF_OVRD 1:1 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UNIT2CLKS_PLL_TURN_OFF_OVRD_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_OVERRIDE_STATUS 4:4 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_OVERRIDE_STATUS_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UPHY_TXCLKREF_BYPASS_DONE_CYA 6:6 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UPHY_TXCLKREF_BYPASS_DONE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_FLAG_CAL_VALID_CYA 7:7 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_FLAG_CAL_VALID_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UPHY_TXCLKREF_BYPASS_CYA 9:9 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UPHY_TXCLKREF_BYPASS_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UPHY_TXCLKREF_BYPASS_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_UPHY_TXCLKREF_BYPASS_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_OVERRIDE_INPUT_STATUS 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_OVERRIDE_INPUT_STATUS_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PHY2CLKS_CAL_DONE_CYA 17:17 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PHY2CLKS_CAL_DONE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PHY2CLKS_RCAL_DONE_CYA 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PHY2CLKS_RCAL_DONE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_RATE_ID_CYA 19:19 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_RATE_ID_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_OVERRIDE_PLL_CONTROLS 20:20 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_OVERRIDE_PLL_CONTROLS_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_RCAL_EN_CYA 21:21 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_RCAL_EN_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_CAL_EN_CYA 22:22 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_CAL_EN_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_IDDQ_CYA 23:23 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_IDDQ_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_SLEEP_CYA 25:24 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_SLEEP_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_ENABLE_CYA 26:26 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_CLKS2PHY_ENABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PLL_OFF_CYA 28:28 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PLL_OFF_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PHY2CLKS_LOCKDET_STATUS_CYA 29:29 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL_PHY2CLKS_LOCKDET_STATUS_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_CTRL__PRIV_LEVEL_MASK 0x001327fc /* */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS 0x00132424 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_FLAG_CAL_VALID 4:4 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_PLL_OFF 5:5 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_FSM_TIMEOUT_VALUE 14:6 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_FSM_TIMEOUT_VALUE_10US 0x0000010E /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_FSM_TIMEOUT_VALUE_INIT 0x0000010E /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_CURRENT_STATE_NVLINK_FSM 18:16 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_CURRENT_STATE_UPHY_FSM 23:20 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_CURRENT_STATE_UPHY_RCAL 25:24 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_FSM_TIMED_OUT 26:26 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_FSM_TIMED_OUT_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_FSM_TIMED_OUT_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_CAL_DONE 27:27 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_CAL_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_CAL_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_DONE 28:28 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_STATUS_RCAL_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_SPARE_RW 0x00132428 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_SPARE_RW_NVLINK_SPARE_RW 31:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_SPARE_RW_NVLINK_SPARE_RW_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_SPARE_RO 0x0013242c /* R--4R */
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#define NV_PTRIM_SYS_NVLINK_NVHS0_SPARE_RO_NVLINK_SPARE_RO 31:0 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL 0x00132600 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_ALT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA 6:3 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_HIGH 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_LOW 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF_DUPLICATE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS 9:8 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_ALT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_TXCLKREF 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS 15:12 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_HIGH 0x00000008 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_LOW 0x00000004 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF_DUPLICATE 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK0_TXRX_SEL_CTRL__PRIV_LEVEL_MASK 0x001327fc /* */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL 0x00132604 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_ALT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA 6:3 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_HIGH 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_LOW 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF_DUPLICATE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS 9:8 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_ALT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_TXCLKREF 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS 15:12 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_HIGH 0x00000008 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_LOW 0x00000004 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF_DUPLICATE 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK1_TXRX_SEL_CTRL__PRIV_LEVEL_MASK 0x001327fc /* */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL 0x00132608 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_ALT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA 6:3 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_HIGH 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_LOW 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF_DUPLICATE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS 9:8 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_ALT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_TXCLKREF 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS 15:12 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_HIGH 0x00000008 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_LOW 0x00000004 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF_DUPLICATE 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK2_TXRX_SEL_CTRL__PRIV_LEVEL_MASK 0x001327fc /* */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL 0x0013260c /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL 0:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_OVERRIDE_CLOCKS_CONTROL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA 2:2 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_ALT 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA 6:3 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_INIT 0x00000001 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_HIGH 0x00000008 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_RX_CLK_LOW 0x00000004 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_SRC_SELECT_CYA_TXCLKREF_DUPLICATE 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS 9:8 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_ALT 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_STS_TXCLKREF 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS 15:12 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_OFF 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_HIGH 0x00000008 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_RX_CLK_LOW 0x00000004 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_STS_TXCLKREF_DUPLICATE 0x00000002 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA 16:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_TX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE 17:17 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_TXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA 18:18 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_NO 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_NVL_RX_CLK_DISABLE_CYA_YES 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE 19:19 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_NO 0x00000000 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL_CLKS2NVL_RXCLK_DISABLE_DONE_YES 0x00000001 /* R---V */
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#define NV_PTRIM_SYS_NVLINK3_TXRX_SEL_CTRL__PRIV_LEVEL_MASK 0x001327fc /* */
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#define NV_PTRIM_SYS_NVLINK_AUX_TX_RDET_DIV 0x00132418 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_NVLINK_DIS_OVRD 19:19 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_NVLINK_DIS_OVRD_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_NVLINK_DIS 20:20 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_AUX_TX_RDET_DIV_LX_AUX_TX_RDET_CLK_NVLINK_DIS_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2 0x0013241c /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_SEL 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_SEL_FAST_STEP_EN_SYSCLK 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_SEL_SAFE_CLK 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_TCLKOUT_EN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_TCLKOUT_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_TCLKOUT_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_PRB2_TCLKOUT_EN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_NVHS_PLL_SELECT 0x00132504 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_NVHS_PLL_SELECT_SEL 1:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_NVHS_PLL_SELECT_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_NVHS_PLL_SELECT_SEL_NVHS0_PAD 0x00000000 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_NVHS_PLL_SELECT_SEL_NVHS1_PAD 0x00000001 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_DEBUG_NVHS_PLL_SELECT_SEL_NVHS2_PAD 0x00000002 /* RW--V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0 0x001325f4 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0_CHIPLETID 7:0 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0_CHIPLETID_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN 30:30 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0_TRIMCAST_JTG_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN 31:31 /* RWIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0_TRIMCAST_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD0__PRIV_LEVEL_MASK 0x001327f8 /* */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1 0x001325f8 /* -W-4R */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_PARTITIONID 7:0 /* -WIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_PARTITIONID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_MACROID 15:8 /* -WIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_MACROID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_TRIMMERID 23:16 /* -WIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_TRIMMERID_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_TRIMVAL 28:24 /* -WIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_TRIMVAL_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_OP 30:30 /* -WIUF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1_OP_INIT 0x00000000 /* -WI-V */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_CONTROL_CMD1__PRIV_LEVEL_MASK 0x001327f8 /* */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_STATUS 0x001325fc /* R--4R */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_STATUS_VALID 0:0 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_STATUS_TRIMVALMATCH 1:1 /* R--UF */
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#define NV_PTRIM_SYS_NVLINK_TRIMCAST_STATUS__PRIV_LEVEL_MASK 0x001327f8 /* */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK 0x00132740 /* RW-4R */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_PROBEID 7:0 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_PROBEID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_MACROID 15:8 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_MACROID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_PARTITIONID 23:16 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_PARTITIONID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_CHIPLETID 27:24 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_CHIPLETID_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_SAFE_CLK_MODEN 30:30 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_SAFE_CLK_MODEN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_PROBE_OUT_ALWAYS_ONN 31:31 /* RWEUF */
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#define NV_PTRIM_SYS_NVLINK_TCLKOUT_CTRL_NVLINK_PROBE_OUT_ALWAYS_ONN_INIT 0x00000000 /* RWE-V */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_GPCCLK 0x00000000 /* */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_HUBCLK 0x00000008 /* */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_LTCCLK 0x00000001 /* */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_SYSCLK 0x00000007 /* */
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#define NV_PTRIM_CLK_NAMEMAP_INDEX_XBARCLK 0x00000002 /* */
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#define NV_PTRIM_GPC_SEL_VCO_GPCCLK_OUT 0:0 /* */
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#define NV_PTRIM_GPC_SEL_VCO_GPCCLK_OUT_BYPASS 0x00000000 /* */
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#define NV_PTRIM_GPC_SEL_VCO_GPCCLK_OUT_INIT 0x00000000 /* */
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#define NV_PTRIM_GPC_SEL_VCO_GPCCLK_OUT_VCO 0x00000001 /* */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO_GPCCLK_OUT 0:0 /* */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO_GPCCLK_OUT_BYPASS 0x00000000 /* */
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#define NV_PTRIM_GPC_STATUS_SEL_VCO_GPCCLK_OUT_VCO 0x00000001 /* */
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#define NV_PTRIM_GPC_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCCLK_OUT 0x00000000 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCCLK_NAFLL 0x00000003 /* */
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#define NV_PTRIM_GPC_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCCLK_NAFLL 0x00000002 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWRCLK_GPCCLK_SLOW_VAL_OVERRIDE 0:0 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWRCLK_GPCCLK_SLOW_VAL_OVERRIDE_INIT 0x00000000 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWRCLK_GPCCLK_SLOW_VAL_OVERRIDE_VALUE 6:1 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_LCLPWRCLK_GPCCLK_SLOW_VAL_OVERRIDE_VALUE_INIT 0x00000000 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWRCLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE 7:7 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWRCLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_INIT 0x00000000 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWRCLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_VALUE 8:8 /* */
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#define NV_PTRIM_GPC_CLK_OVERRIDE_HW_SIGNALS_PWRCLK_GPCCLK_LOC_SLOW_REQ_OVERRIDE_VALUE_INIT 0x00000000 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCCLK_ALT 0x00000041 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCCLK_OUT 0x00000040 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCCLK_REF 0x00000042 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_HUBCLK_OUT 0x00000010 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_LTCCLK_ALT 0x00000051 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_LTCCLK_OUT 0x00000050 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_LTCCLK_REF 0x00000052 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_SYSCLK_OUT 0x00000000 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_SYSCLK_REF 0x00000002 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_XBARCLK_ALT 0x00000061 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_XBARCLK_OUT 0x00000060 /* */
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#define NV_PTRIM_SYS_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_XBARCLK_REF 0x00000062 /* */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_ALT_SYSCLK 0x00000003 /* */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_SYSCLK_DVCO 0x00000005 /* */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_SYSCLK_LDIV_VCO_IP 0x00000002 /* */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_SYSPLL_SELECT_SYSPLL_SYSCLK_OP 0x00000004 /* */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_ALT_XBARCLK 0x00000003 /* */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_XBARCLK_LDIV_VCO_IP 0x00000002 /* */
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#define NV_PTRIM_SYS_PLLS_PRB_SELECT_PLLS_O_SRC_XBARPLL_SELECT_XBARPLL_XBARCLK_OP 0x00000004 /* */
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#define NV_PTRIM_SYS_FR_CLK_CNTR_SYSCLK_CFG_SOURCE_SYSCLK_NAFLL 0x00000003 /* */
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#define NV_PVTRIM_SYS_FR_CLK_CNTR_HUBCLK_CFG_SOURCE_HUBCLK_DIV32_FTM 0x00000002 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPCCLK_CAPABILITY 0:0 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPCCLK_CAPABILITY_INIT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPCCLK_CAPABILITY_PRESENT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_GPCCLK_CAPABILITY_REMOVED 0x00000000 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTCCLK_CAPABILITY 1:1 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTCCLK_CAPABILITY_INIT 0x00000000 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTCCLK_CAPABILITY_PRESENT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_LTCCLK_CAPABILITY_REMOVED 0x00000000 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBARCLK_CAPABILITY 2:2 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBARCLK_CAPABILITY_INIT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBARCLK_CAPABILITY_PRESENT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_XBARCLK_CAPABILITY_REMOVED 0x00000000 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYSCLK_CAPABILITY 7:7 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYSCLK_CAPABILITY_INIT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYSCLK_CAPABILITY_PRESENT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_SYSCLK_CAPABILITY_REMOVED 0x00000000 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUBCLK_CAPABILITY 8:8 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUBCLK_CAPABILITY_INIT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUBCLK_CAPABILITY_PRESENT 0x00000001 /* */
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#define NV_PTRIM_SYS_PHYSICAL_CLKS_0_HUBCLK_CAPABILITY_REMOVED 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_CORE_LINEARDIV_DEBUG_DIVIDE_SELECT_GPCCLK_OUT 0x00000000 /* */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_CFG_SOURCE_GPCCLK_NAFLL 0x00000003 /* */
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#define NV_PTRIM_GPC_BCAST_FR_CLK_CNTR_NCGPCCLK_FREQ_PID_CFG_SOURCE_GPCCLK_NAFLL 0x00000002 /* */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_XBARCLK_CFG_SOURCE_XBARCLK_NAFLL 0x00000003 /* */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCXBARNAFLL_FREQ_PID_CFG_SOURCE_XBARCLK_NAFLL 0x00000002 /* */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NVDCLK_CFG_SOURCE_NVDCLK_NAFLL 0x00000003 /* */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCNVDNAFLL_FREQ_PID_CFG_SOURCE_NVDCLK_NAFLL 0x00000002 /* */
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#define NV_PTRIM_SYS_NAFLL_FR_CLK_CNTR_NCSYSNAFLL_FREQ_PID_CFG_SOURCE_SYSCLK_NAFLL 0x00000002 /* */
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#endif // __ga102_dev_trim_h__
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