97 lines
6.1 KiB
C
97 lines
6.1 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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/* This file is autogenerated by ref2h.pl. Do not edit */
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/* ------------------------- System Includes -------------------------------- */
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#include "dev_pwr_pri.h"
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#include "dev_chiplet_pwr.h"
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/* ------------------------- Macros and Defines ----------------------------- */
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// Per Parition Profile Values for various Feature. (Value taken from the PARTITION register)
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#define PROFILE_POWER_ON 0x0
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#define PROFILE_RPPG 0x1
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#define PROFILE_RPG 0x2
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/* =============================================================== */
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// Profile Bit Position in Partition regsiter
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/* =============================================================== */
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#define PROFILE0_BIT_POS 0
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#define PROFILE1_BIT_POS 2
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#define PROFILE2_BIT_POS 4
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#define PROFILE3_BIT_POS 6
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/* =============================================================== */
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// Bit position for Autoincrement setting
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/* =============================================================== */
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#define PARTITION1_INDEX_WRITEINCR_BIT_POSITION 9
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/* =============================================================== */
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// FEATURE | PROFILE MAPPING
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/* =============================================================== */
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// GR-RPPG | PROFILE0
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// GR-RPG | PROFILE1
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// MS-RPPG | PROFILE0
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// L2-RPG | PROFILE1
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/* =============================================================== */
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/* =============================================================== */
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// Macros for SW use while programing the Profile
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/* =============================================================== */
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// Profile to be used by SW for RPPG feature
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#define SRAM_PG_PROFILE_RPPG NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE0
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// Profile to be used by SW for RPG feature
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#define SRAM_PG_PROFILE_RPG NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE1
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// Profile to be used by SW for L2RPG feature
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#define SRAM_PG_PROFILE_L2RPG NV_CPWR_PMU_RAM_TARGET_SEQ_PROFILE1
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/* =============================================================== */
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#define FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED (NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED << PARTITION1_INDEX_WRITEINCR_BIT_POSITION)
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/* =============================================================== */ \
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/* ------- Program the MS PROFILEs for MS-RPPG & L2-RPG ---------- */ \
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/* =============================================================== */ \
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/* =============================================================== */ \
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/* ------------------ FBP ---------------------- */
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/* =============================================================== */ \
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// This macro is defined in the format:
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// _op_(RegAddr, regVal, wrCount)
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//
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// regAddr - Register address to program
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// regVal - Value to program in this register
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// wrCount - Number of times this register has to be written with same value (for Auto increment feature on write for all the partition in given chiplet)
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/* =============================================================== */ \
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#define SRAM_PG_PROFILE_INIT(_op_) \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX, (FBPS_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED | NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN), 1) \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P0 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P1 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P2 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P3 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P4 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P5 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P6 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P7 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P8 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_POWER_ON << PROFILE0_BIT_POS), 1) /* P9 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P10 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P11 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P12 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P13 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P14 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P15 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P16 */ \
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_op_(NV_PCHIPLET_PWR_FBPS_POWER_CTRL_MS_RAM_PARTITION1, (PROFILE_RPPG << PROFILE1_BIT_POS) | (PROFILE_RPPG << PROFILE0_BIT_POS), 1) /* P17 */
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