117 lines
7.4 KiB
C
117 lines
7.4 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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/* This file is autogenerated by ref2h.pl. Do not edit */
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#define PRIV_BLOCKER_MS_WL_RANGE_START_0 DEVICE_BASE(NV_PCFG)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_0 DEVICE_EXTENT(NV_PCFG)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_1 DEVICE_BASE(NV_PCFG1)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_1 DEVICE_EXTENT(NV_PCFG1)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_2 DEVICE_BASE(NV_XP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_2 DEVICE_EXTENT(NV_XP)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_3 DEVICE_BASE(NV_PMC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_3 DEVICE_EXTENT(NV_PMC)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_4 DEVICE_BASE(NV_PBUS)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_4 DEVICE_EXTENT(NV_PBUS)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_5 DEVICE_BASE(NV_PBUS)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_5 DEVICE_EXTENT(NV_PBUS)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_6 DEVICE_BASE(NV_PTIMER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_6 DEVICE_EXTENT(NV_PTIMER)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_7 DEVICE_BASE(NV_PPBDMA)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_7 DEVICE_EXTENT(NV_PPBDMA)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_8 DEVICE_BASE(NV_PTOP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_8 DEVICE_EXTENT(NV_PTOP)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_9 DEVICE_BASE(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_9 DEVICE_EXTENT(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_10 DEVICE_BASE(NV_PERF_PMMFBP)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_10 DEVICE_EXTENT(NV_PERF_PMMFBP)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_11 DEVICE_BASE(NV_PERF_PMMSYS)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_11 DEVICE_EXTENT(NV_PERF_PMMSYS)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_12 DEVICE_BASE(NV_PERF_PMMFBPROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_12 DEVICE_EXTENT(NV_PERF_PMMFBPROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_13 DEVICE_BASE(NV_PERF_PMMGPCROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_13 DEVICE_EXTENT(NV_PERF_PMMGPCROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_14 DEVICE_BASE(NV_PERF_PMMSYSROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_14 DEVICE_EXTENT(NV_PERF_PMMSYSROUTER)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_15 DEVICE_BASE(NV_HDACODEC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_15 DEVICE_EXTENT(NV_HDACODEC)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_16 DEVICE_BASE(NV_PPWR)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_16 DEVICE_EXTENT(NV_PPWR)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_17 DEVICE_BASE(NV_THERM)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_17 DEVICE_EXTENT(NV_THERM)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_18 DEVICE_BASE(NV_FUSE)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_18 DEVICE_EXTENT(NV_FUSE)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_19 DEVICE_BASE(NV_PMGR)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_19 DEVICE_EXTENT(NV_PMGR)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_20 DEVICE_BASE(NV_PSEC)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_20 DEVICE_EXTENT(NV_PSEC)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_21 DEVICE_BASE(NV_CTRL)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_21 DEVICE_EXTENT(NV_CTRL)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_22 DEVICE_BASE(NV_PERF_PMASYS)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_22 DEVICE_EXTENT(NV_PERF_PMASYS)
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#define PRIV_BLOCKER_MS_WL_RANGE_START_23 DEVICE_BASE(NV_PIOCTRL)
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#define PRIV_BLOCKER_MS_WL_RANGE_END_23 DEVICE_EXTENT(NV_PIOCTRL)
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/* #define PRIV_BLOCKER_MS_WL_RANGE_START(24-31) WHITE CYA START ADDRESS */
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/* #define PRIV_BLOCKER_MS_WL_RANGE_END(24-31) WHITE CYA END ADDRESS */
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#define PRIV_BLOCKER_MS_BL_RANGE_START_0 NV_PBUS_BAR0_WINDOW
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#define PRIV_BLOCKER_MS_BL_RANGE_END_0 NV_PBUS_BAR0_WINDOW
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#define PRIV_BLOCKER_MS_BL_RANGE_START_1 NV_PBUS_BAR1_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_END_1 NV_PBUS_BAR1_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_START_2 NV_PBUS_BAR2_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_END_2 NV_PBUS_BAR2_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_START_3 NV_PBUS_FLUSH_BIND_CTL
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#define PRIV_BLOCKER_MS_BL_RANGE_END_3 NV_PBUS_FLUSH_BIND_CTL
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/* FIXME - Range 4-5 were vacated by removed pfifo registers */
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/* Copying range 3 redundantly to preserve the defines until they are repurposed */
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#define PRIV_BLOCKER_MS_BL_RANGE_START_4 NV_PBUS_FLUSH_BIND_CTL
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#define PRIV_BLOCKER_MS_BL_RANGE_END_4 NV_PBUS_FLUSH_BIND_CTL
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#define PRIV_BLOCKER_MS_BL_RANGE_START_5 NV_PBUS_FLUSH_BIND_CTL
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#define PRIV_BLOCKER_MS_BL_RANGE_END_5 NV_PBUS_FLUSH_BIND_CTL
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/* End of redundant ranges */
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#define PRIV_BLOCKER_MS_BL_RANGE_START_6 DEVICE_BASE(NV_RUNLIST_GLOBAL_PRI_RANGE_0)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_6 DEVICE_EXTENT(NV_RUNLIST_GLOBAL_PRI_RANGE_0)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_7 DEVICE_BASE(NV_CHRAM_GLOBAL_PRI_RANGE_0)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_7 DEVICE_EXTENT(NV_CHRAM_GLOBAL_PRI_RANGE_0)
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/* Note: NV_PPBDMA will need to be replaced with NV_PBDMA_GLOBAL_PRI_RANGE_0 */
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/* (this will need to happen when NV_PPBDMA is replaced with 0-based NV_PBDMA) */
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#define PRIV_BLOCKER_MS_BL_RANGE_START_8 DEVICE_BASE(NV_PPBDMA)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_8 DEVICE_EXTENT(NV_PPBDMA)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_9 DEVICE_BASE(NV_UFLUSH)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_9 DEVICE_EXTENT(NV_UFLUSH)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_10 DEVICE_BASE(NV_UFLUSH)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_10 DEVICE_EXTENT(NV_UFLUSH)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_11 DEVICE_BASE(NV_PRAMIN)
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#define PRIV_BLOCKER_MS_BL_RANGE_END_11 DEVICE_EXTENT(NV_PRAMIN)
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#define PRIV_BLOCKER_MS_BL_RANGE_START_12 NV_PERF_PMASYS_MEM_BLOCK
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#define PRIV_BLOCKER_MS_BL_RANGE_END_12 NV_PERF_PMASYS_MEM_BLOCK
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/* #define PRIV_BLOCKER_MS_BL_RANGE_START(24-31) BLACKLIST CYA START ADDRESS */
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/* #define PRIV_BLOCKER_MS_BL_RANGE_END(24-31) BLACKLIST CYA END ADDRESS */
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/* SW needs code to program NV_PPWR_PMU_MUTEX(RM_PMU_MUTEX_ID_GPIO) to PRIV_BLOCKER_MS_BL_RANGE_END(24) if PSI enabled */
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#define PRIV_BLOCKER_GR_WL_RANGE_START_0 0x00000000
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#define PRIV_BLOCKER_GR_WL_RANGE_END_0 0xffffffff
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#define PRIV_BLOCKER_GR_BL_RANGE_START_0 DEVICE_BASE(NV_PGRAPH)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_0 DEVICE_EXTENT(NV_PGRAPH)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_1 DEVICE_BASE(NV_PTRIM_GPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_1 DEVICE_EXTENT(NV_PTRIM_GPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_2 DEVICE_BASE(NV_PTRIM_GPC_BC)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_2 DEVICE_EXTENT(NV_PTRIM_GPC_BC)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_3 DEVICE_BASE(NV_PCHIPLET_PWR)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_3 DEVICE_EXTENT(NV_PCHIPLET_PWR)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_4 DEVICE_BASE(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_END_4 DEVICE_EXTENT(NV_PERF_PMMGPC)
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#define PRIV_BLOCKER_GR_BL_RANGE_START_5 NV_XBAR_MXBAR_CS_PRI_SYS0_HXI_PREG_CG1_SLCG
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#define PRIV_BLOCKER_GR_BL_RANGE_END_5 NV_XBAR_MXBAR_CS_PRI_SYS0_HXI_PREG_CG1_SLCG
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#define PRIV_BLOCKER_GR_BL_RANGE_START_6 NV_XBAR_MXBAR_PRI_GPC0_GNIC
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#define PRIV_BLOCKER_GR_BL_RANGE_END_6 NV_XBAR_MXBAR_PRI_GPC0_GNIC
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